diff options
Diffstat (limited to 'arch/arm/boards/pcm037/lowlevel_init.S')
| -rw-r--r-- | arch/arm/boards/pcm037/lowlevel_init.S | 65 |
1 files changed, 36 insertions, 29 deletions
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S index a6747c2482..f9ecce1141 100644 --- a/arch/arm/boards/pcm037/lowlevel_init.S +++ b/arch/arm/boards/pcm037/lowlevel_init.S @@ -17,9 +17,10 @@ * */ -#include <mach/imx-regs.h> +#include <mach/imx31-regs.h> #include <mach/imx-pll.h> #include <asm/barebox-arm-head.h> +#include <mach/esdctl.h> #define writel(val, reg) \ ldr r0, =reg; \ @@ -46,24 +47,30 @@ reset: common_reset r0 - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR) + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) DELAY 0x40000 - writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR) - writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR) - - writel(PDR0_CSI_PODF(0xff1) | \ - PDR0_PER_PODF(7) | \ - PDR0_HSP_PODF(3) | \ - PDR0_NFC_PODF(5) | \ - PDR0_IPG_PODF(1) | \ - PDR0_MAX_PODF(3) | \ - PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + CCM_PDR0) - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL) + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR) + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) + + writel(MX31_PDR0_CSI_PODF(0xff1) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0) + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | + IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL) + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL) /* Configure IOMUXC * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) @@ -96,19 +103,19 @@ clear_iomux: #elif defined CONFIG_PCM037_SDRAM_BANK0_256MB #define ROWS0 ESDCTL0_ROW14 #endif - writel(0x00000004, ESDMISC) - writel(0x006ac73a, ESDCFG0) - writel(0x90100000 | ROWS0, ESDCTL0) + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0) + writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS0, ESDCTL0) + writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x12344321, MX31_CSD0_BASE_ADDR) writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0xb0100000 | ROWS0, ESDCTL0) + writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33) writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS0, ESDCTL0) + writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR) - writel(0x0000000c, ESDMISC) + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) #ifndef CONFIG_PCM037_SDRAM_BANK1_NONE #if defined CONFIG_PCM037_SDRAM_BANK1_128MB @@ -116,18 +123,18 @@ clear_iomux: #elif defined CONFIG_PCM037_SDRAM_BANK1_256MB #define ROWS1 ESDCTL0_ROW14 #endif - writel(0x006ac73a, ESDCFG1) - writel(0x90100000 | ROWS1, ESDCTL1) + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1) + writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS1, ESDCTL1) + writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0x12344321, MX31_CSD1_BASE_ADDR) writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0xb0100000 | ROWS1, ESDCTL1) + writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33) writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS1, ESDCTL1) + writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR) - writel(0x0000000c, ESDMISC) + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) #endif #ifdef CONFIG_NAND_IMX_BOOT |