diff options
Diffstat (limited to 'arch/arm/boards/pcm038/pcm038.c')
| -rw-r--r-- | arch/arm/boards/pcm038/pcm038.c | 183 |
1 files changed, 60 insertions, 123 deletions
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c index d481bdc576..badc978a24 100644 --- a/arch/arm/boards/pcm038/pcm038.c +++ b/arch/arm/boards/pcm038/pcm038.c @@ -30,17 +30,13 @@ #include <generated/mach-types.h> #include <partition.h> #include <fs.h> -#include <fcntl.h> #include <nand.h> -#include <command.h> #include <spi/spi.h> #include <io.h> #include <mach/imx-nand.h> #include <mach/imx-pll.h> #include <mach/imxfb.h> -#include <asm/mmu.h> #include <i2c/i2c.h> -#include <usb/ulpi.h> #include <mach/spi.h> #include <mach/iomux-mx27.h> #include <mach/devices-imx27.h> @@ -110,27 +106,67 @@ static struct imx_fb_platform_data pcm038_fb_data = { .dmacr = 0x00020010, }; -#ifdef CONFIG_USB -static void pcm038_usbh_init(void) +/** + * The spctl0 register is a beast: Seems you can read it + * only one times without writing it again. + */ +static inline uint32_t get_pll_spctl10(void) { - uint32_t temp; + uint32_t reg; - temp = readl(IMX_OTG_BASE + 0x600); - temp &= ~((3 << 21) | 1); - temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(temp, IMX_OTG_BASE + 0x600); + reg = SPCTL0; + SPCTL0 = reg; + + return reg; +} - temp = readl(IMX_OTG_BASE + 0x584); - temp &= ~(3 << 30); - temp |= 2 << 30; - writel(temp, IMX_OTG_BASE + 0x584); +/** + * If the PLL settings are in place switch the CPU core frequency to the max. value + */ +static int pcm038_power_init(void) +{ +#ifdef CONFIG_MFD_MC13XXX + uint32_t spctl0 = get_pll_spctl10(); + struct mc13xxx *mc13xxx = mc13xxx_get(); - mdelay(10); + /* PLL registers already set to their final values? */ + if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { + console_flush(); + if (mc13xxx) { + mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), + MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | + MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | + MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); + + mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), + MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1A_SOFTSTART | + MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1B_SOFTSTART | + MC13783_SW_PLL_FACTOR(32)); - ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1); -} + /* wait for required power level to run the CPU at 400 MHz */ + udelay(100000); + CSCR = CSCR_VAL_FINAL; + PCDR0 = 0x130410c3; + PCDR1 = 0x09030911; + + /* Clocks have changed. Notify clients */ + clock_notifier_call_chain(); + } else { + printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); + } + } #endif + /* clock gating enable */ + GPCR = 0x00050f08; + + return 0; +} + static int pcm038_mem_init(void) { arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024); @@ -202,19 +238,6 @@ static int pcm038_devices_init(void) PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD, - /* USB host 2 */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, /* I2C1 */ PD17_PF_I2C_DATA | GPIO_PUEN, PD18_PF_I2C_CLK, @@ -229,9 +252,6 @@ static int pcm038_devices_init(void) /* configure SRAM on cs1 */ imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); - /* configure SJA1000 on cs4 */ - imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); - /* initizalize gpios */ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); @@ -239,12 +259,11 @@ static int pcm038_devices_init(void) PCCR0 |= PCCR0_CSPI1_EN; PCCR1 |= PCCR1_PERCLK2_EN; - gpio_direction_output(GPIO_PORTD | 28, 0); - gpio_set_value(GPIO_PORTD | 28, 0); - spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); imx27_add_spi0(&pcm038_spi_0_data); + pcm038_power_init(); + add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); @@ -253,11 +272,6 @@ static int pcm038_devices_init(void) imx27_add_i2c0(NULL); imx27_add_i2c1(NULL); -#ifdef CONFIG_USB - pcm038_usbh_init(); - add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); -#endif - /* Register the fec device after the PLL re-initialisation * as the fec depends on the (now higher) ipg clock */ @@ -269,19 +283,19 @@ static int pcm038_devices_init(void) case GPCR_BOOT_16BIT_NAND_512: case GPCR_BOOT_8BIT_NAND_512: devfs_add_partition("nand0", 0x00000, 0x80000, - PARTITION_FIXED, "self_raw"); + DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", 0x80000, 0x100000, - PARTITION_FIXED, "env_raw"); + DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); envdev = "NAND"; break; default: devfs_add_partition("nor0", 0x00000, 0x80000, - PARTITION_FIXED, "self0"); + DEVFS_PARTITION_FIXED, "self0"); devfs_add_partition("nor0", 0x80000, 0x100000, - PARTITION_FIXED, "env0"); + DEVFS_PARTITION_FIXED, "env0"); protect_file("/dev/env0", 1); envdev = "NOR"; @@ -305,80 +319,3 @@ static int pcm038_console_init(void) } console_initcall(pcm038_console_init); - -#ifdef CONFIG_MFD_MC13XXX -static int pmic_power(void) -{ - struct mc13xxx *mc13xxx; - - mc13xxx = mc13xxx_get(); - if (!mc13xxx) - return -ENODEV; - - mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), - MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | - MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | - MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); - - mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), - MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1A_SOFTSTART | - MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1B_SOFTSTART | - MC13783_SW_PLL_FACTOR(32)); - - return 0; -} -#else -# define pmic_power() (1) -#endif - -/** - * The spctl0 register is a beast: Seems you can read it - * only one times without writing it again. - */ -static inline uint32_t get_pll_spctl10(void) -{ - uint32_t reg; - - reg = SPCTL0; - SPCTL0 = reg; - - return reg; -} - -/** - * If the PLL settings are in place switch the CPU core frequency to the max. value - */ -static int pcm038_power_init(void) -{ - uint32_t spctl0; - - spctl0 = get_pll_spctl10(); - - /* PLL registers already set to their final values? */ - if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { - console_flush(); - if (!pmic_power()) { - /* wait for required power level to run the CPU at 400 MHz */ - udelay(100000); - CSCR = CSCR_VAL_FINAL; - PCDR0 = 0x130410c3; - PCDR1 = 0x09030911; - /* Clocks have changed. Notify clients */ - clock_notifier_call_chain(); - } else { - printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); - } - } - - /* clock gating enable */ - GPCR = 0x00050f08; - - return 0; -} - -late_initcall(pcm038_power_init); - |