diff options
Diffstat (limited to 'arch/arm/boards/pcm043/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/pcm043/lowlevel.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index 4516e9f017..06f05abef1 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -18,7 +18,7 @@ */ #include <common.h> #include <init.h> -#include <mach/imx-regs.h> +#include <mach/imx35-regs.h> #include <mach/imx-pll.h> #include <mach/esdctl.h> #include <asm/cache-l2x0.h> @@ -52,8 +52,7 @@ static void __bare_init __naked insdram(void) writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ - r = STACK_BASE + STACK_SIZE - 12; - __asm__ __volatile__("mov sp, %0" : : "r"(r)); + arm_setup_stack(STACK_BASE + STACK_SIZE - 12); imx_nand_load_image(_text, barebox_image_size); @@ -66,6 +65,7 @@ void __bare_init __naked reset(void) uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; + unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; int i; @@ -110,28 +110,28 @@ void __bare_init __naked reset(void) * End of ARM1136 init */ - writel(0x003F4208, ccm_base + CCM_CCMR); + writel(0x003F4208, ccm_base + MX35_CCM_CCMR); /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); + writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); /* Check silicon revision and use 532MHz if >=2.1 */ r = readl(MX35_IIM_BASE_ADDR + 0x24); if (r >= IMX35_CHIP_REVISION_2_1) - writel(CCM_PDR0_532, ccm_base + CCM_PDR0); + writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0); else - writel(CCM_PDR0_399, ccm_base + CCM_PDR0); + writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); - r = readl(ccm_base + CCM_CGR0); + r = readl(ccm_base + MX35_CCM_CGR0); r |= 0x00300000; - writel(r, ccm_base + CCM_CGR0); + writel(r, ccm_base + MX35_CCM_CGR0); - r = readl(ccm_base + CCM_CGR1); + r = readl(ccm_base + MX35_CCM_CGR1); r |= 0x00000C00; r |= 0x00000003; - writel(r, ccm_base + CCM_CGR1); + writel(r, ccm_base + MX35_CCM_CGR1); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; @@ -154,17 +154,17 @@ void __bare_init __naked reset(void) writel(r, iomuxc_base + 0x7a4); /* MDDR init, enable mDDR*/ - writel(0x00000304, ESDMISC); /* was 0x00000004 */ + writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */ /* set timing paramters */ - writel(0x0025541F, ESDCFG0); + writel(0x0025541F, esdctl_base + IMX_ESDCFG0); /* select Precharge-All mode */ - writel(0x92220000, ESDCTL0); + writel(0x92220000, esdctl_base + IMX_ESDCTL0); /* Precharge-All */ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Load-Mode-Register mode */ - writel(0xB8001000, ESDCTL0); + writel(0xB8001000, esdctl_base + IMX_ESDCTL0); /* Load reg EMR2 */ writeb(0xda, 0x84000000); /* Load reg EMR3 */ @@ -175,18 +175,18 @@ void __bare_init __naked reset(void) writeb(0xda, 0x80000333); /* select Precharge-All mode */ - writel(0x92220000, ESDCTL0); + writel(0x92220000, esdctl_base + IMX_ESDCTL0); /* Precharge-All */ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Manual-Refresh mode */ - writel(0xA2220000, ESDCTL0); + writel(0xA2220000, esdctl_base + IMX_ESDCTL0); /* Manual-Refresh 2 times */ writel(0x87654321, MX35_CSD0_BASE_ADDR); writel(0x87654321, MX35_CSD0_BASE_ADDR); /* select Load-Mode-Register mode */ - writel(0xB2220000, ESDCTL0); + writel(0xB2220000, esdctl_base + IMX_ESDCTL0); /* Load reg MR -- CL3, BL8, end DLL reset */ writeb(0xda, 0x80000233); /* Load reg EMR1 -- OCD default */ @@ -198,12 +198,12 @@ void __bare_init __naked reset(void) * DSIZ32-bit, BL8, COL10-bit, ROW13-bit * disable PWT & PRCT * disable Auto-Refresh */ - writel(0x82220080, ESDCTL0); + writel(0x82220080, esdctl_base + IMX_ESDCTL0); /* enable Auto-Refresh */ - writel(0x82228080, ESDCTL0); + writel(0x82228080, esdctl_base + IMX_ESDCTL0); /* enable Auto-Refresh */ - writel(0x00002000, ESDCTL1); + writel(0x00002000, esdctl_base + IMX_ESDCTL1); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ |