1 files changed, 29 insertions, 19 deletions

diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
index bd46df0962..a43406e1a2 100644
--- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
+++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
 /*
  * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
  * Applications Processor Reference Manual, Rev. 0.2".
@@ -10,10 +12,10 @@
 #include <config.h>
 #include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx-pll.h>
-#include <mach/esdctl.h>
-#include <mach/imx-nand.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx-pll.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/imx-nand.h>
 
 enum {
 	PHYCARD_MICRON_64MB,
@@ -77,7 +79,24 @@ static void sdram_init(int sdram)
 			MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
 }
 
-static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram)
+extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[];
+
+static void __noreturn phytec_phycard_imx27_start(void)
+{
+	void *fdt;
+
+	fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset();
+
+	imx27_barebox_entry(fdt);
+}
+
+static void __noreturn phytec_phycard_imx27_load_nand(void)
+{
+	imx27_nand_load_image();
+	phytec_phycard_imx27_start();
+}
+
+static noinline void __bare_init phytec_phycard_imx27_common_init(int sdram)
 {
 	unsigned long r;
 
@@ -92,7 +111,7 @@ static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int
 	/* Skip SDRAM initialization if we run from RAM */
         r = get_pc();
         if (r > 0xa0000000 && r < 0xc0000000)
-                imx27_barebox_entry(fdt);
+		phytec_phycard_imx27_start();
 
 	/* 399 MHz */
 	writel(IMX_PLL_PD(0) |
@@ -117,29 +136,20 @@ static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int
 
 	sdram_init(sdram);
 
-	imx27_barebox_boot_nand_external(fdt);
+	imx27_nand_relocate_to_sdram(phytec_phycard_imx27_load_nand);
+	phytec_phycard_imx27_start();
 }
 
-extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[];
-
 ENTRY_FUNCTION(start_phytec_phycard_imx27_64mb, r0, r1, r2)
 {
-	void *fdt;
-
 	arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE);
 
-	fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset();
-
-	phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_64MB);
+	phytec_phycard_imx27_common_init(PHYCARD_MICRON_64MB);
 }
 
 ENTRY_FUNCTION(start_phytec_phycard_imx27_128mb, r0, r1, r2)
 {
-	void *fdt;
-
 	arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE);
 
-	fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset();
-
-	phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_128MB);
+	phytec_phycard_imx27_common_init(PHYCARD_MICRON_128MB);
 }