diff options
Diffstat (limited to 'arch/arm/boards/phytec-som-imx8mq/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/phytec-som-imx8mq/lowlevel.c | 68 |
1 files changed, 22 insertions, 46 deletions
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 4e52b92ad3..362b3ed823 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -4,67 +4,48 @@ */ #include <common.h> +#include <firmware.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx8-ccm-regs.h> -#include <mach/iomux-mx8.h> -#include <mach/imx8-ddrc.h> -#include <mach/xload.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mq.h> +#include <soc/imx8m/ddr.h> +#include <mach/imx/xload.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/mmu.h> -#include <mach/atf.h> -#include <mach/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> #include "ddr.h" -extern char __dtb_imx8mq_phytec_phycore_som_start[]; +extern char __dtb_z_imx8mq_phytec_phycore_som_start[]; #define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); - imx8_uart_setup_ll(); + imx8m_uart_setup(uart); - putc_ll('>'); -} - -static void phytec_imx8mq_som_sram_setup(void) -{ - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - int ret = -ENOTSUPP; - - ddr_init(); + pbl_set_putc(imx_uart_putc, uart); - imx8_get_boot_source(&src, &instance); - - if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_start_image(instance); - - BUG_ON(ret); + putc_ll('>'); } static __noreturn noinline void phytec_phycore_imx8mq_start(void) { - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + setup_uart(); if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { /* @@ -73,7 +54,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * that means DDR needs to be initialized for the * first time. */ - phytec_imx8mq_som_sram_setup(); + ddr_init(); } /* * Straight from the power-on we are at EL3, so the following @@ -83,18 +64,13 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * initialization routine, it is EL2 which means we'll skip * loadting ATF blob again */ - if (current_el() == 3) { - const u8 *bl31; - size_t bl31_size; - - get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); - imx8mq_atf_load_bl31(bl31, bl31_size); - } + if (current_el() == 3) + imx8mq_load_and_start_image_via_tfa(); /* * Standard entry we hit once we initialized both DDR and ATF */ - imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start); + imx8mq_barebox_entry(__dtb_z_imx8mq_phytec_phycore_som_start); } /* @@ -112,7 +88,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR, * executing start_phytec_phycore_imx8mq() the third time * * 6. Standard barebox boot flow continues |