diff options
Diffstat (limited to 'arch/arm/boards/protonic-imx6/padsetup-q.imxcfg')
| -rw-r--r-- | arch/arm/boards/protonic-imx6/padsetup-q.imxcfg | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg new file mode 100644 index 0000000000..c58a481e13 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e0420 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e05a8 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e05b0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e0524 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e051c PAD_SDQS /* SDQS3_P */ +wm 32 0x020e0518 PAD_SDQS /* SDQS4_P */ +wm 32 0x020e050c PAD_SDQS /* SDQS5_P */ +wm 32 0x020e05b8 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e05c0 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e05ac PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e05b4 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0528 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e0520 PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0514 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0510 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e05bc PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e05c4 PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e056c PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0578 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0588 PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0594 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e057c PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e0590 0x00003000 /* SDCKE0 */ +wm 32 0x020e0598 0x00003000 /* SDCKE1 */ +wm 32 0x020e058c 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e059c 0x00003030 /* ODT0 */ +wm 32 0x020e05a0 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0784 PAD_BxDS /* B0DS */ +wm 32 0x020e0788 PAD_BxDS /* B1DS */ +wm 32 0x020e0794 PAD_BxDS /* B2DS */ +wm 32 0x020e079c PAD_BxDS /* B3DS */ +wm 32 0x020e07a0 PAD_BxDS /* B4DS */ +wm 32 0x020e07a4 PAD_BxDS /* B5DS */ +wm 32 0x020e07a8 PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0758 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0774 0x00020000 /* DDRMODE data */ + +wm 32 0x020e078c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0798 0x000c0000 /* DDR_TYPE DDR3 */ |