diff options
Diffstat (limited to 'arch/arm/boards/reflex-achilles/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/reflex-achilles/lowlevel.c | 53 |
1 files changed, 25 insertions, 28 deletions
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index f910b67d5f..12ead6d6dd 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -8,34 +10,39 @@ #include <asm/unaligned.h> #include <debug_ll.h> #include <pbl.h> -#include <mach/arria10-sdram.h> -#include <mach/arria10-regs.h> -#include <mach/arria10-reset-manager.h> -#include <mach/arria10-clock-manager.h> -#include <mach/arria10-pinmux.h> -#include <mach/arria10-fpga.h> +#include <mach/socfpga/arria10-sdram.h> +#include <mach/socfpga/arria10-regs.h> +#include <mach/socfpga/arria10-reset-manager.h> +#include <mach/socfpga/arria10-clock-manager.h> +#include <mach/socfpga/arria10-pinmux.h> +#include <mach/socfpga/arria10-fpga.h> +#include <mach/socfpga/init.h> #include "pll-config-arria10.c" #include "pinmux-config-arria10.c" -#include <mach/generic.h> +#include <mach/socfpga/generic.h> #define BAREBOX_PART 0 #define BITSTREAM_PART 1 #define BAREBOX1_OFFSET SZ_1M -#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K -#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K -#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_512K) +#define BAREBOX3_OFFSET (BAREBOX2_OFFSET + SZ_512K) +#define BAREBOX4_OFFSET (BAREBOX3_OFFSET + SZ_512K) +// Offset from the start of the second partition on the eMMC. #define BITSTREAM1_OFFSET 0x0 -#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) + +extern char __dtb_z_socfpga_arria10_achilles_start[]; -extern char __dtb_socfpga_arria10_achilles_start[]; +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) -static noinline void achilles_start(void) +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2) { int pbl_index = 0; int barebox = 0; int bitstream = 0; - arm_early_mmu_cache_invalidate(); + arm_cpu_lowlevel_init(); + arria10_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -74,31 +81,21 @@ static noinline void achilles_start(void) arria10_start_image(barebox); } -ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2) -{ - arm_cpu_lowlevel_init(); - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - achilles_start(); -} - ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2) { void *fdt; - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } -ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r1, r2) { void *fdt; arm_cpu_lowlevel_init(); - - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - - arm_early_mmu_cache_invalidate(); + arria10_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -112,7 +109,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arria10_ddr_calibration_sequence(); - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } |