diff options
Diffstat (limited to 'arch/arm/boards/sama5d3_xplained/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/sama5d3_xplained/lowlevel.c | 60 |
1 files changed, 50 insertions, 10 deletions
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index 8653c48c69..d66b10fa8f 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -1,23 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause /* - * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 + * Copyright (C) 2014, Atmel Corporation + * Copyright (C) 2018 Ahmad Fatoum, Pengutronix */ #include <common.h> #include <init.h> #include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/iomux.h> +#include <mach/at91/sama5d3.h> +#include <mach/at91/sama5d3-xplained-ddramc.h> +#include <mach/at91/xload.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> +/* PCK = 528MHz, MCK = 132MHz */ +#define MASTER_CLOCK 132000000 -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +static void dbgu_init(void) { - arm_cpu_lowlevel_init(); + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB); - barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); + at91_mux_pio3_pin(pio, pin_to_mask(AT91_PIN_PB31), AT91_MUX_PERIPH_A, 0); + + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU); + at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), MASTER_CLOCK, 115200); + + putc_ll('>'); + pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1)); +} + +SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_xload_mmc, r4) +{ + sama5d3_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + dbgu_init(); + + sama5d3_udelay_init(MASTER_CLOCK); + sama5d3_xplained_ddrconf(); + + sama5d3_atmci_start_image(0, MASTER_CLOCK, 0); +} + +extern char __dtb_z_at91_sama5d3_xplained_start[]; + +SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained, r4) +{ + void *fdt; + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + dbgu_init(); + + fdt = __dtb_z_at91_sama5d3_xplained_start + get_runtime_offset(); + + barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt); } |