diff options
Diffstat (limited to 'arch/arm/boards/skov-imx6/lowlevel.c')
| -rw-r--r-- | arch/arm/boards/skov-imx6/lowlevel.c | 283 |
1 files changed, 76 insertions, 207 deletions
diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c index eab797faa1..16809dd4a6 100644 --- a/arch/arm/boards/skov-imx6/lowlevel.c +++ b/arch/arm/boards/skov-imx6/lowlevel.c @@ -3,19 +3,20 @@ #define pr_fmt(fmt) "skov-imx6: " fmt #include <common.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <io.h> -#include <mach/imx6-mmdc.h> -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6.h> -#include <mach/xload.h> -#include <mach/esdctl.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> #include <serial/imx-uart.h> -#include <mach/iomux-mx6.h> -#include <mach/imx-gpio.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/imx-gpio.h> #include "version.h" static void __udelay(int us) @@ -28,122 +29,6 @@ static void __udelay(int us) /* ------------------------------------------------------------------------ */ /* - * Micron MT41K512M16HA-125 IT:E -> 8 GBit = 64 Meg x 16 x 8 banks - * - * Speed Grade Data Rate (MT/s) tRCD-tRP-CL tRCD(ns) tRP(ns) CL(ns) - * -125 1600 11-11-11 13.75 13.75 13.75 - * (=800 MHz) - * - * Memory configuration used by variant: - * - "Max Performance", 64 bit data bus, 1066 MHz, 4 GiB memory - */ -static const struct mx6_ddr3_cfg skov_imx6_cfg_4x512Mb_1066MHz = { - .mem_speed = 1066, - .density = 8, /* GiBit */ - .width = 16, /* 16 bit data per device */ - .banks = 8, - .rowaddr = 16, /* 64 k */ - .coladdr = 10, /* 1 k */ - .pagesz = 2, /* [kiB] */ - .trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */ - .trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */ - .trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */ - .SRT = 0, -}; - -static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x512Mb_1066MHz = { - .dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */ - .cs_density = 32, /* four 8 GBit devices connected */ - .ncs = 1, /* one CS line for all devices */ - .cs1_mirror = 1, /* TODO */ - .bi_on = 1, /* TODO */ - .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ - .rtt_wr = 0, /* is LW_EN is 0 in their code */ - .ralat = 5, /* TODO */ - .walat = 1, /* TODO */ - .mif3_mode = 3, /* TODO */ - .rst_to_cke = 0x23, /* used in their code as well */ - .sde_to_rst = 0x10, /* used in their code as well */ - .pd_fast_exit = 0, /* TODO */ -}; - -static const struct mx6_mmdc_calibration skov_imx6_calib_4x512Mb_1066MHz = { - .p0_mpwldectrl0 = 0x001a0017, - .p0_mpwldectrl1 = 0x001F001F, - .p0_mpdgctrl0 = 0x43040319, - .p0_mpdgctrl1 = 0x03040279, - .p0_mprddlctl = 0x4d434248, - .p0_mpwrdlctl = 0x34424543, - - .p1_mpwldectrl0 = 0x00170027, - .p1_mpwldectrl1 = 0x000a001f, - .p1_mpdgctrl0 = 0x43040321, - .p1_mpdgctrl1 = 0x03030251, - .p1_mprddlctl = 0x42413c4d, - .p1_mpwrdlctl = 0x49324933, -}; - -/* ------------------------------------------------------------------------ */ - -/* - * Micron MT41K256M16HA-125 IT:E -> 4 GBit = 32 Meg x 16 x 8 banks - * - * Speed Grade Data Rate (MT/s) tRCD-tRP-CL tRCD(ns) tRP(ns) CL(ns) - * -125 1600 11-11-11 13.75 13.75 13.75 - * (=800 MHz) - * - * Memory configuration used by variant: - * - "Max Performance", 64 bit data bus, 1066 MHz, 2 GiB memory - */ -static const struct mx6_ddr3_cfg skov_imx6_cfg_4x256Mb_1066MHz = { - .mem_speed = 1066, - .density = 4, /* GiBit */ - .width = 16, /* 16 bit data per device */ - .banks = 8, - .rowaddr = 15, /* 32 k */ - .coladdr = 10, /* 1 k */ - .pagesz = 2, /* [kiB] */ - .trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */ - .trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */ - .trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */ - .SRT = 0, -}; - -static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x256Mb_1066MHz = { - .dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */ - .cs_density = 16, /* four 4 GBit devices connected */ - .ncs = 1, /* one CS line for all devices */ - .cs1_mirror = 1, /* TODO */ - .bi_on = 1, /* TODO */ - .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ - .rtt_wr = 0, /* is LW_EN is 0 in their code */ - .ralat = 5, /* TODO */ - .walat = 1, /* TODO */ - .mif3_mode = 3, /* TODO */ - .rst_to_cke = 0x23, /* used in their code as well */ - .sde_to_rst = 0x10, /* used in their code as well */ - .pd_fast_exit = 0, /* TODO */ -}; - -static const struct mx6_mmdc_calibration skov_imx6_calib_4x256Mb_1066MHz = { - .p0_mpwldectrl0 = 0x001a0017, - .p0_mpwldectrl1 = 0x001F001F, - .p0_mpdgctrl0 = 0x43040319, - .p0_mpdgctrl1 = 0x03040279, - .p0_mprddlctl = 0x4d434248, - .p0_mpwrdlctl = 0x34424543, - - .p1_mpwldectrl0 = 0x00170027, - .p1_mpwldectrl1 = 0x000a001f, - .p1_mpdgctrl0 = 0x43040321, - .p1_mpdgctrl1 = 0x03030251, - .p1_mprddlctl = 0x42413c4d, - .p1_mpwrdlctl = 0x49324933, -}; - -/* ------------------------------------------------------------------------ */ - -/* * Micron MT41K128M16JT-125 IT:K -> 2 GBit = 16 Meg x 16 x 8 banks * * Speed Grade Data Rate (MT/s) tRCD-tRP-CL tRCD(ns) tRP(ns) CL(ns) @@ -174,33 +59,33 @@ static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x128Mb_1066MHz = { .dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */ .cs_density = 8, /* four 2 GBit devices connected */ .ncs = 1, /* one CS line for all devices */ - .cs1_mirror = 1, /* TODO */ - .bi_on = 1, /* TODO */ + .cs1_mirror = 1, + .bi_on = 1, .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ .rtt_wr = 0, /* is LW_EN is 0 in their code */ - .ralat = 5, /* TODO */ - .walat = 1, /* TODO */ - .mif3_mode = 3, /* TODO */ - .rst_to_cke = 0x23, /* used in their code as well */ - .sde_to_rst = 0x10, /* used in their code as well */ - .pd_fast_exit = 0, /* TODO */ + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .pd_fast_exit = 1, }; /* calibration info for the "max performance" and "high performance" */ static const struct mx6_mmdc_calibration skov_imx6_calib_4x128Mb_1066MHz = { - .p0_mpwldectrl0 = 0x0011000E, - .p0_mpwldectrl1 = 0x000E001B, - .p0_mpdgctrl0 = 0x42720306, - .p0_mpdgctrl1 = 0x026F0266, - .p0_mprddlctl = 0x45393B3E, - .p0_mpwrdlctl = 0x40434541, - - .p1_mpwldectrl0 = 0x00190015, - .p1_mpwldectrl1 = 0x00070018, - .p1_mpdgctrl0 = 0x4273030A, - .p1_mpdgctrl1 = 0x02740240, - .p1_mprddlctl = 0x403A3747, - .p1_mpwrdlctl = 0x473E4A3B, + .p0_mpwldectrl0 = 0x00230023, + .p0_mpwldectrl1 = 0x0029001E, + .p0_mpdgctrl0 = 0x43400350, + .p0_mpdgctrl1 = 0x03380330, + .p0_mprddlctl = 0x3E323638, + .p0_mpwrdlctl = 0x383A3E3A, + + .p1_mpwldectrl0 = 0x001F002A, + .p1_mpwldectrl1 = 0x001A0028, + .p1_mpdgctrl0 = 0x43300340, + .p1_mpdgctrl1 = 0x03340300, + .p1_mprddlctl = 0x383A3242, + .p1_mpwrdlctl = 0x4232463A, }; /* ------------------------------------------------------------------------ */ @@ -214,21 +99,21 @@ static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { .dram_sdqs5 = 0x00000030, .dram_sdqs6 = 0x00000030, .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, - .dram_reset = 0x00020030, + .dram_reset = 0x00000030, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x00003030, .dram_sdodt1 = 0x00003030, @@ -295,25 +180,25 @@ static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_2x128Mb_800MHz = { .dsize = 1, /* 32 bit wide = 2 devices, 16 bit each */ .cs_density = 4, /* two 2 GBit devices connected */ .ncs = 1, /* one CS line for all devices */ - .cs1_mirror = 1, /* TODO */ - .bi_on = 1, /* TODO */ + .cs1_mirror = 1, + .bi_on = 1, .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ .rtt_wr = 0, /* is LW_EN is 0 in their code */ - .ralat = 5, /* TODO */ - .walat = 1, /* TODO */ - .mif3_mode = 3, /* TODO */ - .rst_to_cke = 0x23, /* used in their code as well */ - .sde_to_rst = 0x10, /* used in their code as well */ - .pd_fast_exit = 0, /* TODO */ + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .pd_fast_exit = 1, }; static const struct mx6_mmdc_calibration skov_imx6_calib_2x128Mb_800MHz = { - .p0_mpwldectrl0 = 0x0040003C, - .p0_mpwldectrl1 = 0x0032003E, - .p0_mpdgctrl0 = 0x42350231, - .p0_mpdgctrl1 = 0x021A0218, - .p0_mprddlctl = 0x4B4B4E49, - .p0_mpwrdlctl = 0x3F3F3035, + .p0_mpwldectrl0 = 0x004A004B, + .p0_mpwldectrl1 = 0x00420046, + .p0_mpdgctrl0 = 0x42400240, + .p0_mpdgctrl1 = 0x02300230, + .p0_mprddlctl = 0x464A4A4A, + .p0_mpwrdlctl = 0x32342A32, }; /* ------------------------------------------------------------------------ */ @@ -327,21 +212,21 @@ static const struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { .dram_sdqs5 = 0x00000030, .dram_sdqs6 = 0x00000030, .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x0000030, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, - .dram_reset = 0x00020030, + .dram_reset = 0x00000030, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x00003030, .dram_sdodt1 = 0x00003030, @@ -529,26 +414,6 @@ static void skov_imx6_init(int cpu_type, unsigned board_variant) int instance; switch (board_variant) { - case 12: /* P2 i.MX6Q, max performance */ - if (cpu_type != IMX6_CPUTYPE_IMX6Q) { - pr_err("Invalid SoC! i.MX6Q expected\n"); - return; - } - pr_debug("Initializing a P2 max performance system...\n"); - spl_imx6q_dram_init(&skov_imx6_sysinfo_4x256Mb_1066MHz, - &skov_imx6_calib_4x256Mb_1066MHz, - &skov_imx6_cfg_4x256Mb_1066MHz); - break; - case 18: /* i.MX6Q+ */ - if (cpu_type != IMX6_CPUTYPE_IMX6Q) { - pr_err("Invalid SoC! i.MX6Q expected\n"); - return; - } - pr_debug("Initializing board variant 18\n"); - spl_imx6q_dram_init(&skov_imx6_sysinfo_4x512Mb_1066MHz, - &skov_imx6_calib_4x512Mb_1066MHz, - &skov_imx6_cfg_4x512Mb_1066MHz); - break; case 19: /* i.MX6S "Solo_R512M_F2G" */ if (cpu_type != IMX6_CPUTYPE_IMX6S) { pr_err("Invalid SoC! i.MX6S expected\n"); @@ -618,6 +483,7 @@ static void skov_imx6_init(int cpu_type, unsigned board_variant) extern char __dtb_z_imx6q_skov_imx6_start[]; extern char __dtb_z_imx6dl_skov_imx6_start[]; +extern char __dtb_z_imx6s_skov_imx6_start[]; /* called twice: once for SDRAM setup only, second for devicetree setup */ static noinline void skov_imx6_start(void) @@ -640,8 +506,11 @@ static noinline void skov_imx6_start(void) /* boot this platform (second call) */ switch (cpu_type) { case IMX6_CPUTYPE_IMX6S: + pr_debug("Startup i.MX6S based system...\n"); + imx6q_barebox_entry(__dtb_z_imx6s_skov_imx6_start); + break; case IMX6_CPUTYPE_IMX6DL: - pr_debug("Startup i.MX6S/DL based system...\n"); + pr_debug("Startup i.MX6DL based system...\n"); imx6q_barebox_entry(__dtb_z_imx6dl_skov_imx6_start); break; case IMX6_CPUTYPE_IMX6D: @@ -654,7 +523,7 @@ static noinline void skov_imx6_start(void) ENTRY_FUNCTION(start_imx6_skov_imx6, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx6_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); |