diff options
Diffstat (limited to 'arch/arm/boards/terasic-de0-nano-soc/sdram_config.h')
| -rw-r--r-- | arch/arm/boards/terasic-de0-nano-soc/sdram_config.h | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h b/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h index 292ff6d4d7..7a7a9549ca 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h +++ b/arch/arm/boards/terasic-de0-nano-soc/sdram_config.h @@ -73,12 +73,12 @@ #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0) #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0) #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0) -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x3FFD1088) +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x0) #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210) -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x1EF84) -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x2020) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x10441) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x78) #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0) -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0xF800) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0x0) #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200) #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555) @@ -100,9 +100,13 @@ (0x0101) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x3) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x311) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0) -#endif /*#ifndef__SDRAM_CONFIG_H*/ +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR (2) +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC (2) +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2) + +#endif /*#ifndef__SDRAM_CONFIG_H */ |