1 files changed, 131 insertions, 0 deletions
diff --git a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg
new file mode 100644
index 0000000000..39f2a8a221
--- /dev/null
+++ b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg
@@ -0,0 +1,131 @@
+/*
+ * These values are taken from:
+ * repository: https://github.com/UDOOboard/uboot-imx
+ * branch: udoo/2015.04.imx
+ * file: board/udoo/udoo_neo/udoo_neo.cfg
+ */
+
+loadaddr 0x80000000
+soc imx6
+dcdofs 0x400
+
+/* Enable all clocks */
+wm 32 0x020c4068 0xffffffff
+wm 32 0x020c406c 0xffffffff
+wm 32 0x020c4070 0xffffffff
+wm 32 0x020c4074 0xffffffff
+wm 32 0x020c4078 0xffffffff
+wm 32 0x020c407c 0xffffffff
+wm 32 0x020c4080 0xffffffff
+wm 32 0x020c4084 0xffffffff
+/********************************************/
+
+/* IOMUX */
+/* DDR IO TYPE */
+wm 32 0x020e0618 0x000c0000
+wm 32 0x020e05fc 0x00000000
+/********************************************/
+
+/* CLOCK */
+wm 32 0x020e032c 0x00000030
+/********************************************/
+
+/* ADDRESS */
+wm 32 0x020e0300 0x00000020
+wm 32 0x020e02fc 0x00000020
+wm 32 0x020e05f4 0x00000020
+/********************************************/
+
+/* CONTROL */
+wm 32 0x020e0340 0x00000020
+
+wm 32 0x020e0320 0x00000000
+wm 32 0x020e0310 0x00000020
+wm 32 0x020e0314 0x00000020
+wm 32 0x020e0614 0x00000020
+/********************************************/
+
+/* DATA STROBE */
+wm 32 0x020e05f8 0x00020000
+wm 32 0x020e0330 0x00000028
+wm 32 0x020e0334 0x00000028
+wm 32 0x020e0338 0x00000028
+wm 32 0x020e033c 0x00000028
+/********************************************/
+
+/* DATA */
+wm 32 0x020e0608 0x00020000
+wm 32 0x020e060c 0x00000028
+wm 32 0x020e0610 0x00000028
+wm 32 0x020e061c 0x00000028
+wm 32 0x020e0620 0x00000028
+wm 32 0x020e02ec 0x00000028
+wm 32 0x020e02f0 0x00000028
+wm 32 0x020e02f4 0x00000028
+wm 32 0x020e02f8 0x00000028
+/********************************************/
+
+/* Calibrations */
+/* ZQ */
+wm 32 0x021b0800 0xa1390003
+/********************************************/
+
+/* write leveling */
+wm 32 0x021b080c 0x000E000B
+wm 32 0x021b0810 0x000E0010
+/********************************************/
+
+/* DQS Read Gate */
+wm 32 0x021b083c 0x41600158
+wm 32 0x021b0840 0x01500140
+/********************************************/
+
+/* Read/Write Delay */
+wm 32 0x021b0848 0x3A383E3E
+wm 32 0x021b0850 0x3A383C38
+/********************************************/
+
+/* read data bit delay */
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+/********************************************/
+
+/* Complete calibration by forced measurment */
+wm 32 0x021b08b8 0x00000800
+/********************************************/
+
+/* MMDC init */
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
+wm 32 0x021b0004 0x0002002d
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b000c 0x676b52f3
+wm 32 0x021b0010 0xb66d8b63
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b0018 0x00011740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x006b1023
+wm 32 0x021b0040 0x0000005f
+wm 32 0x021b0000 0x83190000
+/********************************************/
+
+/* Initialize MT41K256M16HA-125 */
+/* MR2 */
+wm 32 0x021b001c 0x04008032
+/* MR3 */
+wm 32 0x021b001c 0x00008033
+/* MR1 */
+wm 32 0x021b001c 0x00048031
+/* MR0 */
+wm 32 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+wm 32 0x021b001c 0x04008040
+/********************************************/
+
+/* final DDR setup, before operation start */
+wm 32 0x021b0020 0x00000800
+wm 32 0x021b0818 0x00011117
+wm 32 0x021b001c 0x00000000
+/********************************************/