diff options
Diffstat (limited to 'arch/arm/boards')
1094 files changed, 40566 insertions, 17478 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 6cb40d084b..98eab17af2 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -1,8 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + # keep sorted by CONFIG_* macro name. obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/ obj-$(CONFIG_MACH_AFI_GF) += afi-gf/ obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/ obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/ +obj-$(CONFIG_MACH_AT91RM9200EK) += at91rm9200ek/ obj-$(CONFIG_MACH_AT91SAM9260EK) += at91sam9260ek/ obj-$(CONFIG_MACH_AT91SAM9261EK) += at91sam9261ek/ obj-$(CONFIG_MACH_AT91SAM9263EK) += at91sam9263ek/ @@ -14,9 +17,12 @@ obj-$(CONFIG_MACH_AT91SAM9N12EK) += at91sam9n12ek/ obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ +obj-$(CONFIG_MACH_BEAGLEPLAY) += beagleplay/ +obj-$(CONFIG_MACH_CALAO) += calao/ obj-$(CONFIG_MACH_CANON_A1100) += canon-a1100/ obj-$(CONFIG_MACH_CM_FX6) += cm-fx6/ obj-$(CONFIG_MACH_NITROGEN6) += boundarydevices-nitrogen6/ +obj-$(CONFIG_MACH_NOVENA) += novena/ obj-$(CONFIG_MACH_CCMX51) += ccxmx51/ obj-$(CONFIG_MACH_CCMX53) += ccxmx53/ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ @@ -38,33 +44,25 @@ obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += efika-mx-smartbook/ obj-$(CONFIG_MACH_EMBEDSKY_E9) += embedsky-e9/ obj-$(CONFIG_MACH_EMBEST_MARSBOARD) += embest-marsboard/ obj-$(CONFIG_MACH_EMBEST_RIOTBOARD) += embest-riotboard/ -obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += eukrea_cpuimx25/ -obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27/ -obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += eukrea_cpuimx35/ -obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += eukrea_cpuimx51/ obj-$(CONFIG_MACH_ELTEC_HIPERCAM) += eltec-hipercam/ -obj-$(CONFIG_MACH_FREESCALE_MX25_3STACK) += freescale-mx25-3ds/ -obj-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += freescale-mx35-3ds/ obj-y += freescale-mx51-babbage/ obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += freescale-mx53-qsb/ -obj-$(CONFIG_MACH_FREESCALE_MX53_SMD) += freescale-mx53-smd/ obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/ obj-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += freescale-mx7-sabresd/ +obj-$(CONFIG_MACH_MEERKAT96) += meerkat96/ obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/ obj-$(CONFIG_MACH_GK802) += gk802/ obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += globalscale-guruplug/ obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox/ obj-$(CONFIG_MACH_GRINN_LITEBOARD) += grinn-liteboard/ -obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/ obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/ obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/ obj-$(CONFIG_MACH_GW_VENTANA) += gateworks-ventana/ obj-$(CONFIG_MACH_HABA_KNX_LITE) += haba-knx/ -obj-$(CONFIG_MACH_HIGHBANK) += highbank/ -obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ -obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/ -obj-$(CONFIG_MACH_KINDLE3) += kindle3/ +obj-$(CONFIG_MACH_INNOCOMM_WB15) += innocomm-imx8mm-wb15/ +obj-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += kamstrup-mx7-concentrator/ +obj-$(CONFIG_MACH_KARO_QSXP_ML81) += karo-qsxp-ml81/ obj-$(CONFIG_MACH_KONTRON_SAMX6I) += kontron-samx6i/ obj-$(CONFIG_MACH_LENOVO_IX4_300D) += lenovo-ix4-300d/ obj-$(CONFIG_MACH_LUBBOCK) += lubbock/ @@ -75,8 +73,7 @@ obj-$(CONFIG_MACH_MB7707) += module-mb7707/ obj-$(CONFIG_MACH_MIOA701) += mioa701/ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/ -obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard/ -obj-$(CONFIG_MACH_NESO) += guf-neso/ +obj-$(CONFIG_MACH_MYIRTECH_X335X) += myirtech-x335x/ obj-$(CONFIG_MACH_NETGEAR_RN104) += netgear-rn104/ obj-$(CONFIG_MACH_NETGEAR_RN2120) += netgear-rn2120/ obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/ @@ -84,25 +81,36 @@ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/ obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/ obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/ obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += nxp-imx8mq-evk/ +obj-$(CONFIG_MACH_NXP_IMX8MM_EVK) += nxp-imx8mm-evk/ +obj-$(CONFIG_MACH_NXP_IMX8MN_EVK) += nxp-imx8mn-evk/ +obj-$(CONFIG_MACH_NXP_IMX8MP_EVK) += nxp-imx8mp-evk/ +obj-$(CONFIG_MACH_CONGATEC_QMX8P_SOM) += congatec-qmx8p/ +obj-$(CONFIG_MACH_TQ_MBA8MPXL) += tqma8mpxl/ obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/ obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/ obj-$(CONFIG_MACH_PANDA) += panda/ obj-$(CONFIG_MACH_PCA100) += phytec-phycard-imx27/ obj-$(CONFIG_MACH_PCAAL1) += phytec-phycard-omap3/ obj-$(CONFIG_MACH_PCAAXL2) += phytec-phycard-omap4/ -obj-$(CONFIG_MACH_PCM037) += phytec-phycore-imx31/ +obj-$(CONFIG_MACH_PCM027) += phytec-phycore-pxa270/ obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/ -obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/ obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/ obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/ +obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += phytec-phycore-stm32mp1/ +obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += phytec-som-imx8mm/ obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += phytec-som-imx8mq/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ obj-$(CONFIG_MACH_PM9263) += pm9263/ obj-$(CONFIG_MACH_PM9G45) += pm9g45/ +obj-$(CONFIG_MACH_POLYHEX_DEBIX) += polyhex-debix/ +obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/ +obj-$(CONFIG_MACH_PROTONIC_IMX8M) += protonic-imx8m/ +obj-$(CONFIG_MACH_PROTONIC_MECSBC) += protonic-mecsbc/ +obj-$(CONFIG_MACH_PROTONIC_STM32MP1) += protonic-stm32mp1/ obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/ obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/ obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/ @@ -111,22 +119,34 @@ obj-$(CONFIG_MACH_REALQ7) += datamodul-edm-qmx6/ obj-$(CONFIG_MACH_RPI_COMMON) += raspberry-pi/ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/ obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/ +obj-$(CONFIG_MACH_AC_SXB) += ac-sxb/ +obj-$(CONFIG_MACH_SKOV_IMX6) += skov-imx6/ +obj-$(CONFIG_MACH_SKOV_IMX8MP) += skov-imx8mp/ obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += freescale-mx6sx-sabresdb/ +obj-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += sama5d27-giantboard/ obj-$(CONFIG_MACH_SAMA5D27_SOM1) += sama5d27-som1/ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/ obj-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += microchip-ksz9477-evb/ +obj-$(CONFIG_MACH_MICROCHIP_SAMA5D3_EDS) += microchip-sama5d3-eds/ obj-$(CONFIG_MACH_SAMA5D4_XPLAINED) += sama5d4_xplained/ +obj-$(CONFIG_MACH_SAMA5D4_WIFX) += sama5d4_wifx/ obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ +obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ +obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += enclustra-aa1/ obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ +obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += terasic-de10-nano/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ -obj-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2/ +obj-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp15xx-dkx/ +obj-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp13xx-dk/ +obj-$(CONFIG_MACH_LXA_MC1) += lxa-mc1/ +obj-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp15x-ev1/ obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ @@ -136,11 +156,11 @@ obj-$(CONFIG_MACH_KINDLE_MX50) += kindle-mx50/ obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += toradex-colibri-t20/ obj-$(CONFIG_MACH_TOSHIBA_AC100) += toshiba-ac100/ obj-$(CONFIG_MACH_TQMA53) += tqma53/ +obj-$(CONFIG_MACH_TQMA6UL) += tqma6ulx/ obj-$(CONFIG_MACH_TQMA6X) += tqma6x/ obj-$(CONFIG_MACH_TURRIS_OMNIA) += turris-omnia/ obj-$(CONFIG_MACH_TX25) += karo-tx25/ obj-$(CONFIG_MACH_TX28) += karo-tx28/ -obj-$(CONFIG_MACH_TX51) += karo-tx51/ obj-$(CONFIG_MACH_TX53) += karo-tx53/ obj-$(CONFIG_MACH_TX6X) += karo-tx6x/ obj-$(CONFIG_MACH_UDOO) += udoo/ @@ -155,11 +175,14 @@ obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/ obj-$(CONFIG_MACH_ZEDBOARD) += avnet-zedboard/ obj-$(CONFIG_MACH_ZYLONITE) += zylonite/ obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/ +obj-$(CONFIG_MACH_VARISCITE_SOM_MX7) += variscite-som-mx7/ obj-$(CONFIG_MACH_VSCOM_BALTOS) += vscom-baltos/ -obj-$(CONFIG_MACH_QEMU_VIRT64) += qemu-virt64/ obj-$(CONFIG_MACH_WARP7) += element14-warp7/ +obj-$(CONFIG_MACH_WEBASTO_CCBV2) += webasto-ccbv2/ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ +obj-$(CONFIG_MACH_XILINX_ZCU102) += xilinx-zcu102/ obj-$(CONFIG_MACH_XILINX_ZCU104) += xilinx-zcu104/ +obj-$(CONFIG_MACH_XILINX_ZCU106) += xilinx-zcu106/ obj-$(CONFIG_MACH_ZII_COMMON) += zii-common/ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/ obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/ @@ -167,5 +190,18 @@ obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += zii-imx8mq-dev/ obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/ obj-$(CONFIG_MACH_ZII_IMX7D_DEV) += zii-imx7d-dev/ obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/ +obj-$(CONFIG_MACH_LS1028ARDB) += ls1028ardb/ obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/ obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/ +obj-$(CONFIG_MACH_LS1021AIOT) += ls1021aiot/ +obj-$(CONFIG_MACH_MNT_REFORM) += mnt-reform/ +obj-$(CONFIG_MACH_SKOV_ARM9CPU) += skov-arm9cpu/ +obj-$(CONFIG_MACH_RK3568_EVB) += rockchip-rk3568-evb/ +obj-$(CONFIG_MACH_RK3568_BPI_R2PRO) += rockchip-rk3568-bpi-r2pro/ +obj-$(CONFIG_MACH_PINE64_QUARTZ64) += pine64-quartz64/ +obj-$(CONFIG_MACH_RADXA_ROCK3) += radxa-rock3/ +obj-$(CONFIG_MACH_RADXA_ROCK5) += radxa-rock5/ +obj-$(CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP) += variscite-dt8mcustomboard-imx8mp/ +obj-$(CONFIG_MACH_RADXA_CM3) += radxa-cm3/ +obj-$(CONFIG_MACH_TQMA93XX) += tqma93xx/ +obj-$(CONFIG_MACH_WOLFVISION_PF5) += wolfvision-pf5/ diff --git a/arch/arm/boards/a9m2410/Makefile b/arch/arm/boards/a9m2410/Makefile deleted file mode 100644 index 4bf737c1fc..0000000000 --- a/arch/arm/boards/a9m2410/Makefile +++ /dev/null @@ -1,3 +0,0 @@ - -lwl-y += lowlevel_init.o -obj-y += a9m2410.o diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c deleted file mode 100644 index 44cf51b212..0000000000 --- a/arch/arm/boards/a9m2410/a9m2410.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <asm/sections.h> -#include <partition.h> -#include <nand.h> -#include <io.h> -#include <mach/devices-s3c24xx.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c24xx-nand.h> -#include <mach/s3c-generic.h> -#include <mach/s3c-busctl.h> -#include <mach/s3c24xx-gpio.h> - -// {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, -static struct s3c24x0_nand_platform_data nand_info = { - .nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1) -}; - -static int a9m2410_mem_init(void) -{ - resource_size_t size; - - /* - * Note: On this card the second SDRAM page is not used - */ - s3c24xx_disable_second_sdram_bank(); - size = s3c24xx_get_memory_size(); - - /* ---------- configure the GPIOs ------------- */ - writel(0x007FFFFF, S3C_GPACON); - writel(0x00000000, S3C_GPCCON); - writel(0x00000000, S3C_GPCUP); - writel(0x00000000, S3C_GPDCON); - writel(0x00000000, S3C_GPDUP); - writel(0xAAAAAAAA, S3C_GPECON); - writel(0x0000E03F, S3C_GPEUP); - writel(0x00000000, S3C_GPBCON); /* all inputs */ - writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */ - writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */ - writel(0x000000FF, S3C_GPFUP); - writel(readl(S3C_GPGDAT) | 0x0010, S3C_GPGDAT); /* switch off LCD backlight */ - writel(0xFF00A938, S3C_GPGCON); /* switch off USB device */ - writel(0x0000F000, S3C_GPGUP); - writel(readl(S3C_GPHDAT) | 0x100, S3C_GPHDAT); /* switch BOOTINT/GPIO_ON# to high */ - writel(0x000007FF, S3C_GPHUP); - writel(0x0029FAAA, S3C_GPHCON); - /* - * USB port1 normal, USB port0 normal, USB1 pads for device - * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1, - * 2nd SDRAM bank off (only bank 1 is used) - */ - writel(0x40140, S3C_MISCCR); - - arm_add_mem_device("ram0", S3C_SDRAM_BASE, size); - - return 0; -} -mem_initcall(a9m2410_mem_init); - -static const struct devfs_partition a9m2410_nand0_partitions[] = { - { - .offset = 0, - .size = 0x40000, - .flags = DEVFS_PARTITION_FIXED, - .name = "self_raw", - .bbname = "self0", - }, { - .offset = DEVFS_PARTITION_APPEND, - .size = 0x20000, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw", - .bbname = "env0", - }, { - /* sentinel */ - } -}; - -static int a9m2410_devices_init(void) -{ - uint32_t reg; - - /* ----------- configure the access to the outer space ---------- */ - reg = readl(S3C_BWSCON); - - /* CS#1 to access the network controller */ - reg &= ~0xf0; - reg |= 0xe0; - writel(0x1350, S3C_BANKCON1); - - /* CS#2 to the dual 16550 UART */ - reg &= ~0xf00; - reg |= 0x400; - writel(0x0d50, S3C_BANKCON2); - - writel(reg, S3C_BWSCON); - - /* release the reset signal to the network and UART device */ - reg = readl(S3C_MISCCR); - reg |= 0x10000; - writel(reg, S3C_MISCCR); - - /* ----------- the devices the boot loader should work with -------- */ - s3c24xx_add_nand(&nand_info); - /* - * SMSC 91C111 network controller on the baseboard - * connected to CS line 1 and interrupt line - * GPIO3, data width is 32 bit - */ - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, S3C_CS1_BASE + 0x300, - 16, IORESOURCE_MEM, NULL); - - if (IS_ENABLED(CONFIG_NAND)) - devfs_create_partitions("nand0", a9m2410_nand0_partitions); - - armlinux_set_architecture(MACH_TYPE_A9M2410); - - return 0; -} - -device_initcall(a9m2410_devices_init); - -static int a9m2410_console_init(void) -{ - barebox_set_model("Digi A9M2410"); - barebox_set_hostname("a9m2410"); - - s3c24xx_add_uart1(); - return 0; -} - -console_initcall(a9m2410_console_init); diff --git a/arch/arm/boards/a9m2410/config.h b/arch/arm/boards/a9m2410/config.h deleted file mode 100644 index 1da99eacee..0000000000 --- a/arch/arm/boards/a9m2410/config.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file - * @brief Global defintions for the ARM S3C2410 based a9m2410 CPU card - */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/** - * The external clock reference is a 12.0MHz crystal - */ -#define S3C24XX_CLOCK_REFERENCE 12000000 - -/** - * Define the main clock configuration to be used in register CLKDIVN - * - * We must limit the frequency of the connected SDRAMs with the clock ratio - * setup to 1:2:4. This will result into FCLK:HCLK:PCLK = 200Mhz:100MHz:50MHz - */ -#define BOARD_SPECIFIC_CLKDIVN 0x003 - -/** - * Define the MPLL configuration to be used in register MPLLCON - * - * We want the MPLL to run at 202.80MHz - */ -#define BOARD_SPECIFIC_MPLL ((0xA1 << 12) + (3 << 4) + 1) - -/** - * Define the UPLL configuration to be used in register UPLLCON - * - * We want the UPLL to run at 48.0MHz - */ -#define BOARD_SPECIFIC_UPLL ((0x78 << 12) + (2 << 4) + 3) - -/* - * SDRAM configuration for Samsung K4M563233E - * - 2M x 32Bit x 4 Banks Mobile SDRAM - * - 90 pin FBGA - * - CL2@100MHz - */ -/* - * SDRAM uses 32bit width - */ -#define BOARD_SPECIFIC_BWSCON ((0x02 << 24) + (0x02 << 28)) -/* - * 32MiB SDRAM in bank6 - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ -#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + 0x1) -/* - * No memory in bank7 - */ -#define BOARD_SPECIFIC_BANKCON7 ((0x3 << 15) + (0x0 << 2) + 0x1) -/* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 - */ -#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) -/* - * SDRAM banksize - * - BURST_EN = 1 (= burst mode enabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 000 (= 32MiB) - */ -#define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (0 << 4) + 0) -/* - * SDRAM mode register bank6 - * CL = 010 (= 2 clocks) - */ -#define BOARD_SPECIFIC_MRSRB6 (0x2 << 4) -/* - * SDRAM mode register bank7 - * CL = 010 (= 2 clocks) - */ -#define BOARD_SPECIFIC_MRSRB7 (0x2 << 4) - -/* - * Flash access timings - * Tacls = 0ns (but 20ns data setup time) - * Twrph0 = 25ns (write) 35ns (read) - * Twrph1 = 10ns (10ns data hold time) - * Read cycle time = 50ns - * - * Assumed HCLK is 100MHz - * Tacls = 1 (-> 20ns) - * Twrph0 = 3 (-> 40ns) - * Twrph1 = 1 (-> 20ns) - * Cycle time = 80ns - */ -#define A9M2410_TACLS 1 -#define A9M2410_TWRPH0 3 -#define A9M2410_TWRPH1 1 - -/* needed in the generic NAND boot code only */ -#ifdef CONFIG_S3C_NAND_BOOT -# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1) -#endif - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/a9m2410/env/bin/_update b/arch/arm/boards/a9m2410/env/bin/_update deleted file mode 100644 index 014bce3512..0000000000 --- a/arch/arm/boards/a9m2410/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/a9m2410/env/bin/boot b/arch/arm/boards/a9m2410/env/bin/boot deleted file mode 100644 index 59fa60e4e9..0000000000 --- a/arch/arm/boards/a9m2410/env/bin/boot +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xnand ]; then - root=nand - kernel=nand -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xnand ]; then - bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" -fi - -bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" - -if [ x$kernel = xnet ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nand0.kernel.bb -fi - diff --git a/arch/arm/boards/a9m2410/env/bin/init b/arch/arm/boards/a9m2410/env/bin/init deleted file mode 100644 index dd94ef6be0..0000000000 --- a/arch/arm/boards/a9m2410/env/bin/init +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config - -if [ -e /dev/nand0 ]; then - addpart /dev/nand0 $nand_parts -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" -fi - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [<imagename>] to update kernel into flash" - echo "type update_root [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot diff --git a/arch/arm/boards/a9m2410/env/bin/update_kernel b/arch/arm/boards/a9m2410/env/bin/update_kernel deleted file mode 100644 index c43a55785b..0000000000 --- a/arch/arm/boards/a9m2410/env/bin/update_kernel +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -. /env/config - -part=/dev/nand0.kernel.bb - -if [ x$1 = x ]; then - image=$uimage -else - image=$1 -fi - -. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2410/env/bin/update_root b/arch/arm/boards/a9m2410/env/bin/update_root deleted file mode 100644 index 34139e5dce..0000000000 --- a/arch/arm/boards/a9m2410/env/bin/update_root +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = x ]; then - image=$jffs2 -else - image=$1 -fi - -. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2410/env/config b/arch/arm/boards/a9m2410/env/config deleted file mode 100644 index 2b09318934..0000000000 --- a/arch/arm/boards/a9m2410/env/config +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'nand'' -kernel=net -root=net - -uimage=uImage-a9m2410 -jffs2=root-a9m2410.jffs2 - -autoboot_timeout=3 - -nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2410/root" -bootargs="console=ttySAC0,38400" - -nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" -rootpart_nand="/dev/mtdblock3" - -# use 'dhcp' to do dhcp in barebox and in kernel -#ip=dhcp - -# or set your networking parameters here -eth0.ipaddr=192.168.42.31 -eth0.netmask=255.255.0.0 -eth0.gateway=192.168.23.1 -eth0.serverip=192.168.23.2 -#eth0.ethaddr= diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S deleted file mode 100644 index b772b1f7f0..0000000000 --- a/arch/arm/boards/a9m2410/lowlevel_init.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * - */ - -#include <config.h> -#include <linux/sizes.h> -#include <mach/s3c-iomap.h> -#include <asm/barebox-arm-head.h> - - .section ".text_bare_init.barebox_arm_reset_vector","ax" - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - - bl s3c24x0_disable_wd - - /* skip everything here if we are already running from SDRAM */ - cmp pc, #S3C_SDRAM_BASE - blo 1f - cmp pc, #S3C_SDRAM_END - bhs 1f - - b out - -/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ -1: - bl s3c24x0_pll_init - - bl s3c24x0_sdram_init - -#ifdef CONFIG_S3C_NAND_BOOT -/* up to here we are running from the internal SRAM area */ - bl s3c24x0_nand_boot -#endif -out: - mov r0, #S3C_SDRAM_BASE - mov r1, #SZ_32M - mov r2, #0 - b barebox_arm_entry diff --git a/arch/arm/boards/a9m2440/Makefile b/arch/arm/boards/a9m2440/Makefile deleted file mode 100644 index f21d389c14..0000000000 --- a/arch/arm/boards/a9m2440/Makefile +++ /dev/null @@ -1,4 +0,0 @@ - -lwl-y += lowlevel_init.o -obj-y += a9m2440.o -obj-$(CONFIG_MACH_A9M2410DEV) += a9m2410dev.o diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c deleted file mode 100644 index b115c4a954..0000000000 --- a/arch/arm/boards/a9m2440/a9m2410dev.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2009 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -/** - * @file - * @brief a9m2410dev Baseboad specific initialization routines - * - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <io.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c-busctl.h> -#include <mach/s3c24xx-gpio.h> - -#include "baseboards.h" - -/** - * Initialize the CPU to be able to work with the a9m2410dev evaluation board - */ -int a9m2410dev_devices_init(void) -{ - unsigned int reg; - - /* ---------- configure the GPIOs ------------- */ - writel(0x007FFFFF, S3C_GPACON); - writel(0x00000000, S3C_GPCCON); - writel(0x00000000, S3C_GPCUP); - writel(0x00000000, S3C_GPDCON); - writel(0x00000000, S3C_GPDUP); - writel(0xAAAAAAAA, S3C_GPECON); - writel(0x0000E03F, S3C_GPEUP); - writel(0x00000000, S3C_GPBCON); /* all inputs */ - writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */ - writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */ - writel(0x000000FF, S3C_GPFUP); - writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */ - writel(0x0100A93A, S3C_GPGCON); /* switch on USB device */ - writel(0x0000F000, S3C_GPGUP); - writel(0x0029FAAA, S3C_GPHCON); - - writel((1 << 12) | (0 << 11), S3C_GPJDAT); - writel(0x0016aaaa, S3C_GPJCON); - writel(~((0<<12)| (1<<11)), S3C_GPJUP); - - writel((0 << 12) | (0 << 11), S3C_GPJDAT); - writel(0x0016aaaa, S3C_GPJCON); - writel(0x00001fff, S3C_GPJUP); - - writel(0x00000000, S3C_DSC0); - writel(0x00000000, S3C_DSC1); - - /* - * USB port1 normal, USB port0 normal, USB1 pads for device - * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1, - */ - writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR); - - /* ----------- configure the access to the outer space ---------- */ - reg = readl(S3C_BWSCON); - - /* CS#1 to access the network controller */ - reg &= ~0xf0; - reg |= 0xe0; - writel(0x1350, S3C_BANKCON1); - - /* CS#2 to the dual 16550 UART */ - reg &= ~0xf00; - reg |= 0x400; - writel(0x0d50, S3C_BANKCON2); - - writel(reg, S3C_BWSCON); - - /* release the reset signal to the network and UART device */ - reg = readl(S3C_MISCCR); - reg |= 0x10000; - writel(reg, S3C_MISCCR); - - return 0; -} diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c deleted file mode 100644 index 587baf6cfd..0000000000 --- a/arch/arm/boards/a9m2440/a9m2440.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) 2009 Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <nand.h> -#include <io.h> -#include <mach/devices-s3c24xx.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c24xx-nand.h> -#include <mach/s3c-generic.h> -#include <mach/s3c-busctl.h> -#include <mach/s3c24xx-gpio.h> - -#include "baseboards.h" - -static struct s3c24x0_nand_platform_data nand_info = { - .nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) -}; - -static int a9m2440_check_for_ram(uint32_t addr) -{ - uint32_t tmp1, tmp2; - int rc = 0; - - tmp1 = readl(addr); - tmp2 = readl(addr + sizeof(uint32_t)); - - writel(0xaaaaaaaa, addr); - writel(0x55555555, addr + sizeof(uint32_t)); - if ((readl(addr) != 0xaaaaaaaa) || (readl(addr + sizeof(uint32_t)) != 0x55555555)) - rc = 1; /* seems no RAM */ - - writel(0x55555555, addr); - writel(0xaaaaaaaa, addr + sizeof(uint32_t)); - if ((readl(addr) != 0x55555555) || (readl(addr + sizeof(uint32_t)) != 0xaaaaaaaa)) - rc = 1; /* seems no RAM */ - - writel(tmp1, addr); - writel(tmp2, addr + sizeof(uint32_t)); - - return rc; -} - -static int a9m2440_mem_init(void) -{ - /* - * The special SDRAM setup code for this machine will always enable - * both SDRAM banks. But the second SDRAM device may not exists! - * So we must check here, if the second bank is populated to get the - * correct RAM size. - */ - switch (readl(S3C_BANKSIZE) & 0x7) { - case 0: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - case 1: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - case 2: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - case 4: - case 5: - case 6: /* not supported on this machine */ - break; - default: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - } - - arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size()); - - return 0; -} -mem_initcall(a9m2440_mem_init); - -static int a9m2440_devices_init(void) -{ - uint32_t reg; - - /* ----------- configure the access to the outer space ---------- */ - reg = readl(S3C_BWSCON); - - /* CS#5 to access the network controller */ - reg &= ~0x00f00000; - reg |= 0x00d00000; /* 16 bit */ - writel(0x1f4c, S3C_BANKCON5); - - writel(reg, S3C_BWSCON); - -#ifdef CONFIG_MACH_A9M2410DEV - a9m2410dev_devices_init(); -#endif - - /* release the reset signal to external devices */ - reg = readl(S3C_MISCCR); - reg |= 0x10000; - writel(reg, S3C_MISCCR); - - /* ----------- the devices the boot loader should work with -------- */ - s3c24xx_add_nand(&nand_info); - /* - * cs8900 network controller onboard - * Connected to CS line 5 + A24 and interrupt line EINT9, - * data width is 16 bit - */ - add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, - S3C_CS5_BASE + (1 << 24) + 0x300, 16, IORESOURCE_MEM, NULL); - -#ifdef CONFIG_NAND - /* ----------- add some vital partitions -------- */ - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - armlinux_set_architecture(MACH_TYPE_A9M2440); - - return 0; -} - -device_initcall(a9m2440_devices_init); - -static int a9m2440_console_init(void) -{ - barebox_set_model("Digi A9M2440"); - barebox_set_hostname("a9m2440"); - - s3c24xx_add_uart1(); - return 0; -} - -console_initcall(a9m2440_console_init); diff --git a/arch/arm/boards/a9m2440/baseboards.h b/arch/arm/boards/a9m2440/baseboards.h deleted file mode 100644 index f963edf1bc..0000000000 --- a/arch/arm/boards/a9m2440/baseboards.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2009 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#ifdef CONFIG_MACH_A9M2410DEV -extern int a9m2410dev_devices_init(void); -#endif diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h deleted file mode 100644 index 71d1225d18..0000000000 --- a/arch/arm/boards/a9m2440/config.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card - */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/** - * The external clock reference is a 16.9344 MHz crystal - */ -#define S3C24XX_CLOCK_REFERENCE 16934400 - -/** - * Define the main clock configuration to be used in register CLKDIVN - * - * We must limit the frequency of the connected SDRAMs with the clock ratio - * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz - */ -#define BOARD_SPECIFIC_CLKDIVN 0x05 - -/** - * Define the MPLL configuration to be used in register MPLLCON - * - * We want the MPLL to run at 399.65 MHz - */ -#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1) - -/** - * Define the UPLL configuration to be used in register UPLLCON - * - * We want the UPLL to run at 47.98 MHz - */ -#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2) - -/* - * Flash access timings - * Tacls = 0ns (but 20ns data setup time) - * Twrph0 = 25ns (write) 35ns (read) - * Twrph1 = 10ns (10ns data hold time) - * Read cycle time = 50ns - * - * Assumed HCLK is 100MHz - * Tacls = 1 (-> 20ns) - * Twrph0 = 3 (-> 40ns) - * Twrph1 = 1 (-> 20ns) - * Cycle time = 80ns - */ -#define A9M2440_TACLS 1 -#define A9M2440_TWRPH0 3 -#define A9M2440_TWRPH1 1 - -/* needed in the generic NAND boot code only */ -#ifdef CONFIG_S3C_NAND_BOOT -# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) -#endif - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/a9m2440/env/bin/_update b/arch/arm/boards/a9m2440/env/bin/_update deleted file mode 100644 index b10682ece4..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/_update +++ /dev/null @@ -1,34 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/a9m2440/env/bin/boot b/arch/arm/boards/a9m2440/env/bin/boot deleted file mode 100644 index 86e22cf9ff..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/boot +++ /dev/null @@ -1,40 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xnand ]; then - root=nand - kernel=nand -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$root = xnand ]; then - bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" -fi -if [ x$root = xnet ]; then - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" - if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" - else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" - fi -fi - -bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" - -bootargs="$bootargs cs89x0_media=rj45 cs89x0_mac=$eth0.ethaddr" - -if [ x$kernel = xnet ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nand0.kernel.bb -fi - diff --git a/arch/arm/boards/a9m2440/env/bin/init b/arch/arm/boards/a9m2440/env/bin/init deleted file mode 100644 index dd94ef6be0..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/init +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config - -if [ -e /dev/nand0 ]; then - addpart /dev/nand0 $nand_parts -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" -fi - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [<imagename>] to update kernel into flash" - echo "type update_root [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot diff --git a/arch/arm/boards/a9m2440/env/bin/update_kernel b/arch/arm/boards/a9m2440/env/bin/update_kernel deleted file mode 100644 index c43a55785b..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/update_kernel +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -. /env/config - -part=/dev/nand0.kernel.bb - -if [ x$1 = x ]; then - image=$uimage -else - image=$1 -fi - -. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2440/env/bin/update_root b/arch/arm/boards/a9m2440/env/bin/update_root deleted file mode 100644 index 46cbca5beb..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/update_root +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -. /env/config - -part=/dev/nand0.root.bb - -if [ x$1 = x ]; then - image=$jffs2 -else - image=$1 -fi - -. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2440/env/config b/arch/arm/boards/a9m2440/env/config deleted file mode 100644 index d1fb01b731..0000000000 --- a/arch/arm/boards/a9m2440/env/config +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'nand'' -kernel=net -root=net - -uimage=uImage-a9m2440 -jffs2=root-a9m2440.jffs2 - -autoboot_timeout=3 - -nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2440/root" -bootargs="console=ttySAC0,38400" - -nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" -rootpart_nand="/dev/mtdblock3" - -# use 'dhcp' to do dhcp in barebox and in kernel -#ip=dhcp - -# or set your networking parameters here -eth0.ipaddr=192.168.42.32 -eth0.netmask=255.255.0.0 -eth0.gateway=192.168.23.1 -eth0.serverip=192.168.23.2 -#eth0.ethaddr= diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S deleted file mode 100644 index 2c51e05806..0000000000 --- a/arch/arm/boards/a9m2440/lowlevel_init.S +++ /dev/null @@ -1,245 +0,0 @@ -/* - * - */ - -#include <config.h> -#include <linux/sizes.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c24xx-gpio.h> -#include <asm/barebox-arm-head.h> - - .section ".text_bare_init.barebox_arm_reset_vector","ax" - -/* - * To be able to setup the SDRAM interface correctly, we need some - * external information about the connected SDRAM devices. - * - * When we set GPH8, we can read at GPB: - * Bit 0..1: Memory device size -> 00=16M, 01=64M, 10=32M, 11=128M - * Bit 2: CL setting - * - * Some remarks: The CL setting seems useless. It always signals a CL3 - * requirement, but the SDRAM types I found on the cards are supporting - * CL2 @ 100 MHz. But also these SDRAM types are only support 105 MHz max. - * So, we never need CL3 because we can't run the CPU at 533 MHz (which - * implies an 133 MHz SDRAM clock). - * All devices are connected via 32 bit databus - * - * Note: I was able to check the 32 MiB and 64 MiB configuration only. I didn't - * had access to a 16 MiB nor 128 MiB config. - * - */ - -sdram_init: - /* - * Read the configuration. After reset until any GPIO port is - * configured yet, these pins show external settings, to detect - * the SDRAM size. - */ - ldr r1, =S3C_GPBDAT - ldr r4, [r1] - and r4, r4, #0x3 - - ldr r1, =S3C_MEMCTL_BASE - /* configure both SDRAM areas with 32 bit data bus width */ - ldr r0, =((0x2 << 24) + (0x2 << 28)) - str r0, [r1], #0x1c /* post add register offset for bank6 */ - - /* - * With the configuration we simply need to calculate an offset into - * our table with the predefined SDRAM settings - */ - adr r0, SDRAMDATA - mov r2, #6*4 /* # of bytes per table entry */ - mul r3, r4, r2 - add r0, r0, r3 /* start address of the entry */ - - /* - * store the table entry data into the registers - */ -1: - ldr r3, [r0], #4 - str r3, [r1], #4 - subs r2, r2, #4 - bne 1b - -/* TODO: Check if the second bank is populated, and switch it off if not */ - - mov pc, lr - -/* - * we need 4 sets of memory settings per main CPU clock speed - * - * 400MHz main speed: - * - 16 MiB in the first bank, maybe 16 MiB in the second bank (untested!) - * - 32 MiB in the first bank, maybe 32 MiB in the second bank (CL=2) - * - 64 MiB in the first bank, maybe 64 MiB in the second bank (CL=2) - * - 128 MiB in the first bank, maybe 128 MiB in the second bank (untested!) - * - * Note: SDRAM clock runs at 100MHz - */ - -SDRAMDATA: -/* --------------------------- 16 MiB @ 100MHz --------------------------- */ - /* - * - MT = 11 (= sync dram type) - * - Trcd = 01 (= CL3) - * - SCAN = 00 (= 8 bit columns) - */ - .word ((0x3 << 15) + (0x1 << 2) + (0x0)) - .word ((0x3 << 15) + (0x1 << 2) + (0x0)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 11 (= 7 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = FIXME - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x3 << 18) + 468) - /* - * SDRAM banksize - * - BURST_EN = 0 (= burst mode disabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 010 (= 128MiB) FIXME????? - */ - .word ((0 << 7) + (1 << 5) + (1 << 4) + 2) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------- one or two banks with 64 MiB @ 100MHz -------------------- */ - - /* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) - /* - * SDRAM banksize - * - BURST_EN = 1 (= burst mode enabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 001 (= 64 MiB) - */ - .word ((1 << 7) + (1 << 5) + (1 << 4) + 1) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------- one or two banks with 32 MiB @ 100MHz -------------------- */ - - /* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) - /* - * SDRAM banksize - * - BURST_EN = 1 (= burst mode enabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 000 (= 32 MiB) - */ - .word ((1 << 7) + (1 << 5) + (1 << 4) + 0) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------ one or two banks with 128 MiB @ 100MHz -------------------- */ - - /* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 7.5 = 2049 - FIXME = 1259 - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x1 << 20) + (0x3 << 18) + 1259) - /* - * SDRAM banksize - * - BURST_EN = 0 (= burst mode disabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 010 (= 128MiB) - */ - .word (0x32) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------------------------------------------------------------------ */ - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - - bl s3c24x0_disable_wd - - /* skip everything here if we are already running from SDRAM */ - cmp pc, #S3C_SDRAM_BASE - blo 1f - cmp pc, #S3C_SDRAM_END - bhs 1f - - b out - -/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ -1: - bl s3c24x0_pll_init - - bl sdram_init - -#ifdef CONFIG_S3C_NAND_BOOT -/* up to here we are running from the internal SRAM area */ - bl s3c24x0_nand_boot -#endif -out: - mov r0, #S3C_SDRAM_BASE - mov r1, #SZ_32M - mov r2, #0 - b barebox_arm_entry diff --git a/arch/arm/boards/ac-sxb/Makefile b/arch/arm/boards/ac-sxb/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/ac-sxb/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/ac-sxb/board.c b/arch/arm/boards/ac-sxb/board.c new file mode 100644 index 0000000000..d631bb543a --- /dev/null +++ b/arch/arm/boards/ac-sxb/board.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +#include <common.h> +#include <init.h> +#include <mach/imx/bbu.h> + +static int sxb_coredevices_init(void) +{ + if (!of_machine_is_compatible("ac,imx7d-sxb")) + return 0; + + imx7_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", 0); + + return 0; +} +coredevice_initcall(sxb_coredevices_init); diff --git a/arch/arm/boards/ac-sxb/flash-header-mx7d-lpddr2.imxcfg b/arch/arm/boards/ac-sxb/flash-header-mx7d-lpddr2.imxcfg new file mode 100644 index 0000000000..0b99f86d8b --- /dev/null +++ b/arch/arm/boards/ac-sxb/flash-header-mx7d-lpddr2.imxcfg @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +soc imx7 +loadaddr 0x00910000 +max_load_size 0x10000 +ivtofs 0x400 diff --git a/arch/arm/boards/ac-sxb/lowlevel.c b/arch/arm/boards/ac-sxb/lowlevel.c new file mode 100644 index 0000000000..713d8ce5f8 --- /dev/null +++ b/arch/arm/boards/ac-sxb/lowlevel.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright (C) 2017 Atlas Copco Industrial Technique + */ + +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <io.h> +#include <common.h> +#include <linux/sizes.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx/imx7-ccm-regs.h> +#include <mach/imx/iomux-mx7.h> +#include <mach/imx/debug_ll.h> +#include <asm/cache.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/xload.h> +#include <mach/imx/imx7-ddr-regs.h> + +struct reginit { + u32 address; + u32 value; +}; + +static const struct reginit imx7d_ixb_dcd[] = { + {0x30340004, 0x4f400005}, + {0x30391000, 0x00000002}, + {MX7_DDRC_MSTR, 0x03020004}, + {MX7_DDRC_RFSHTMG, 0x00200038}, + {MX7_DDRC_MP_PCTRL_0, 0x00000001}, + {MX7_DDRC_INIT0, 0x00350001}, + {MX7_DDRC_INIT2, 0x00001105}, + {MX7_DDRC_INIT3, 0x00c20006}, + {MX7_DDRC_INIT4, 0x00020000}, + {MX7_DDRC_INIT5, 0x00110006}, + {MX7_DDRC_RANKCTL, 0x0000033f}, + {MX7_DDRC_DRAMTMG0, 0x080e110b}, + {MX7_DDRC_DRAMTMG1, 0x00020211}, + {MX7_DDRC_DRAMTMG2, 0x02040705}, + {MX7_DDRC_DRAMTMG3, 0x00504000}, + {MX7_DDRC_DRAMTMG4, 0x05010307}, + {MX7_DDRC_DRAMTMG5, 0x02020404}, + {MX7_DDRC_DRAMTMG6, 0x02020003}, + {MX7_DDRC_DRAMTMG7, 0x00000202}, + {MX7_DDRC_DRAMTMG8, 0x00000202}, + {MX7_DDRC_ZQCTL0, 0x20600018}, + {MX7_DDRC_ZQCTL1, 0x00e00100}, + {MX7_DDRC_DFITMG0, 0x02098203}, + {MX7_DDRC_DFITMG1, 0x00060303}, + {MX7_DDRC_DFIUPD0, 0x80400003}, + {MX7_DDRC_DFIUPD1, 0x00100020}, + {MX7_DDRC_DFIUPD2, 0x80100004}, + {MX7_DDRC_ADDRMAP0, 0x00000015}, + {MX7_DDRC_ADDRMAP1, 0x00080808}, + {MX7_DDRC_ADDRMAP4, 0x00000f0f}, + {MX7_DDRC_ADDRMAP5, 0x07070707}, + {MX7_DDRC_ADDRMAP6, 0x0f0f0707}, + {MX7_DDRC_ODTCFG, 0x06000600}, + {MX7_DDRC_ODTMAP, 0x00000000}, + {0x30391000, 0x00000000}, + {MX7_DDR_PHY_PHY_CON0, 0x17421640}, + {MX7_DDR_PHY_PHY_CON1, 0x10210100}, + {MX7_DDR_PHY_PHY_CON2, 0x00010000}, + {MX7_DDR_PHY_PHY_CON4, 0x00050408}, + {MX7_DDR_PHY_MDLL_CON0, 0x1010007e}, + {MX7_DDR_PHY_RODT_CON0, 0x01010000}, + {MX7_DDR_PHY_DRVDS_CON0, 0x00000d6e}, + {MX7_DDR_PHY_OFFSET_WR_CON0, 0x06060606}, + {MX7_DDR_PHY_OFFSET_RD_CON0, 0x0a0a0a0a}, + {MX7_DDR_PHY_CMD_SDLL_CON0, 0x01000008}, + {MX7_DDR_PHY_CMD_SDLL_CON0, 0x00000008}, + {MX7_DDR_PHY_LP_CON0, 0x0000000f}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e487304}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e4c7304}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e4c7306}, + {MX7_DDR_PHY_ZQ_CON0, 0x0e487304}, + {0x30384130, 0x00000000}, + {0x30340020, 0x00000178}, + {0x30384130, 0x00000002}, +}; + +static inline void write_regs(const struct reginit *initvals, int count) +{ + int i; + + for (i = 0; i < count; i++) + writel(initvals[i].value, initvals[i].address); +} + +extern char __dtb_z_ac_sxb_start[]; + +static inline void setup_uart(void) +{ + imx7_early_setup_uart_clock(1); + + imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); + + imx7_uart_setup_ll(); + + putc_ll('>'); +} + +static noinline void imx7d_sxb_sram_setup(void) +{ + int ret; + + relocate_to_current_adr(); + setup_c(); + + pr_debug("configuring ddr...\n"); + write_regs(imx7d_ixb_dcd, ARRAY_SIZE(imx7d_ixb_dcd)); + + ret = imx7_esdhc_start_image(2); + + BUG_ON(ret); +} + +ENTRY_FUNCTION(start_ac_sxb, r0, r1, r2) +{ + imx7_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + if (get_pc() < 0x80000000) + imx7d_sxb_sram_setup(); + + imx7d_barebox_entry(__dtb_z_ac_sxb_start + get_runtime_offset()); +} diff --git a/arch/arm/boards/advantech-mx6/Makefile b/arch/arm/boards/advantech-mx6/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/advantech-mx6/Makefile +++ b/arch/arm/boards/advantech-mx6/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c index 4a30a845f1..8261875d63 100644 --- a/arch/arm/boards/advantech-mx6/board.c +++ b/arch/arm/boards/advantech-mx6/board.c @@ -1,23 +1,11 @@ -/* - * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Christoph Fritz <chf.fritz@googlemail.com> #include <common.h> #include <init.h> #include <platform_data/eth-fec.h> #include <bootsource.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> static int ar8035_phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg index 996ecc708d..91a8babafd 100644 --- a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg +++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e0774 0x000C0000 wm 32 0x020e0754 0x00000000 diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c index de1d344dc1..edd5971c35 100644 --- a/arch/arm/boards/advantech-mx6/lowlevel.c +++ b/arch/arm/boards/advantech-mx6/lowlevel.c @@ -1,26 +1,15 @@ -/* - * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Christoph Fritz <chf.fritz@googlemail.com> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <image-metadata.h> -#include <mach/generic.h> -#include <mach/esdctl.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/iomux-mx6.h> #include <linux/sizes.h> static inline void setup_uart(void) diff --git a/arch/arm/boards/afi-gf/Makefile b/arch/arm/boards/afi-gf/Makefile index 399a4b8cc0..8d1041650e 100644 --- a/arch/arm/boards/afi-gf/Makefile +++ b/arch/arm/boards/afi-gf/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o bbenv-y += defaultenv-gf diff --git a/arch/arm/boards/afi-gf/board.c b/arch/arm/boards/afi-gf/board.c index 14e2603910..66288ca5b7 100644 --- a/arch/arm/boards/afi-gf/board.c +++ b/arch/arm/boards/afi-gf/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de> #include <common.h> #include <string.h> @@ -20,8 +8,8 @@ #include <envfs.h> #include <bootsource.h> #include <asm/armlinux.h> -#include <mach/bbu.h> -#include <mach/am33xx-generic.h> +#include <mach/omap/bbu.h> +#include <mach/omap/am33xx-generic.h> static int board_console_init(void) { diff --git a/arch/arm/boards/afi-gf/config.h b/arch/arm/boards/afi-gf/config.h deleted file mode 100644 index aeeda3695b..0000000000 --- a/arch/arm/boards/afi-gf/config.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c index da4a000675..5c38198a36 100644 --- a/arch/arm/boards/afi-gf/lowlevel.c +++ b/arch/arm/boards/afi-gf/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <init.h> #include <linux/sizes.h> #include <io.h> @@ -5,15 +7,17 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <linux/bitops.h> -#include <mach/am33xx-generic.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/am33xx-mux.h> -#include <mach/wdt.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/emif4.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/am33xx-mux.h> #include <debug_ll.h> +#include <mach/omap/debug_ll.h> /* AM335X EMIF Register values */ #define VTP_CTRL_READY (0x1 << 5) @@ -128,34 +132,35 @@ static void board_config_vtp(void) static void board_config_emif_ddr(void) { + const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE); u32 i; /*Program EMIF0 CFG Registers*/ - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); - __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); - __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); - __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); - __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); - - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); - - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + __raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_2); + __raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1); + __raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); + __raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2); + __raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); + __raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3); + __raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); + + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2); + + __raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL); + __raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); for (i = 0; i < 5000; i++) { } - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); - __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); + __raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL); + __raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); - __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG); + __raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2); } static void board_config_ddr(void) @@ -207,13 +212,7 @@ static noinline int gf_sram_init(void) fdt = __dtb_z_am335x_afi_gf_start; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); /* Setup the PLLs and the clocks for the peripherals */ am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200); @@ -228,7 +227,7 @@ static noinline int gf_sram_init(void) am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE); am33xx_enable_uart2_pin_mux(); - omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE); + omap_debug_ll_init(); putc_ll('>'); barebox_arm_entry(0x80000000, SZ_256M, fdt); diff --git a/arch/arm/boards/altera-socdk/Makefile b/arch/arm/boards/altera-socdk/Makefile index 8c927fe291..ea898309d7 100644 --- a/arch/arm/boards/altera-socdk/Makefile +++ b/arch/arm/boards/altera-socdk/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += lowlevel.o board.o pbl-y += lowlevel.o diff --git a/arch/arm/boards/altera-socdk/board.c b/arch/arm/boards/altera-socdk/board.c index f4b1dcd324..bf0a5664fe 100644 --- a/arch/arm/boards/altera-socdk/board.c +++ b/arch/arm/boards/altera-socdk/board.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <types.h> #include <driver.h> @@ -8,7 +10,7 @@ #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/cyclone5-regs.h> +#include <mach/socfpga/cyclone5-regs.h> static int ksz9021rn_phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/altera-socdk/config.h b/arch/arm/boards/altera-socdk/config.h deleted file mode 100644 index da84fa5f6b..0000000000 --- a/arch/arm/boards/altera-socdk/config.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing */ diff --git a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c index a199e4da1c..982bef52bf 100644 --- a/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c +++ b/arch/arm/boards/altera-socdk/iocsr_config_cyclone5.c @@ -27,9 +27,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/cyclone5-scan-manager.h> +#include <mach/socfpga/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, @@ -57,7 +57,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x000C0300, 0x10040000, @@ -115,7 +115,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x80040100, 0x00000000, @@ -149,7 +149,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, diff --git a/arch/arm/boards/altera-socdk/lowlevel.c b/arch/arm/boards/altera-socdk/lowlevel.c index 36dbc55b96..1e62ab70e7 100644 --- a/arch/arm/boards/altera-socdk/lowlevel.c +++ b/arch/arm/boards/altera-socdk/lowlevel.c @@ -1,4 +1,4 @@ -#define SECT(name) __attribute__((section("socfpga_socdk_" #name))) name +// SPDX-License-Identifier: GPL-2.0-only #include "sdram_config.h" #include "pinmux_config.c" @@ -9,7 +9,7 @@ #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" -#include <mach/lowlevel.h> +#include <mach/socfpga/lowlevel.h> SOCFPGA_C5_ENTRY(start_socfpga_socdk, socfpga_cyclone5_socdk, SZ_1G); SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_socdk_xload, SZ_1G); diff --git a/arch/arm/boards/altera-socdk/pinmux_config.c b/arch/arm/boards/altera-socdk/pinmux_config.c index 8bdaaedb80..ff784bbecf 100644 --- a/arch/arm/boards/altera-socdk/pinmux_config.c +++ b/arch/arm/boards/altera-socdk/pinmux_config.c @@ -30,7 +30,7 @@ #include <common.h> /* pin MUX configuration data */ -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c index c9011b2e21..6531383807 100644 --- a/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c +++ b/arch/arm/boards/altera-socdk/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = { +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, 0x10080431, diff --git a/arch/arm/boards/animeo_ip/Makefile b/arch/arm/boards/animeo_ip/Makefile index 61c714b45d..149c41024a 100644 --- a/arch/arm/boards/animeo_ip/Makefile +++ b/arch/arm/boards/animeo_ip/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c index 07daaf4ffd..452e005046 100644 --- a/arch/arm/boards/animeo_ip/init.c +++ b/arch/arm/boards/animeo_ip/init.c @@ -9,23 +9,23 @@ #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <linux/clk.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> #include <local_mac_address.h> static bool animeo_ip_is_buco; @@ -55,7 +55,7 @@ static int animeo_ip_get_pio_revision(int gpio, char *name) static void animeo_ip_detect_version(void) { - struct device_d *dev = NULL; + struct device *dev = NULL; char *model, *version; int val; @@ -311,7 +311,7 @@ static int animeo_ip_devices_init(void) device_initcall(animeo_ip_devices_init); -static struct device_d *usart0, *usart1; +static struct device *usart0, *usart1; static void animeo_ip_shutdown_uart(void __iomem *base) { diff --git a/arch/arm/boards/animeo_ip/lowlevel.c b/arch/arm/boards/animeo_ip/lowlevel.c index 7f52f824df..df02e834c3 100644 --- a/arch/arm/boards/animeo_ip/lowlevel.c +++ b/arch/arm/boards/animeo_ip/lowlevel.c @@ -7,14 +7,13 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_animeo_ip, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/archosg9/Makefile b/arch/arm/boards/archosg9/Makefile index a78956f4e4..790ff623f5 100644 --- a/arch/arm/boards/archosg9/Makefile +++ b/arch/arm/boards/archosg9/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o obj-$(CONFIG_ARM_BOARD_APPEND_ATAG) += archos_features.o lwl-y += lowlevel.o mux.o diff --git a/arch/arm/boards/archosg9/archos_features.c b/arch/arm/boards/archosg9/archos_features.c index 0cffac7780..8642d344a5 100644 --- a/arch/arm/boards/archosg9/archos_features.c +++ b/arch/arm/boards/archosg9/archos_features.c @@ -1,14 +1,5 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later + #include <common.h> #include <asm/setup.h> #include "archos_features.h" diff --git a/arch/arm/boards/archosg9/archos_features.h b/arch/arm/boards/archosg9/archos_features.h index 5769c6c668..f46b9e9eb8 100644 --- a/arch/arm/boards/archosg9/archos_features.h +++ b/arch/arm/boards/archosg9/archos_features.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ARCHOS_FEATURES_H #define __ARCHOS_FEATURES_H diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c index 52f7e86fbe..fbf05a4408 100644 --- a/arch/arm/boards/archosg9/board.c +++ b/arch/arm/boards/archosg9/board.c @@ -1,24 +1,14 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <clock.h> #include <init.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-devices.h> -#include <mach/omap4_rom_usb.h> -#include <mach/omap-fb.h> +#include <asm/mach-types.h> +#include <mach/omap/devices.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-devices.h> +#include <mach/omap/omap4_rom_usb.h> #include <linux/sizes.h> #include <i2c/i2c.h> #include <gpio.h> @@ -43,13 +33,17 @@ static int archosg9_console_init(void) { + int ret; + barebox_set_model("Archos G9"); barebox_set_hostname("g9"); - if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT) && - omap4_usbboot_ready()) { - add_generic_device("serial_omap4_usbboot", DEVICE_ID_DYNAMIC - , NULL, 0, 0, 0, NULL); + if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)) { + ret = omap4_usbboot_open(); + if (!ret) { + add_generic_device("serial_omap4_usbboot", DEVICE_ID_DYNAMIC + , NULL, 0, 0, 0, NULL); + } } if (IS_ENABLED(CONFIG_DRIVER_SERIAL_NS16550)) { omap44xx_add_uart1(); diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c index 2a93428462..2c3d0e1ee4 100644 --- a/arch/arm/boards/archosg9/lowlevel.c +++ b/arch/arm/boards/archosg9/lowlevel.c @@ -1,25 +1,15 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <io.h> #include <init.h> #include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-generic.h> -#include <mach/omap4-clock.h> -#include <mach/syslib.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-generic.h> +#include <mach/omap/omap4-clock.h> +#include <mach/omap/syslib.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> #include "mux.h" @@ -48,7 +38,7 @@ static noinline void archosg9_init_lowlevel(void) struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; - set_muxconf_regs(); + archosg9_set_muxconf_regs(); omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1380); diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c index e9cb3c43b0..d51ccefba4 100644 --- a/arch/arm/boards/archosg9/mux.c +++ b/arch/arm/boards/archosg9/mux.c @@ -1,21 +1,11 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <init.h> #include <io.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-clock.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-clock.h> #include "mux.h" static const struct pad_conf_entry core_padconf_array[] = { @@ -257,7 +247,8 @@ static const struct pad_conf_entry wkup_padconf_array[] = { { JTAG_TDO , IEN | PTU | M0 }, }; -void set_muxconf_regs(void){ +void archosg9_set_muxconf_regs(void) +{ omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, ARRAY_SIZE(core_padconf_array)); omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, diff --git a/arch/arm/boards/archosg9/mux.h b/arch/arm/boards/archosg9/mux.h index 97297b64bb..d4b0c9da86 100644 --- a/arch/arm/boards/archosg9/mux.h +++ b/arch/arm/boards/archosg9/mux.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _MUX_H #define _MUX_H -void set_muxconf_regs(void); +void archosg9_set_muxconf_regs(void); #endif /* _MUX_H */ diff --git a/arch/arm/boards/at91rm9200ek/Makefile b/arch/arm/boards/at91rm9200ek/Makefile index a07c06a6d9..da5c1038b2 100644 --- a/arch/arm/boards/at91rm9200ek/Makefile +++ b/arch/arm/boards/at91rm9200ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/at91rm9200ek/config.h b/arch/arm/boards/at91rm9200ek/config.h index 5f4f6fe1ae..a3a0be18ec 100644 --- a/arch/arm/boards/at91rm9200ek/config.h +++ b/arch/arm/boards/at91rm9200ek/config.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __CONFIG_H #define __CONFIG_H diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c index 2d9318575c..49a227805a 100644 --- a/arch/arm/boards/at91rm9200ek/init.c +++ b/arch/arm/boards/at91rm9200ek/init.c @@ -1,36 +1,22 @@ -/* - * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <gpio.h> #include <fcntl.h> #include <io.h> #include <envfs.h> #include <linux/sizes.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/iomux.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> #include <spi/spi.h> static struct macb_platform_data ether_pdata = { diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c index b132ccc084..f412de7d4a 100644 --- a/arch/arm/boards/at91rm9200ek/lowlevel.c +++ b/arch/arm/boards/at91rm9200ek/lowlevel.c @@ -7,21 +7,22 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> -#include <mach/at91rm9200_mc.h> -#include <mach/at91rm9200.h> -#include <mach/at91_pio.h> -#include <mach/at91_pmc.h> -#include <mach/hardware.h> +#include <mach/at91/at91rm9200_mc.h> +#include <mach/at91/at91rm9200.h> +#include <mach/at91/at91_pio.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/hardware.h> + +#include "config.h" void static inline access_sdram(void) { writel(0x00000000, AT91_CHIPSELECT_1); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_at91rm9200ek, r0, r1, r2) { u32 r; int i; diff --git a/arch/arm/boards/at91sam9260ek/Makefile b/arch/arm/boards/at91sam9260ek/Makefile index 9cc933a287..7aa83a7736 100644 --- a/arch/arm/boards/at91sam9260ek/Makefile +++ b/arch/arm/boards/at91sam9260ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c index 037f46a78d..eab3649883 100644 --- a/arch/arm/boards/at91sam9260ek/init.c +++ b/arch/arm/boards/at91sam9260ek/init.c @@ -1,31 +1,21 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> #include <envfs.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <nand.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <linux/sizes.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_rstc.h> #include <linux/clk.h> /* diff --git a/arch/arm/boards/at91sam9260ek/lowlevel.c b/arch/arm/boards/at91sam9260ek/lowlevel.c index 7f52f824df..c574e4aeb0 100644 --- a/arch/arm/boards/at91sam9260ek/lowlevel.c +++ b/arch/arm/boards/at91sam9260ek/lowlevel.c @@ -7,14 +7,24 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_at91sam9260ek, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); + + barebox_arm_entry(AT91_CHIPSELECT_1, + at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), + NULL); +} + +AT91_ENTRY_FUNCTION(start_at91sam9g20ek, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile index e7a9cde419..91e0037d6d 100644 --- a/arch/arm/boards/at91sam9261ek/Makefile +++ b/arch/arm/boards/at91sam9261ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index a469dba92e..da305fe9ed 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> @@ -20,20 +7,20 @@ #include <envfs.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91sam9_smc.h> #include <platform_data/eth-dm9000.h> #include <gpio_keys.h> #include <readkey.h> diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c index bb9b905c65..55393567ea 100644 --- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c +++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c @@ -4,10 +4,9 @@ * Under GPLv2 */ -#include <asm/barebox-arm.h> - -#include <mach/at91sam926x_board_init.h> -#include <mach/at91sam9261_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9261_matrix.h> #define MASTER_CLOCK 200 @@ -117,7 +116,16 @@ static void __bare_init at91sam9261ek_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_at91sam9261ek, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE); + + at91sam9261ek_init(); +} + +AT91_ENTRY_FUNCTION(start_at91sam9g10ek, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9263ek/Makefile b/arch/arm/boards/at91sam9263ek/Makefile index d4d5e76395..7f4c1bfac3 100644 --- a/arch/arm/boards/at91sam9263ek/Makefile +++ b/arch/arm/boards/at91sam9263ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + ifeq ($(CONFIG_OFDEVICE),) obj-y += init.o endif diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c index f7461ce041..6b618e9d00 100644 --- a/arch/arm/boards/at91sam9263ek/init.c +++ b/arch/arm/boards/at91sam9263ek/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> @@ -22,20 +8,19 @@ #include <envfs.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> #include <gpio.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/at91sam9_smc.h> static struct atmel_nand_data nand_pdata = { .ale = 21, diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c index 0bf0e0fb4e..aea772c743 100644 --- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c +++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c @@ -6,10 +6,9 @@ #include <linux/sizes.h> -#include <asm/barebox-arm.h> - -#include <mach/at91sam926x_board_init.h> -#include <mach/at91sam9263_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9263_matrix.h> #define MASTER_PLL_MUL 171 #define MASTER_PLL_DIV 14 @@ -117,7 +116,7 @@ static void __bare_init at91sam9263ek_init(void *fdt) extern char __dtb_z_at91sam9263ek_start[]; -ENTRY_FUNCTION(start_at91sam9263ek, r0, r1, r2) +AT91_ENTRY_FUNCTION(start_at91sam9263ek, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/at91sam9263ek/of_init.c b/arch/arm/boards/at91sam9263ek/of_init.c index 259287ccb5..7bdc6cc0f0 100644 --- a/arch/arm/boards/at91sam9263ek/of_init.c +++ b/arch/arm/boards/at91sam9263ek/of_init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2017 Sam Ravnborg <sam@ravnborg.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sam Ravnborg <sam@ravnborg.org> #include <common.h> #include <envfs.h> @@ -18,14 +7,17 @@ #include <gpio.h> #include <io.h> -#include <mach/at91sam9263_matrix.h> -#include <mach/at91sam9_smc.h> -#include <mach/at91_rtt.h> -#include <mach/hardware.h> -#include <mach/iomux.h> +#include <mach/at91/at91sam9263_matrix.h> +#include <mach/at91/at91sam9_smc.h> +#include <mach/at91/at91_rtt.h> +#include <mach/at91/hardware.h> +#include <mach/at91/iomux.h> static int add_smc_devices(void) { + if (!of_machine_is_compatible("atmel,at91sam9263ek")) + return 0; + add_generic_device("at91sam9-smc", 0, NULL, AT91SAM9263_BASE_SMC0, 0x200, IORESOURCE_MEM, NULL); add_generic_device("at91sam9-smc", 1, NULL, AT91SAM9263_BASE_SMC1, 0x200, diff --git a/arch/arm/boards/at91sam9m10g45ek/Makefile b/arch/arm/boards/at91sam9m10g45ek/Makefile index da011f825b..291716cbf0 100644 --- a/arch/arm/boards/at91sam9m10g45ek/Makefile +++ b/arch/arm/boards/at91sam9m10g45ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c index 2660104946..821228c2e1 100644 --- a/arch/arm/boards/at91sam9m10g45ek/init.c +++ b/arch/arm/boards/at91sam9m10g45ek/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> @@ -24,19 +10,19 @@ #include <envfs.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/iomux.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio_keys.h> #include <readkey.h> #include <spi/spi.h> diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c index 0f3a035d1d..a24b26e5cb 100644 --- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c +++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c @@ -7,13 +7,11 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_ddrsdrc.h> -#include <mach/hardware.h> -#include <mach/at91sam9_ddrsdr.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_at91sam9m10g45ek, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9m10ihd/Makefile b/arch/arm/boards/at91sam9m10ihd/Makefile index 06193007ad..8bf9a102fe 100644 --- a/arch/arm/boards/at91sam9m10ihd/Makefile +++ b/arch/arm/boards/at91sam9m10ihd/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o obj-y += hw_version.o diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.c b/arch/arm/boards/at91sam9m10ihd/hw_version.c index cab26b0ac4..0b8b7cc884 100644 --- a/arch/arm/boards/at91sam9m10ihd/hw_version.c +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <fs.h> @@ -146,7 +133,7 @@ static void at91sam9m10ihd_devices_detect_one(const char *name) struct one_wire_info info; struct board_info* binfo; struct vendor_info* vinfo; - struct device_d *dev = NULL; + struct device *dev = NULL; char str[16]; u8 vendor_id = 0; diff --git a/arch/arm/boards/at91sam9m10ihd/hw_version.h b/arch/arm/boards/at91sam9m10ihd/hw_version.h index b9133440d3..a08bbc0529 100644 --- a/arch/arm/boards/at91sam9m10ihd/hw_version.h +++ b/arch/arm/boards/at91sam9m10ihd/hw_version.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #ifndef __HW_REVISION_H__ #define __HW_REVISION_H__ diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c index 5008e0f67e..763dffb6ce 100644 --- a/arch/arm/boards/at91sam9m10ihd/init.c +++ b/arch/arm/boards/at91sam9m10ihd/init.c @@ -10,19 +10,19 @@ #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/board.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/board.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91sam9_smc.h> #include <input/qt1070.h> #include <readkey.h> #include <linux/w1-gpio.h> diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c index e07ff892cd..7eba24f3e4 100644 --- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c +++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c @@ -7,14 +7,12 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/at91sam9g45.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/at91sam9g45.h> -#include <mach/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_at91sam9m10ihd, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9n12ek/Makefile b/arch/arm/boards/at91sam9n12ek/Makefile index 458b055918..6ba8b4e38f 100644 --- a/arch/arm/boards/at91sam9n12ek/Makefile +++ b/arch/arm/boards/at91sam9n12ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index 72c6ff84ee..4503e96af9 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -1,41 +1,28 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9x5_matrix.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9x5_matrix.h> #include <input/qt1070.h> #include <readkey.h> #include <spi/spi.h> diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c index 5bc18f8fca..4b981fd49f 100644 --- a/arch/arm/boards/at91sam9n12ek/lowlevel.c +++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c @@ -7,13 +7,11 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_at91sam9n12ek, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9x5ek/Makefile b/arch/arm/boards/at91sam9x5ek/Makefile index 4939b7e17e..c6c1ad9670 100644 --- a/arch/arm/boards/at91sam9x5ek/Makefile +++ b/arch/arm/boards/at91sam9x5ek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o obj-y += hw_version.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-at91sam9x5ek diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.c b/arch/arm/boards/at91sam9x5ek/hw_version.c index f15cd3dc0c..1224f4753c 100644 --- a/arch/arm/boards/at91sam9x5ek/hw_version.c +++ b/arch/arm/boards/at91sam9x5ek/hw_version.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <init.h> @@ -162,7 +149,7 @@ static void at91sam9x5ek_devices_detect_one(const char *name) struct one_wire_info info; struct board_info* binfo; struct vendor_info* vinfo; - struct device_d *dev = NULL; + struct device *dev = NULL; char str[16]; u8 vendor_id = 0; diff --git a/arch/arm/boards/at91sam9x5ek/hw_version.h b/arch/arm/boards/at91sam9x5ek/hw_version.h index 3f3c8003d9..322ad6bc37 100644 --- a/arch/arm/boards/at91sam9x5ek/hw_version.h +++ b/arch/arm/boards/at91sam9x5ek/hw_version.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #ifndef __HW_REVISION_H__ #define __HW_REVISION_H__ diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c index 65493ebbcd..c3d0f2ce89 100644 --- a/arch/arm/boards/at91sam9x5ek/init.c +++ b/arch/arm/boards/at91sam9x5ek/init.c @@ -1,41 +1,27 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9x5_matrix.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9x5_matrix.h> #include <input/qt1070.h> #include <readkey.h> #include <linux/w1-gpio.h> diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c index c1433c8f7e..5dbac307ac 100644 --- a/arch/arm/boards/at91sam9x5ek/lowlevel.c +++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c @@ -1,15 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/barebox-arm.h> #include <io.h> #include <debug_ll.h> extern char __dtb_z_at91sam9x5ek_start[]; -ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2) +AT91_ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/avnet-zedboard/Makefile b/arch/arm/boards/avnet-zedboard/Makefile index a2c3104e6c..da63d2625f 100644 --- a/arch/arm/boards/avnet-zedboard/Makefile +++ b/arch/arm/boards/avnet-zedboard/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o -lwl-y += flash_header.o diff --git a/arch/arm/boards/avnet-zedboard/board.c b/arch/arm/boards/avnet-zedboard/board.c index 722bda302e..15332189ca 100644 --- a/arch/arm/boards/avnet-zedboard/board.c +++ b/arch/arm/boards/avnet-zedboard/board.c @@ -1,54 +1,19 @@ -/* - * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> #include <asm/armlinux.h> #include <common.h> #include <environment.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <init.h> -#include <mach/devices.h> -#include <mach/zynq7000-regs.h> +#include <mach/zynq/zynq7000-regs.h> #include <linux/sizes.h> -static int zedboard_mem_init(void) -{ - arm_add_mem_device("ram0", 0, SZ_512M); - - return 0; -} -mem_initcall(zedboard_mem_init); - -static struct macb_platform_data macb_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RGMII, - .phy_addr = 0x0, -}; - -static int zedboard_device_init(void) -{ - zynq_add_eth0(&macb_pdata); - - return 0; -} -device_initcall(zedboard_device_init); static int zedboard_console_init(void) { - barebox_set_model("Avnet ZedBoard"); barebox_set_hostname("zedboard"); - zynq_add_uart1(); - return 0; } console_initcall(zedboard_console_init); diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c b/arch/arm/boards/avnet-zedboard/flash_header.c deleted file mode 100644 index d9eb35b0d5..0000000000 --- a/arch/arm/boards/avnet-zedboard/flash_header.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm/byteorder.h> -#include <mach/zynq-flash-header.h> -#include <mach/zynq7000-regs.h> -#include <asm/barebox-arm-head.h> - -#define REG(a, v) { .addr = cpu_to_le32(a), .val = cpu_to_le32(v), } - -struct zynq_reg_entry __ps7reg_entry_section reg_entry[] = { - REG(ZYNQ_SLCR_UNLOCK, 0x0000DF0D), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_CLK_621_TRUE, 0x00000001), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_APER_CLK_CTRL, 0x01FC044D), - - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028008), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CFG, 0x000FA220), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028011), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_ARM_PLL_CTRL, 0x00028000), - - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E008), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CFG, 0x001452C0), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E011), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E010), - REG(ZYNQ_CLOCK_CTRL_BASE + ZYNQ_IO_PLL_CTRL, 0x0001E000), - - REG(0xf8000150, 0x00000a03), - - /* stop */ - REG(0xFFFFFFFF, 0x00000000), -}; - -struct zynq_flash_header __flash_header_section flash_header = { - .width_det = WIDTH_DETECTION_MAGIC, - .image_id = IMAGE_IDENTIFICATION, - .enc_stat = 0x0, - .user = 0x0, - .flash_offset = 0x8c0, - .length = (unsigned int)&_barebox_image_size, - .res0 = 0x0, - .start_of_exec = 0x0, - .total_len = (unsigned int)&_barebox_image_size, - .res1 = 0x1, - .checksum = 0x0, - .res2 = 0x0, -}; diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index cf3c4ebd0c..6e5a17d7ef 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -1,34 +1,33 @@ -/* - * - * (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + #include <common.h> #include <io.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <mach/zynq7000-regs.h> +#include <mach/zynq/init.h> +#include <mach/zynq/zynq7000-regs.h> +#include <serial/cadence.h> #define DCI_DONE (1 << 13) #define PLL_ARM_LOCK (1 << 0) #define PLL_DDR_LOCK (1 << 1) #define PLL_IO_LOCK (1 << 2) -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +extern char __dtb_z_zynq_zed_start[]; + +static void avnet_zedboard_ps7_init(void) { + /* + * Read OCM mapping configuration, if only the upper 64 KByte are + * mapped to the high address, it's very likely that we just got control + * from the BootROM. If the mapping is changed something other than the + * BootROM was running before us. Skip PS7 init to avoid cutting the + * branch we are sitting on in that case. + */ + if ((readl(0xf8000910) & 0xf) != 0x8) + return; + /* open sesame */ writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); @@ -229,13 +228,22 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) /* UART1 pinmux */ writel(0x000002E1, ZYNQ_MIO_BASE + 0xC8); writel(0x000002E0, ZYNQ_MIO_BASE + 0xCC); + /* QSPI pinmux */ + writel(0x00001602, ZYNQ_MIO_BASE + 0x04); + writel(0x00000702, ZYNQ_MIO_BASE + 0x08); + writel(0x00000702, ZYNQ_MIO_BASE + 0x0c); + writel(0x00000702, ZYNQ_MIO_BASE + 0x10); + writel(0x00000702, ZYNQ_MIO_BASE + 0x14); + writel(0x00000702, ZYNQ_MIO_BASE + 0x18); + writel(0x00000602, ZYNQ_MIO_BASE + 0x20); /* poor mans clkctrl */ writel(0x00001403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL); + writel(0x00000101, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_LQSPI_CLK_CTRL); /* GEM0 */ writel(0x00000001, 0xf8000138); - writel(0x00500801, 0xf8000140); + writel(0x00100801, 0xf8000140); writel(0x00000302, 0xf8000740); writel(0x00000302, 0xf8000744); writel(0x00000302, 0xf8000748); @@ -248,14 +256,58 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) writel(0x00001303, 0xf8000764); writel(0x00001303, 0xf8000768); writel(0x00001303, 0xf800076C); - writel(0x00001280, 0xf80007D0); - writel(0x00001280, 0xf80007D4); + writel(0x00000280, 0xf80007D0); + writel(0x00000280, 0xf80007D4); writel(0x00000001, 0xf8000B00); + /* FPGA Clock Control */ + writel(0x00101400, 0xf8000170); + writel(0x00101400, 0xf8000180); + writel(0x00101400, 0xf8000190); + writel(0x00101400, 0xf80001a0); + + /* PCAP Clock Control */ + writel(0x00000501, 0xf8000168); + /* lock up. secure, secure */ writel(0x0000767B, ZYNQ_SLCR_LOCK); +} + +static void avnet_zedboard_pbl_console_init(void) +{ + relocate_to_current_adr(); + setup_c(); + barrier(); + + cadence_uart_init((void *)ZYNQ_UART1_BASE_ADDR); + pbl_set_putc(cadence_uart_putc, (void *)ZYNQ_UART1_BASE_ADDR); + + pr_debug("\nAvnet ZedBoard PBL\n"); +} + +ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2) +{ + + void *fdt = __dtb_z_zynq_zed_start + get_runtime_offset(); + + /* MIO_07 in GPIO Mode 3.3V VIO, can be uncomented because it is the default value */ + writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); + writel(0x00000600, 0xF800071C ); + writel(0x0000767B, ZYNQ_SLCR_LOCK); + + /* turns on the LED MIO_07 */ + writel((1<<7), 0xe000a204 ); // Direction + writel((1<<7), 0xe000a208 ); // Output enable + writel((1<<7), 0xe000a040 ); // DATA Register arm_cpu_lowlevel_init(); - barebox_arm_entry(0, SZ_512M, NULL); + zynq_cpu_lowlevel_init(); + + avnet_zedboard_ps7_init(); + + if (IS_ENABLED(CONFIG_PBL_CONSOLE)) + avnet_zedboard_pbl_console_init(); + + barebox_arm_entry(0, SZ_512M, fdt); } diff --git a/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg new file mode 100644 index 0000000000..c6a96aec7b --- /dev/null +++ b/arch/arm/boards/avnet-zedboard/zedboard.zynqcfg @@ -0,0 +1,24 @@ +#include <zynq/zynq7000-header-regs.h> + +wm 32 ZYNQ_SLCR_UNLOCK 0x0000DF0D +wm 32 ZYNQ_CLK_621_TRUE 0x00000001 +wm 32 ZYNQ_APER_CLK_CTRL 0x01FC044D + +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028008 +wm 32 ZYNQ_ARM_PLL_CFG 0x000FA220 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028010 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028011 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028010 +wm 32 ZYNQ_ARM_PLL_CTRL 0x00028000 + +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E008 +wm 32 ZYNQ_IO_PLL_CFG 0x001452C0 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E010 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E011 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E010 +wm 32 ZYNQ_IO_PLL_CTRL 0x0001E000 + +wm 32 ZYNQ_SDIO_CLK_CTRL 0x00000a03 + +/* stop */ +wm 32 0xFFFFFFFF 0x00000000 diff --git a/arch/arm/boards/beagle/Makefile b/arch/arm/boards/beagle/Makefile index 3bee9a22ab..e273f4a3da 100644 --- a/arch/arm/boards/beagle/Makefile +++ b/arch/arm/boards/beagle/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-beagle diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c index 460f42ac2d..f9d7f74288 100644 --- a/arch/arm/boards/beagle/board.c +++ b/arch/arm/boards/beagle/board.c @@ -1,19 +1,5 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) #include <common.h> #include <console.h> @@ -25,14 +11,14 @@ #include <filetype.h> #include <envfs.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/gpmc.h> -#include <mach/gpmc_nand.h> -#include <mach/ehci.h> -#include <mach/omap3-devices.h> +#include <asm/mach-types.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/gpmc_nand.h> +#include <mach/omap/ehci.h> +#include <mach/omap/omap3-devices.h> #include <i2c/i2c.h> #include <linux/err.h> -#include <usb/ehci.h> +#include <linux/usb/ehci.h> #include <asm/barebox-arm.h> #ifdef CONFIG_DRIVER_SERIAL_NS16550 diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c index 30cc1f2c54..e4610722f6 100644 --- a/arch/arm/boards/beagle/lowlevel.c +++ b/arch/arm/boards/beagle/lowlevel.c @@ -1,18 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <init.h> +#include <mach/omap/debug_ll.h> #include <debug_ll.h> #include <io.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/control.h> -#include <mach/generic.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> -#include <mach/omap3-mux.h> -#include <mach/sdrc.h> -#include <mach/syslib.h> -#include <mach/sys_info.h> -#include <generated/mach-types.h> +#include <mach/omap/control.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/omap3-mux.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/syslib.h> +#include <mach/omap/sys_info.h> +#include <asm/mach-types.h> /** * @brief Do the pin muxing required for Board operation. @@ -194,7 +197,7 @@ static noinline int beagle_board_init(void) mux_config(); - omap_uart_lowlevel_init((void *)OMAP3_UART3_BASE); + omap_debug_ll_init(); /* Dont reconfigure SDRAM while running in SDRAM! */ if (!in_sdram) diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile index 21a1a29d0b..108e481be3 100644 --- a/arch/arm/boards/beaglebone/Makefile +++ b/arch/arm/boards/beaglebone/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o bbenv-y += defaultenv-beaglebone diff --git a/arch/arm/boards/beaglebone/beaglebone.h b/arch/arm/boards/beaglebone/beaglebone.h index a4f48e5b0b..c95936a84f 100644 --- a/arch/arm/boards/beaglebone/beaglebone.h +++ b/arch/arm/boards/beaglebone/beaglebone.h @@ -1,7 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __BOARD_BEAGLEBONE_H #define __BOARD_BEAGLEBONE_H -#include <mach/am33xx-generic.h> +#include <mach/omap/am33xx-generic.h> static inline int is_beaglebone_black(void) { diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c index 819bdfae46..43e2d81f38 100644 --- a/arch/arm/boards/beaglebone/board.c +++ b/arch/arm/boards/beaglebone/board.c @@ -1,20 +1,6 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de> /** * @file @@ -31,13 +17,13 @@ #include <net.h> #include <bootsource.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/am33xx-silicon.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/gpmc.h> +#include <asm/mach-types.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/gpmc.h> #include <linux/err.h> -#include <mach/bbu.h> +#include <mach/omap/bbu.h> #include "beaglebone.h" diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c index 91d143e415..5dc49dfaaf 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -1,19 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <init.h> #include <linux/sizes.h> #include <io.h> #include <linux/string.h> #include <debug_ll.h> +#include <mach/omap/debug_ll.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/am33xx-mux.h> -#include <mach/am33xx-generic.h> -#include <mach/wdt.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/am33xx-mux.h> +#include <mach/omap/am33xx-generic.h> #include "beaglebone.h" @@ -116,13 +118,7 @@ static noinline int beaglebone_sram_init(void) else sdram_size = SZ_256M; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); /* Setup the PLLs and the clocks for the peripherals */ if (is_beaglebone_black()) { @@ -137,7 +133,7 @@ static noinline int beaglebone_sram_init(void) am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); am33xx_enable_uart0_pin_mux(); - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); + omap_debug_ll_init(); putc_ll('>'); barebox_arm_entry(0x80000000, sdram_size, fdt); diff --git a/arch/arm/boards/beagleplay/Makefile b/arch/arm/boards/beagleplay/Makefile new file mode 100644 index 0000000000..69935cc168 --- /dev/null +++ b/arch/arm/boards/beagleplay/Makefile @@ -0,0 +1 @@ +pbl-y += lowlevel.o entry.o diff --git a/arch/arm/boards/beagleplay/entry.S b/arch/arm/boards/beagleplay/entry.S new file mode 100644 index 0000000000..6e4c7196f3 --- /dev/null +++ b/arch/arm/boards/beagleplay/entry.S @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> +#include <asm/image.h> + +#define IMAGE_FLAGS \ + (ARM64_IMAGE_FLAG_PAGE_SIZE_4K << ARM64_IMAGE_FLAG_PAGE_SIZE_SHIFT) | \ + (ARM64_IMAGE_FLAG_PHYS_BASE << ARM64_IMAGE_FLAG_PHYS_BASE_SHIFT) + +.section .text_head_entry_start_beagleplay +ENTRY("start_beagleplay") + adr x1, 0 /* code0 */ + b 2f /* code1 */ + .xword 0x80000 /* Image load offset */ + .xword _barebox_image_size /* Effective Image size */ + .xword IMAGE_FLAGS /* Kernel flags */ + .xword 0 /* reserved */ + .xword 0 /* reserved */ + .xword 0 /* reserved */ + .ascii ARM64_IMAGE_MAGIC /* magic number */ + .int 0 /* reserved (PE-COFF offset) */ + .asciz "barebox" /* unused for now */ +2: + mov sp, x1 + /* Stack now grows into the 0x80000 image load offset specified + * above. This is more than enough until FDT /memory is decoded. + */ + b beagleplay +ENTRY_PROC_END(start_beagleplay) diff --git a/arch/arm/boards/beagleplay/lowlevel.c b/arch/arm/boards/beagleplay/lowlevel.c new file mode 100644 index 0000000000..9d76dbd0a2 --- /dev/null +++ b/arch/arm/boards/beagleplay/lowlevel.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <pbl.h> + +/* Called from assembly */ +void beagleplay(void); + +static noinline void beagleplay_continue(void) +{ + unsigned long membase, memsize; + extern char __dtb_k3_am625_beagleplay_start[]; + + fdt_find_mem(__dtb_k3_am625_beagleplay_start, &membase, &memsize); + + barebox_arm_entry(membase, memsize, __dtb_k3_am625_beagleplay_start); +} + +void beagleplay(void) +{ + putc_ll('>'); + + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + + setup_c(); + + beagleplay_continue(); +} diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg index c5a286b4e0..65752f1790 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x128mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x00020036 wm 32 MX6_MMDC_P0_MDCFG0 0x555A7974 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg index 4d8a715150..7a72599b06 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x256mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x00020036 wm 32 MX6_MMDC_P0_MDCFG0 0x898E7974 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg index 6409b745d7..dffe480b8e 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/1066mhz_4x512mx16-qp.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2016 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Boundary Devices /* NOC setup */ wm 32 0x00bb0008 0x00000004 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg index 936a2f54bf..0be615baad 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x128mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x0002002D wm 32 MX6_MMDC_P0_MDCFG0 0x40435323 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg index 09c855544d..6d7e17027f 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/800mhz_4x256mx16.imxcfg @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices wm 32 MX6_MMDC_P0_MDPDC 0x0002002D wm 32 MX6_MMDC_P0_MDCFG0 0x696C5323 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/Makefile b/arch/arm/boards/boundarydevices-nitrogen6/Makefile index 0ec04ce898..da63d2625f 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/Makefile +++ b/arch/arm/boards/boundarydevices-nitrogen6/Makefile @@ -1,2 +1,4 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/boundarydevices-nitrogen6/board.c b/arch/arm/boards/boundarydevices-nitrogen6/board.c index d9514d9d48..a57cef4fbe 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/board.c +++ b/arch/arm/boards/boundarydevices-nitrogen6/board.c @@ -1,24 +1,13 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix #include <common.h> #include <init.h> #include <environment.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <linux/phy.h> #include <linux/micrel_phy.h> -#include <mach/imx6.h> +#include <mach/imx/imx6.h> static int nitrogen6x_devices_init(void) { diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg index 47b572db46..8aa14f3080 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> #include "ram-base.imxcfg" #include "800mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg index cf3716dbaa..5544c25e36 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> #include "ram-base.imxcfg" #include "800mhz_4x256mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg index 8ed987daa8..4cde5c0818 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> #include "ram-base.imxcfg" #include "1066mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg index e6d97d11c1..4b38b1bfc9 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> #include "ram-base.imxcfg" #include "1066mhz_4x256mx16.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg index 50bbfc5bdd..2d43222530 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> #include "ram-base.imxcfg" #include "1066mhz_4x512mx16-qp.imxcfg" diff --git a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c index 74ff71fc24..8ab5116d8e 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c +++ b/arch/arm/boards/boundarydevices-nitrogen6/lowlevel.c @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> -#include <mach/generic.h> -#include <mach/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/esdctl.h> #include <asm/barebox-arm.h> extern char __dtb_imx6q_nitrogen6x_start[]; diff --git a/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg index 5d675883fd..bf2aec5d96 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/ram-base.imxcfg @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 diff --git a/arch/arm/boards/calao/Makefile b/arch/arm/boards/calao/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/calao/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/calao/board.c b/arch/arm/boards/calao/board.c new file mode 100644 index 0000000000..cc369c4cf1 --- /dev/null +++ b/arch/arm/boards/calao/board.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <deep-probe.h> +#include <of.h> + +static const struct of_device_id calao_of_match[] = { + { .compatible = "calao,tny-a9260" }, + { .compatible = "calao,tny-a9g20" }, + { .compatible = "calao,usb-a9260" }, + { .compatible = "calao,usb-a9g20" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(calao_of_match); diff --git a/arch/arm/boards/calao/lowlevel.c b/arch/arm/boards/calao/lowlevel.c new file mode 100644 index 0000000000..2a081a97a4 --- /dev/null +++ b/arch/arm/boards/calao/lowlevel.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <init.h> +#include <debug_ll.h> +#include <asm/reloc.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> + +static void dbgu_init(void) +{ + /* pinmux/clocks/uart already configured by first stage */ + putc_ll('>'); +} + +#define CALAO_ENTRY_2ND(entrypoint, dtbname) \ +AT91_ENTRY_FUNCTION(entrypoint, r0, r1, r2) { \ + extern char __dtb_z_##dtbname##_start[]; \ + arm_cpu_lowlevel_init(); \ + arm_setup_stack(AT91SAM9260_SRAM_END); \ + dbgu_init(); \ + at91sam9260_barebox_entry(runtime_address(__dtb_z_##dtbname##_start)); \ +} + +CALAO_ENTRY_2ND(start_tny_a9260, tny_a9260); +CALAO_ENTRY_2ND(start_tny_a9g20, tny_a9g20); +CALAO_ENTRY_2ND(start_usb_a9260, usb_a9260); +CALAO_ENTRY_2ND(start_usb_a9g20, usb_a9g20); diff --git a/arch/arm/boards/canon-a1100/Makefile b/arch/arm/boards/canon-a1100/Makefile index b08c4a93ca..458f520900 100644 --- a/arch/arm/boards/canon-a1100/Makefile +++ b/arch/arm/boards/canon-a1100/Makefile @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c index b75a1bfa60..47a9564e0f 100644 --- a/arch/arm/boards/canon-a1100/lowlevel.c +++ b/arch/arm/boards/canon-a1100/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> diff --git a/arch/arm/boards/ccxmx51/Makefile b/arch/arm/boards/ccxmx51/Makefile index 50cf929c5d..9fbde144a5 100644 --- a/arch/arm/boards/ccxmx51/Makefile +++ b/arch/arm/boards/ccxmx51/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += ccxmx51.o lwl-y += lowlevel.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-ccxmx51 diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 13fba51fec..4ea71fe26b 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -16,12 +16,12 @@ #include <mfd/mc13xxx.h> #include <mfd/mc13892.h> -#include <mach/bbu.h> -#include <mach/esdctl.h> -#include <mach/iim.h> -#include <mach/imx5.h> -#include <mach/imx51-regs.h> -#include <mach/revision.h> +#include <mach/imx/bbu.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/iim.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx51-regs.h> +#include <mach/imx/revision.h> static const struct ccxmx_ident { char *id_string; @@ -31,7 +31,7 @@ static const struct ccxmx_ident { unsigned char eth1:1; unsigned char wless:1; unsigned char accel:1; -} *ccxmx_id, ccxmx51_ids[] = { +} ccxmx51_ids[] = { [0x00] = { NULL /* Unknown */, 0, 0, 0, 0, 0, 0 }, [0x01] = { NULL /* Not supported */, 0, 0, 0, 0, 0, 0 }, [0x02] = { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 800, 1, 1, 1, 1 }, @@ -52,7 +52,9 @@ static const struct ccxmx_ident { [0x11] = { "i.MX515@800MHz, PHY, Accel", SZ_128M, 800, 1, 0, 0, 1 }, [0x12] = { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 600, 1, 0, 1, 1 }, [0x13] = { "i.MX515@800MHz, PHY, Accel", SZ_512M, 800, 1, 0, 0, 1 }, -}; + [0x14] = { NULL, 0, 0, 0, 0, 0, 0 }, + [0x15] = { "i.MX515@600MHz, PHY, Accel", SZ_512M, 600, 1, 0, 0, 1 }, +}, *ccxmx_id = &ccxmx51_ids[0]; static u32 boardserial; @@ -172,7 +174,7 @@ static void ccxmx51_power_init(struct mc13xxx *mc13xxx) static void ccxmx51_disable_device(struct device_node *root, const char *label) { - struct device_node *np = of_find_node_by_name(root, label); + struct device_node *np = of_find_node_by_name_address(root, label); if (np) of_device_disable(np); } @@ -187,11 +189,15 @@ static int ccxmx51_board_fixup(struct device_node *root, void *unused) if (!ccxmx_id->eth0) ccxmx51_disable_device(root, "ethernet@83fec000"); - if (!ccxmx_id->eth1) + if (!ccxmx_id->eth1) { ccxmx51_disable_device(root, "lan9221@5,0"); + ccxmx51_disable_device(root, "ethernet@5,0"); + } - if (!ccxmx_id->wless) + if (!ccxmx_id->wless) { ccxmx51_disable_device(root, "esdhc@70008000"); + ccxmx51_disable_device(root, "mmc@70008000"); + } serial = basprintf("%08x%08x", 0, boardserial); of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1); @@ -228,18 +234,21 @@ static __init int ccxmx51_init(void) { char manloc = 'N'; u8 hwid[6]; + int ret; if (!ccxmx51_is_compatible()) return 0; - if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || - (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids))) { - printf("Unknown board variant (0x%02x). System halted.\n", hwid[0]); + ret = imx_iim_read(1, 9, hwid, sizeof(hwid)); + if ((ret == sizeof(hwid)) && (hwid[0] < ARRAY_SIZE(ccxmx51_ids))) + ccxmx_id = &ccxmx51_ids[hwid[0]]; + + if (!ccxmx_id->mem_sz) { + printf("Unknown/unsupported board variant (0x%02x).\n" + "System halted.\n", hwid[0]); hang(); } - ccxmx_id = &ccxmx51_ids[hwid[0]]; - switch (hwid[2] & 0xc0) { case 0x00: manloc = 'B'; diff --git a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg b/arch/arm/boards/ccxmx51/flash-header-x16.imxcfg index 5b51106284..6d77324fc8 100644 --- a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg +++ b/arch/arm/boards/ccxmx51/flash-header-x16.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx51 -dcdofs 0x400 loadaddr 0x90000000 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 @@ -23,8 +25,8 @@ wm 32 0x73fa882c 0x00000004 wm 32 0x73fa88a4 0x00000004 wm 32 0x73fa88ac 0x00000004 wm 32 0x73fa88b8 0x00000004 -wm 32 0x83fd9000 0x82a20000 -wm 32 0x83fd9008 0x82a20000 +wm 32 0x83fd9000 0x82a10000 +wm 32 0x83fd9008 0x82a10000 wm 32 0x83fd9010 0x000ad0d0 wm 32 0x83fd9004 0x3f3584ab wm 32 0x83fd900c 0x3f3584ab @@ -52,8 +54,8 @@ wm 32 0x83fd9014 0x0632801c wm 32 0x83fd9014 0x0380801d wm 32 0x83fd9014 0x0040801d wm 32 0x83fd9014 0x00008004 -wm 32 0x83fd9000 0xb2a20000 -wm 32 0x83fd9008 0xb2a20000 +wm 32 0x83fd9000 0xb2a10000 +wm 32 0x83fd9008 0xb2a10000 wm 32 0x83fd9010 0x000ad6d0 wm 32 0x83fd9034 0x90000000 wm 32 0x83fd9014 0x00000000 diff --git a/arch/arm/boards/ccxmx51/flash-header.imxcfg b/arch/arm/boards/ccxmx51/flash-header-x32.imxcfg index 251c4c1b9b..6480aa590e 100644 --- a/arch/arm/boards/ccxmx51/flash-header.imxcfg +++ b/arch/arm/boards/ccxmx51/flash-header-x32.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 @@ -57,4 +59,3 @@ wm 32 0x83fd9008 0xb2a20000 wm 32 0x83fd9010 0x000ad6d0 wm 32 0x83fd9034 0x90000000 wm 32 0x83fd9014 0x00000000 - diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c index adcb30a7ff..b0881f9c5b 100644 --- a/arch/arm/boards/ccxmx51/lowlevel.c +++ b/arch/arm/boards/ccxmx51/lowlevel.c @@ -2,22 +2,61 @@ /* Author: Alexander Shiyan <shc_work@mail.ru> */ #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx51.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <mach/imx51-regs.h> +#include <mach/imx/imx51-regs.h> -ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2) +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = IOMEM(MX51_IOMUXC_BASE_ADDR); + void __iomem *ccmbase = IOMEM(MX51_CCM_BASE_ADDR); + + /* + * Restore CCM values that might be changed by the Mask ROM + * code. + * + * Source: RealView debug scripts provided by Freescale + */ + writel(MX5_CCM_CBCDR_RESET_VALUE, ccmbase + MX5_CCM_CBCDR); + writel(MX5_CCM_CSCMR1_RESET_VALUE, ccmbase + MX5_CCM_CSCMR1); + writel(MX5_CCM_CSCDR1_RESET_VALUE, ccmbase + MX5_CCM_CSCDR1); + + imx_setup_pad(iomuxbase, MX51_PAD_UART1_TXD__UART1_TXD); + + imx51_uart_setup_ll(); + + putc_ll('>'); +} + +static inline void start_ccxmx51(void) { extern char __dtb_imx51_ccxmx51_start[]; void *fdt; imx5_cpu_lowlevel_init(); + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + arm_setup_stack(0x20000000); fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset(); barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, fdt); } + +ENTRY_FUNCTION(start_ccxmx51_x16, r0, r1, r2) +{ + start_ccxmx51(); +} + +ENTRY_FUNCTION(start_ccxmx51_x32, r0, r1, r2) +{ + start_ccxmx51(); +} diff --git a/arch/arm/boards/ccxmx53/Makefile b/arch/arm/boards/ccxmx53/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/ccxmx53/Makefile +++ b/arch/arm/boards/ccxmx53/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/ccxmx53/board.c b/arch/arm/boards/ccxmx53/board.c index 9d81cd80a3..26654193ad 100644 --- a/arch/arm/boards/ccxmx53/board.c +++ b/arch/arm/boards/ccxmx53/board.c @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2015 Jason Cobham <cobham.jason@gmail.com> - * - * Board specific file for the Digi ConnectCore ccxmx53 SoM - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Jason Cobham <cobham.jason@gmail.com> + +/* Board specific file for the Digi ConnectCore ccxmx53 SoM */ #include <common.h> #include <init.h> @@ -21,14 +9,14 @@ #include <i2c/i2c.h> #include <gpio.h> -#include <generated/mach-types.h> -#include <mach/imx5.h> -#include <mach/generic.h> -#include <mach/imx53-regs.h> -#include <mach/esdctl.h> +#include <asm/mach-types.h> +#include <mach/imx/imx5.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/esdctl.h> #include <asm/armlinux.h> -#include <mach/bbu.h> -#include <mach/iim.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iim.h> struct ccwmx53_ident { diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg index 68d947c01d..c049b2a10f 100644 --- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00200000 wm 32 0x53fa8558 0x00200040 wm 32 0x53fa8560 0x00200000 diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg index b707dd64a6..a6460e0333 100644 --- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00200000 wm 32 0x53fa8558 0x00200040 wm 32 0x53fa8560 0x00200000 diff --git a/arch/arm/boards/ccxmx53/lowlevel.c b/arch/arm/boards/ccxmx53/lowlevel.c index 1d2d8c6d90..74fde99337 100644 --- a/arch/arm/boards/ccxmx53/lowlevel.c +++ b/arch/arm/boards/ccxmx53/lowlevel.c @@ -1,25 +1,13 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> #include <debug_ll.h> #include <common.h> #include <linux/sizes.h> #include <io.h> -#include <mach/imx53-regs.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <image-metadata.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/chumby_falconwing/Makefile b/arch/arm/boards/chumby_falconwing/Makefile index cf92c6a9ea..6aaff6cdf7 100644 --- a/arch/arm/boards/chumby_falconwing/Makefile +++ b/arch/arm/boards/chumby_falconwing/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y = falconwing.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c index ea64fd6f47..9221590455 100644 --- a/arch/arm/boards/chumby_falconwing/falconwing.c +++ b/arch/arm/boards/chumby_falconwing/falconwing.c @@ -1,17 +1,6 @@ -/* - * (C) Copyright 2010 Juergen Beisert - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix + #include <common.h> #include <init.h> #include <gpio.h> @@ -20,18 +9,17 @@ #include <errno.h> #include <mci.h> #include <linux/sizes.h> -#include <usb/ehci.h> +#include <linux/usb/ehci.h> #include <asm/armlinux.h> #include <asm/barebox-arm.h> #include <io.h> #include <asm/mmu.h> -#include <generated/mach-types.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include <mach/mci.h> -#include <mach/fb.h> -#include <mach/usb.h> -#include <mach/iomux.h> +#include <asm/mach-types.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/mci.h> +#include <mach/mxs/fb.h> +#include <mach/mxs/usb.h> +#include <mach/mxs/iomux.h> static struct mxs_mci_platform_data mci_pdata = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED, diff --git a/arch/arm/boards/chumby_falconwing/lowlevel.c b/arch/arm/boards/chumby_falconwing/lowlevel.c index 0277b5d083..fdda6ba5f2 100644 --- a/arch/arm/boards/chumby_falconwing/lowlevel.c +++ b/arch/arm/boards/chumby_falconwing/lowlevel.c @@ -1,12 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx23-regs.h> -#include <generated/mach-types.h> +#include <mach/mxs/imx23-regs.h> +#include <asm/mach-types.h> + +static noinline void continue_imx_entry(size_t size) +{ + static struct barebox_arm_boarddata boarddata = { + .magic = BAREBOX_ARM_BOARDDATA_MAGIC, + .machine = MACH_TYPE_CHUMBY, + }; + + barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); +} ENTRY_FUNCTION(start_chumby_falconwing, r0, r1, r2) { arm_cpu_lowlevel_init(); - barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, (void *)MACH_TYPE_CHUMBY); + + relocate_to_current_adr(); + setup_c(); + + continue_imx_entry(SZ_64M); } diff --git a/arch/arm/boards/clep7212/Makefile b/arch/arm/boards/clep7212/Makefile index a5001df9b5..85d92c8a7f 100644 --- a/arch/arm/boards/clep7212/Makefile +++ b/arch/arm/boards/clep7212/Makefile @@ -1,3 +1,5 @@ -obj-y += clep7212.o +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o lwl-y += lowlevel.o -bbenv-y += defaultenv-clep7212 +bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-clep7212 diff --git a/arch/arm/boards/clep7212/board.c b/arch/arm/boards/clep7212/board.c new file mode 100644 index 0000000000..b3983f2f49 --- /dev/null +++ b/arch/arm/boards/clep7212/board.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> + +#include <envfs.h> +#include <init.h> +#include <of.h> + +static __init int clep7212_init(void) +{ + if (of_machine_is_compatible("cirrus,clep7212")) + defaultenv_append_directory(defaultenv_clep7212); + + return 0; +} +device_initcall(clep7212_init); diff --git a/arch/arm/boards/clep7212/clep7212.c b/arch/arm/boards/clep7212/clep7212.c deleted file mode 100644 index 641fa15021..0000000000 --- a/arch/arm/boards/clep7212/clep7212.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include <common.h> -#include <driver.h> -#include <envfs.h> -#include <init.h> -#include <partition.h> -#include <io.h> -#include <linux/sizes.h> -#include <asm/armlinux.h> -#include <asm/mmu.h> -#include <generated/mach-types.h> - -#include <mach/clps711x.h> -#include <mach/devices.h> - -static int clps711x_devices_init(void) -{ - u32 serial_h = 0, serial_l = readl(UNIQID); - void *cfi_io; - - /* Setup Chipselects */ - clps711x_setup_memcfg(0, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_16); - clps711x_setup_memcfg(1, MEMCFG_WAITSTATE_6_1 | MEMCFG_BUS_WIDTH_8); - clps711x_setup_memcfg(2, MEMCFG_WAITSTATE_8_3 | MEMCFG_BUS_WIDTH_16 | - MEMCFG_CLKENB); - clps711x_setup_memcfg(3, MEMCFG_WAITSTATE_7_1 | MEMCFG_BUS_WIDTH_32); - - cfi_io = map_io_sections(CS0_BASE, (void *)0x90000000, SZ_32M); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_io, SZ_32M, - IORESOURCE_MEM); - - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, - "self0"); - devfs_add_partition("nor0", SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, - "env0"); - - armlinux_set_architecture(MACH_TYPE_CLEP7212); - armlinux_set_serial(((u64)serial_h << 32) | serial_l); - - defaultenv_append_directory(defaultenv_clep7212); - - return 0; -} -device_initcall(clps711x_devices_init); - -static int clps711x_console_init(void) -{ - barebox_set_model("Cirrus Logic CLEP7212"); - barebox_set_hostname("clep7212"); - - clps711x_add_uart(0); - - return 0; -} -console_initcall(clps711x_console_init); diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c index 231329025b..ba402cecea 100644 --- a/arch/arm/boards/clep7212/lowlevel.c +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -1,28 +1,21 @@ -/* - * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> #include <common.h> -#include <init.h> +#include <asm/barebox-arm.h> +#include <linux/sizes.h> +#include <mach/clps711x/clps711x.h> -#include <asm/barebox-arm-head.h> +extern char __dtb_ep7212_clep7212_start[]; -#include <mach/clps711x.h> - -#ifdef CONFIG_CLPS711X_RAISE_CPUFREQ -# define CLPS711X_CPU_PLL_MULT 50 -#else -# define CLPS711X_CPU_PLL_MULT 40 -#endif - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +ENTRY_FUNCTION_WITHSTACK(start_ep7212_clep7212, + CS6_BASE + 48 * SZ_1K, r0, r1, r2) { + void *fdt; + arm_cpu_lowlevel_init(); - clps711x_barebox_entry(CLPS711X_CPU_PLL_MULT, NULL); + fdt = __dtb_ep7212_clep7212_start; + + clps711x_start(fdt + get_runtime_offset()); } diff --git a/arch/arm/boards/cm-fx6/Makefile b/arch/arm/boards/cm-fx6/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/cm-fx6/Makefile +++ b/arch/arm/boards/cm-fx6/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/cm-fx6/board.c b/arch/arm/boards/cm-fx6/board.c index f4380629e3..c70989476b 100644 --- a/arch/arm/boards/cm-fx6/board.c +++ b/arch/arm/boards/cm-fx6/board.c @@ -1,27 +1,16 @@ -/* - * Copyright (C) 2015 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx6-regs.h> -#include <mach/bbu.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/bbu.h> #include <asm/armlinux.h> #include <linux/phy.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> -#include <mach/imx6.h> +#include <mach/imx/imx6.h> #include <net.h> static int phy_fixup(struct phy_device *phydev) diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg index 9e8dce5877..da4cd4bebf 100644 --- a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg +++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg @@ -1,4 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x00907000 max_load_size 0x11000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/cm-fx6/lowlevel.c b/arch/arm/boards/cm-fx6/lowlevel.c index fd86e159aa..029586294f 100644 --- a/arch/arm/boards/cm-fx6/lowlevel.c +++ b/arch/arm/boards/cm-fx6/lowlevel.c @@ -1,17 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define pr_fmt(fmt) "cm-fx6: " fmt #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <io.h> -#include <mach/imx6-mmdc.h> -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6.h> -#include <mach/xload.h> -#include <mach/esdctl.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> #include <serial/imx-uart.h> enum ddr_config { @@ -332,7 +335,7 @@ static noinline void cm_fx6_start(void) ENTRY_FUNCTION(start_imx6_cm_fx6, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx6_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -359,7 +362,7 @@ static noinline void utilite_start(void) ENTRY_FUNCTION(start_imx6_utilite, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx6_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); diff --git a/arch/arm/boards/congatec-qmx8p/Makefile b/arch/arm/boards/congatec-qmx8p/Makefile new file mode 100644 index 0000000000..b3ae72be3e --- /dev/null +++ b/arch/arm/boards/congatec-qmx8p/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/congatec-qmx8p/board.c b/arch/arm/boards/congatec-qmx8p/board.c new file mode 100644 index 0000000000..fcec2a17c4 --- /dev/null +++ b/arch/arm/boards/congatec-qmx8p/board.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2023 Juergen Borleis, Pengutronix +// SPDX-FileCopyrightText: 2023 Johannes Zink, Pengutronix + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/imx/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx8mp.h> +#include <gpio.h> +#include <envfs.h> + +/* Phy regulator handling in Linux is broken for the MX8 EQOs, as the + * 'phy-regulators' properties are not handed down properly, so this is + * currently not set in the kernel DT. + * As a workaround, enable the regulator manually via GPIO. */ +#define EQOS_PWR_PIN IMX_GPIO_NR(1, 5) /* ENET_PWREN# */ +static void setup_ethernet_phy(void) +{ + u32 val; + + of_device_ensure_probed_by_alias("gpio0"); + + if (gpio_direction_output(EQOS_PWR_PIN, 0)) { + pr_err("eqos phy power: failed to request pin\n"); + return; + } + + /* the phy needs roughly 200ms delay after power-on */ + mdelay(200); + + /* Enable RGMII TX clk output */ + val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN; + writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); +} + +static int congatec_qmx8p_probe(struct device *dev) +{ + setup_ethernet_phy(); + + imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", + "/dev/m25p0.boot", BBU_HANDLER_FLAG_DEFAULT); + + return 0; +} + +static const struct of_device_id congatec_qmx8p_of_match[] = { + { .compatible = "congatec,qmx8p" }, + { /* Sentinel */ } +}; +BAREBOX_DEEP_PROBE_ENABLE(congatec_qmx8p_of_match); + +static struct driver congatec_qmx8p_som_driver = { + .name = "som-congatec-qmx8p", + .probe = congatec_qmx8p_probe, + .of_compatible = congatec_qmx8p_of_match, +}; +coredevice_platform_driver(congatec_qmx8p_som_driver); diff --git a/arch/arm/boards/congatec-qmx8p/flash-header-congatec-qmx8p.imxcfg b/arch/arm/boards/congatec-qmx8p/flash-header-congatec-qmx8p.imxcfg new file mode 100644 index 0000000000..70c57768eb --- /dev/null +++ b/arch/arm/boards/congatec-qmx8p/flash-header-congatec-qmx8p.imxcfg @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 + +flexspi_ivtofs 0x0 +flexspi_fcfbofs 0x400 diff --git a/arch/arm/boards/congatec-qmx8p/lowlevel.c b/arch/arm/boards/congatec-qmx8p/lowlevel.c new file mode 100644 index 0000000000..1889b9bb33 --- /dev/null +++ b/arch/arm/boards/congatec-qmx8p/lowlevel.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2023 Pengutronix + +#include <common.h> +#include <debug_ll.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <asm/sections.h> +#include <image-metadata.h> +#include <mach/imx/atf.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/xload.h> +#include <mfd/pca9450.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <soc/fsl/fsl_udc.h> +#include <soc/imx8m/ddr.h> + +extern char __dtb_z_imx8mp_koenigbauer_alphajet_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL) +/* + * SoC UART 1 is the standard console on the KB base board + */ +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART1_TXD__UART1_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART1_RXD__UART1_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM, increase + * VDD_ARM to OD voltage 0.95v + */ + { PCA9450_BUCK2OUT_DVS0, 0x1C }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +extern struct dram_timing_info dram_timing_4g; + +static void start_tfa(void) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mp_early_clock_init(); + power_init_board(); + + imx8mp_ddr_init(&dram_timing_4g, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); +} + +static __noreturn noinline void congatec_qmx8p_start(char dtb[]) +{ + setup_uart(); + + start_tfa(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(dtb); +} + +ENTRY_FUNCTION(start_koenigbauer_alphajet, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + congatec_qmx8p_start(__dtb_z_imx8mp_koenigbauer_alphajet_start); +} diff --git a/arch/arm/boards/congatec-qmx8p/lpddr4-timing.c b/arch/arm/boards/congatec-qmx8p/lpddr4-timing.c new file mode 100644 index 0000000000..6d10b530ba --- /dev/null +++ b/arch/arm/boards/congatec-qmx8p/lpddr4-timing.c @@ -0,0 +1,1832 @@ +// SPDX-License-Identifier: GPL-2.0+ +// SPDX-FileCopyrightText: 2019 NXP + +#include <common.h> +#include <soc/imx8m/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg_4g[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1322 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x3d0118 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028112a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1020 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0x6001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040105 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1020 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +static struct dram_cfg_param ddr_fsp0_cfg_4g[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_cfg_param ddr_fsp1_cfg_4g[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_cfg_param ddr_fsp2_cfg_4g[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_cfg_param ddr_fsp0_2d_cfg_4g[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg_4g[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg_4g, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_4g), + }, { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg_4g, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_4g), + }, { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg_4g, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_4g), + }, { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg_4g, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_4g), + }, +}; + +struct dram_timing_info dram_timing_4g = { + .ddrc_cfg = ddr_ddrc_cfg_4g, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_4g), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg_4g, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_4g), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/crystalfontz-cfa10036/Makefile b/arch/arm/boards/crystalfontz-cfa10036/Makefile index 5b764a6981..3cd1cecaa7 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/Makefile +++ b/arch/arm/boards/crystalfontz-cfa10036/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += cfa10036.o hwdetect.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c index 29b91e775f..dd6d62b165 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c +++ b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c @@ -1,19 +1,8 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * Copyright (C) 2011 Marc Kleine-Budde, Pengutronix <mkl@pengutronix.de> - * Copyright (C) 2011 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> - * Copyright (C) 2012 Maxime Ripard, Free Electrons <maxime.ripard@free-electrons.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Wolfram Sang <w.sang@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2012 Maxime Ripard <maxime.ripard@free-electrons.com>, Free Electrons #include <common.h> #include <environment.h> @@ -30,18 +19,17 @@ #include <i2c/i2c-gpio.h> #include <i2c/at24.h> -#include <mach/clock.h> -#include <mach/imx-regs.h> -#include <mach/iomux.h> -#include <mach/mci.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/iomux.h> +#include <mach/mxs/mci.h> #include <asm/armlinux.h> #include <asm/mmu.h> #include <asm/barebox-arm.h> -#include <mach/fb.h> +#include <mach/mxs/fb.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include "hwdetect.h" diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index e4ccbdb2a3..fc39f0849a 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Free Electrons - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Free Electrons #include <common.h> @@ -112,4 +99,4 @@ void cfa10036_detect_hw(void) pr_info("Booting on a CFA10036 with %s\n", board_name); } -BAREBOX_MAGICVAR_NAMED(global_board_variant, global.board.variant, "The board variant"); +BAREBOX_MAGICVAR(global.board.variant, "The board variant"); diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h index 2a5330ea17..63c4a5b037 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Free Electrons - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Free Electrons #ifndef __HWDETECT_H__ #define __HWDETECT_H__ diff --git a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c index 1bc5947682..447ef0dc66 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c +++ b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c @@ -1,12 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx28-regs.h> -#include <generated/mach-types.h> +#include <mach/mxs/imx28-regs.h> +#include <asm/mach-types.h> + +static noinline void continue_imx_entry(size_t size) +{ + static struct barebox_arm_boarddata boarddata = { + .magic = BAREBOX_ARM_BOARDDATA_MAGIC, + .machine = MACH_TYPE_CFA10036, + }; + + barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); +} ENTRY_FUNCTION(start_cfa10036, r0, r1, r2) { arm_cpu_lowlevel_init(); - barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, (void *)MACH_TYPE_CFA10036); + + relocate_to_current_adr(); + setup_c(); + + continue_imx_entry(SZ_128M); } diff --git a/arch/arm/boards/datamodul-edm-qmx6/Makefile b/arch/arm/boards/datamodul-edm-qmx6/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/Makefile +++ b/arch/arm/boards/datamodul-edm-qmx6/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index d93c940e3d..93abce33af 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -1,26 +1,9 @@ -/* - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ - -#include <generated/mach-types.h> +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix + +#include <asm/mach-types.h> #include <environment.h> #include <bootsource.h> -#include <partition.h> #include <common.h> #include <envfs.h> #include <linux/sizes.h> @@ -28,18 +11,19 @@ #include <gpio.h> #include <of.h> +#include <linux/mdio.h> +#include <linux/phy.h> #include <linux/micrel_phy.h> #include <mfd/stmpe-i2c.h> #include <asm/armlinux.h> #include <asm/io.h> -#include <mach/devices-imx6.h> -#include <mach/imx6-regs.h> -#include <mach/iomux-mx6.h> -#include <mach/generic.h> -#include <mach/imx6.h> -#include <mach/bbu.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6.h> +#include <mach/imx/bbu.h> #define RQ7_GPIO_ENET_PHYADD2 IMX_GPIO_NR(6, 30) #define RQ7_GPIO_ENET_MODE0 IMX_GPIO_NR(6, 25) @@ -65,9 +49,9 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev) * min rx data delay, max rx/tx clock delay, * min rx/tx control delay */ - phy_write_mmd_indirect(dev, 4, 2, 0); - phy_write_mmd_indirect(dev, 5, 2, 0); - phy_write_mmd_indirect(dev, 8, 2, 0x03ff); + phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x03ff); return 0; } diff --git a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg index 400a870154..139e6df792 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg +++ b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x00907000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c index 23074326b5..9566e492e3 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c +++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> + #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -20,8 +9,8 @@ #include <asm/mmu.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-mmdc.h> -#include <mach/generic.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/generic.h> static void sdram_init(void) { diff --git a/arch/arm/boards/delphi-poc20/env/boot/mmc b/arch/arm/boards/delphi-poc20/env/boot/mmc deleted file mode 100644 index d5e202f395..0000000000 --- a/arch/arm/boards/delphi-poc20/env/boot/mmc +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/mnt/mmc/zImage" -global.bootm.oftree="/mnt/mmc/oftree" -global.linux.bootargs.dyn.root="root=mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/dfi-fs700-m60/Makefile b/arch/arm/boards/dfi-fs700-m60/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/dfi-fs700-m60/Makefile +++ b/arch/arm/boards/dfi-fs700-m60/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c index 2cb8e3106f..a0cdc5b93a 100644 --- a/arch/arm/boards/dfi-fs700-m60/board.c +++ b/arch/arm/boards/dfi-fs700-m60/board.c @@ -1,24 +1,9 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix + #define pr_fmt(fmt) "dfi-fs700-m60: " fmt -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <environment.h> #include <bootsource.h> #include <globalvar.h> @@ -35,9 +20,9 @@ #include <asm/mmu.h> #include <asm/io.h> -#include <mach/imx6-regs.h> -#include <mach/generic.h> -#include <mach/bbu.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/generic.h> +#include <mach/imx/bbu.h> /* * This board can have 512MiB, 1GiB or 2GiB of SDRAM. The actual amount of SDRAM diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg index 2be0210dd6..8eec14b014 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 wm 32 MX6_IOM_DRAM_DQM5 0x00020030 diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg index fb34903e27..9573459bd5 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg index 42e98d65d3..b6318e8812 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x17800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c index 520ed4c46b..1ca0d6f090 100644 --- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c +++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> + #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -19,8 +8,8 @@ #include <asm/mmu.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-regs.h> -#include <mach/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/generic.h> #include <debug_ll.h> diff --git a/arch/arm/boards/digi-ccimx6ulsom/Makefile b/arch/arm/boards/digi-ccimx6ulsom/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/Makefile +++ b/arch/arm/boards/digi-ccimx6ulsom/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/digi-ccimx6ulsom/board.c b/arch/arm/boards/digi-ccimx6ulsom/board.c index 1fb451548f..ef6828c02c 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/board.c +++ b/arch/arm/boards/digi-ccimx6ulsom/board.c @@ -1,26 +1,10 @@ -/* - * Copyright (C) 2019 Rouven Czerwinski, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Rouven Czerwinski, Pengutronix #include <common.h> #include <init.h> -#include <mach/generic.h> -#include <mach/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/bbu.h> static int digi_ccimx6ulsbcpro_device_init(void) { diff --git a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg index 36edad7a3e..6f1c5bc8a7 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg +++ b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c index 7bf1db8120..08651f0779 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c +++ b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c @@ -1,7 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> #include <asm/cache.h> diff --git a/arch/arm/boards/dss11/Makefile b/arch/arm/boards/dss11/Makefile index e11fd5b692..d59545033d 100644 --- a/arch/arm/boards/dss11/Makefile +++ b/arch/arm/boards/dss11/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c index 0d0b5e29bf..41c2b10972 100644 --- a/arch/arm/boards/dss11/init.c +++ b/arch/arm/boards/dss11/init.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2011 Michael Grzeschik <mgr@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Michael Grzeschik <mgr@pengutronix.de> #include <common.h> #include <net.h> @@ -18,19 +7,19 @@ #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <asm/io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> +#include <linux/mtd/rawnand.h> #include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_rstc.h> #include <linux/clk.h> static struct atmel_nand_data nand_pdata = { diff --git a/arch/arm/boards/dss11/lowlevel.c b/arch/arm/boards/dss11/lowlevel.c index 7f52f824df..be2675369c 100644 --- a/arch/arm/boards/dss11/lowlevel.c +++ b/arch/arm/boards/dss11/lowlevel.c @@ -7,14 +7,12 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_dss11, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/duckbill/Makefile b/arch/arm/boards/duckbill/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/duckbill/Makefile +++ b/arch/arm/boards/duckbill/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/duckbill/board.c b/arch/arm/boards/duckbill/board.c index 13d4ae43cf..edb9320f0e 100644 --- a/arch/arm/boards/duckbill/board.c +++ b/arch/arm/boards/duckbill/board.c @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * Copyright (C) 2011 Marc Kleine-Budde, Pengutronix <mkl@pengutronix.de> - * Copyright (C) 2011 Wolfram Sang, Pengutronix <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2011 Wolfram Sang <w.sang@pengutronix.de>, Pengutronix #include <common.h> #include <environment.h> @@ -22,14 +11,13 @@ #include <io.h> #include <net.h> -#include <mach/clock.h> -#include <mach/imx-regs.h> -#include <mach/iomux-imx28.h> -#include <mach/iomux.h> -#include <mach/ocotp.h> -#include <mach/devices.h> -#include <mach/usb.h> -#include <usb/fsl_usb2.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/iomux-imx28.h> +#include <mach/mxs/iomux.h> +#include <mach/mxs/ocotp.h> +#include <mach/mxs/devices.h> +#include <mach/mxs/usb.h> +#include <linux/usb/fsl_usb2.h> #include <asm/armlinux.h> #include <asm/mmu.h> diff --git a/arch/arm/boards/duckbill/lowlevel.c b/arch/arm/boards/duckbill/lowlevel.c index 22987a6cdb..71862ec4b7 100644 --- a/arch/arm/boards/duckbill/lowlevel.c +++ b/arch/arm/boards/duckbill/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define pr_fmt(fmt) "I2SE Duckbill: " fmt #define DEBUG @@ -5,11 +7,11 @@ #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx28-regs.h> -#include <mach/init.h> +#include <mach/mxs/imx28-regs.h> +#include <mach/mxs/init.h> #include <io.h> #include <debug_ll.h> -#include <mach/iomux.h> +#include <mach/mxs/iomux.h> #include <stmp-device.h> extern char __dtb_imx28_duckbill_start[]; diff --git a/arch/arm/boards/ebv-socrates/Makefile b/arch/arm/boards/ebv-socrates/Makefile index 8c927fe291..ea898309d7 100644 --- a/arch/arm/boards/ebv-socrates/Makefile +++ b/arch/arm/boards/ebv-socrates/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += lowlevel.o board.o pbl-y += lowlevel.o diff --git a/arch/arm/boards/ebv-socrates/board.c b/arch/arm/boards/ebv-socrates/board.c index 965150f9a3..79085a5bb5 100644 --- a/arch/arm/boards/ebv-socrates/board.c +++ b/arch/arm/boards/ebv-socrates/board.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <types.h> #include <driver.h> @@ -11,7 +13,7 @@ #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/cyclone5-regs.h> +#include <mach/socfpga/cyclone5-regs.h> static int phy_fixup(struct phy_device *dev) { diff --git a/arch/arm/boards/ebv-socrates/config.h b/arch/arm/boards/ebv-socrates/config.h deleted file mode 100644 index da84fa5f6b..0000000000 --- a/arch/arm/boards/ebv-socrates/config.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing */ diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c index 6153de9005..a769ff5366 100644 --- a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c +++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c @@ -27,9 +27,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/cyclone5-scan-manager.h> +#include <mach/socfpga/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x000C0300, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0CC20D80, 0x0C3000FF, 0x0A804001, diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c index ed2d4a72a5..56b0f43a33 100644 --- a/arch/arm/boards/ebv-socrates/lowlevel.c +++ b/arch/arm/boards/ebv-socrates/lowlevel.c @@ -1,4 +1,4 @@ -#define SECT(name) __attribute__((section("ebv_socrates_" #name))) name +// SPDX-License-Identifier: GPL-2.0-only #include "sdram_config.h" #include "pinmux_config.c" @@ -9,7 +9,7 @@ #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" -#include <mach/lowlevel.h> +#include <mach/socfpga/lowlevel.h> static inline void ledon(void) { diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c index 89e6b33c86..faa3122466 100644 --- a/arch/arm/boards/ebv-socrates/pinmux_config.c +++ b/arch/arm/boards/ebv-socrates/pinmux_config.c @@ -30,7 +30,7 @@ #include <common.h> /* pin MUX configuration data */ -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ @@ -238,4 +238,4 @@ static unsigned long SECT(sys_mgr_init_table)[] = { 0, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ -}; +};
\ No newline at end of file diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto.h b/arch/arm/boards/ebv-socrates/sequencer_auto.h index 59aa9cf816..d52e19548a 100644 --- a/arch/arm/boards/ebv-socrates/sequencer_auto.h +++ b/arch/arm/boards/ebv-socrates/sequencer_auto.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #define __RW_MGR_ac_mrs1 0x04 #define __RW_MGR_ac_mrs3 0x06 #define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c index c52da56b79..1a19310dcb 100644 --- a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c +++ b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c @@ -1,5 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only + static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c index e261ecb6c1..c818d725b8 100644 --- a/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c +++ b/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + static const uint32_t inst_rom_init_size = 128; static const uint32_t inst_rom_init[128] = { diff --git a/arch/arm/boards/ebv-socrates/sequencer_defines.h b/arch/arm/boards/ebv-socrates/sequencer_defines.h index 1ebbc48011..bef98641aa 100644 --- a/arch/arm/boards/ebv-socrates/sequencer_defines.h +++ b/arch/arm/boards/ebv-socrates/sequencer_defines.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _SEQUENCER_DEFINES_H_ #define _SEQUENCER_DEFINES_H_ diff --git a/arch/arm/boards/edb93xx/Makefile b/arch/arm/boards/edb93xx/Makefile index eec5ed2658..be969bde20 100644 --- a/arch/arm/boards/edb93xx/Makefile +++ b/arch/arm/boards/edb93xx/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only obj-y += edb93xx.o lwl-y += flash_cfg.o pll_cfg.o sdram_cfg.o diff --git a/arch/arm/boards/edb93xx/early_udelay.h b/arch/arm/boards/edb93xx/early_udelay.h index 97e018aefc..b902c3bfb7 100644 --- a/arch/arm/boards/edb93xx/early_udelay.h +++ b/arch/arm/boards/edb93xx/early_udelay.h @@ -1,20 +1,5 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> #include <common.h> diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c index 99c69548bd..a3fb14822a 100644 --- a/arch/arm/boards/edb93xx/edb93xx.c +++ b/arch/arm/boards/edb93xx/edb93xx.c @@ -1,32 +1,16 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> #include <common.h> #include <driver.h> #include <environment.h> #include <fs.h> #include <init.h> -#include <partition.h> #include <asm/armlinux.h> #include <io.h> #include <malloc.h> -#include <generated/mach-types.h> -#include <mach/ep93xx-regs.h> +#include <asm/mach-types.h> +#include <mach/ep93xx/ep93xx-regs.h> #include <platform_data/eth-ep93xx.h> #include "edb93xx.h" diff --git a/arch/arm/boards/edb93xx/edb93xx.h b/arch/arm/boards/edb93xx/edb93xx.h index 43459091f9..efbe87684e 100644 --- a/arch/arm/boards/edb93xx/edb93xx.h +++ b/arch/arm/boards/edb93xx/edb93xx.h @@ -1,20 +1,5 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> #if defined(CONFIG_MACH_EDB9301) #define MACH_TYPE MACH_TYPE_EDB9301 diff --git a/arch/arm/boards/edb93xx/flash_cfg.c b/arch/arm/boards/edb93xx/flash_cfg.c index f2d5800efd..2c471c7721 100644 --- a/arch/arm/boards/edb93xx/flash_cfg.c +++ b/arch/arm/boards/edb93xx/flash_cfg.c @@ -1,31 +1,19 @@ -/* - * Flash setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + +/* Flash setup for Cirrus edb93xx boards */ #include <common.h> -#include <mach/ep93xx-regs.h> +#include <mach/ep93xx/ep93xx-regs.h> #include <io.h> #define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ 1 << SMC_BCR_MW_SHIFT) +/* Called from assembly */ +void flash_cfg(void); + void flash_cfg(void) { struct smc_regs *smc = (struct smc_regs *)SMC_BASE; diff --git a/arch/arm/boards/edb93xx/pll_cfg.c b/arch/arm/boards/edb93xx/pll_cfg.c index 9d7e1781e7..1a1c01aba2 100644 --- a/arch/arm/boards/edb93xx/pll_cfg.c +++ b/arch/arm/boards/edb93xx/pll_cfg.c @@ -1,30 +1,17 @@ -/* - * PLL setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> +// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> + +/* PLL setup for Cirrus edb93xx boards */ #include <common.h> #include <io.h> #include "pll_cfg.h" #include "early_udelay.h" +/* Called from assembly */ +void pll_cfg(void); + void pll_cfg(void) { struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; diff --git a/arch/arm/boards/edb93xx/pll_cfg.h b/arch/arm/boards/edb93xx/pll_cfg.h index 07231d7b3e..662c92337a 100644 --- a/arch/arm/boards/edb93xx/pll_cfg.h +++ b/arch/arm/boards/edb93xx/pll_cfg.h @@ -1,25 +1,10 @@ -/* - * PLL register values for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> + +/* PLL register values for Cirrus edb93xx boards */ #include <config.h> -#include <mach/ep93xx-regs.h> +#include <mach/ep93xx/ep93xx-regs.h> #if defined(CONFIG_MACH_EDB9301) /* diff --git a/arch/arm/boards/edb93xx/sdram_cfg.c b/arch/arm/boards/edb93xx/sdram_cfg.c index 5c2a5372e0..3cee834910 100644 --- a/arch/arm/boards/edb93xx/sdram_cfg.c +++ b/arch/arm/boards/edb93xx/sdram_cfg.c @@ -1,22 +1,6 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> +// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> #include <common.h> #include <io.h> @@ -33,6 +17,9 @@ static void precharge_all_banks(void); static void setup_refresh_timer(void); static void program_mode_registers(void); +/* Called from assembly */ +void sdram_cfg(void); + void sdram_cfg(void) { struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; diff --git a/arch/arm/boards/edb93xx/sdram_cfg.h b/arch/arm/boards/edb93xx/sdram_cfg.h index 0dc1df24b2..ddb9e442ed 100644 --- a/arch/arm/boards/edb93xx/sdram_cfg.h +++ b/arch/arm/boards/edb93xx/sdram_cfg.h @@ -1,25 +1,9 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> +// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> #include <config.h> -#include <mach/ep93xx-regs.h> +#include <mach/ep93xx/ep93xx-regs.h> #define SDRAM_BASE_ADDR CONFIG_EP93XX_SDRAM_BANK0_BASE diff --git a/arch/arm/boards/efika-mx-smartbook/Makefile b/arch/arm/boards/efika-mx-smartbook/Makefile index 73d7b9696c..497da461ef 100644 --- a/arch/arm/boards/efika-mx-smartbook/Makefile +++ b/arch/arm/boards/efika-mx-smartbook/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-efikasb diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c index ec41eb8c11..5101e3a558 100644 --- a/arch/arm/boards/efika-mx-smartbook/board.c +++ b/arch/arm/boards/efika-mx-smartbook/board.c @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <environment.h> #include <bootsource.h> -#include <partition.h> #include <common.h> #include <envfs.h> #include <fcntl.h> @@ -32,13 +19,12 @@ #include <asm/armlinux.h> -#include <mach/devices-imx51.h> -#include <mach/imx51-regs.h> -#include <mach/iomux-mx51.h> -#include <mach/revision.h> -#include <mach/generic.h> -#include <mach/imx5.h> -#include <mach/bbu.h> +#include <mach/imx/imx51-regs.h> +#include <mach/imx/iomux-mx51.h> +#include <mach/imx/revision.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx5.h> +#include <mach/imx/bbu.h> #define GPIO_BACKLIGHT_POWER IMX_GPIO_NR(4, 12) #define GPIO_BACKLIGHT_PWM IMX_GPIO_NR(1, 2) diff --git a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg index 53875ed319..de28650519 100644 --- a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg +++ b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000000 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/efika-mx-smartbook/lowlevel.c b/arch/arm/boards/efika-mx-smartbook/lowlevel.c index 3881678d85..cf2f145e74 100644 --- a/arch/arm/boards/efika-mx-smartbook/lowlevel.c +++ b/arch/arm/boards/efika-mx-smartbook/lowlevel.c @@ -1,9 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx5.h> +#include <mach/imx/imx5.h> extern char __dtb_imx51_genesi_efika_sb_start[]; diff --git a/arch/arm/boards/element14-warp7/Makefile b/arch/arm/boards/element14-warp7/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/element14-warp7/Makefile +++ b/arch/arm/boards/element14-warp7/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/element14-warp7/board.c b/arch/arm/boards/element14-warp7/board.c index 84fc885da1..0013421df0 100644 --- a/arch/arm/boards/element14-warp7/board.c +++ b/arch/arm/boards/element14-warp7/board.c @@ -1,25 +1,13 @@ -/* - * Copyright (C) 2017 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> #include <environment.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <mach/generic.h> +#include <asm/mach-types.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> static int warp7_devices_init(void) diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg index 7aa5dd8d45..c17321ad3a 100644 --- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg +++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg @@ -11,9 +11,9 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx7-ddr-regs.h> +#include <mach/imx/imx7-ddr-regs.h> wm 32 0x30340004 0x4F400005 diff --git a/arch/arm/boards/element14-warp7/lowlevel.c b/arch/arm/boards/element14-warp7/lowlevel.c index 6ca733a0be..c6ddfea5a4 100644 --- a/arch/arm/boards/element14-warp7/lowlevel.c +++ b/arch/arm/boards/element14-warp7/lowlevel.c @@ -1,12 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define DEBUG #include <io.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> +#include <mach/imx/debug_ll.h> extern char __dtb_imx7s_warp_start[]; diff --git a/arch/arm/boards/eltec-hipercam/Makefile b/arch/arm/boards/eltec-hipercam/Makefile index 092c31d6b2..5678718188 100644 --- a/arch/arm/boards/eltec-hipercam/Makefile +++ b/arch/arm/boards/eltec-hipercam/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o diff --git a/arch/arm/boards/eltec-hipercam/board.c b/arch/arm/boards/eltec-hipercam/board.c index 04ad253e6c..b8ad17992c 100644 --- a/arch/arm/boards/eltec-hipercam/board.c +++ b/arch/arm/boards/eltec-hipercam/board.c @@ -1,22 +1,10 @@ -/* - * Copyright (C) 2015 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Sascha Hauer <s.hauer@pengutronix.de> #include <common.h> #include <init.h> #include <bbu.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> static int hipercam_init(void) { diff --git a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg index f04adf86a4..3a96910708 100644 --- a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg +++ b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 diff --git a/arch/arm/boards/eltec-hipercam/lowlevel.c b/arch/arm/boards/eltec-hipercam/lowlevel.c index 2f2cd9aab7..154c0e58f5 100644 --- a/arch/arm/boards/eltec-hipercam/lowlevel.c +++ b/arch/arm/boards/eltec-hipercam/lowlevel.c @@ -1,26 +1,16 @@ -/* - * Copyright (C) 2015 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Sascha Hauer <s.hauer@pengutronix.de> + #include <common.h> #include <linux/sizes.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/sections.h> #include <asm/mmu.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> static void setup_uart(void) { diff --git a/arch/arm/boards/embedsky-e9/Makefile b/arch/arm/boards/embedsky-e9/Makefile index 86afde47fb..116bbfb4c2 100644 --- a/arch/arm/boards/embedsky-e9/Makefile +++ b/arch/arm/boards/embedsky-e9/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-e9 diff --git a/arch/arm/boards/embedsky-e9/board.c b/arch/arm/boards/embedsky-e9/board.c index 0f47677bb0..6052805b8a 100644 --- a/arch/arm/boards/embedsky-e9/board.c +++ b/arch/arm/boards/embedsky-e9/board.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2014 Andrey Panov <rockford@yandex.ru> * @@ -6,42 +8,29 @@ * * based on arch/arm/boards/freescale-mx6-sabrelite/board.c * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx6-regs.h> -#include <gpio.h> +#include <mach/imx/imx6-regs.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <linux/phy.h> #include <asm/io.h> #include <asm/mmu.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #include <net.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/iomux-mx6.h> #include <spi/spi.h> -#include <mach/spi.h> -#include <mach/usb.h> +#include <mach/imx/spi.h> +#include <mach/imx/usb.h> #include <envfs.h> #include <bootsource.h> #include <bbu.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #define PHY_ID_RTL8211E 0x001cc915 #define PHY_ID_MASK 0xffffffff @@ -102,8 +91,4 @@ static int e9_coredevices_init(void) return 0; } -/* - * Do this before the fec initializes but after our - * gpios are available. - */ coredevice_initcall(e9_coredevices_init); diff --git a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg index 1139312da6..19e0039980 100644 --- a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg +++ b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/embedsky-e9/lowlevel.c b/arch/arm/boards/embedsky-e9/lowlevel.c index 845c4ec90c..fddc88df52 100644 --- a/arch/arm/boards/embedsky-e9/lowlevel.c +++ b/arch/arm/boards/embedsky-e9/lowlevel.c @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/embest-marsboard/Makefile b/arch/arm/boards/embest-marsboard/Makefile index ef5219444c..eaa6ace2f4 100644 --- a/arch/arm/boards/embest-marsboard/Makefile +++ b/arch/arm/boards/embest-marsboard/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-mars diff --git a/arch/arm/boards/embest-marsboard/board.c b/arch/arm/boards/embest-marsboard/board.c index 66893434c2..1a5e5a8491 100644 --- a/arch/arm/boards/embest-marsboard/board.c +++ b/arch/arm/boards/embest-marsboard/board.c @@ -8,8 +8,10 @@ #include <common.h> #include <init.h> #include <envfs.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> +#include <linux/mdio.h> #include <linux/phy.h> +#include <deep-probe.h> static int ar8035_phy_fixup(struct phy_device *dev) { @@ -18,37 +20,22 @@ static int ar8035_phy_fixup(struct phy_device *dev) /* Ar803x phy SmartEEE feature cause link status generates glitch, * which cause ethernet link down/up issue, so disable SmartEEE */ - phy_write(dev, 0xd, 0x3); - phy_write(dev, 0xe, 0x805d); - phy_write(dev, 0xd, 0x4003); + val = phy_read_mmd(dev, MDIO_MMD_PCS, 0x805d); + phy_write(dev, MII_MMD_DATA, val & ~(1 << 8)); - val = phy_read(dev, 0xe); - phy_write(dev, 0xe, val & ~(1 << 8)); + val = phy_read_mmd(dev, MDIO_MMD_PCS, 0x4003); + phy_write(dev, MII_MMD_DATA, val & ~(1 << 8)); - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); - phy_write(dev, 0xd, 0x4007); - - val = phy_read(dev, 0xe); + val = phy_read_mmd(dev, MDIO_MMD_PCS, 0x4007); val &= 0xffe3; val |= 0x18; - phy_write(dev, 0xe, val); - - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); + phy_write(dev, MII_MMD_DATA, val); return 0; } -static int marsboard_device_init(void) +static int marsboard_device_init(struct device *dev) { - if (!of_machine_is_compatible("embest,imx6q-marsboard")) - return 0; - barebox_set_hostname("marsboard"); phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); @@ -60,4 +47,16 @@ static int marsboard_device_init(void) return 0; } -device_initcall(marsboard_device_init); + +static const struct of_device_id marsboard_of_match[] = { + { .compatible = "embest,imx6q-marsboard" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(marsboard_of_match); + +static struct driver marsboard_driver = { + .name = "board-mars", + .probe = marsboard_device_init, + .of_compatible = marsboard_of_match, +}; +postcore_platform_driver(marsboard_driver); diff --git a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg index bdaf60cb4a..5cf7201e88 100644 --- a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg +++ b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e05a8 0x00000030 wm 32 0x020e05b0 0x00000030 diff --git a/arch/arm/boards/embest-marsboard/lowlevel.c b/arch/arm/boards/embest-marsboard/lowlevel.c index 9e20a2ec06..84378c00f2 100644 --- a/arch/arm/boards/embest-marsboard/lowlevel.c +++ b/arch/arm/boards/embest-marsboard/lowlevel.c @@ -6,10 +6,11 @@ #include <common.h> #include <io.h> #include <asm/barebox-arm.h> -#include <mach/imx6.h> -#include <mach/esdctl.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/iomux-mx6.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/embest-riotboard/Makefile b/arch/arm/boards/embest-riotboard/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/embest-riotboard/Makefile +++ b/arch/arm/boards/embest-riotboard/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/embest-riotboard/board.c b/arch/arm/boards/embest-riotboard/board.c index eb956f1f50..ebaff48388 100644 --- a/arch/arm/boards/embest-riotboard/board.c +++ b/arch/arm/boards/embest-riotboard/board.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2014 Eric Bénard <eric@eukrea.com> - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Eric Bénard <eric@eukrea.com> +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <asm/armlinux.h> #include <asm/io.h> @@ -21,59 +10,35 @@ #include <envfs.h> #include <gpio.h> #include <init.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> -#include <mach/imx6.h> -#include <mach/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6.h> +#include <mach/imx/bbu.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <linux/sizes.h> #include <linux/phy.h> +#include <deep-probe.h> -static int ar8035_phy_fixup(struct phy_device *dev) +static int riotboard_probe(struct device *dev) { - u16 val; - - /* Ar803x phy SmartEEE feature cause link status generates glitch, - * which cause ethernet link down/up issue, so disable SmartEEE - */ - phy_write(dev, 0xd, 0x3); - phy_write(dev, 0xe, 0x805d); - phy_write(dev, 0xd, 0x4003); - - val = phy_read(dev, 0xe); - phy_write(dev, 0xe, val & ~(1 << 8)); - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); - phy_write(dev, 0xd, 0x4007); - - val = phy_read(dev, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(dev, 0xe, val); - - /* introduce tx clock delay */ - phy_write(dev, 0x1d, 0x5); - val = phy_read(dev, 0x1e); - val |= 0x0100; - phy_write(dev, 0x1e, val); - - return 0; -} - -static int riotboard_device_init(void) -{ - if (!of_machine_is_compatible("riot,imx6s-riotboard")) - return 0; - - phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); - imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.barebox", BBU_HANDLER_FLAG_DEFAULT); + imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc2", 0); barebox_set_hostname("riotboard"); return 0; } -device_initcall(riotboard_device_init); + +static const struct of_device_id riotboard_of_match[] = { + { .compatible = "riot,imx6s-riotboard"}, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(riotboard_of_match); + +static struct driver riotboard_board_driver = { + .name = "board-riotboard", + .probe = riotboard_probe, + .of_compatible = DRV_OF_COMPAT(riotboard_of_match), +}; +device_platform_driver(riotboard_board_driver); diff --git a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg index c9a8098f6d..5464e2461d 100644 --- a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg +++ b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x20000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c b/arch/arm/boards/embest-riotboard/lowlevel.c index 07f669fc03..9ea92f5091 100644 --- a/arch/arm/boards/embest-riotboard/lowlevel.c +++ b/arch/arm/boards/embest-riotboard/lowlevel.c @@ -1,4 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -7,7 +10,7 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6.h> +#include <mach/imx/imx6.h> extern char __dtb_imx6s_riotboard_start[]; diff --git a/arch/arm/boards/enclustra-aa1/Makefile b/arch/arm/boards/enclustra-aa1/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/enclustra-aa1/board.c b/arch/arm/boards/enclustra-aa1/board.c new file mode 100644 index 0000000000..de886f21aa --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/board.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <init.h> +#include <io.h> +#include <bbu.h> +#include <mach/socfpga/arria10-system-manager.h> + +static int aa1_init(void) +{ + int pbl_index = 0; + uint32_t flag_barebox1 = 0; + uint32_t flag_barebox2 = 0; + + if (!of_machine_is_compatible("enclustra,mercury-aa1")) + return 0; + + pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD); + + pr_debug("Current barebox instance %d\n", pbl_index); + + switch (pbl_index) { + case 0: + flag_barebox1 |= BBU_HANDLER_FLAG_DEFAULT; + break; + case 1: + flag_barebox2 |= BBU_HANDLER_FLAG_DEFAULT; + break; + }; + + bbu_register_std_file_update("emmc-barebox1-xload", flag_barebox1, + "/dev/mmc0.barebox1-xload", + filetype_socfpga_xload); + + bbu_register_std_file_update("emmc-barebox1", 0, + "/dev/mmc0.barebox1", + filetype_arm_barebox); + + bbu_register_std_file_update("emmc-barebox2-xload", flag_barebox2, + "/dev/mmc0.barebox2-xload", + filetype_socfpga_xload); + + bbu_register_std_file_update("emmc-barebox2", 0, + "/dev/mmc0.barebox2", + filetype_arm_barebox); + return 0; +} +postcore_initcall(aa1_init); diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c new file mode 100644 index 0000000000..ba4d562e5f --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/lowlevel.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <linux/sizes.h> +#include <io.h> +#include <memory.h> +#include <asm/barebox-arm.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/unaligned.h> +#include <debug_ll.h> +#include <pbl.h> +#include <mach/socfpga/arria10-sdram.h> +#include <mach/socfpga/arria10-regs.h> +#include <mach/socfpga/arria10-reset-manager.h> +#include <mach/socfpga/arria10-clock-manager.h> +#include <mach/socfpga/arria10-pinmux.h> +#include <mach/socfpga/arria10-fpga.h> +#include <mach/socfpga/init.h> +#include "pll-config-arria10.c" +#include "pinmux-config-arria10.c" +#include <mach/socfpga/generic.h> +#include <mach/socfpga/init.h> + +#define BAREBOX_PART 0 +// the bitstream is located in the second partition in the partition table +#define BITSTREAM_PART 1 +#define BAREBOX1_OFFSET SZ_1M +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_1M) +// Offset from the start of the second partition on the eMMC. +#define BITSTREAM1_OFFSET 0x0 +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) + +extern char __dtb_z_socfpga_arria10_mercury_aa1_start[]; + +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) + +ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2) +{ + int pbl_index = 0; + int barebox = 0; + int bitstream = 0; + + arm_cpu_lowlevel_init(); + arria10_cpu_lowlevel_init(); + + relocate_to_current_adr(); + + setup_c(); + + arria10_init(&mainpll_cfg, &perpll_cfg, pinmux); + + arria10_prepare_mmc(BAREBOX_PART, BITSTREAM_PART); + + pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD); + + /* Allow booting from both PBL0 and PBL1 to allow atomic updates. + * Bitstreams redundant too and expected to reside in the second + * partition. + * There is a fixed relation between the PBL/barebox instance and its + * bitstream location (offset) that requires to update them together */ + switch (pbl_index) { + case 0: + barebox = BAREBOX1_OFFSET; + bitstream = BITSTREAM1_OFFSET; + break; + case 1: + barebox = BAREBOX2_OFFSET; + bitstream = BITSTREAM2_OFFSET; + break; + case 2: + case 3: + /* Left blank for future extension */ + break; + default: + /* If we get an undefined pbl index, use the first and hope for the best. + * We could bail out, but user wouldn't see anything on the console + * and wouldn't know what happend anyway. */ + barebox = BAREBOX1_OFFSET; + bitstream = BITSTREAM1_OFFSET; + break; + } + + arria10_load_fpga(bitstream, SZ_32M); + + arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux); + + arria10_ddr_calibration_sequence(); + + arria10_start_image(barebox); +} + +ENTRY_FUNCTION(start_socfpga_aa1, r0, r1, r2) +{ + void *fdt; + + fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_2G, fdt); +} + +ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + arria10_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + arria10_init(&mainpll_cfg, &perpll_cfg, pinmux); + + /* wait for fpga_usermode */ + a10_wait_for_usermode(0x1000000); + + arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux); + + arria10_ddr_calibration_sequence(); + + fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset(); + + barebox_arm_entry(0x0, SZ_2G, fdt); +} diff --git a/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c new file mode 100644 index 0000000000..fea88e3336 --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/socfpga/arria10-pinmux.h> + +static uint32_t pinmux[] = { +[arria10_pinmux_shared_io_q3_7] = 0, +[arria10_pinmux_shared_io_q3_6] = 15, +[arria10_pinmux_shared_io_q3_5] = 15, +[arria10_pinmux_shared_io_q3_4] = 15, +[arria10_pinmux_shared_io_q3_3] = 15, +[arria10_pinmux_shared_io_q3_2] = 15, +[arria10_pinmux_shared_io_q3_1] = 15, +[arria10_pinmux_shared_io_q2_12] = 4, +[arria10_pinmux_shared_io_q2_11] = 4, +[arria10_pinmux_shared_io_q2_10] = 4, +[arria10_pinmux_shared_io_q2_8] = 4, +[arria10_pinmux_shared_io_q2_9] = 4, +[arria10_pinmux_shared_io_q2_7] = 4, +[arria10_pinmux_shared_io_q2_6] = 4, +[arria10_pinmux_shared_io_q2_5] = 4, +[arria10_pinmux_shared_io_q2_4] = 4, +[arria10_pinmux_shared_io_q2_3] = 4, +[arria10_pinmux_shared_io_q2_2] = 4, +[arria10_pinmux_shared_io_q2_1] = 4, +[arria10_pinmux_shared_io_q1_12] = 8, +[arria10_pinmux_shared_io_q1_10] = 8, +[arria10_pinmux_shared_io_q1_11] = 8, +[arria10_pinmux_shared_io_q1_9] = 8, +[arria10_pinmux_shared_io_q1_8] = 8, +[arria10_pinmux_shared_io_q1_7] = 8, +[arria10_pinmux_shared_io_q1_6] = 8, +[arria10_pinmux_shared_io_q1_5] = 8, +[arria10_pinmux_shared_io_q1_4] = 8, +[arria10_pinmux_shared_io_q1_3] = 8, +[arria10_pinmux_shared_io_q1_2] = 8, +[arria10_pinmux_shared_io_q1_1] = 8, +[arria10_pinmux_shared_io_q4_12] = 15, +[arria10_pinmux_shared_io_q4_11] = 15, +[arria10_pinmux_shared_io_q4_10] = 3, +[arria10_pinmux_shared_io_q4_9] = 3, +[arria10_pinmux_shared_io_q4_8] = 3, +[arria10_pinmux_shared_io_q4_7] = 3, +[arria10_pinmux_shared_io_q4_6] = 10, +[arria10_pinmux_shared_io_q4_4] = 10, +[arria10_pinmux_shared_io_q4_5] = 10, +[arria10_pinmux_shared_io_q4_3] = 10, +[arria10_pinmux_shared_io_q4_2] = 10, +[arria10_pinmux_shared_io_q4_1] = 10, +[arria10_pinmux_shared_io_q3_12] = 1, +[arria10_pinmux_shared_io_q3_11] = 1, +[arria10_pinmux_shared_io_q3_10] = 15, +[arria10_pinmux_shared_io_q3_9] = 15, +[arria10_pinmux_shared_io_q3_8] = 0, +[arria10_pinmux_dedicated_io_7] = 8, +[arria10_pinmux_dedicated_io_8] = 8, +[arria10_pinmux_dedicated_io_9] = 8, +[arria10_pinmux_dedicated_io_10] = 15, +[arria10_pinmux_dedicated_io_11] = 15, +[arria10_pinmux_dedicated_io_12] = 8, +[arria10_pinmux_dedicated_io_13] = 8, +[arria10_pinmux_dedicated_io_14] = 8, +[arria10_pinmux_dedicated_io_15] = 8, +[arria10_pinmux_dedicated_io_16] = 13, +[arria10_pinmux_dedicated_io_17] = 13, +[arria10_pinmux_dedicated_io_4] = 8, +[arria10_pinmux_dedicated_io_5] = 8, +[arria10_pinmux_dedicated_io_6] = 8, +[arria10_pincfg_dedicated_io_bank] = 0x101, +[arria10_pincfg_dedicated_io_1] = 0xb080a, +[arria10_pincfg_dedicated_io_2] = 0xb080a, +[arria10_pincfg_dedicated_io_3] = 0xb080a, +[arria10_pincfg_dedicated_io_4] = 0xa282a, +[arria10_pincfg_dedicated_io_5] = 0xa282a, +[arria10_pincfg_dedicated_io_6] = 0x8282a, +[arria10_pincfg_dedicated_io_7] = 0xa282a, +[arria10_pincfg_dedicated_io_8] = 0xa282a, +[arria10_pincfg_dedicated_io_9] = 0xa282a, +[arria10_pincfg_dedicated_io_10] = 0xa280a, +[arria10_pincfg_dedicated_io_11] = 0xa280a, +[arria10_pincfg_dedicated_io_12] = 0xa280a, +[arria10_pincfg_dedicated_io_13] = 0xa280a, +[arria10_pincfg_dedicated_io_14] = 0xa280a, +[arria10_pincfg_dedicated_io_15] = 0xa280a, +[arria10_pincfg_dedicated_io_16] = 0x8282a, +[arria10_pincfg_dedicated_io_17] = 0xa280a, +[arria10_pinmux_rgmii0_usefpga] = 0, +[arria10_pinmux_rgmii1_usefpga] = 0, +[arria10_pinmux_rgmii2_usefpga] = 0, +[arria10_pinmux_nand_usefpga] = 0, +[arria10_pinmux_qspi_usefpga] = 0, +[arria10_pinmux_sdmmc_usefpga] = 0, +[arria10_pinmux_spim0_usefpga] = 0, +[arria10_pinmux_spim1_usefpga] = 0, +[arria10_pinmux_spis0_usefpga] = 0, +[arria10_pinmux_spis1_usefpga] = 0, +[arria10_pinmux_uart0_usefpga] = 0, +[arria10_pinmux_uart1_usefpga] = 0, +[arria10_pinmux_i2c0_usefpga] = 0, +[arria10_pinmux_i2c1_usefpga] = 0, +[arria10_pinmux_i2cemac0_usefpga] = 0, +[arria10_pinmux_i2cemac1_usefpga] = 0, +[arria10_pinmux_i2cemac2_usefpga] = 0, +}; + diff --git a/arch/arm/boards/enclustra-aa1/pll-config-arria10.c b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c new file mode 100644 index 0000000000..8178550d7d --- /dev/null +++ b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/socfpga/arria10-clock-manager.h> + +static struct arria10_mainpll_cfg mainpll_cfg = { + .cntr15clk_cnt = 900, + .cntr2clk_cnt = 900, + .cntr3clk_cnt = 900, + .cntr4clk_cnt = 900, + .cntr5clk_cnt = 900, + .cntr6clk_cnt = 7, + .cntr7clk_cnt = 15, + .cntr7clk_src = 0, + .cntr8clk_cnt = 7, + .cntr9clk_cnt = 900, + .cntr9clk_src = 0, + .mpuclk_cnt = 0, + .mpuclk_src = 0, + .nocclk_cnt = 0, + .nocclk_src = 0, + .nocdiv_csatclk = 0, + .nocdiv_cspdbgclk = 1, + .nocdiv_cstraceclk = 0, + .nocdiv_l4mainclk = 0, + .nocdiv_l4mpclk = 1, + .nocdiv_l4spclk = 2, + .vco0_psrc = 0, + .vco1_denom = 32, + .vco1_numer = 1584, + .mpuclk = 0x3840001, + .nocclk = 0x3840007, +}; + +static struct arria10_perpll_cfg perpll_cfg = { + .cntr2clk_cnt = 5, + .cntr2clk_src = 1, + .cntr3clk_cnt = 900, + .cntr3clk_src = 1, + .cntr4clk_cnt = 14, + .cntr4clk_src = 1, + .cntr5clk_cnt = 374, + .cntr5clk_src = 1, + .cntr6clk_cnt = 900, + .cntr6clk_src = 0, + .cntr7clk_cnt = 900, + .cntr8clk_cnt = 900, + .cntr8clk_src = 0, + .cntr9clk_cnt = 900, + .emacctl_emac0sel = 0, + .emacctl_emac1sel = 0, + .emacctl_emac2sel = 0, + .gpiodiv_gpiodbclk = 32000, + .vco0_psrc = 0, + .vco1_denom = 32, + .vco1_numer = 1485, +}; diff --git a/arch/arm/boards/eukrea_cpuimx25/Makefile b/arch/arm/boards/eukrea_cpuimx25/Makefile deleted file mode 100644 index 159701d37a..0000000000 --- a/arch/arm/boards/eukrea_cpuimx25/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -obj-y += eukrea_cpuimx25.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx25 diff --git a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/bin/init_board b/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/bin/init_board deleted file mode 100644 index 8f4151c357..0000000000 --- a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/bin/init_board +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/sh - -if [ -f /env/logo.bmp ]; then - splash /env/logo.bmp - fb0.enable=1 -elif [ -f /env/logo.bmp.lzo ]; then - uncompress /env/logo.bmp.lzo /logo.bmp - splash /logo.bmp - fb0.enable=1 -fi - -if [ ! -z $use_dfu ]; then - gpio_get_value 82 - if [ $? -eq 0 ]; then - gpio_set_value 83 0 - usbserial - timeout -s -a 2 - gpio_get_value 82 - if [ $? -eq 0 ]; then - usbserial -d - dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r - gpio_get_value 82 - if [ $? -eq 0 ]; then - usbserial - autoboot_timeout=60 - else - reset - fi - else - autoboot_timeout=28 - fi - fi -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" - saveenv -fi diff --git a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/config b/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/config deleted file mode 100644 index da19677574..0000000000 --- a/arch/arm/boards/eukrea_cpuimx25/defaultenv-eukrea_cpuimx25/config +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -# otg port mode : can be 'host' or 'device' -otg_mode="device" -# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA -video="CMO-QVGA" - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=none - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp' or 'nand' -kernel_loc=nand -# can be either 'net', 'nand' or 'initrd' -rootfs_loc=nand - -# rootfs -rootfs_type=ubifs -rootfsimage=${global.hostname}/rootfs.$rootfs_type - -# kernel -kernelimage=${global.hostname}/uImage-${global.hostname}.bin - -# barebox and it's env -bareboximage=${global.hostname}/barebox-${global.hostname}.bin -bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin - -nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}" - -autoboot_timeout=1 - -bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=imxfb:$video" - -nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)" -rootfs_mtdblock_nand=3 -nand_device="mxc_nand" -ubiroot="${global.hostname}-rootfs" -device_type="nand" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c deleted file mode 100644 index 76d6f5ba86..0000000000 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <gpio.h> -#include <environment.h> -#include <mach/imx25-regs.h> -#include <asm/armlinux.h> -#include <asm/barebox-arm.h> -#include <asm/sections.h> -#include <io.h> -#include <asm/mmu.h> -#include <led.h> -#include <envfs.h> - -#include <partition.h> -#include <generated/mach-types.h> -#include <mach/imx-nand.h> -#include <mach/imxfb.h> -#include <mach/iim.h> -#include <platform_data/eth-fec.h> -#include <nand.h> -#include <mach/iomux-mx25.h> -#include <i2c/i2c.h> -#include <usb/fsl_usb2.h> -#include <mach/usb.h> -#include <mach/devices-imx25.h> -#include <asm/barebox-arm-head.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, - .phy_addr = 0, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, -}; - -static struct fb_videomode imxfb_mode = { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = KHZ2PICOS(6500), - .hsync_len = 30, - .left_margin = 38, - .right_margin = 20, - .vsync_len = 3, - .upper_margin = 15, - .lower_margin = 4, -}; - -static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = { - .mode = &imxfb_mode, - .num_modes = 1, - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x80040060, - .pcr = 0xCAD08B80, - .bpp = 16, -}; - -struct gpio_led led0 = { - .gpio = 2 * 32 + 19, - .active_low = 1, -}; - -static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = { - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - /* UART1 */ - MX25_PAD_UART1_RXD__UART1_RXD, - MX25_PAD_UART1_TXD__UART1_TXD, - MX25_PAD_UART1_RTS__UART1_RTS, - MX25_PAD_UART1_CTS__UART1_CTS, - /* LCDC */ - MX25_PAD_LD0__LD0, - MX25_PAD_LD1__LD1, - MX25_PAD_LD2__LD2, - MX25_PAD_LD3__LD3, - MX25_PAD_LD4__LD4, - MX25_PAD_LD5__LD5, - MX25_PAD_LD6__LD6, - MX25_PAD_LD7__LD7, - MX25_PAD_LD8__LD8, - MX25_PAD_LD9__LD9, - MX25_PAD_LD10__LD10, - MX25_PAD_LD11__LD11, - MX25_PAD_LD12__LD12, - MX25_PAD_LD13__LD13, - MX25_PAD_LD14__LD14, - MX25_PAD_LD15__LD15, - MX25_PAD_GPIO_E__LD16, - MX25_PAD_GPIO_F__LD17, - MX25_PAD_LSCLK__LSCLK, - MX25_PAD_OE_ACD__OE_ACD, - MX25_PAD_VSYNC__VSYNC, - MX25_PAD_HSYNC__HSYNC, - /* BACKLIGHT CONTROL */ - MX25_PAD_PWM__GPIO_1_26, - /* I2C */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, - /* SDCard */ - MX25_PAD_SD1_CLK__SD1_CLK, - MX25_PAD_SD1_CMD__SD1_CMD, - MX25_PAD_SD1_DATA0__SD1_DATA0, - MX25_PAD_SD1_DATA1__SD1_DATA1, - MX25_PAD_SD1_DATA2__SD1_DATA2, - MX25_PAD_SD1_DATA3__SD1_DATA3, - /* LED */ - MX25_PAD_POWER_FAIL__GPIO_3_19, - /* SWITCH */ - MX25_PAD_VSTBY_ACK__GPIO_3_18, -}; - -#ifdef CONFIG_USB -#ifndef CONFIG_USB_GADGET -struct imxusb_platformdata otg_pdata = { - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, - .mode = IMX_USB_MODE_HOST, - .phymode = USBPHY_INTERFACE_MODE_UTMI, -}; -#endif - -struct imxusb_platformdata hs_pdata = { - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, - .mode = IMX_USB_MODE_HOST, -}; -#endif - -#ifdef CONFIG_USB_GADGET -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; -#endif - -static int eukrea_cpuimx25_devices_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, - ARRAY_SIZE(eukrea_cpuimx25_pads)); - - led_gpio_register(&led0); - - imx25_iim_register_fec_ethaddr(); - imx25_add_fec(&fec_info); - - nand_info.width = 1; - imx25_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, - DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", 0x40000, 0x20000, - DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - /* enable LCD */ - gpio_direction_output(26, 1); - gpio_set_value(26, 1); - - /* LED : default OFF */ - gpio_direction_output(2 * 32 + 19, 1); - - /* Switch : input */ - gpio_direction_input(2 * 32 + 18); - - imx25_add_fb(&eukrea_cpuimx25_fb_data); - -#ifdef CONFIG_USB_GADGET - /* Workaround ENGcm09152 */ - writel(readl(MX25_USB_OTG_BASE_ADDR + 0x608) | (1 << 23), MX25_USB_OTG_BASE_ADDR + 0x608); - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX25_USB_OTG_BASE_ADDR, 0x200, - IORESOURCE_MEM, &usb_pdata); -#endif - -#ifdef CONFIG_USB -#ifndef CONFIG_USB_GADGET - imx_add_usb((void *)MX25_USB_OTG_BASE_ADDR, 0, &otg_pdata); -#endif - imx_add_usb((void *)MX25_USB_HS_BASE_ADDR, 1, &hs_pdata); -#endif - - imx25_add_mmc0(NULL); - imx25_add_i2c0(NULL); - - armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25SD); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_eukrea_cpuimx25); - - return 0; -} - -device_initcall(eukrea_cpuimx25_devices_init); - -static int eukrea_cpuimx25_console_init(void) -{ - barebox_set_model("Eukrea CPUIMX25"); - barebox_set_hostname("eukrea-cpuimx25"); - - imx25_add_uart0(); - return 0; -} - -console_initcall(eukrea_cpuimx25_console_init); diff --git a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg deleted file mode 100644 index b0c3b69b46..0000000000 --- a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg +++ /dev/null @@ -1,17 +0,0 @@ -soc imx25 -loadaddr 0x80000000 -dcdofs 0x400 - -wm 32 0xb8001008 0x00000000 -wm 32 0xb8001010 0x00000004 -wm 32 0xb8001000 0x92100000 -wm 8 0x80000400 0x12344321 -wm 32 0xb8001000 0xa2100000 -wm 32 0x80000000 0x12344321 -wm 32 0x80000000 0x12344321 -wm 32 0xb8001000 0xb2100000 -wm 8 0x80000033 0xda -wm 8 0x81000000 0xff -wm 32 0xb8001000 0x82216080 -wm 32 0xb8001004 0x00295729 -wm 32 0x53f80008 0x20034000 diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c deleted file mode 100644 index c16316d4a1..0000000000 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <mach/imx25-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/sections.h> -#include <asm-generic/memory_layout.h> -#include <asm/system.h> - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - uint32_t r; - register uint32_t loops = 0x20000; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE); - - /* restart the MPLL and wait until it's stable */ - writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27), - MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); - while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {}; - - /* Configure dividers and ARM clock source - * ARM @ 400 MHz - * AHB @ 133 MHz - */ - writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); - - /* Enable UART1 / FEC / */ -/* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0); - writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1); - writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2);*/ - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, 0x43f00000); - writel(0x77777777, 0x43f00004); - writel(0x77777777, 0x53f00000); - writel(0x77777777, 0x53f00004); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup - * MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB - */ - writel(0x00002143, 0x43f04000); - writel(0x00002143, 0x43f04100); - writel(0x00002143, 0x43f04200); - writel(0x00002143, 0x43f04300); - writel(0x00002143, 0x43f04400); - /* SGPCR - always park on last master */ - writel(0x10, 0x43f04010); - writel(0x10, 0x43f04110); - writel(0x10, 0x43f04210); - writel(0x10, 0x43f04310); - writel(0x10, 0x43f04410); - /* MGPCR - restore default values */ - writel(0x0, 0x43f04800); - writel(0x0, 0x43f04900); - writel(0x0, 0x43f04a00); - writel(0x0, 0x43f04b00); - writel(0x0, 0x43f04c00); - - /* Configure M3IF registers - * M3IF Control Register (M3IFCTL) for MX25 - * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001 - * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000 - * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000 - * MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 - * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000 - * MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000 - * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000 - * ---------- - * 0x00000001 - */ - writel(0x1, 0xb8003000); - - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); - r &= ~0xf; - r |= 0x1; - writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0x90000000) - goto out; - - /* Init Mobile DDR */ - writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); - - writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400); - writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX25_CSD0_BASE_ADDR); - writeb(0xda, MX25_CSD0_BASE_ADDR); - writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33); - writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); - writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx25_barebox_boot_nand_external(0); - -out: - imx25_barebox_entry(NULL); -} diff --git a/arch/arm/boards/eukrea_cpuimx27/Makefile b/arch/arm/boards/eukrea_cpuimx27/Makefile deleted file mode 100644 index 2c3148abd0..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/Makefile +++ /dev/null @@ -1,3 +0,0 @@ - -lwl-y += lowlevel_init.o -obj-y += eukrea_cpuimx27.o diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/_update b/arch/arm/boards/eukrea_cpuimx27/env/bin/_update deleted file mode 100644 index 014bce3512..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot deleted file mode 100644 index 0e1c80a932..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot +++ /dev/null @@ -1,53 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xnand ]; then - root=nand - kernel=nand -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$1 = xnor ]; then - root=nor - kernel=nor -fi - -if [ x$root = xnet ]; then - if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" - else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" - fi -else - bootargs="$bootargs ip=off" -fi - -if [ x$rootfstype = xubifs ]; then - bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum rootfstype=ubifs" -else - if [ x$root = xnand ]; then - bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" - elif [ x$root = xnor ]; then - bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" - fi -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -elif [ $kernel = nor ]; then - bootm /dev/nor0.kernel -else - bootm /dev/nand0.kernel.bb -fi - diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/init b/arch/arm/boards/eukrea_cpuimx27/env/bin/init deleted file mode 100644 index e3c109135a..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/env/bin/init +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -if [ -e /dev/nor0 ]; then - addpart /dev/nor0 $nor_parts -fi - -if [ -e /dev/nand0 ]; then - addpart /dev/nand0 $nand_parts -fi - -if [ -f /env/logo.bmp ]; then - splash /env/logo.bmp - fb0.enable=1 -elif [ -f /env/logo.bmp.lzo ]; then - uncompress /env/logo.bmp.lzo /logo.bmp - splash /logo.bmp - fb0.enable=1 -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" - saveenv -fi - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" - echo "type update_root nand|nor [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel deleted file mode 100644 index 05c822d860..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_kernel +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -if [ x$1 = xnand ]; then - part=/dev/nand0.kernel.bb -elif [ x$1 = xnor ]; then - part=/dev/nor0.kernel -else - echo "usage: $0 nor|nand [imagename]" - exit 1 -fi - -. /env/bin/_update $2 diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root b/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root deleted file mode 100644 index eaf36ebcea..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/env/bin/update_root +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -if [ x$1 = xnand ]; then - part=/dev/nand0.root.bb -elif [ x$1 = xnor ]; then - part=/dev/nor0.root -else - echo "usage: $0 nor|nand [imagename]" - exit 1 -fi - -. /env/bin/_update $2 - diff --git a/arch/arm/boards/eukrea_cpuimx27/env/config b/arch/arm/boards/eukrea_cpuimx27/env/config deleted file mode 100644 index 7f5600339f..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/env/config +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -# can be either 'net', 'nor' or 'nand'' -kernel=nor -root=nor -rootfstype=ubifs - -basedir=cpuimx27 -uimage=$basedir/uImage -rootfs=$basedir/rootfs - -autoboot_timeout=1 - -# DVI-SVGA DVI-VGA CMO-QVGA -video="CMO-QVGA" -bootargs="console=ttymxc0,115200 fec_mac=$eth0.ethaddr video=mxcfb:$video" - -nor_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)" -rootpart_nor="/dev/mtdblock3" - -nand_parts="-(nand)" -rootpart_nand="" - -rootpartnum=3 -ubiroot="eukrea-cpuimx27-rootfs" - -nfsroot="" - -# use 'dhcp' to do dhcp in barebox and in kernel -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c deleted file mode 100644 index 52971ed7ee..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (C) 2009 Eric Benard, Eukrea Electromatique - * Based on pcm038.c which is : - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <errno.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <mach/imx27-regs.h> -#include <notifier.h> -#include <gpio.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <asm/barebox-arm.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <fs.h> -#include <fcntl.h> -#include <nand.h> -#include <command.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <mach/imx-pll.h> -#include <mach/weim.h> -#include <mach/imxfb.h> -#include <platform_data/serial-ns16550.h> -#include <asm/mmu.h> -#include <i2c/i2c.h> -#include <mfd/lp3972.h> -#include <mach/iomux-mx27.h> -#include <mach/devices-imx27.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 1, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#ifdef CONFIG_DRIVER_SERIAL_NS16550 -static struct NS16550_plat quad_uart_serial_plat = { - .clock = 14745600, - .shift = 1, -}; - -#ifdef CONFIG_EUKREA_CPUIMX27_QUART1 -#define QUART_OFFSET 0x200000 -#elif defined CONFIG_EUKREA_CPUIMX27_QUART2 -#define QUART_OFFSET 0x400000 -#elif defined CONFIG_EUKREA_CPUIMX27_QUART3 -#define QUART_OFFSET 0x800000 -#elif defined CONFIG_EUKREA_CPUIMX27_QUART4 -#define QUART_OFFSET 0x1000000 -#endif -#endif - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("lp3972", 0x34), - }, -}; - -#ifdef CONFIG_DRIVER_VIDEO_IMX -static struct fb_videomode imxfb_mode = { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = 156000, - .hsync_len = 30, - .left_margin = 38, - .right_margin = 20, - .vsync_len = 3, - .upper_margin = 15, - .lower_margin = 4, -}; - -static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = { - .mode = &imxfb_mode, - .num_modes = 1, - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, - .pcr = 0xFAD08B80, - .bpp = 16, -}; -#endif - -static int eukrea_cpuimx27_devices_init(void) -{ - char *envdev = "no"; - int i; - - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, -#ifdef CONFIG_DRIVER_SERIAL_IMX - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, -#endif -#ifdef CONFIG_DRIVER_VIDEO_IMX - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA31_PF_OE_ACD, - GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT, - GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT, -#endif - }; - - /* configure 16 bit nor flash on cs0 */ - imx27_setup_weimcs(0, 0x00008F03, 0xA0330D01, 0x002208C0); - - /* initialize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx27_gpio_mode(mode[i]); - - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); -#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC2000000, 32 * 1024 * 1024, 0); -#endif - imx27_add_nand(&nand_info); - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - imx27_add_i2c0(NULL); - - devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - envdev = "NOR"; - - printf("Using environment in %s Flash\n", envdev); - -#ifdef CONFIG_DRIVER_VIDEO_IMX - imx_add_fb((void *)0x10021000, &eukrea_cpuimx27_fb_data); - gpio_direction_output(GPIO_PORTE | 5, 0); - gpio_set_value(GPIO_PORTE | 5, 1); - gpio_direction_output(GPIO_PORTA | 25, 0); - gpio_set_value(GPIO_PORTA | 25, 1); -#endif - - armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX27); - - return 0; -} - -device_initcall(eukrea_cpuimx27_devices_init); - -static int eukrea_cpuimx27_console_init(void) -{ - uint32_t val; - - barebox_set_model("Eukrea CPUIMX27"); - barebox_set_hostname("eukrea-cpuimx27"); - -#ifdef CONFIG_DRIVER_SERIAL_IMX - imx27_add_uart0(); -#endif - /* configure 8 bit UART on cs3 */ - val = readl(MX27_SYSCTRL_BASE_ADDR + MX27_FMCR); - val &= ~0x2; - writel(val, MX27_SYSCTRL_BASE_ADDR + MX27_FMCR); - - imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000); -#ifdef CONFIG_DRIVER_SERIAL_NS16550 - add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf, - IORESOURCE_MEM | IORESOURCE_MEM_16BIT, - &quad_uart_serial_plat); -#endif - return 0; -} - -console_initcall(eukrea_cpuimx27_console_init); - -static int eukrea_cpuimx27_late_init(void) -{ -#ifdef CONFIG_MFD_LP3972 - struct i2c_client *client; - u8 reg[1]; -#endif - console_flush(); - imx27_add_fec(&fec_info); - -#ifdef CONFIG_MFD_LP3972 - client = lp3972_get_client(); - if (!client) - return -ENODEV; - reg[0] = 0xa0; - i2c_write_reg(client, 0x39, reg, sizeof(reg)); -#endif - return 0; -} - -late_initcall(eukrea_cpuimx27_late_init); diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S deleted file mode 100644 index b3504832d7..0000000000 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ /dev/null @@ -1,134 +0,0 @@ -#include <config.h> -#include <asm-generic/memory_layout.h> -#include <mach/imx27-regs.h> -#include <mach/esdctl.h> -#include <asm/barebox-arm-head.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB -#define ROWS0 ESDCTL0_ROW14 -#define CFG0 0x0029572D -#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB -#define ROWS0 ESDCTL0_ROW13 -#define CFG0 0x00095728 -#endif - -#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10) - -.macro sdram_init - /* - * DDR on CSD0 - */ - /* Enable DDR SDRAM operation */ - writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - - /* Set the driving strength */ - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) - writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) - writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) - - /* Initial reset */ - writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0) - - /* precharge CSD0 all banks */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - - ldr r0, =0xa0000f00 - mov r1, #0 - mov r2, #8 -1: - str r1, [r0] - subs r2, #1 - bne 1b - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - ldr r0, =0xA0000033 - mov r1, #0xda - strb r1, [r0] -#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB - ldr r0, =0xA2000000 -#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB - ldr r0, =0xA1000000 -#endif - mov r1, #0xff - strb r1, [r0] - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) -.endm - - .section ".text_bare_init","ax" - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - - ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) - writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) - writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) - - /* disable mpll/spll */ - ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR - ldr r1, [r0] - bic r1, r1, #0x03 - str r1, [r0] - - /* - * pll clock initialization - see section 3.4.3 of the i.MX27 manual - */ - /* MPLL = 399 MHz */ - writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0) - /* SPLL = 240 MHz */ - writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) - writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, - MX27_CCM_BASE_ADDR + MX27_CSCR) - - /* add some delay here */ - mov r1, #0x1000 -1: subs r1, r1, #0x1 - bne 1b - - /* clock gating enable */ - writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) - - /* peripheral clock divider */ - /* FIXME */ - writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0) - /* PERDIV1=08 @133 MHz */ - writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1) - /* PERDIV1=04 @266 MHz */ - - /* skip sdram initialization if we run from ram */ - cmp pc, #0xa0000000 - bls 1f - cmp pc, #0xc0000000 - bhi 1f - - b imx27_barebox_entry -1: - sdram_init - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - mov r0, #0 - b imx27_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - -ret: - b imx27_barebox_entry diff --git a/arch/arm/boards/eukrea_cpuimx35/Makefile b/arch/arm/boards/eukrea_cpuimx35/Makefile deleted file mode 100644 index 3ef2c4e5f5..0000000000 --- a/arch/arm/boards/eukrea_cpuimx35/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -obj-y += eukrea_cpuimx35.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx35 diff --git a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board b/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board deleted file mode 100644 index 2a07a8425a..0000000000 --- a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/bin/init_board +++ /dev/null @@ -1,41 +0,0 @@ -#!/bin/sh - -if [ -f /env/logo.bmp ]; then - splash /env/logo.bmp - fb0.enable=1 - gpio_set_value 1 1 -elif [ -f /env/logo.bmp.lzo ]; then - uncompress /env/logo.bmp.lzo /logo.bmp - splash /logo.bmp - fb0.enable=1 - gpio_set_value 1 1 -fi - -gpio_get_value 89 -if [ $? -eq 0 ]; then - gpio_set_value 93 0 - usbserial - timeout -s -a 2 - gpio_get_value 89 - if [ $? -eq 0 ]; then - usbserial -d - dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r - gpio_get_value 89 - if [ $? -eq 0 ]; then - usbserial - autoboot_timeout=60 - else - reset - fi - else - autoboot_timeout=28 - fi -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" - saveenv -fi diff --git a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config b/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config deleted file mode 100644 index 05c4391d35..0000000000 --- a/arch/arm/boards/eukrea_cpuimx35/defaultenv-eukrea_cpuimx35/config +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -# otg port mode : can be 'host' or 'device' -otg_mode="device" -# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA -video="CMO-QVGA" - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=none - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp' or 'nand' -kernel_loc=nand -# can be either 'net', 'nand' or 'initrd' -rootfs_loc=nand - -# rootfs -rootfs_type=ubifs -rootfsimage=${global.hostname}/rootfs.$rootfs_type - -# kernel -kernelimage=${global.hostname}/uImage-${global.hostname}.bin - -# barebox and it's env -bareboximage=${global.hostname}/barebox-${global.hostname}.bin -bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin - -nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}" - -autoboot_timeout=1 - -bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=mx3fb:$video" - -nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)" -rootfs_mtdblock_nand=3 -nand_device="mxc_nand" -ubiroot="${global.hostname}-rootfs" -device_type="nand" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c deleted file mode 100644 index a10763780e..0000000000 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * 2009 Marc Kleine-Budde, Pengutronix - * (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Derived from: - * - * * mx35_3stack.c - board file for uboot-v1 - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - */ - -#include <common.h> -#include <command.h> -#include <environment.h> -#include <errno.h> -#include <fcntl.h> -#include <platform_data/eth-fec.h> -#include <fs.h> -#include <init.h> -#include <nand.h> -#include <net.h> -#include <partition.h> -#include <gpio.h> -#include <envfs.h> - -#include <asm/armlinux.h> -#include <io.h> -#include <generated/mach-types.h> -#include <asm/mmu.h> - -#include <mach/imx-nand.h> -#include <mach/imx35-regs.h> -#include <mach/iomux-mx35.h> -#include <mach/iomux-v3.h> -#include <mach/imx-ipu-fb.h> -#include <mach/imx-pll.h> -#include <i2c/i2c.h> -#include <usb/fsl_usb2.h> -#include <mach/usb.h> -#include <mach/devices-imx35.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 0, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct fb_videomode imxfb_mode = { - .name = "CMO_QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = KHZ2PICOS(7000), - .left_margin = 68, - .right_margin = 20, - .upper_margin = 15, - .lower_margin = 4, - .hsync_len = 30, - .vsync_len = 3, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static void eukrea_cpuimx35_enable_display(int enable) -{ - gpio_direction_output(4, enable); -} - -static struct imx_ipu_fb_platform_data ipu_fb_data = { - .mode = &imxfb_mode, - .num_modes = 1, - .bpp = 16, - .enable = eukrea_cpuimx35_enable_display, -}; - -#ifdef CONFIG_USB -#ifndef CONFIG_USB_GADGET -struct imxusb_platformdata otg_pdata = { - .flags = MXC_EHCI_INTERFACE_DIFF_UNI, - .mode = IMX_USB_MODE_HOST, - .phymode = USBPHY_INTERFACE_MODE_UTMI, -}; -#endif - -struct imxusb_platformdata hs_pdata = { - .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, - .mode = IMX_USB_MODE_HOST, -}; -#endif - -#ifdef CONFIG_USB_GADGET -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; -#endif - -static int eukrea_cpuimx35_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(eukrea_cpuimx35_mmu_init); - -static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - - MX35_PAD_RXD1__UART1_RXD_MUX, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_CTS1__UART1_CTS, - - MX35_PAD_LD23__GPIO3_29, - MX35_PAD_CONTRAST__GPIO1_1, - MX35_PAD_D3_CLS__GPIO1_4, - - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - - MX35_PAD_LD19__GPIO3_25, -}; - -static int eukrea_cpuimx35_devices_init(void) -{ -#ifdef CONFIG_USB_GADGET - unsigned int tmp; -#endif - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, - ARRAY_SIZE(eukrea_cpuimx35_pads)); - - imx35_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - imx35_add_fec(&fec_info); - imx35_add_fb(&ipu_fb_data); - - imx35_add_i2c0(NULL); - imx35_add_mmc0(NULL); - - /* led default off */ - gpio_direction_output(32 * 2 + 29, 1); - - /* Switch : input */ - gpio_direction_input(32 * 2 + 25); - - /* screen default on to prevent flicker */ - gpio_direction_output(4, 0); - /* backlight default off */ - gpio_direction_output(1, 0); - -#ifdef CONFIG_USB -#ifndef CONFIG_USB_GADGET - imx_add_usb((void *)MX35_USB_OTG_BASE_ADDR, 0, &otg_pdata); -#endif - imx_add_usb((void *)MX35_USB_HS_BASE_ADDR, 1, &hs_pdata); -#endif - -#ifdef CONFIG_USB_GADGET - /* Workaround ENGcm09152 */ - tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608); - writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608); - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX35_USB_OTG_BASE_ADDR, 0x200, - IORESOURCE_MEM, &usb_pdata); -#endif - armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35SD); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_eukrea_cpuimx35); - - return 0; -} - -device_initcall(eukrea_cpuimx35_devices_init); - -static int eukrea_cpuimx35_console_init(void) -{ - barebox_set_model("Eukrea CPUIMX35"); - barebox_set_hostname("eukrea-cpuimx35"); - - imx35_add_uart0(); - return 0; -} - -console_initcall(eukrea_cpuimx35_console_init); - -static int eukrea_cpuimx35_core_init(void) -{ - u32 reg; - - /* enable clock for I2C1, ESDHC1, USB and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - reg |= 0x3 << MX35_CCM_CGR0_ESDHC1_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT, - reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); - reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); - reg &= 0x00FFFFFF; - writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); - reg &= 0x00FFFFFF; - writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - writel(0x40, MX35_M3IF_BASE_ADDR); - - return 0; -} - -core_initcall(eukrea_cpuimx35_core_init); - -static int do_cpufreq(int argc, char *argv[]) -{ - unsigned long freq; - - if (argc != 2) - return COMMAND_ERROR_USAGE; - - freq = simple_strtoul(argv[1], NULL, 0); - - switch (freq) { - case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - default: - return COMMAND_ERROR_USAGE; - } - - printf("Switched CPU frequency to %luMHz\n", freq); - - return 0; -} - -BAREBOX_CMD_START(cpufreq) - .cmd = do_cpufreq, - BAREBOX_CMD_DESC("adjust CPU frequency") - BAREBOX_CMD_OPTS("399|532") - BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) -BAREBOX_CMD_END diff --git a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg deleted file mode 100644 index 85200bbb50..0000000000 --- a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg +++ /dev/null @@ -1,19 +0,0 @@ -soc imx35 -loadaddr 0x80000000 -dcdofs 0x400 - -wm 32 0x53F80004 0x00821000 -wm 32 0x53F80004 0x00821000 -wm 32 0xb8001010 0x00000004 -wm 32 0xB8001010 0x0000000C -wm 32 0xb8001004 0x0009572B -wm 32 0xb8001000 0x92220000 -wm 8 0x80000400 0xda -wm 32 0xb8001000 0xa2220000 -wm 32 0x80000000 0x12344321 -wm 32 0x80000000 0x12344321 -wm 32 0xb8001000 0xb2220000 -wm 8 0x80000033 0xda -wm 8 0x82000000 0xda -wm 32 0xb8001000 0x82224080 -wm 32 0xb8001010 0x00000004 diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c deleted file mode 100644 index ab5235f7f0..0000000000 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <mach/imx35-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/cache-l2x0.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/sections.h> -#include <asm-generic/memory_layout.h> -#include <asm/system.h> - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - uint32_t r, s; - unsigned long ccm_base = MX35_CCM_BASE_ADDR; - register uint32_t loops = 0x20000; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE); - - r = get_cr(); - r |= CR_Z; /* Flow prediction (Z) */ - r |= CR_U; /* unaligned accesses */ - r |= CR_FI; /* Low Int Latency */ - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); - s |= 0x7; - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); - - set_cr(r); - - r = 0; - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * Branch predicition is now enabled. Flush the BTAC to ensure a valid - * starting point. Don't flush BTAC while it is disabled to avoid - * ARM1136 erratum 408023. - */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); - - /* invalidate I cache and D cache */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); - - /* invalidate TLBs */ - __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); - - /* Drain the write buffer */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); - - /* Also setup the Peripheral Port Remap register inside the core */ - r = 0x40000015; /* start from AIPS 2GB region */ - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * End of ARM1136 init - */ - - writel(0x003F4208, ccm_base + MX35_CCM_CCMR); - - /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - - writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); - writel(0x00001000, ccm_base + MX35_CCM_PDR0); - - r = readl(ccm_base + MX35_CCM_CGR0); - r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR0); - - r = readl(ccm_base + MX35_CCM_CGR1); - r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR1); - - /* enable watchdog asap */ - r = readl(ccm_base + MX35_CCM_CGR2); - r |= 0x3 << MX35_CCM_CGR2_WDOG_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR2); - - r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - r |= 0x1000; - writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0x90000000) - goto out; - - /* Init Mobile DDR */ - writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); - - writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); - writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX35_CSD0_BASE_ADDR); - writeb(0xda, MX35_CSD0_BASE_ADDR); - writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); - writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); - writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - imx35_barebox_boot_nand_external(0); - } - -out: - imx35_barebox_entry(NULL); -} diff --git a/arch/arm/boards/eukrea_cpuimx51/Makefile b/arch/arm/boards/eukrea_cpuimx51/Makefile deleted file mode 100644 index e8c84fe17d..0000000000 --- a/arch/arm/boards/eukrea_cpuimx51/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += eukrea_cpuimx51.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-eukrea_cpuimx51 diff --git a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/bin/init_board b/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/bin/init_board deleted file mode 100644 index 0af65822f1..0000000000 --- a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/bin/init_board +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -if [ -f /env/logo.bmp ]; then - splash /env/logo.bmp - fb0.enable=1 - gpio_set_value 1 1 -elif [ -f /env/logo.bmp.lzo ]; then - uncompress /env/logo.bmp.lzo /logo.bmp - splash /logo.bmp - fb0.enable=1 - gpio_set_value 1 1 -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" - saveenv -fi diff --git a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/config b/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/config deleted file mode 100644 index 57abc1ee3d..0000000000 --- a/arch/arm/boards/eukrea_cpuimx51/defaultenv-eukrea_cpuimx51/config +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -# otg port mode : can be 'host' or 'device' -otg_mode="device" -# video mode : can be 'CMO-QVGA' or 'URT-WVGA' or any modefb mode -# ex : 640x480M-16@60 800x600M-24@60 1024x768M-16@60 -video="CMO-QVGA" -# screen type : can be 'tft' or 'dvi' -screen_type="tft" - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=none - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp' or 'nand' -kernel_loc=nand -# can be either 'net', 'nand' or 'initrd' -rootfs_loc=nand - -# rootfs -rootfs_type=ubifs -rootfsimage=${global.hostname}/rootfs.$rootfs_type - -# kernel -kernelimage=${global.hostname}/uImage-${global.hostname}.bin - -# barebox and it's env -bareboximage=${global.hostname}/barebox-${global.hostname}.bin -bareboxenvimage=${global.hostname}/bareboxenv-${global.hostname}.bin - -nfsroot="$eth0.serverip:/srv/nfs/${global.hostname}" - -autoboot_timeout=1 - -bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=$video screen_type=$screen_type" - -nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)" -rootfs_mtdblock_nand=3 -nand_device="mxc_nand" -ubiroot="${global.hostname}-rootfs" -device_type="nand" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c deleted file mode 100644 index bb493d7c64..0000000000 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * (c) 2011 Eukrea Electromatique, Eric Bénard <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <mach/imx51-regs.h> -#include <platform_data/eth-fec.h> -#include <gpio.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <fs.h> -#include <envfs.h> -#include <fcntl.h> -#include <nand.h> -#include <spi/spi.h> -#include <io.h> -#include <asm/mmu.h> -#include <mach/imx-nand.h> -#include <mach/spi.h> -#include <mach/generic.h> -#include <mach/imx5.h> -#include <mach/iomux-mx51.h> -#include <mach/devices-imx51.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - /* FEC */ - NEW_PAD_CTRL(MX51_PAD_DISP2_DAT1__FEC_RX_ER, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT15__FEC_TDATA0, - MX51_PAD_DISP2_DAT6__FEC_TDATA1, - MX51_PAD_DISP2_DAT7__FEC_TDATA2, - MX51_PAD_DISP2_DAT8__FEC_TDATA3, - MX51_PAD_DISP2_DAT9__FEC_TX_EN, - NEW_PAD_CTRL(MX51_PAD_DISP2_DAT10__FEC_COL, MX51_PAD_CTRL_5), - NEW_PAD_CTRL(MX51_PAD_DISP2_DAT11__FEC_RX_CLK, MX51_PAD_CTRL_5), - NEW_PAD_CTRL(MX51_PAD_DISP2_DAT12__FEC_RX_DV, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT13__FEC_TX_CLK, - MX51_PAD_DI2_PIN4__FEC_CRS, - MX51_PAD_DI2_PIN2__FEC_MDC, - NEW_PAD_CTRL(MX51_PAD_DI2_PIN3__FEC_MDIO, MX51_PAD_CTRL_5), - MX51_PAD_DISP2_DAT14__FEC_RDATA0, - MX51_PAD_DI2_DISP_CLK__FEC_RDATA1, - NEW_PAD_CTRL(MX51_PAD_DI_GP4__FEC_RDATA2, MX51_PAD_CTRL_5), - NEW_PAD_CTRL(MX51_PAD_DISP2_DAT0__FEC_RDATA3, MX51_PAD_CTRL_5), - MX51_PAD_DI_GP3__FEC_TX_ER, - MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */ - /* NAND */ - MX51_PAD_NANDF_D7__NANDF_D7, - MX51_PAD_NANDF_D6__NANDF_D6, - MX51_PAD_NANDF_D5__NANDF_D5, - MX51_PAD_NANDF_D4__NANDF_D4, - MX51_PAD_NANDF_D3__NANDF_D3, - MX51_PAD_NANDF_D2__NANDF_D2, - MX51_PAD_NANDF_D1__NANDF_D1, - MX51_PAD_NANDF_D0__NANDF_D0, - MX51_PAD_NANDF_RB0__NANDF_RB0, - MX51_PAD_NANDF_RB1__NANDF_RB1, - MX51_PAD_NANDF_CS0__NANDF_CS0, - MX51_PAD_NANDF_CS1__NANDF_CS1, - /* LCD BL */ - MX51_PAD_DI1_D1_CS__GPIO3_4, -#ifdef CONFIG_MCI_IMX_ESDHC - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, -#endif -}; - -#define GPIO_LAN8700_RESET (1 * 32 + 31) -#define GPIO_LCD_BL (2 * 32 + 4) - -static int eukrea_cpuimx51_devices_init(void) -{ - imx51_add_fec(&fec_info); -#ifdef CONFIG_MCI_IMX_ESDHC - imx51_add_mmc0(NULL); -#endif - imx51_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - gpio_direction_output(GPIO_LAN8700_RESET, 0); - gpio_set_value(GPIO_LAN8700_RESET, 1); - gpio_direction_output(GPIO_LCD_BL, 0); - - armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_eukrea_cpuimx51); - - return 0; -} - -device_initcall(eukrea_cpuimx51_devices_init); - -static int eukrea_cpuimx51_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads)); - - barebox_set_model("Eukrea CPUIMX51"); - barebox_set_hostname("eukrea-cpuimx51"); - - imx51_init_lowlevel(800); - - imx51_add_uart0(); - - return 0; -} - -console_initcall(eukrea_cpuimx51_console_init); diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c deleted file mode 100644 index 6762fdad4b..0000000000 --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c +++ /dev/null @@ -1,11 +0,0 @@ -#include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> -#include <asm/barebox-arm-head.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - imx5_cpu_lowlevel_init(); - arm_setup_stack(0x20000000); - imx51_barebox_entry(NULL); -} diff --git a/arch/arm/boards/freescale-mx21-ads/Makefile b/arch/arm/boards/freescale-mx21-ads/Makefile deleted file mode 100644 index a43425b9ea..0000000000 --- a/arch/arm/boards/freescale-mx21-ads/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -lwl-y += lowlevel_init.o -obj-y += imx21ads.o diff --git a/arch/arm/boards/freescale-mx21-ads/env/bin/init b/arch/arm/boards/freescale-mx21-ads/env/bin/init deleted file mode 100644 index 224a6b40be..0000000000 --- a/arch/arm/boards/freescale-mx21-ads/env/bin/init +++ /dev/null @@ -1 +0,0 @@ -# Dummy Init environment script diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c deleted file mode 100644 index 2c54cd7030..0000000000 --- a/arch/arm/boards/freescale-mx21-ads/imx21ads.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2009 Ivo Clarysse - * - * Based on imx27ads.c, - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <mach/imx21-regs.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <asm/barebox-arm.h> -#include <io.h> -#include <gpio.h> -#include <mach/weim.h> -#include <partition.h> -#include <fs.h> -#include <linux/sizes.h> -#include <fcntl.h> -#include <generated/mach-types.h> -#include <mach/imx-nand.h> -#include <mach/imxfb.h> -#include <mach/iomux-mx21.h> -#include <mach/devices-imx21.h> - -#define MX21ADS_IO_REG 0xCC800000 -#define MX21ADS_IO_LCDON (1 << 9) - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, -}; - -/* Sharp LQ035Q7DB02 QVGA display */ -static struct fb_videomode imx_fb_modedata = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, - .left_margin = 6, - .right_margin = 16, - .upper_margin = 8, - .lower_margin = 10, - .hsync_len = 2, - .vsync_len = 1, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct imx_fb_platform_data imx_fb_data = { - .mode = &imx_fb_modedata, - .num_modes = 1, - .cmap_greyscale = 0, - .cmap_inverse = 0, - .cmap_static = 0, - .pwmr = 0x00a903ff, - .lscr1 = 0x00120300, - .dmacr = 0x00020008, - .pcr = 0xfb108bc7, - .bpp = 16, -}; - -static int imx21ads_timing_init(void) -{ - u32 temp; - - /* Configure External Interface Module */ - /* CS0: burst flash */ - imx21_setup_eimcs(0, 0x00003E00, 0x00000E01); - - /* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */ - imx21_setup_eimcs(1, 0x00002000, 0x11118501); - - /* CS2-CS5: disable */ - imx21_setup_eimcs(2, 0x0, 0x0); - imx21_setup_eimcs(3, 0x0, 0x0); - imx21_setup_eimcs(4, 0x0, 0x0); - imx21_setup_eimcs(5, 0x0, 0x0); - - temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0); - temp &= ~0xF000; - temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */ - writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0); - - return 0; -} - -core_initcall(imx21ads_timing_init); - -static int mx21ads_mem_init(void) -{ - arm_add_mem_device("ram0", 0xc0000000, SZ_64M); - - return 0; -} -mem_initcall(mx21ads_mem_init); - -static int mx21ads_devices_init(void) -{ - int i; - unsigned int mode[] = { - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - }; - - /* initizalize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx21_gpio_mode(mode[i]); - - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR, - 32 * 1024 * 1024, 0); - imx21_add_nand(&nand_info); - add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, - MX21_CS1_BASE_ADDR, 0x1000, - IORESOURCE_MEM, NULL); - imx21_add_fb(&imx_fb_data); - - armlinux_set_architecture(MACH_TYPE_MX21ADS); - - return 0; -} - -device_initcall(mx21ads_devices_init); - -static int mx21ads_enable_display(void) -{ - u16 tmp; - - tmp = readw(MX21ADS_IO_REG); - tmp |= MX21ADS_IO_LCDON; - writew(tmp, MX21ADS_IO_REG); - return 0; -} - -late_initcall(mx21ads_enable_display); - -static int mx21ads_console_init(void) -{ - barebox_set_model("Freescale i.MX21 ADS"); - barebox_set_hostname("mx21ads"); - - imx21_add_uart0(); - return 0; -} - -console_initcall(mx21ads_console_init); diff --git a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S deleted file mode 100644 index 16739b5577..0000000000 --- a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2010 Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <config.h> -#include <linux/sizes.h> -#include <asm-generic/memory_layout.h> -#include <mach/imx21-regs.h> -#include <asm/barebox-arm-head.h> - - .section ".text_bare_init","ax" - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - -/* - * Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to - * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21 - * reference manual. - */ - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0 - ldr r1, =0x00040304 - str r1, [r0] - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1 - ldr r1, =0xfffbfcfb - str r1, [r0] - - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0 - ldr r1, =0x3ffc0000 - str r1, [r0] - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1 - ldr r1, =0xffffffff - str r1, [r0] - -/* - * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable - * the clock to peripherals. - */ - ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR - ldr r1, =0x17180607 - str r1, [r0] - - ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1 - ldr r1, =0x0e000000 - str r1, [r0] - - -/* - * SDRAM and SDRAM controller configuration - */ - - /* - * CSD1 not required, because the MX21ADS board only contains 64Mbyte. - * CS3 can therefore be made available. - */ - ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR - ldr r1, =0xffffffc9 - str r1, [r0] - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #0xc0000000 - bls 1f - cmp pc, #0xc8000000 - bhi 1f - - b ret -1: - - /* Precharge */ - ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0 - ldr r1, =0x92120300 - str r1, [r0] - ldr r2, =0xc0200000 - ldr r1, [r2] - - bl mem_delay - - /* Auto refresh */ - ldr r1, =0xa2120300 - str r1, [r0] - ldr r2, =0xc0000000 - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - - /* Set mode register */ - ldr r1, =0xB2120300 - str r1, [r0] - ldr r1, =0xC0119800 - ldr r2, [r1] - - bl mem_delay - - /* Back to Normal Mode */ - ldr r1, =0x8212F339 - str r1, [r0] - - /* Set NFC_CLK to 24MHz */ - ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0 - ldr r1, =0x6419a007 - str r1, [r0] - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - - /* Setup a temporary stack in SRAM */ - ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4 - - b imx21_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - -ret: - mov r0, #0xc0000000 - mov r1, #SZ_64M - mov r2, #0 - b barebox_arm_entry - -/* - * spin for a while. we need to wait at least 200 usecs. - */ -mem_delay: - mov r4, #0x4000 -spin: subs r4, r4, #1 - bne spin - mov pc, lr - diff --git a/arch/arm/boards/freescale-mx23-evk/Makefile b/arch/arm/boards/freescale-mx23-evk/Makefile index 3e0026252c..7723ad93b0 100644 --- a/arch/arm/boards/freescale-mx23-evk/Makefile +++ b/arch/arm/boards/freescale-mx23-evk/Makefile @@ -1,3 +1,4 @@ -# +# SPDX-License-Identifier: GPL-2.0-only + obj-y := mx23-evk.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx23-evk/lowlevel.c b/arch/arm/boards/freescale-mx23-evk/lowlevel.c index 99e08d88c7..195ade3a7f 100644 --- a/arch/arm/boards/freescale-mx23-evk/lowlevel.c +++ b/arch/arm/boards/freescale-mx23-evk/lowlevel.c @@ -1,12 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx23-regs.h> +#include <mach/mxs/imx23-regs.h> + +static noinline void continue_imx_entry(size_t size) +{ + static struct barebox_arm_boarddata boarddata = { + .magic = BAREBOX_ARM_BOARDDATA_MAGIC, + .machine = MACH_TYPE_MX23EVK, + }; + + barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); +} ENTRY_FUNCTION(start_imx23_evk, r0, r1, r2) { arm_cpu_lowlevel_init(); - barebox_arm_entry(IMX_MEMORY_BASE, SZ_32M, (void *)MACH_TYPE_MX23EVK); + + relocate_to_current_adr(); + setup_c(); + + continue_imx_entry(SZ_32M); } diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c index 75a7d5a6b4..d4de99eafb 100644 --- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c +++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c @@ -1,18 +1,6 @@ -/* - * (C) Copyright 2010 Juergen Beisert - Pengutronix - * (C) Copyright 2011 Wolfram Sang - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert, Pengutronix +// SPDX-FileCopyrightText: 2011 Wolfram Sang, Pengutronix #include <common.h> #include <init.h> @@ -21,14 +9,13 @@ #include <mci.h> #include <linux/err.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <asm/barebox-arm.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include <mach/mci.h> -#include <usb/fsl_usb2.h> -#include <mach/usb.h> -#include <mach/iomux.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/mci.h> +#include <linux/usb/fsl_usb2.h> +#include <mach/mxs/usb.h> +#include <mach/mxs/iomux.h> static struct mxs_mci_platform_data mci_pdata = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED, @@ -91,9 +78,7 @@ static int register_persistent_environment(void) /* use the full partition as our persistent environment storage */ cdev = devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); - if (IS_ERR(cdev)) - return PTR_ERR(cdev); - return 0; + return PTR_ERR_OR_ZERO(cdev); } static int mx23_evk_devices_init(void) diff --git a/arch/arm/boards/freescale-mx25-3ds/3stack.c b/arch/arm/boards/freescale-mx25-3ds/3stack.c deleted file mode 100644 index 3ab8c4ad52..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/3stack.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <gpio.h> -#include <environment.h> -#include <mach/imx25-regs.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <asm/barebox-arm.h> -#include <io.h> -#include <envfs.h> -#include <partition.h> -#include <generated/mach-types.h> -#include <mach/imx-nand.h> -#include <platform_data/eth-fec.h> -#include <nand.h> -#include <mach/iomux-mx25.h> -#include <mach/generic.h> -#include <mach/iim.h> -#include <linux/err.h> -#include <i2c/i2c.h> -#include <mfd/mc34704.h> -#include <mach/devices-imx25.h> -#include <asm/barebox-arm-head.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, - .phy_addr = 1, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, -}; - -#ifdef CONFIG_USB -static void imx25_usb_init(void) -{ - unsigned int tmp; - - /* Host 2 */ - tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~(3 << 21); - tmp |= (2 << 21) | (1 << 4) | (1 << 5); - writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584); - tmp |= 3 << 30; - writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584); - - /* Set to Host mode */ - tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8); - writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8); -} -#endif - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("mc34704", 0x54), - }, -}; - -static int imx25_3ds_pmic_init(void) -{ - struct mc34704 *pmic; - - pmic = mc34704_get(); - if (pmic == NULL) - return -EIO; - - return mc34704_reg_write(pmic, 0x2, 0x9); -} - -static int imx25_3ds_fec_init(void) -{ - int ret; - - ret = imx25_3ds_pmic_init(); - if (ret < 0) - return ret; - - /* - * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. - * Assert FEC_RESET_B, then power up the PHY by asserting - * FEC_ENABLE, at the same time lifting FEC_RESET_B. - * - * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 - * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 - */ - writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */ - writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */ - -#define FEC_ENABLE_GPIO 35 -#define FEC_RESET_B_GPIO 104 - - /* make the pins output */ - gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ - gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ - udelay(2); - - /* turn on power & lift reset */ - gpio_set_value(FEC_ENABLE_GPIO, 1); - gpio_set_value(FEC_RESET_B_GPIO, 1); - - return 0; -} -late_initcall(imx25_3ds_fec_init); - -static int imx25_3ds_devices_init(void) -{ -#ifdef CONFIG_USB - /* USB does not work yet. Don't know why. Maybe - * the CPLD has to be initialized. - */ - imx25_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL); -#endif - - imx25_iim_register_fec_ethaddr(); - imx25_add_fec(&fec_info); - - add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); - - if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) - nand_info.width = 2; - - imx25_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - imx25_add_i2c0(NULL); - - armlinux_set_architecture(MACH_TYPE_MX25_3DS); - armlinux_set_serial(imx_uid()); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_freescale_mx25_3ds); - - return 0; -} - -device_initcall(imx25_3ds_devices_init); - -static iomux_v3_cfg_t imx25_pads[] = { - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_POWER_FAIL__POWER_FAIL, - MX25_PAD_A17__GPIO_2_3, - MX25_PAD_D12__GPIO_4_8, - /* UART1 */ - MX25_PAD_UART1_RXD__UART1_RXD, - MX25_PAD_UART1_TXD__UART1_TXD, - MX25_PAD_UART1_RTS__UART1_RTS, - MX25_PAD_UART1_CTS__UART1_CTS, - /* USBH2 */ - MX25_PAD_D9__USBH2_PWR, - MX25_PAD_D8__USBH2_OC, - MX25_PAD_LD0__USBH2_CLK, - MX25_PAD_LD1__USBH2_DIR, - MX25_PAD_LD2__USBH2_STP, - MX25_PAD_LD3__USBH2_NXT, - MX25_PAD_LD4__USBH2_DATA0, - MX25_PAD_LD5__USBH2_DATA1, - MX25_PAD_LD6__USBH2_DATA2, - MX25_PAD_LD7__USBH2_DATA3, - MX25_PAD_HSYNC__USBH2_DATA4, - MX25_PAD_VSYNC__USBH2_DATA5, - MX25_PAD_LSCLK__USBH2_DATA6, - MX25_PAD_OE_ACD__USBH2_DATA7, - /* i2c */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, -}; - -static int imx25_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); - - writel(0x03010101, 0x53f80024); - - barebox_set_model("Freescale i.MX25 3DS"); - barebox_set_hostname("mx25-3stack"); - - imx25_add_uart0(); - return 0; -} - -console_initcall(imx25_console_init); - -static int imx25_core_setup(void) -{ - writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); - return 0; - -} -core_initcall(imx25_core_setup); diff --git a/arch/arm/boards/freescale-mx25-3ds/Makefile b/arch/arm/boards/freescale-mx25-3ds/Makefile deleted file mode 100644 index 20787efc94..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel_init.o -obj-y += 3stack.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-mx25-3ds diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/_update b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/_update deleted file mode 100644 index 014bce3512..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/boot b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/boot deleted file mode 100644 index 7bbff2d1f6..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/boot +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xnand ]; then - root=nand - kernel=nand -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$1 = xnor ]; then - root=nor - kernel=nor -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xnand ]; then - bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" -elif [ x$root = xnor ]; then - bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -elif [ $kernel = nor ]; then - bootm /dev/nor0.kernel -else - bootm /dev/nand0.kernel.bb -fi - diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/init b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/init deleted file mode 100644 index 8eafa34dc8..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/init +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -if [ -e /dev/nor0 ]; then - addpart /dev/nor0 $nor_parts -fi - -if [ -e /dev/nand0 ]; then - addpart /dev/nand0 $nand_parts -fi - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" - echo "type update_root nand|nor [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_kernel b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_kernel deleted file mode 100644 index 05c822d860..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_kernel +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -if [ x$1 = xnand ]; then - part=/dev/nand0.kernel.bb -elif [ x$1 = xnor ]; then - part=/dev/nor0.kernel -else - echo "usage: $0 nor|nand [imagename]" - exit 1 -fi - -. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_root b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_root deleted file mode 100644 index eaf36ebcea..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/bin/update_root +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -if [ x$1 = xnand ]; then - part=/dev/nand0.root.bb -elif [ x$1 = xnor ]; then - part=/dev/nor0.root -else - echo "usage: $0 nor|nand [imagename]" - exit 1 -fi - -. /env/bin/_update $2 - diff --git a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/config b/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/config deleted file mode 100644 index 8469935b20..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/defaultenv-freescale-mx25-3ds/config +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/sh - -# can be either 'net', 'nor' or 'nand'' -kernel=net -root=net - -uimage=uImage-pcm043 -jffs2=root-pcm043.jffs2 - -autoboot_timeout=3 - -nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root" -bootargs="console=ttymxc0,115200" - -nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)" -rootpart_nor="/dev/mtdblock3" - -nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),108416k(root),-(kernel1)" -rootpart_nand="/dev/mtdblock7" - -# use 'dhcp' to do dhcp in barebox and in kernel -#ip=dhcp - -# or set your networking parameters here -eth0.ipaddr=192.168.3.11 -eth0.netmask=255.255.255.0 -#eth0.gateway=a.b.c.d -eth0.serverip=192.168.3.10 -#eth0.ethaddr= diff --git a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg deleted file mode 100644 index f195e8c002..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg +++ /dev/null @@ -1,42 +0,0 @@ -soc imx25 -loadaddr 0x80000000 -dcdofs 0x400 -wm 32 0xb8002050 0x0000d843 -wm 32 0xb8002054 0x22252521 -wm 32 0xb8002058 0x22220a00 -#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 -wm 32 0xb8001004 0x0076e83a -wm 32 0xb8001010 0x00000304 -wm 32 0xb8001000 0x92210000 -wm 32 0x80000f00 0x12344321 -wm 32 0xb8001000 0xb2210000 -wm 8 0x82000000 0xda -wm 8 0x83000000 0xda -wm 8 0x81000400 0xda -wm 8 0x80000333 0xda -wm 32 0xb8001000 0x92210000 -wm 32 0x80000400 0x12344321 -wm 32 0xb8001000 0xa2210000 -wm 32 0x80000000 0x87654321 -wm 32 0x80000000 0x87654321 -wm 32 0xb8001000 0xb2210000 -wm 8 0x80000233 0xda -wm 8 0x81000780 0xda -wm 8 0x81000400 0xda -wm 32 0xb8001000 0x82216080 -#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR -wm 32 0xb8001010 0x00000004 -wm 32 0xb8001000 0x92100000 -wm 8 0x80000400 0x21 -wm 32 0xb8001000 0xa2100000 -wm 32 0x80000000 0x12344321 -wm 32 0x80000000 0x12344321 -wm 32 0xb8001000 0xb2100000 -wm 8 0x80000033 0xda -wm 8 0x81000000 0xff -wm 32 0xb8001000 0x82216880 -wm 32 0xb8001004 0x00295729 -#else -#error "Unsupported SDRAM type" -#endif -wm 32 0x53f80008 0x20034000 diff --git a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S deleted file mode 100644 index bf3830d8d6..0000000000 --- a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S +++ /dev/null @@ -1,229 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/sizes.h> -#include <asm-generic/memory_layout.h> -#include <mach/imx25-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/barebox-arm-head.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define writeb(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - strb r1, [r0]; - -/* Assuming 24MHz input clock */ -#define MPCTL_PARAM_532_MX25 \ - (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) - -.section ".text_bare_init","ax" - -ARM_PPMRR: .word 0x40000015 -L2CACHE_PARAM: .word 0x00030024 -CCM_CCMR_W: .word 0x003F4208 -CCM_PDR0_W: .word 0x00801000 -MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 -MPCTL_PARAM_532_W: .word MPCTL_PARAM_532_MX25 -PPCTL_PARAM_W: .word PPCTL_PARAM_300 -CCM_BASE_ADDR_W: .word MX25_CCM_BASE_ADDR - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - -#define MX25_CCM_MCR 0x64 - - ldr r0, CCM_BASE_ADDR_W - /* default CLKO to 1/32 of the ARM core */ - ldr r1, [r0, #MX25_CCM_MCR] - bic r1, r1, #0x00F00000 - bic r1, r1, #0x7F000000 - mov r2, #0x5F000000 - add r2, r2, #0x00200000 - orr r1, r1, r2 - str r1, [r0, #MX25_CCM_MCR] - - /* enable all the clocks */ - writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0) - writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1) - writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2) - writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) - - /* Setup a temporary stack in SRAM */ - ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #0x80000000 - bls 1f - cmp pc, #0x90000000 - bhi 1f - - b imx25_barebox_entry - -1: - ldr r0, ESDCTL_BASE_W - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - mov r12, #0x00 - mov r2, #0x1 /* mDDR */ - mov r1, #MX25_CSD0_BASE_ADDR - bl setup_sdram_bank -// cmp r3, #0x0 -// orreq r12, r12, #1 -// eorne r2, r2, #0x1 -// blne setup_sdram_bank - - ldr r3, ESDCTL_DELAY5 - str r3, [r0, #0x30] - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - - mov r0, #0 - b imx25_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - -ret: - b imx25_barebox_entry - -/* - * r0: control base, r1: ram bank base - * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working - */ -setup_sdram_bank: - mov r3, #0xE /* 0xA + 0x4 */ - tst r2, #0x1 - orreq r3, r3, #0x300 /* DDR2 */ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: adr r4, ESDCTL_CONFIG - tst r2, #0x1 - ldreq r3, [r4, #0x0] - ldrne r3, [r4, #0x4] - cmp r1, #MX25_CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, RAM_PARAM1_MDDR - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #MX25_CSD1_BASE_ADDR - ldr r3, ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, RAM_PARAM4_MDDR - strb r3, [r1, r4] - ldr r4, RAM_PARAM5_MDDR - strb r3, [r1, r4] - ldr r4, RAM_PARAM3_MDDR - strb r3, [r1, r4] - ldr r4, RAM_PARAM2_MDDR - strb r3, [r1, r4] - - ldr r3, ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, RAM_PARAM1_MDDR - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #MX25_CSD1_BASE_ADDR - ldr r3, ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - adr r4, RAM_PARAM6_MDDR - tst r2, #0x1 - ldreq r4, [r4, #0x0] - ldrne r4, [r4, #0x4] - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, RAM_PARAM7_MDDR - streqb r3, [r1, r4] - adr r4, RAM_PARAM3_MDDR - ldreq r4, [r4, #0x0] - ldrne r4, [r4, #0x4] - strb r3, [r1, r4] - - cmp r1, #MX25_CSD1_BASE_ADDR - ldr r3, ESDCTL_0x82226080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr - -RAM_PARAM1_MDDR: .word 0x00000400 -RAM_PARAM2_MDDR: .word 0x00000333 -RAM_PARAM3_MDDR: .word 0x02000400 - .word 0x02000000 -RAM_PARAM4_MDDR: .word 0x04000000 -RAM_PARAM5_MDDR: .word 0x06000000 -RAM_PARAM6_MDDR: .word 0x00000233 - .word 0x00000033 -RAM_PARAM7_MDDR: .word 0x02000780 -ESDCTL_0x92220000: .word 0x92210000 -ESDCTL_0xA2220000: .word 0xA2210000 -ESDCTL_0xB2220000: .word 0xB2210000 -ESDCTL_0x82226080: .word 0x82216080 -ESDCTL_CONFIG: .word 0x007FFC3F - .word 0x007FFC3F -ESDCTL_DELAY5: .word 0x00F49F00 -ESDCTL_BASE_W: .word MX25_ESDCTL_BASE_ADDR - diff --git a/arch/arm/boards/freescale-mx27-ads/Makefile b/arch/arm/boards/freescale-mx27-ads/Makefile deleted file mode 100644 index 398db9b6b9..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/Makefile +++ /dev/null @@ -1,3 +0,0 @@ - -lwl-y += lowlevel_init.o -obj-y += imx27ads.o diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/_update b/arch/arm/boards/freescale-mx27-ads/env/bin/_update deleted file mode 100644 index 014bce3512..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/boot b/arch/arm/boards/freescale-mx27-ads/env/bin/boot deleted file mode 100644 index 3859dc113b..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/env/bin/boot +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xflash ]; then - root=flash - kernel=flash -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xflash ]; then - bootargs="$bootargs root=$rootpart rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nor0.kernel -fi - diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/init b/arch/arm/boards/freescale-mx27-ads/env/bin/init deleted file mode 100644 index 48e2139f7d..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/env/bin/init +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -addpart /dev/nor0 $mtdparts - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [<imagename>] to update kernel into flash" - echo "type udate_root [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot
\ No newline at end of file diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel b/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel deleted file mode 100644 index 1ad95fc5d6..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -part=/dev/nor0.kernel - -. /env/bin/_update $1 diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/update_root b/arch/arm/boards/freescale-mx27-ads/env/bin/update_root deleted file mode 100644 index b757a5b922..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/env/bin/update_root +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$jffs2 -part=/dev/nor0.root - -. /env/bin/_update $1 diff --git a/arch/arm/boards/freescale-mx27-ads/env/config b/arch/arm/boards/freescale-mx27-ads/env/config deleted file mode 100644 index f18a86b7c1..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/env/config +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'flash' -kernel=net -root=net - -# use 'dhcp' todo dhcp in barebox and in kernel -ip=dhcp - -eth0.ipaddr=192.168.23.164 -eth0.netmask=255.255.255.0 -eth0.gateway=192.168.23.2 -eth0.serverip=192.168.23.2 - -uimage=uImage-mx27ads -jffs2=root-mx27ads.jffs2 - -autoboot_timeout=3 - -nfsroot="/tmp/imx27ads" -bootargs="console=ttymxc0,115200" - -mtdparts="128k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" -rootpart="/dev/mtdblock3" - diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.c b/arch/arm/boards/freescale-mx27-ads/imx27ads.c deleted file mode 100644 index c0f4e464c1..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/imx27ads.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <mach/imx27-regs.h> -#include <asm/armlinux.h> -#include <io.h> -#include <platform_data/eth-fec.h> -#include <gpio.h> -#include <mach/weim.h> -#include <partition.h> -#include <fs.h> -#include <fcntl.h> -#include <generated/mach-types.h> -#include <mach/iomux-mx27.h> -#include <mach/devices-imx27.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 1, -}; - -static int imx27ads_timing_init(void) -{ - /* configure cpld on cs4 */ - imx27_setup_weimcs(4, 0x0000DCF6, 0x444A4541, 0x44443302); - - /* configure synchronous mode for - * 16 bit nor flash on cs0 */ - imx27_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800); - - writew(0x00f0, 0xc0000000); - writew(0x00aa, 0xc0000aaa); - writew(0x0055, 0xc0000554); - writew(0x00d0, 0xc0000aaa); - writew(0x66ca, 0xc0000aaa); - writew(0x00f0, 0xc0000000); - - imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900); - - /* Select FEC data through data path */ - writew(0x0020, MX27_CS4_BASE_ADDR + 0x10); - - /* Enable CPLD FEC data path */ - writew(0x0010, MX27_CS4_BASE_ADDR + 0x14); - - return 0; -} - -core_initcall(imx27ads_timing_init); - -static int mx27ads_devices_init(void) -{ - int i; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - }; - - /* initizalize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx27_gpio_mode(mode[i]); - - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); - - imx27_add_fec(&fec_info); - devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - - armlinux_set_architecture(MACH_TYPE_MX27ADS); - - return 0; -} - -device_initcall(mx27ads_devices_init); - -static int mx27ads_console_init(void) -{ - barebox_set_model("Freescale i.MX27 ADS"); - barebox_set_hostname("mx27ads"); - - imx27_add_uart0(); - return 0; -} - -console_initcall(mx27ads_console_init); - diff --git a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S deleted file mode 100644 index e79b96dd2c..0000000000 --- a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S +++ /dev/null @@ -1,114 +0,0 @@ -/* - * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia - * Applications Processor Reference Manual, Rev. 0.2". - * - */ - -#include <config.h> -#include <mach/imx27-regs.h> -#include <asm/barebox-arm-head.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0)) - -.macro sdram_init - /* - * DDR on CSD0 - */ - writel(0x00000008, 0xD8001010) - writel(0x55555555, 0x10027828) - writel(0x55555555, 0x10027830) - writel(0x55555555, 0x10027834) - writel(0x00005005, 0x10027838) - writel(0x15555555, 0x1002783C) - writel(0x00000004, 0xD8001010) - writel(0x006ac73a, 0xD8001004) - writel(0x92100000, 0xD8001000) - writel(0x00000000, 0xA0000F00) - writel(0xA2100000, 0xD8001000) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0xA2200000, 0xD8001000) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0xb2100000, 0xD8001000) - ldr r0, =0xA0000033 - mov r1, #0xda - strb r1, [r0] - ldr r0, =0xA1000000 - mov r1, #0xff - strb r1, [r0] - writel(0x82226080, 0xD8001000) -.endm - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - - ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) - writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) - writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) - - /* disable mpll/spll */ - ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR - ldr r1, [r0] - bic r1, r1, #0x03 - str r1, [r0] - - /* - * pll clock initialization - see section 3.4.3 of the i.MX27 manual - * - * FIXME: Using the 399*2 MHz values from table 3-8 doens't work - * with 1.2 V core voltage! Find out if this is - * documented somewhere. - */ - writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */ - writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */ - - /* - * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz - * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz - * System clock (HCLK) = 133 MHz - */ - writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, - MX27_CCM_BASE_ADDR + MX27_CSCR) - - /* add some delay here */ - mov r1, #0x1000 -1: subs r1, r1, #0x1 - bne 1b - - /* clock gating enable */ - writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) - - /* peripheral clock divider */ - /* FIXME */ - writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0) - /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz */ - writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1) - /* skip sdram initialization if we run from ram */ - cmp pc, #0xa0000000 - bls 1f - cmp pc, #0xc0000000 - bhi 1f - - b imx27_barebox_entry -1: - sdram_init - - b imx27_barebox_entry - diff --git a/arch/arm/boards/freescale-mx28-evk/Makefile b/arch/arm/boards/freescale-mx28-evk/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx28-evk/Makefile +++ b/arch/arm/boards/freescale-mx28-evk/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx28-evk/board.c b/arch/arm/boards/freescale-mx28-evk/board.c index 92097a2bca..1c5d2da5a6 100644 --- a/arch/arm/boards/freescale-mx28-evk/board.c +++ b/arch/arm/boards/freescale-mx28-evk/board.c @@ -9,7 +9,7 @@ #include <common.h> #include <init.h> #include <net.h> -#include <mach/ocotp.h> +#include <mach/mxs/ocotp.h> static void mx28_evk_get_ethaddr(void) { diff --git a/arch/arm/boards/freescale-mx28-evk/lowlevel.c b/arch/arm/boards/freescale-mx28-evk/lowlevel.c index 82411bb516..42ac33fbbd 100644 --- a/arch/arm/boards/freescale-mx28-evk/lowlevel.c +++ b/arch/arm/boards/freescale-mx28-evk/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define pr_fmt(fmt) "Freescale MX28evk: " fmt #define DEBUG @@ -5,11 +7,11 @@ #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx28-regs.h> -#include <mach/init.h> +#include <mach/mxs/imx28-regs.h> +#include <mach/mxs/init.h> #include <io.h> #include <debug_ll.h> -#include <mach/iomux.h> +#include <mach/mxs/iomux.h> #include <stmp-device.h> extern char __dtb_imx28_evk_start[]; diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.c b/arch/arm/boards/freescale-mx35-3ds/3stack.c deleted file mode 100644 index 97a9968706..0000000000 --- a/arch/arm/boards/freescale-mx35-3ds/3stack.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * 2009 Marc Kleine-Budde, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Derived from: - * - * * mx35_3stack.c - board file for uboot-v1 - * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - */ - -#include <common.h> -#include <environment.h> -#include <errno.h> -#include <fcntl.h> -#include <platform_data/eth-fec.h> -#include <fs.h> -#include <init.h> -#include <nand.h> -#include <net.h> -#include <envfs.h> -#include <linux/sizes.h> -#include <partition.h> -#include <gpio.h> - -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <asm/barebox-arm.h> -#include <io.h> -#include <generated/mach-types.h> - -#include <mach/weim.h> -#include <mach/imx-nand.h> -#include <mach/imx35-regs.h> -#include <mach/iomux-mx35.h> -#include <mach/iomux-v3.h> -#include <mach/imx-ipu-fb.h> -#include <mach/generic.h> -#include <mach/devices-imx35.h> -#include <mach/revision.h> - -#include <i2c/i2c.h> -#include <mfd/mc13xxx.h> -#include <mfd/mc9sdz60.h> - - -/* Board rev for the PDK 3stack */ -#define MX35PDK_BOARD_REV_1 0 -#define MX35PDK_BOARD_REV_2 1 - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 0x1F, -}; - -struct imx_nand_platform_data nand_info = { - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("mc13892", 0x08), - }, { - I2C_BOARD_INFO("mc9sdz60", 0x69), - }, -}; - -/* - * Generic display, shipped with the PDK - */ -static struct fb_videomode CTP_CLAA070LC0ACW = { - /* 800x480 @ 60 Hz */ - .name = "CTP-CLAA070LC0ACW", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(27000), - .left_margin = 50, - .right_margin = 50, /* whole line should have 900 clocks */ - .upper_margin = 10, - .lower_margin = 10, /* whole frame should have 500 lines */ - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct imx_ipu_fb_platform_data ipu_fb_data = { - .mode = &CTP_CLAA070LC0ACW, - .num_modes = 1, - .bpp = 16, -}; - -/* - * Revision to be passed to kernel. The kernel provided - * by freescale relies on this. - * - * C --> CPU type - * S --> Silicon revision - * B --> Board rev - * - * 31 20 16 12 8 4 0 - * | Cmaj | Cmin | B | Smaj | Smin| - * - * e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2 -*/ -static unsigned int imx35_3ds_system_rev = 0x00035000; - -static void set_silicon_rev( int rev) -{ - imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF); -} - -static void set_board_rev(int rev) -{ - imx35_3ds_system_rev = (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -static const struct devfs_partition f3s_nand0_partitions[] = { - { - .offset = 0, - .size = 0x40000, - .flags = DEVFS_PARTITION_FIXED, - .name = "self_raw", - .bbname = "self0", - }, { - .offset = DEVFS_PARTITION_APPEND, /* 0x40000 */ - .size = 0x80000, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw", - .bbname = "env0", - }, { - /* sentinel */ - } -}; - -static const struct devfs_partition f3s_nor0_partitions[] = { - { - .offset = 0, - .size = 0x40000, - .flags = DEVFS_PARTITION_FIXED, - .name = "self0", - }, { - .offset = DEVFS_PARTITION_APPEND, /* 0x40000 */ - .size = 0x80000, - .flags = DEVFS_PARTITION_FIXED, - .name = "env0", - }, { - /* sentinel */ - } -}; - -static int f3s_devices_init(void) -{ - uint32_t reg; - - /* CS0: Nor Flash */ - imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); - /* some fuses provide us vital information about connected hardware */ - if (reg & 0x20000000) - nand_info.width = 2; /* 16 bit */ - else - nand_info.width = 1; /* 8 bit */ - - /* - * This platform supports NOR and NAND - */ - imx35_add_nand(&nand_info); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0); - - switch ((reg >> 25) & 0x3) { - case 0x01: /* NAND is the source */ - devfs_create_partitions("nand0", f3s_nand0_partitions); - break; - - case 0x00: /* NOR is the source */ - devfs_create_partitions("nor0", f3s_nor0_partitions); - protect_file("/dev/env0", 1); - break; - } - - set_silicon_rev(imx_silicon_revision()); - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - imx35_add_i2c0(NULL); - - imx35_add_fec(&fec_info); - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE, - IORESOURCE_MEM, NULL); - - imx35_add_mmc0(NULL); - - imx35_add_fb(&ipu_fb_data); - - armlinux_set_architecture(MACH_TYPE_MX35_3DS); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_freescale_mx35_3ds); - - return 0; -} - -device_initcall(f3s_devices_init); - -static int f3s_enable_display(void) -{ - /* Enable power to the LCD. (bit 6 hi.) */ - mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40); - - return 0; -} - -late_initcall(f3s_enable_display); - -static iomux_v3_cfg_t f3s_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - - MX35_PAD_RXD1__UART1_RXD_MUX, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_CTS1__UART1_CTS, - - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - - MX35_PAD_WDOG_RST__GPIO1_6, - MX35_PAD_COMPARE__GPIO1_5, - - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, -}; - -static int f3s_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); - - barebox_set_model("Freescale i.MX35 3DS"); - barebox_set_hostname("mx35-3stack"); - - imx35_add_uart0(); - return 0; -} - -console_initcall(f3s_console_init); - -static int f3s_core_init(void) -{ - u32 reg; - - /* CS5: smc9117 */ - imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00); - - /* enable clock for I2C1 and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); - reg &= 0x00FFFFFF; - writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); - reg &= 0x00FFFFFF; - writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - return 0; -} - -core_initcall(f3s_core_init); - -static int f3s_get_rev(struct mc13xxx *mc13xxx) -{ - u32 rev; - int err; - - err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev); - if (err) - return err; - - if (rev == 0x00ffffff) - return -ENODEV; - - return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1; -} - -static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx) -{ - int err = 0; - - /* COMPARE pin (GPIO1_5) as output and set high */ - gpio_direction_output( 32*0 + 5 , 1); - - err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03); - err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01); - if (err) - printf("mc13892 Init sequence failed, the system might not be working!\n"); - - return err; -} - -static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60) -{ - int err = 0; - - err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04); - - err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00); - mdelay(200); - err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80); - - if (err) - dev_err(&mc9sdz60->client->dev, - "Init sequence failed, the system might not be working!\n"); - - return err; -} - -static int f3s_pmic_init(void) -{ - struct mc13xxx *mc13xxx; - struct mc9sdz60 *mc9sdz60; - int rev; - - mc13xxx = mc13xxx_get(); - if (!mc13xxx) { - printf("FAILED to get PMIC handle!\n"); - return 0; - } - - rev = f3s_get_rev(mc13xxx); - switch (rev) { - case MX35PDK_BOARD_REV_1: - break; - case MX35PDK_BOARD_REV_2: - f3s_pmic_init_v2(mc13xxx); - break; - default: - printf("FAILED to identify board revision!\n"); - return 0; - } - - set_board_rev(rev); - printf("i.MX35 PDK CPU board version %d.\n", rev ); - - mc9sdz60 = mc9sdz60_get(); - if (!mc9sdz60) { - printf("FAILED to get mc9sdz60 handle!\n"); - return 0; - } - - f3s_pmic_init_all(mc9sdz60); - - armlinux_set_revision(imx35_3ds_system_rev); - - return 0; -} - -late_initcall(f3s_pmic_init); diff --git a/arch/arm/boards/freescale-mx35-3ds/Makefile b/arch/arm/boards/freescale-mx35-3ds/Makefile deleted file mode 100644 index c192854f0b..0000000000 --- a/arch/arm/boards/freescale-mx35-3ds/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += 3stack.o -lwl-y += lowlevel_init.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-mx35-3ds diff --git a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h deleted file mode 100644 index 3bcb470b74..0000000000 --- a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * (C) Copyright 2008 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __BOARD_MX35_3STACK_H -#define __BOARD_MX35_3STACK_H - -#define UNALIGNED_ACCESS_ENABLE -#define LOW_INT_LATENCY_ENABLE -#define BRANCH_PREDICTION_ENABLE - -#define L2CC_AUX_CTL_CONFIG 0x00030024 - -#define AIPS_MPR_CONFIG 0x77777777 -#define AIPS_OPACR_CONFIG 0x00000000 - -/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_MPR_CONFIG 0x00302154 -/* SGPCR - always park on last master */ -#define MAX_SGPCR_CONFIG 0x00000010 -/* MGPCR - restore default values */ -#define MAX_MGPCR_CONFIG 0x00000000 - -/* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ -#define M3IF_CONFIG 0x00000040 - -#define DBG_BASE_ADDR WEIM_CTRL_CS5 -#define DBG_CSCR_U_CONFIG 0x0000D843 -#define DBG_CSCR_L_CONFIG 0x22252521 -#define DBG_CSCR_A_CONFIG 0x22220A00 - -#define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00821000 - -#define PLL_BRM_OFFSET 31 -#define PLL_PD_OFFSET 26 -#define PLL_MFD_OFFSET 16 -#define PLL_MFI_OFFSET 10 - -#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) -#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) -#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) -#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - -/*MEMORY SETING*/ -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080 - -#define ESDCTL_PRECHARGE 0x00000400 - -#define ESDCTL_MDDR_CONFIG 0x007FFC3F -#define ESDCTL_MDDR_MR 0x00000033 -#define ESDCTL_MDDR_EMR 0x02000000 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 - -#define ESDCTL_DELAY_LINE5 0x00F49F00 -#endif /* __BOARD_MX35_3STACK_H */ diff --git a/arch/arm/boards/freescale-mx35-3ds/defaultenv-freescale-mx35-3ds/config b/arch/arm/boards/freescale-mx35-3ds/defaultenv-freescale-mx35-3ds/config deleted file mode 100644 index af2fb6b2bc..0000000000 --- a/arch/arm/boards/freescale-mx35-3ds/defaultenv-freescale-mx35-3ds/config +++ /dev/null @@ -1,51 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nor_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nor=3 - -nand_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nand=7 -nand_device=mxc_nand - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg deleted file mode 100644 index 6eb8bc242c..0000000000 --- a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg +++ /dev/null @@ -1,34 +0,0 @@ -soc imx35 -loadaddr 0x80000000 -dcdofs 0x400 - -wm 32 0xb8002050 0x0000d843 -wm 32 0xb8002054 0x22252521 -wm 32 0xb8002058 0x22220a00 -wm 32 0xb8001010 0x00000304 -wm 32 0xb8001010 0x0000030c -wm 32 0xb8001004 0x007ffc3f -wm 32 0xb800100c 0x007ffc3f -wm 32 0xb8001000 0x92220000 -wm 32 0xb8001008 0x92220000 -wm 32 0x80000400 0x12345678 -wm 32 0x90000400 0x12345678 -wm 32 0xb8001000 0xa2220000 -wm 32 0xb8001008 0xa2220000 -wm 32 0x80000000 0x87654321 -wm 32 0x90000000 0x87654321 -wm 32 0x80000000 0x87654321 -wm 32 0x90000000 0x87654321 -wm 32 0xb8001000 0xb2220000 -wm 32 0xb8001008 0xb2220000 -wm 8 0x80000233 0xda -wm 8 0x90000233 0xda -wm 8 0x82000780 0xda -wm 8 0x92000780 0xda -wm 8 0x82000400 0xda -wm 8 0x92000400 0xda -wm 32 0xb8001000 0x82226080 -wm 32 0xb8001008 0x82226080 -wm 32 0xb8001004 0x007ffc3f -wm 32 0xb800100c 0x007ffc3f -wm 32 0xb8001010 0x00000304 diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S deleted file mode 100644 index 011de6dadf..0000000000 --- a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S +++ /dev/null @@ -1,257 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <mach/imx35-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/cache-l2x0.h> -#include <asm-generic/memory_layout.h> -#include <asm/barebox-arm-head.h> - -#include "board-mx35_3stack.h" - -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 -#define ESDCTL_BASE_ADDR 0xB8001000 - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define writeb(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - strb r1, [r0]; - - .section ".text_bare_init","ax" - -ARM_PPMRR: .word 0x40000015 -L2CACHE_PARAM: .word 0x00030024 -CCM_CCMR_W: .word 0x003F4208 -CCM_PDR0_W: .word 0x00001000 -MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 -MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 -PPCTL_PARAM_W: .word PPCTL_PARAM_300 -CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - - /* Setup a temporary stack in internal SRAM */ - ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 - - mrc 15, 0, r1, c1, c0, 0 - - mrc 15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr 15, 0, r0, c1, c0, 1 - - orr r1, r1, #(1 << 11) /* Flow prediction (Z) */ - orr r1, r1, #(1 << 22) /* unaligned accesses */ - orr r1, r1, #(1 << 21) /* Low Int Latency */ - - mcr 15, 0, r1, c1, c0, 0 - - mov r0, #0 - mcr 15, 0, r0, c15, c2, 4 - - /* - * Branch predicition is now enabled. Flush the BTAC to ensure a valid - * starting point. Don't flush BTAC while it is disabled to avoid - * ARM1136 erratum 408023. - */ - mov r0, #0 - mcr p15, 0, r0, c7, c5, 6 /* flush entire BTAC */ - - mov r0, #0 - mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ - mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ - - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, ARM_PPMRR /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - -/* - * End of ARM1136 init - */ - ldr r0, CCM_BASE_ADDR_W - - ldr r2, CCM_CCMR_W - str r2, [r0, #MX35_CCM_CCMR] - - ldr r3, MPCTL_PARAM_532_W /* consumer path*/ - - /* Set MPLL, arm clock and ahb clock */ - str r3, [r0, #MX35_CCM_MPCTL] - - ldr r1, PPCTL_PARAM_W - str r1, [r0, #MX35_CCM_PPCTL] - - ldr r1, CCM_PDR0_W - str r1, [r0, #MX35_CCM_PDR0] - - ldr r1, [r0, #MX35_CCM_CGR0] - orr r1, r1, #0x00300000 - str r1, [r0, #MX35_CCM_CGR0] - - ldr r1, [r0, #MX35_CCM_CGR1] - orr r1, r1, #0x00000C00 - orr r1, r1, #0x00000003 - str r1, [r0, #MX35_CCM_CGR1] - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #CSD0_BASE_ADDR - bls 1f - cmp pc, #CSD1_BASE_ADDR - bhi 1f - - b imx35_barebox_entry - -1: - ldr r0, =ESDCTL_BASE_ADDR - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - /* ip(r12) has used to save lr register in upper calling */ - mov fp, lr - - /* setup bank 0 */ - mov r5, #0x00 - mov r2, #0x00 - mov r1, #MX35_CSD0_BASE_ADDR - bl setup_sdram_bank - - /* setup bank 1 */ - mov r5, #0x00 - mov r2, #0x00 - mov r1, #MX35_CSD1_BASE_ADDR - bl setup_sdram_bank - - mov lr, fp - - ldr r3, =ESDCTL_DELAY_LINE5 - str r3, [r0, #0x30] - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - mov r0, #0 - b imx35_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - - b imx35_barebox_entry - -/* - * r0: ESDCTL control base, r1: sdram slot base - * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base - */ -setup_sdram_bank: - mov r3, #0xE /* 0xA + 0x4 */ - tst r2, #0x1 - orreq r3, r3, #0x300 /* DDR2 */ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: tst r2, #0x1 - ldreq r3, =ESDCTL_DDR2_CONFIG - ldrne r3, =ESDCTL_MDDR_CONFIG - cmp r1, #CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_DDR2_EMR2 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EMR3 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EN_DLL - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_RESET_DLL - strb r3, [r1, r4] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - tst r2, #0x1 - ldreq r4, =ESDCTL_DDR2_MR - ldrne r4, =ESDCTL_MDDR_MR - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT - streqb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_EN_DLL - ldrne r4, =ESDCTL_MDDR_EMR - strb r3, [r1, r4] - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0x82228080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr diff --git a/arch/arm/boards/freescale-mx51-babbage/Makefile b/arch/arm/boards/freescale-mx51-babbage/Makefile index b6e085818f..aed38f2eaa 100644 --- a/arch/arm/boards/freescale-mx51-babbage/Makefile +++ b/arch/arm/boards/freescale-mx51-babbage/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_MACH_FREESCALE_MX51_PDK_POWER) += power.o obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += board.o lwl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += lowlevel.o diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c index 4839aa5683..1d4fb2d8c6 100644 --- a/arch/arm/boards/freescale-mx51-babbage/board.c +++ b/arch/arm/boards/freescale-mx51-babbage/board.c @@ -1,45 +1,30 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #define pr_fmt(fmt) "babbage: " fmt #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx51-regs.h> +#include <mach/imx/imx51-regs.h> #include <gpio.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <of.h> #include <fcntl.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <nand.h> #include <notifier.h> #include <spi/spi.h> #include <io.h> #include <asm/mmu.h> -#include <mach/imx5.h> -#include <mach/imx-nand.h> -#include <mach/spi.h> -#include <mach/generic.h> -#include <mach/iomux-mx51.h> -#include <mach/devices-imx51.h> -#include <mach/revision.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx-nand.h> +#include <mach/imx/spi.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx51.h> +#include <mach/imx/revision.h> #define MX51_CCM_CACRR 0x10 diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg index bac6816fee..56e2a9607c 100644 --- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg +++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x90000000 soc imx51 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c index e29a647daa..7d219bad78 100644 --- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c +++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c @@ -1,9 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <debug_ll.h> -#include <mach/clock-imx51_53.h> -#include <mach/iomux-mx51.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/iomux-mx51.h> #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/freescale-mx51-babbage/power.c b/arch/arm/boards/freescale-mx51-babbage/power.c index 6edc672a5a..48dc74dd77 100644 --- a/arch/arm/boards/freescale-mx51-babbage/power.c +++ b/arch/arm/boards/freescale-mx51-babbage/power.c @@ -1,10 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define pr_fmt(fmt) "babbage-power: " fmt #include <common.h> #include <init.h> #include <notifier.h> -#include <mach/revision.h> -#include <mach/imx5.h> +#include <mach/imx/revision.h> +#include <mach/imx/imx5.h> #include <mfd/mc13xxx.h> static void babbage_power_init(struct mc13xxx *mc13xxx) diff --git a/arch/arm/boards/freescale-mx53-qsb/Makefile b/arch/arm/boards/freescale-mx53-qsb/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx53-qsb/Makefile +++ b/arch/arm/boards/freescale-mx53-qsb/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c index 0b1c927b81..a8558eafce 100644 --- a/arch/arm/boards/freescale-mx53-qsb/board.c +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de> #include <environment.h> -#include <partition.h> #include <common.h> #include <linux/sizes.h> #include <gpio.h> @@ -30,14 +17,14 @@ #include <asm/armlinux.h> #include <asm/mmu.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> -#include <mach/imx53-regs.h> -#include <mach/revision.h> -#include <mach/generic.h> -#include <mach/imx5.h> -#include <mach/bbu.h> -#include <mach/iim.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/revision.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx5.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iim.h> /* * Revision to be passed to kernel. The kernel provided diff --git a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg index f43b484ee6..da08c60739 100644 --- a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg +++ b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c index c9044011d5..5870f266d2 100644 --- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c @@ -1,7 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> -#include <mach/imx53-regs.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <image-metadata.h> diff --git a/arch/arm/boards/freescale-mx53-smd/Makefile b/arch/arm/boards/freescale-mx53-smd/Makefile deleted file mode 100644 index 98ed275396..0000000000 --- a/arch/arm/boards/freescale-mx53-smd/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-freescale-mx53-smd diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c deleted file mode 100644 index 2b58f49205..0000000000 --- a/arch/arm/boards/freescale-mx53-smd/board.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <environment.h> -#include <fcntl.h> -#include <platform_data/eth-fec.h> -#include <fs.h> -#include <init.h> -#include <nand.h> -#include <net.h> -#include <partition.h> -#include <linux/sizes.h> -#include <gpio.h> -#include <mci.h> -#include <envfs.h> - -#include <generated/mach-types.h> - -#include <mach/imx53-regs.h> -#include <mach/iomux-mx53.h> -#include <mach/devices-imx53.h> -#include <mach/generic.h> -#include <mach/imx-nand.h> -#include <mach/iim.h> -#include <mach/imx5.h> - -#include <asm/armlinux.h> -#include <io.h> -#include <asm/mmu.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, -}; - -static iomux_v3_cfg_t smd_pads[] = { - /* UART1 */ - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - /* UART2 */ - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - - /* UART3 */ - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - - /* FEC */ - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - /* FEC_nRST */ - MX53_PAD_PATA_DA_0__GPIO7_6, - - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1_CD */ - MX53_PAD_EIM_DA13__GPIO3_13, - /* SD1_WP */ - MX53_PAD_KEY_ROW2__GPIO4_11, - - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, -}; - -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) - -static void smd_fec_reset(void) -{ - gpio_direction_output(SMD_FEC_PHY_RST, 0); - mdelay(1); - gpio_set_value(SMD_FEC_PHY_RST, 1); -} - -#define LOCO_SD1_CD IMX_GPIO_NR(3, 13) -#define LOCO_SD1_WP IMX_GPIO_NR(4, 11) - -static struct esdhc_platform_data loco_sd1_data = { - .cd_gpio = LOCO_SD1_CD, - .wp_gpio = LOCO_SD1_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, - .caps = MMC_CAP_4_BIT_DATA, -}; - -static struct esdhc_platform_data loco_sd3_data = { - .wp_type = ESDHC_WP_NONE, - .cd_type = ESDHC_CD_PERMANENT, -}; - -static int smd_devices_init(void) -{ - imx53_iim_register_fec_ethaddr(); - imx53_add_fec(&fec_info); - imx53_add_mmc0(&loco_sd1_data); - imx53_add_mmc2(&loco_sd3_data); - - smd_fec_reset(); - - armlinux_set_architecture(MACH_TYPE_MX53_SMD); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_freescale_mx53_smd); - - return 0; -} -device_initcall(smd_devices_init); - -static int smd_part_init(void) -{ - devfs_add_partition("disk0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - - return 0; -} -late_initcall(smd_part_init); - -static int smd_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(smd_pads, ARRAY_SIZE(smd_pads)); - - barebox_set_model("Freescale i.MX53 SMD"); - barebox_set_hostname("imx53-smd"); - - imx53_init_lowlevel(1000); - - imx53_add_uart0(); - imx53_add_uart1(); - imx53_add_uart2(); - return 0; -} -console_initcall(smd_console_init); diff --git a/arch/arm/boards/freescale-mx53-smd/defaultenv-freescale-mx53-smd/config b/arch/arm/boards/freescale-mx53-smd/defaultenv-freescale-mx53-smd/config deleted file mode 100644 index 27d2663566..0000000000 --- a/arch/arm/boards/freescale-mx53-smd/defaultenv-freescale-mx53-smd/config +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg b/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg deleted file mode 100644 index 95bcd19805..0000000000 --- a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg +++ /dev/null @@ -1,54 +0,0 @@ -loadaddr 0x70000000 -soc imx53 -dcdofs 0x400 -wm 32 0x53fa8554 0x00300000 -wm 32 0x53fa8558 0x00300040 -wm 32 0x53fa8560 0x00300000 -wm 32 0x53fa8564 0x00300040 -wm 32 0x53fa8568 0x00300040 -wm 32 0x53fa8570 0x00300000 -wm 32 0x53fa8574 0x00300000 -wm 32 0x53fa8578 0x00300000 -wm 32 0x53fa857c 0x00300040 -wm 32 0x53fa8580 0x00300040 -wm 32 0x53fa8584 0x00300000 -wm 32 0x53fa8588 0x00300000 -wm 32 0x53fa8590 0x00300040 -wm 32 0x53fa8594 0x00300000 -wm 32 0x53fa86f0 0x00300000 -wm 32 0x53fa86f4 0x00000000 -wm 32 0x53fa86fc 0x00000000 -wm 32 0x53fa8714 0x00000000 -wm 32 0x53fa8718 0x00300000 -wm 32 0x53fa871c 0x00300000 -wm 32 0x53fa8720 0x00300000 -wm 32 0x53fa8724 0x04000000 -wm 32 0x53fa8728 0x00300000 -wm 32 0x53fa872c 0x00300000 -wm 32 0x63fd9088 0x35343535 -wm 32 0x63fd9090 0x4d444c44 -wm 32 0x63fd907c 0x01370138 -wm 32 0x63fd9080 0x013b013c -wm 32 0x63fd9018 0x00011740 -wm 32 0x63fd9000 0xc3190000 -wm 32 0x63fd900c 0x9f5152e3 -wm 32 0x63fd9010 0xb68e8a63 -wm 32 0x63fd9014 0x01ff00db -wm 32 0x63fd902c 0x000026d2 -wm 32 0x63fd9030 0x009f0e21 -wm 32 0x63fd9008 0x12273030 -wm 32 0x63fd9004 0x0002002d -wm 32 0x63fd901c 0x00008032 -wm 32 0x63fd901c 0x00008033 -wm 32 0x63fd901c 0x00028031 -wm 32 0x63fd901c 0x052080b0 -wm 32 0x63fd901c 0x04008040 -wm 32 0x63fd901c 0x0000803a -wm 32 0x63fd901c 0x0000803b -wm 32 0x63fd901c 0x00028039 -wm 32 0x63fd901c 0x05208138 -wm 32 0x63fd901c 0x04008048 -wm 32 0x63fd9020 0x00005800 -wm 32 0x63fd9040 0x04b80003 -wm 32 0x63fd9058 0x00022227 -wm 32 0x63fd901c 0x00000000 diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c deleted file mode 100644 index fffbfdf0ba..0000000000 --- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c +++ /dev/null @@ -1,12 +0,0 @@ -#include <common.h> -#include <mach/imx53-regs.h> -#include <mach/esdctl.h> -#include <mach/generic.h> -#include <asm/barebox-arm-head.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); - imx53_barebox_entry(NULL); -} diff --git a/arch/arm/boards/freescale-mx53-vmx53/Makefile b/arch/arm/boards/freescale-mx53-vmx53/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/Makefile +++ b/arch/arm/boards/freescale-mx53-vmx53/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx53-vmx53/board.c b/arch/arm/boards/freescale-mx53-vmx53/board.c index 1859aaca26..496ce2c112 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/board.c +++ b/arch/arm/boards/freescale-mx53-vmx53/board.c @@ -1,29 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o. + /* - * Copyright (C) 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o. - * * Board specific file for Voipac X53-DMM-668 module equipped * with i.MX53 CPU - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> #include <init.h> #include <linux/sizes.h> -#include <generated/mach-types.h> -#include <mach/imx5.h> +#include <asm/mach-types.h> +#include <mach/imx/imx5.h> #include <asm/armlinux.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> static int vmx53_late_init(void) { diff --git a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg index 3bf73b65aa..20e028691a 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg +++ b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c index ae94538c9e..4543171ec2 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/freescale-mx6-sabrelite/Makefile b/arch/arm/boards/freescale-mx6-sabrelite/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/Makefile +++ b/arch/arm/boards/freescale-mx6-sabrelite/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index 63fa58886c..fe47743540 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -1,41 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix + /* - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * * based on arch/arm/boards/freescale-mx6-arm2/board.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx6-regs.h> +#include <mach/imx/imx6-regs.h> #include <gpio.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> +#include <of.h> +#include <deep-probe.h> #include <linux/phy.h> #include <asm/io.h> #include <asm/mmu.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #include <net.h> #include <linux/micrel_phy.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/iomux-mx6.h> #include <spi/spi.h> -#include <mach/spi.h> -#include <mach/usb.h> +#include <mach/imx/spi.h> +#include <mach/imx/usb.h> static iomux_v3_cfg_t sabrelite_enet_gpio_pads[] = { /* Ethernet */ @@ -48,18 +39,6 @@ static iomux_v3_cfg_t sabrelite_enet_gpio_pads[] = { MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, }; -static int sabrelite_mem_init(void) -{ - if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && - !of_machine_is_compatible("fsl,imx6dl-sabrelite")) - return 0; - - arm_add_mem_device("ram0", 0x10000000, SZ_1G); - - return 0; -} -mem_initcall(sabrelite_mem_init); - static int ksz9021rn_phy_fixup(struct phy_device *dev) { phy_write(dev, 0x09, 0x0f00); @@ -79,37 +58,37 @@ static int ksz9021rn_phy_fixup(struct phy_device *dev) static struct gpio fec_gpios[] = { { - .gpio = 87, + .gpio = IMX_GPIO_NR(3, 23), .flags = GPIOF_OUT_INIT_LOW, .label = "phy-rst", }, { - .gpio = 190, + .gpio = IMX_GPIO_NR(6, 30), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-addr2", }, { - .gpio = 23, + .gpio = IMX_GPIO_NR(1, 23), .flags = GPIOF_OUT_INIT_LOW, .label = "phy-led-mode", }, { /* MODE strap-in pins: advertise all capabilities */ - .gpio = 185, + .gpio = IMX_GPIO_NR(6, 25), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 187, + .gpio = IMX_GPIO_NR(6, 27), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 188, + .gpio = IMX_GPIO_NR(6, 28), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { - .gpio = 189, + .gpio = IMX_GPIO_NR(6, 29), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-adv1", }, { /* Enable 125 MHz clock output */ - .gpio = 184, + .gpio = IMX_GPIO_NR(6, 24), .flags = GPIOF_OUT_INIT_HIGH, .label = "phy-125MHz", }, @@ -119,10 +98,6 @@ static int sabrelite_ksz9021rn_setup(void) { int ret; - if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && - !of_machine_is_compatible("fsl,imx6dl-sabrelite")) - return 0; - mxc_iomux_v3_setup_multiple_pads(sabrelite_enet_gpio_pads, ARRAY_SIZE(sabrelite_enet_gpio_pads)); @@ -139,25 +114,31 @@ static int sabrelite_ksz9021rn_setup(void) return 0; } -/* - * Do this before the fec initializes but after our - * gpios are available. - */ -fs_initcall(sabrelite_ksz9021rn_setup); static void sabrelite_ehci_init(void) { /* hub reset */ - gpio_direction_output(204, 0); + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); udelay(2000); - gpio_set_value(204, 1); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); } -static int sabrelite_devices_init(void) +static int sabrelite_probe(struct device *dev) { - if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && - !of_machine_is_compatible("fsl,imx6dl-sabrelite")) - return 0; + int ret; + + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + + barebox_set_hostname("sabrelite"); + + ret = of_devices_ensure_probed_by_property("gpio-controller"); + if (ret) + return ret; + + ret = sabrelite_ksz9021rn_setup(); + if (ret) + return ret; sabrelite_ehci_init(); @@ -168,19 +149,21 @@ static int sabrelite_devices_init(void) return 0; } -device_initcall(sabrelite_devices_init); - -static int sabrelite_coredevices_init(void) -{ - if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && - !of_machine_is_compatible("fsl,imx6dl-sabrelite")) - return 0; +static const struct of_device_id sabrelite_match[] = { + { + .compatible = "fsl,imx6q-sabrelite", + }, { + .compatible = "fsl,imx6dl-sabrelite", + }, + { /* Sentinel */ }, +}; - phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, - ksz9021rn_phy_fixup); +static struct driver sabrelite_driver = { + .name = "physom-imx6", + .probe = sabrelite_probe, + .of_compatible = sabrelite_match, +}; - barebox_set_hostname("sabrelite"); +postcore_platform_driver(sabrelite_driver); - return 0; -} -coredevice_initcall(sabrelite_coredevices_init); +BAREBOX_DEEP_PROBE_ENABLE(sabrelite_match); diff --git a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg index 3ce8562f51..7dcaefd697 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 diff --git a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c index c2d7a3c8f3..f1ed31ccad 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c @@ -1,12 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-regs.h> +#include <mach/imx/imx6-regs.h> #include <io.h> -#include <mach/debug_ll.h> -#include <mach/esdctl.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> #include <asm/cache.h> extern char __dtb_imx6q_sabrelite_start[]; diff --git a/arch/arm/boards/freescale-mx6-sabresd/Makefile b/arch/arm/boards/freescale-mx6-sabresd/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/Makefile +++ b/arch/arm/boards/freescale-mx6-sabresd/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c b/arch/arm/boards/freescale-mx6-sabresd/board.c index 595b1eae0b..1db52736f9 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/board.c +++ b/arch/arm/boards/freescale-mx6-sabresd/board.c @@ -1,40 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2013 Hubert Feurstein <h.feurstein@gmail.com> * * based on arch/arm/boards/freescale-mx6-sabrelite/board.c * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx6-regs.h> -#include <gpio.h> +#include <mach/imx/imx6-regs.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <linux/phy.h> #include <asm/io.h> #include <asm/mmu.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #include <net.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/iomux-mx6.h> #include <spi/spi.h> -#include <mach/spi.h> -#include <mach/usb.h> +#include <mach/imx/spi.h> +#include <mach/imx/usb.h> #define PHY_ID_AR8031 0x004dd074 #define AR_PHY_ID_MASK 0xffffffff @@ -64,7 +53,9 @@ static int ar8031_phy_fixup(struct phy_device *dev) static int sabresd_devices_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabresd")) + if (!of_machine_is_compatible("fsl,imx6q-sabresd") && + !of_machine_is_compatible("fsl,imx6qp-sabresd") && + !of_machine_is_compatible("fsl,imx6dl-sabresd")) return 0; armlinux_set_architecture(3980); @@ -76,7 +67,9 @@ device_initcall(sabresd_devices_init); static int sabresd_coredevices_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabresd")) + if (!of_machine_is_compatible("fsl,imx6q-sabresd") && + !of_machine_is_compatible("fsl,imx6qp-sabresd") && + !of_machine_is_compatible("fsl,imx6dl-sabresd")) return 0; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, @@ -84,8 +77,4 @@ static int sabresd_coredevices_init(void) return 0; } -/* - * Do this before the fec initializes but after our - * gpios are available. - */ coredevice_initcall(sabresd_coredevices_init); diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6dl-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6dl-sabresd.imxcfg new file mode 100644 index 0000000000..303b62ce4f --- /dev/null +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6dl-sabresd.imxcfg @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only + +loadaddr 0x10000000 +soc imx6 +ivtofs 0x400 +wm 32 0x020e0774 0x000C0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00000030 +wm 32 0x020e04b8 0x00000030 +wm 32 0x020e076c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e04bc 0x00000030 +wm 32 0x020e04c0 0x00000030 +wm 32 0x020e04c4 0x00000030 +wm 32 0x020e04c8 0x00000030 +wm 32 0x020e04cc 0x00000030 +wm 32 0x020e04d0 0x00000030 +wm 32 0x020e04d4 0x00000030 +wm 32 0x020e04d8 0x00000030 +wm 32 0x020e0760 0x00020000 +wm 32 0x020e0764 0x00000030 +wm 32 0x020e0770 0x00000030 +wm 32 0x020e0778 0x00000030 +wm 32 0x020e077c 0x00000030 +wm 32 0x020e0780 0x00000030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e0470 0x00000030 +wm 32 0x020e0474 0x00000030 +wm 32 0x020e0478 0x00000030 +wm 32 0x020e047c 0x00000030 +wm 32 0x020e0480 0x00000030 +wm 32 0x020e0484 0x00000030 +wm 32 0x020e0488 0x00000030 +wm 32 0x020e048c 0x00000030 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b080c 0x001F001F +wm 32 0x021b0810 0x001F001F +wm 32 0x021b480c 0x001F001F +wm 32 0x021b4810 0x001F001F +wm 32 0x021b083c 0x4220021F +wm 32 0x021b0840 0x0207017E +wm 32 0x021b483c 0x4201020C +wm 32 0x021b4840 0x01660172 +wm 32 0x021b0848 0x4A4D4E4D +wm 32 0x021b4848 0x4A4F5049 +wm 32 0x021b0850 0x3F3C3D31 +wm 32 0x021b4850 0x3238372B +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x0002002D +wm 32 0x021b0008 0x00333030 +wm 32 0x021b000c 0x3F435313 +wm 32 0x021b0010 0xB66E8B63 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x00431023 +wm 32 0x021b0040 0x00000027 +wm 32 0x021b0000 0x831A0000 +wm 32 0x021b001c 0x04008032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x05208030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x0002556D +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +wm 32 0x020c4068 0x00C03F3F +wm 32 0x020c406c 0x0030FC03 +wm 32 0x020c4070 0x0FFFF000 +wm 32 0x020c4074 0x3FF00000 +wm 32 0x020c4078 0x00FFF300 +wm 32 0x020c407c 0x0F0000C3 +wm 32 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +wm 32 0x020e0010 0xF00000CF + +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6q-sabresd.imxcfg index 21f217cdf3..39f8950e8e 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6q-sabresd.imxcfg @@ -1,128 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 +wm 32 0x20e056c 0x00020030 +wm 32 0x20e0578 0x00020030 +wm 32 0x20e0588 0x00020030 +wm 32 0x20e0594 0x00020030 +wm 32 0x20e0798 0x000C0000 +wm 32 0x20e0758 0x00000000 +wm 32 0x20e0588 0x00000030 +wm 32 0x20e0594 0x00000030 +wm 32 0x20e056c 0x00000030 +wm 32 0x20e0578 0x00000030 +wm 32 0x20e074c 0x00000030 +wm 32 0x20e057c 0x00000030 +wm 32 0x20e058c 0x00000000 +wm 32 0x20e059c 0x00000030 +wm 32 0x20e05a0 0x00000030 +wm 32 0x20e078c 0x00000030 +wm 32 0x20e0750 0x00020000 wm 32 0x20e05a8 0x00000030 wm 32 0x20e05b0 0x00000030 wm 32 0x20e0524 0x00000030 wm 32 0x20e051c 0x00000030 - wm 32 0x20e0518 0x00000030 wm 32 0x20e050c 0x00000030 wm 32 0x20e05b8 0x00000030 wm 32 0x20e05c0 0x00000030 - -wm 32 0x20e05ac 0x00020030 -wm 32 0x20e05b4 0x00020030 -wm 32 0x20e0528 0x00020030 -wm 32 0x20e0520 0x00020030 - -wm 32 0x20e0514 0x00020030 -wm 32 0x20e0510 0x00020030 -wm 32 0x20e05bc 0x00020030 -wm 32 0x20e05c4 0x00020030 - -wm 32 0x20e056c 0x00020030 -wm 32 0x20e0578 0x00020030 -wm 32 0x20e0588 0x00020030 -wm 32 0x20e0594 0x00020030 - -wm 32 0x20e057c 0x00020030 -wm 32 0x20e0590 0x00003000 -wm 32 0x20e0598 0x00003000 -wm 32 0x20e058c 0x00000000 - -wm 32 0x20e059c 0x00003030 -wm 32 0x20e05a0 0x00003030 +wm 32 0x20e0774 0x00020000 wm 32 0x20e0784 0x00000030 wm 32 0x20e0788 0x00000030 - wm 32 0x20e0794 0x00000030 wm 32 0x20e079c 0x00000030 wm 32 0x20e07a0 0x00000030 wm 32 0x20e07a4 0x00000030 - wm 32 0x20e07a8 0x00000030 wm 32 0x20e0748 0x00000030 -wm 32 0x20e074c 0x00000030 -wm 32 0x20e0750 0x00020000 - -wm 32 0x20e0758 0x00000000 -wm 32 0x20e0774 0x00020000 -wm 32 0x20e078c 0x00000030 -wm 32 0x20e0798 0x000C0000 - +wm 32 0x20e05ac 0x00000030 +wm 32 0x20e05b4 0x00000030 +wm 32 0x20e0528 0x00000030 +wm 32 0x20e0520 0x00000030 +wm 32 0x20e0514 0x00000030 +wm 32 0x20e0510 0x00000030 +wm 32 0x20e05bc 0x00000030 +wm 32 0x20e05c4 0x00000030 +wm 32 0x21b0800 0xa1390003 +wm 32 0x21b080c 0x001F001F +wm 32 0x21b0810 0x001F001F +wm 32 0x21b480c 0x001F001F +wm 32 0x21b4810 0x001F001F +wm 32 0x21b083c 0x43270338 +wm 32 0x21b0840 0x03200314 +wm 32 0x21b483c 0x431A032F +wm 32 0x21b4840 0x03200263 +wm 32 0x21b0848 0x4B434748 +wm 32 0x21b4848 0x4445404C +wm 32 0x21b0850 0x38444542 +wm 32 0x21b4850 0x4935493A wm 32 0x21b081c 0x33333333 wm 32 0x21b0820 0x33333333 wm 32 0x21b0824 0x33333333 wm 32 0x21b0828 0x33333333 - wm 32 0x21b481c 0x33333333 wm 32 0x21b4820 0x33333333 wm 32 0x21b4824 0x33333333 wm 32 0x21b4828 0x33333333 - -wm 32 0x21b0018 0x00081740 - -wm 32 0x21b001c 0x00008000 +wm 32 0x21b08b8 0x00000800 +wm 32 0x21b48b8 0x00000800 +wm 32 0x21b0004 0x00020036 +wm 32 0x21b0008 0x09444040 wm 32 0x21b000c 0x555A7975 -wm 32 0x21b0010 0xFF538E64 +wm 32 0x21b0010 0xFF538F64 wm 32 0x21b0014 0x01FF00DB -wm 32 0x21b002c 0x000026D2 - -wm 32 0x21b0030 0x005B0E21 -wm 32 0x21b0008 0x09444040 -wm 32 0x21b0004 0x00025576 +wm 32 0x21b0018 0x00001740 +wm 32 0x21b001c 0x00008000 +wm 32 0x21b002c 0x000026d2 +wm 32 0x21b0030 0x005A1023 wm 32 0x21b0040 0x00000027 wm 32 0x21b0000 0x831A0000 - wm 32 0x21b001c 0x04088032 -wm 32 0x21b001c 0x0408803A wm 32 0x21b001c 0x00008033 -wm 32 0x21b001c 0x0000803B -wm 32 0x21b001c 0x00428031 -wm 32 0x21b001c 0x00428039 +wm 32 0x21b001c 0x00048031 wm 32 0x21b001c 0x09408030 -wm 32 0x21b001c 0x09408038 - wm 32 0x21b001c 0x04008040 -wm 32 0x21b001c 0x04008048 -wm 32 0x21b0800 0xA1380003 -wm 32 0x21b4800 0xA1380003 wm 32 0x21b0020 0x00005800 -wm 32 0x21b0818 0x00022227 -wm 32 0x21b4818 0x00022227 - -wm 32 0x21b083c 0x434B0350 -wm 32 0x21b0840 0x034C0359 -wm 32 0x21b483c 0x434B0350 -wm 32 0x21b4840 0x03650348 -wm 32 0x21b0848 0x4436383B -wm 32 0x21b4848 0x39393341 -wm 32 0x21b0850 0x35373933 -wm 32 0x21b4850 0x48254A36 - -wm 32 0x21b080c 0x001F001F -wm 32 0x21b0810 0x001F001F - -wm 32 0x21b480c 0x00440044 -wm 32 0x21b4810 0x00440044 - -wm 32 0x21b08b8 0x00000800 -wm 32 0x21b48b8 0x00000800 - -wm 32 0x21b001c 0x00000000 +wm 32 0x21b0818 0x00011117 +wm 32 0x21b4818 0x00011117 +wm 32 0x21b0004 0x00025576 wm 32 0x21b0404 0x00011006 - -wm 32 0x020c4068 0x00c03f3f -wm 32 0x020c406c 0x0030fc03 -wm 32 0x020c4070 0x0fffc000 -wm 32 0x020c4074 0x3ff00000 -wm 32 0x020c4078 0x00fff300 -wm 32 0x020c407c 0x0f0000c3 -wm 32 0x020c4080 0x000003ff - -# enable AXI cache for VDOA/VPU/IPU -wm 32 0x20e0010 0xf00000cf -# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 -wm 32 0x20e0018 0x007f007f -wm 32 0x20e001c 0x007f007f +wm 32 0x21b001c 0x00000000 diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg new file mode 100644 index 0000000000..224ac3207f --- /dev/null +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6qp-sabresd.imxcfg @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only + +loadaddr 0x10000000 +soc imx6 +ivtofs 0x400 +wm 32 0x20e0798 0x000c0000 +wm 32 0x20e0758 0x00000000 +wm 32 0x20e0588 0x00000030 +wm 32 0x20e0594 0x00000030 +wm 32 0x20e056c 0x00000030 +wm 32 0x20e0578 0x00000030 +wm 32 0x20e074c 0x00000030 +wm 32 0x20e057c 0x00000030 +wm 32 0x20e058c 0x00000000 +wm 32 0x20e059c 0x00000030 +wm 32 0x20e05a0 0x00000030 +wm 32 0x20e078c 0x00000030 +wm 32 0x20e0750 0x00020000 +wm 32 0x20e05a8 0x00000030 +wm 32 0x20e05b0 0x00000030 +wm 32 0x20e0524 0x00000030 +wm 32 0x20e051c 0x00000030 +wm 32 0x20e0518 0x00000030 +wm 32 0x20e050c 0x00000030 +wm 32 0x20e05b8 0x00000030 +wm 32 0x20e05c0 0x00000030 +wm 32 0x20e0774 0x00020000 +wm 32 0x20e0784 0x00000030 +wm 32 0x20e0788 0x00000030 +wm 32 0x20e0794 0x00000030 +wm 32 0x20e079c 0x00000030 +wm 32 0x20e07a0 0x00000030 +wm 32 0x20e07a4 0x00000030 +wm 32 0x20e07a8 0x00000030 +wm 32 0x20e0748 0x00000030 +wm 32 0x20e05ac 0x00000030 +wm 32 0x20e05b4 0x00000030 +wm 32 0x20e0528 0x00000030 +wm 32 0x20e0520 0x00000030 +wm 32 0x20e0514 0x00000030 +wm 32 0x20e0510 0x00000030 +wm 32 0x20e05bc 0x00000030 +wm 32 0x20e05c4 0x00000030 +wm 32 0x21b0800 0xa1390003 +wm 32 0x21b080c 0x001b001e +wm 32 0x21b0810 0x002e0029 +wm 32 0x21b480c 0x001b002a +wm 32 0x21b4810 0x0019002c +wm 32 0x21b083c 0x43240334 +wm 32 0x21b0840 0x0324031a +wm 32 0x21b483c 0x43340344 +wm 32 0x21b4840 0x03280276 +wm 32 0x21b0848 0x44383A3E +wm 32 0x21b4848 0x3C3C3846 +wm 32 0x21b0850 0x2e303230 +wm 32 0x21b4850 0x38283E34 +wm 32 0x21b081c 0x33333333 +wm 32 0x21b0820 0x33333333 +wm 32 0x21b0824 0x33333333 +wm 32 0x21b0828 0x33333333 +wm 32 0x21b481c 0x33333333 +wm 32 0x21b4820 0x33333333 +wm 32 0x21b4824 0x33333333 +wm 32 0x21b4828 0x33333333 +wm 32 0x21b08c0 0x24912249 +wm 32 0x21b48c0 0x24914289 +wm 32 0x21b08b8 0x00000800 +wm 32 0x21b48b8 0x00000800 +wm 32 0x21b0004 0x00020036 +wm 32 0x21b0008 0x24444040 +wm 32 0x21b000c 0x555A7955 +wm 32 0x21b0010 0xFF320F64 +wm 32 0x21b0014 0x01ff00db +wm 32 0x21b0018 0x00001740 +wm 32 0x21b001c 0x00008000 +wm 32 0x21b002c 0x000026d2 +wm 32 0x21b0030 0x005A1023 +wm 32 0x21b0040 0x00000027 +wm 32 0x21b0400 0x14420000 +wm 32 0x21b0000 0x831A0000 +wm 32 0x21b0890 0x00400C58 +wm 32 0x0bb0008 0x00000000 +wm 32 0x0bb000c 0x2891E41A +wm 32 0x0bb0038 0x00000564 +wm 32 0x0bb0014 0x00000040 +wm 32 0x0bb0028 0x00000020 +wm 32 0x0bb002c 0x00000020 +wm 32 0x21b001c 0x04088032 +wm 32 0x21b001c 0x00008033 +wm 32 0x21b001c 0x00048031 +wm 32 0x21b001c 0x09408030 +wm 32 0x21b001c 0x04008040 +wm 32 0x21b0020 0x00005800 +wm 32 0x21b0818 0x00011117 +wm 32 0x21b4818 0x00011117 +wm 32 0x21b0004 0x00025576 +wm 32 0x21b0404 0x00011006 +wm 32 0x21b001c 0x00000000 diff --git a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c index ae847feaa6..7cc08b47d5 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx6-sabresd/lowlevel.c @@ -1,8 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx6.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> @@ -35,3 +38,35 @@ ENTRY_FUNCTION(start_imx6q_sabresd, r0, r1, r2) barebox_arm_entry(0x10000000, SZ_1G, fdt); } + +extern char __dtb_imx6qp_sabresd_start[]; + +ENTRY_FUNCTION(start_imx6qp_sabresd, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx6qp_sabresd_start + get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} + +extern char __dtb_imx6dl_sabresd_start[]; + +ENTRY_FUNCTION(start_imx6dl_sabresd, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx6dl_sabresd_start + get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile b/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c index 0fd9af80cb..22163a4864 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c @@ -1,37 +1,26 @@ -/* - * Copyright (C) 2014 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix + #define pr_fmt(fmt) "imx6sx-sdb: " fmt #include <environment.h> -#include <partition.h> #include <common.h> #include <linux/sizes.h> +#include <linux/phy.h> #include <gpio.h> #include <init.h> #include <io.h> #include <mfd/imx6q-iomuxc-gpr.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <i2c/i2c.h> #include <asm/armlinux.h> -#include <mach/devices-imx6.h> -#include <mach/imx6-regs.h> -#include <mach/iomux-mx6.h> -#include <mach/generic.h> -#include <mach/imx6.h> -#include <mach/bbu.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6.h> +#include <mach/imx/bbu.h> #define PFUZE100_DEVICEID 0x0 #define PFUZE100_REVID 0x3 diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg index a96b3e7154..ebae00b8ea 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c index 6a6e27bf44..721743dadb 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/lowlevel.c @@ -1,21 +1,11 @@ -/* - * Copyright (C) 2014 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/freescale-mx7-sabresd/Makefile b/arch/arm/boards/freescale-mx7-sabresd/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/Makefile +++ b/arch/arm/boards/freescale-mx7-sabresd/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx7-sabresd/board.c b/arch/arm/boards/freescale-mx7-sabresd/board.c index 37941efdbe..03658ddc7c 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/board.c +++ b/arch/arm/boards/freescale-mx7-sabresd/board.c @@ -1,22 +1,12 @@ -/* - * Copyright (C) 2017 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <init.h> #include <io.h> -#include <mach/imx7-regs.h> +#include <mach/imx/imx7-regs.h> #include <linux/phy.h> #include <mfd/imx7-iomuxc-gpr.h> diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg index f4920bc133..0b0780ed9b 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg @@ -1,5 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
\ No newline at end of file +#include <mach/imx/flash-header/imx7d-ddr-sabresd.imxcfg> diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c index f718ea73b3..5a7508143e 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c +++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c @@ -1,31 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <io.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx7-ccm-regs.h> -#include <mach/iomux-mx7.h> -#include <mach/debug_ll.h> +#include <mach/imx/imx7-ccm-regs.h> +#include <mach/imx/iomux-mx7.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> extern char __dtb_imx7d_sdb_start[]; static inline void setup_uart(void) { - void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); - void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); - - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__OSC_24M, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + imx7_early_setup_uart_clock(1); - mx7_setup_pad(iomux, MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); + imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); imx7_uart_setup_ll(); diff --git a/arch/arm/boards/freescale-vf610-twr/Makefile b/arch/arm/boards/freescale-vf610-twr/Makefile index b08c4a93ca..458f520900 100644 --- a/arch/arm/boards/freescale-vf610-twr/Makefile +++ b/arch/arm/boards/freescale-vf610-twr/Makefile @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg index 71150802bf..bad742831a 100644 --- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg +++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg @@ -1,14 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc vf610 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/vf610-iomux-regs.h> -#include <mach/vf610-ddrmc-regs.h> +#include <mach/imx/vf610-iomux-regs.h> +#include <mach/imx/vf610-ddrmc-regs.h> -#include <mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg> -#include <mach/flash-header/vf610-iomux-ddr-default.imxcfg> -#include <mach/flash-header/vf610-ddr-cr-default.imxcfg> -#include <mach/flash-header/vf610-ddr-phy-default.imxcfg> +#include <mach/imx/flash-header/vf610-ddr-pll2-400mhz.imxcfg> +#include <mach/imx/flash-header/vf610-iomux-ddr-default.imxcfg> +#include <mach/imx/flash-header/vf610-ddr-cr-default.imxcfg> +#include <mach/imx/flash-header/vf610-ddr-phy-default.imxcfg> wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c index 8fec9f4b91..c7714f29a2 100644 --- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c +++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c @@ -1,13 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/esdctl.h> -#include <mach/vf610-regs.h> -#include <mach/clock-vf610.h> -#include <mach/iomux-vf610.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/vf610-regs.h> +#include <mach/imx/clock-vf610.h> +#include <mach/imx/iomux-vf610.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/friendlyarm-mini2440/Kconfig b/arch/arm/boards/friendlyarm-mini2440/Kconfig deleted file mode 100644 index feb905e96e..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ - -if MACH_MINI2440 - -config MINI2440_VIDEO - bool - select VIDEO - select DRIVER_VIDEO_S3C24XX - -config MINI2440_VIDEO_N35 - bool "Support N35 display (240x320)" - select MINI2440_VIDEO - help - This adds support for NEC 3.5 inch TFT display, - the most common one used with MINI2440 board. - -config MINI2440_VIDEO_A70 - bool "Support A70 display (800x480)" - select MINI2440_VIDEO - help - This adds support for Innolux 7.0 inch TFT display. - -config MINI2440_VIDEO_SVGA - bool "Support SVGA video adapter" - select MINI2440_VIDEO - help - This adds support for MINI2440 SVGA (1024x768) video output adapter. - -config MINI2440_VIDEO_W35 - bool "Support W35 display (320x240)" - select MINI2440_VIDEO - help - This adds support for Sharp 3.5 inch TFT display. - -endif diff --git a/arch/arm/boards/friendlyarm-mini2440/Makefile b/arch/arm/boards/friendlyarm-mini2440/Makefile deleted file mode 100644 index da3520cc81..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/Makefile +++ /dev/null @@ -1,3 +0,0 @@ - -obj-y += mini2440.o -lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/friendlyarm-mini2440/config.h b/arch/arm/boards/friendlyarm-mini2440/config.h deleted file mode 100644 index 489697f6d5..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/config.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * @brief Global defintions for the ARM S3C2440 based mini2440 CPU card - */ -/* This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/** - * The external clock reference is a 12.00 MHz crystal - */ -#define S3C24XX_CLOCK_REFERENCE 12000000 - -/** - * Define the main clock configuration to be used in register CLKDIVN - * - * We must limit the frequency of the connected SDRAMs with the clock ratio - * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 405Mhz:102MHz:51MHz - */ -#define BOARD_SPECIFIC_CLKDIVN 0x05 - -/** - * Define the MPLL configuration to be used in register MPLLCON - * - * We want the MPLL to run at 405.0 MHz - */ -#define BOARD_SPECIFIC_MPLL ((0x7f << 12) + (2 << 4) + 1) - -/** - * Define the UPLL configuration to be used in register UPLLCON - * - * We want the UPLL to run at 48.0 MHz - */ -#define BOARD_SPECIFIC_UPLL ((0x38 << 12) + (2 << 4) + 2) - -/* - * Flash access timings - * Tacls = 0ns (but 20ns data setup time) - * Twrph0 = 25ns (write) 35ns (read) - * Twrph1 = 10ns (10ns data hold time) - * Read cycle time = 50ns - * - * Assumed HCLK is 100MHz - * Tacls = 1 (-> 20ns) - * Twrph0 = 3 (-> 40ns) - * Twrph1 = 1 (-> 20ns) - * Cycle time = 80ns - */ -#define MINI2440_TACLS 1 -#define MINI2440_TWRPH0 3 -#define MINI2440_TWRPH1 1 - -/* needed in the generic NAND boot code only */ -#ifdef CONFIG_S3C_NAND_BOOT -# define BOARD_DEFAULT_NAND_TIMING \ - CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1) -#endif - -/* - * Needed in the generic SDRAM boot code only - * - * SDRAM configuration - * Two types of SDRAM devices are common on mini2440: - * - Two devices of HY57V561620 to form 64 MiB in bank 6 only - * - http://friendlyarm.net/dl.php?file=HY57V561620.pdf - * - Two devices of MT48LC16M16 to form 64 MiB in bank 6 only - * - http://friendlyarm.net/dl.php?file=MT48LC16M16.pdf - - * Most of the time the CPU is specified for 400 MHz only. As the CPU frequency - * and the SDRAM frequency are fix coupled by 4:1, the SDRAM runs at HCLCK. - * So, we need a 100 MHz timing setup with CL=2 for the SDRAMs. - */ - -/* - * - ST7/WS7/DW7: reserved, this SDRAM bank is not used - * - ST6/WS6/DW6: 32 bit data bus (for SDRAM usage) - * - ST5/WS5/DW5: reserved, to be set by the board init code - * - ST4/WS4/DW4: reserved, to be set by the board init code - * - ST3/WS3/DW3: reserved, to be set by the board init code - * - ST2/WS2/DW2: reserved, to be set by the board init code - * - ST1/WS1/DW1: reserved, to be set by the board init code - * - DW0: not to be changed - */ -#define BOARD_SPECIFIC_BWSCON ((0x3 << 28) | (0x2 << 24) | 0x333330) -/* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ -#define BOARD_SPECIFIC_BANKCON6 ((0x3 << 15) + (0x0 << 2) + (0x1)) -#define BOARD_SPECIFIC_BANKCON7 0 /* disabled */ -/* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refresh = 2^11 + 1 - 100 * 7.8 = 2049 - 780 = 1269 - */ -#define BOARD_SPECIFIC_REFRESH ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 1269) -/* - * SDRAM banksize - * - BURST_EN = 1 (= burst mode enabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 001 (= 64 MiB) - */ -# define BOARD_SPECIFIC_BANKSIZE ((1 << 7) + (1 << 5) + (1 << 4) + 1) -/* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ -# define BOARD_SPECIFIC_MRSRB6 (0x2 << 4) -# define BOARD_SPECIFIC_MRSRB7 0 /* not used */ - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand b/arch/arm/boards/friendlyarm-mini2440/env/boot/nand deleted file mode 100644 index e0ef904432..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/env/boot/nand +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/friendlyarm-mini2440/env/config-board b/arch/arm/boards/friendlyarm-mini2440/env/config-board deleted file mode 100644 index 3e07a015b0..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/env/config-board +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.linux.bootargs.console="console=ttySAC0,115200" - -# -# "mini2440" kernel parameter -# 0 .. 9 = screen type -# b = backlight enabled -# t = touch enabled -# c = camera enabled -# Note: can be "minit2440= " if nothing of these components are connected -# -global.linux.bootargs.base="mini2440=6tb" diff --git a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand b/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand deleted file mode 100644 index b51104ad76..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/env/init/mtdparts-nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="256k(nand0.barebox),128k(nand0.bareboxenv),1536k(nand0.kernel),-(nand0.root)" -kernelname="nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S b/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S deleted file mode 100644 index 43bf49c12c..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/lowlevel_init.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Low level initialization for the FriendlyARM mini2440 board - */ - -#include <config.h> -#include <linux/sizes.h> -#include <mach/s3c-iomap.h> -#include <asm/barebox-arm-head.h> - - .section ".text_bare_init.barebox_arm_reset_vector","ax" - -/* ------------------------------------------------------------------------ */ - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - - bl s3c24x0_disable_wd - - /* skip everything here if we are already running from SDRAM */ - cmp pc, #S3C_SDRAM_BASE - blo 1f - cmp pc, #S3C_SDRAM_END - bhs 1f - - b out - -/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ -1: - bl s3c24x0_pll_init - - bl s3c24x0_sdram_init - -#ifdef CONFIG_S3C_NAND_BOOT -/* up to here we are running from the internal SRAM area */ - bl s3c24x0_nand_boot -#endif -out: - mov r0, #S3C_SDRAM_BASE - mov r1, #SZ_32M - mov r2, #0 - b barebox_arm_entry diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c deleted file mode 100644 index 7f59cb99b2..0000000000 --- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (C) 2010 Marek Belisko <marek.belisko@open-nandra.com> - * - * Based on a9m2440.c board init by Juergen Beisert, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <platform_data/eth-dm9000.h> -#include <nand.h> -#include <mci.h> -#include <fb.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <io.h> -#include <gpio.h> -#include <mach/bbu.h> -#include <mach/iomux.h> -#include <mach/s3c-iomap.h> -#include <mach/devices-s3c24xx.h> -#include <mach/s3c24xx-nand.h> -#include <mach/s3c-generic.h> -#include <mach/s3c-mci.h> -#include <mach/s3c24xx-fb.h> -#include <mach/s3c-busctl.h> -#include <mach/s3c24xx-gpio.h> - -static struct s3c24x0_nand_platform_data nand_info = { - .nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, - MINI2440_TWRPH1), - .flash_bbt = 1, /* same as the kernel */ -}; - -/* - * dm9000 network controller onboard - * Connected to CS line 4 and interrupt line EINT7, - * data width is 16 bit - * Area 1: Offset 0x300...0x303 - * Area 2: Offset 0x304...0x307 - */ -static struct dm9000_platform_data dm9000_data = { - .srom = 1, -}; - -static struct s3c_mci_platform_data mci_data = { - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_detect = 232, /* GPG8_GPIO */ - .detect_invert = 0, -}; - -static struct fb_videomode s3c24x0_fb_modes[] = { -#ifdef CONFIG_MINI2440_VIDEO_N35 - { - .name = "N35", - .refresh = 60, - .xres = 240, - .left_margin = 21, - .right_margin = 38, - .hsync_len = 6, - .yres = 320, - .upper_margin = 4, - .lower_margin = 4, - .vsync_len = 2, - .pixclock = 115913, - .sync = FB_SYNC_USE_PWREN, - .vmode = FB_VMODE_NONINTERLACED, - }, -#endif -#ifdef CONFIG_MINI2440_VIDEO_A70 - { - .name = "A70", - .refresh = 50, - .xres = 800, - .left_margin = 40, - .right_margin = 40, - .hsync_len = 48, - .yres = 480, - .upper_margin = 29, - .lower_margin = 3, - .vsync_len = 3, - .pixclock = 41848, - .sync = FB_SYNC_USE_PWREN | FB_SYNC_DE_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - }, -#endif -#ifdef CONFIG_MINI2440_VIDEO_SVGA - { - .name = "SVGA", - .refresh = 24, - .xres = 1024, - .left_margin = 1, - .right_margin = 2, - .hsync_len = 2, - .yres = 768, - .upper_margin = 200, - .lower_margin = 16, - .vsync_len = 16, - .pixclock = 40492, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT - /* | FB_SYNC_SWAP_HW */ /* FIXME maybe */ , - .vmode = FB_VMODE_NONINTERLACED, - }, -#endif -#ifdef CONFIG_MINI2440_VIDEO_W35 - { - .name = "W35", - .refresh = 60, - .xres = 320, - .left_margin = 68, - .right_margin = 66, - .hsync_len = 4, - .yres = 240, - .upper_margin = 4, - .lower_margin = 4, - .vsync_len = 9, - .pixclock = 115913, - .sync = FB_SYNC_USE_PWREN | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - }, -#endif -}; - -static struct s3c_fb_platform_data s3c24x0_fb_data = { - .mode_list = s3c24x0_fb_modes, - .mode_cnt = sizeof(s3c24x0_fb_modes) / sizeof(struct fb_videomode), - .bits_per_pixel = 16, - .passive_display = 0, -}; - -static const unsigned pin_usage[] = { - /* address bus, used by NOR, SDRAM */ - GPA1_ADDR16, - GPA2_ADDR17, - GPA3_ADDR18, - GPA4_ADDR19, - GPA5_ADDR20, - GPA6_ADDR21, - GPA7_ADDR22, - - GPA8_ADDR23_GPIO | GPIO_IN, - GPA9_ADDR24, /* BA0 */ - GPA10_ADDR25, /* BA1 */ - GPA11_ADDR26_GPIO | GPIO_IN, /* not connected */ - - /* DM9000 requirements */ - GPA15_NGCS4, - GPF7_EINT7, - - /* de-activate the speaker */ - GPB0_GPIO | GPIO_OUT | GPIO_VAL(0), - - /* SD socket */ - GPE5_SDCLK, - GPE6_SDCMD, - GPE7_SDDAT0, - GPE8_SDDAT1, - GPE9_SDDAT2, - GPE10_SDDAT3, - GPG8_GPIO | GPIO_IN, /* change detection */ - GPH8_GPIO | GPIO_IN, /* write protection sense */ - - /* NAND requirements */ - GPA17_CLE, - GPA18_ALE, - GPA19_NFWE, - GPA20_NFRE, - GPA21_NRSTOUT, - GPA22_NFCE, - - /* Video out */ - GPC0_LEND, - GPC1_VCLK, - GPC2_VLINE, - GPC3_VFRAME, - GPC4_VM, - GPC5_LPCOE, - GPC6_LPCREV, - GPC7_LPCREVB, - GPG4_LCD_PWREN, - - GPC8_VD0, - GPC9_VD1, - GPC10_VD2, - GPC11_VD3, - GPC12_VD4, - GPC13_VD5, - GPC14_VD6, - GPC15_VD7, - GPD0_VD8, - GPD1_VD9, - GPD2_VD10, - GPD3_VD11, - GPD4_VD12, - GPD5_VD13, - GPD6_VD14, - GPD7_VD15, - GPD8_VD16, - GPD9_VD17, - GPD10_VD18, - GPD11_VD19, - GPD12_VD20, - GPD13_VD21, - GPD14_VD22, - GPD15_VD23, - - /* K6 or CON12, pin 6, external pull up */ - GPG11_EINT19 | GPIO_IN, - /* K5 or CON12, pin 5*/ - GPG7_EINT15 | GPIO_IN, - /* K4 or CON12, pin 4 */ - GPG6_EINT14 | GPIO_IN, - /* K3 or CON12, pin 3 */ - GPG5_EINT13 | GPIO_IN, - /* K2 or CON12, pin 2 */ - GPG3_EINT11 | GPIO_IN, - /* K1 or CON12, pin 1, external pull up */ - GPG0_EINT8 | GPIO_IN, - - /* LED 1 1=off */ - GPB5_GPIO | GPIO_OUT | GPIO_VAL(1), - /* LED 2 1=off */ - GPB6_GPIO | GPIO_OUT | GPIO_VAL(1), - /* LED 3 1=off */ - GPB7_GPIO | GPIO_OUT | GPIO_VAL(1), - /* LED 4 1=off */ - GPB8_GPIO | GPIO_OUT | GPIO_VAL(1), - - /* camera interface (ignore it) */ - GPJ0_GPIO | GPIO_IN, - GPJ1_GPIO | GPIO_IN, - GPJ2_GPIO | GPIO_IN, - GPJ3_GPIO | GPIO_IN, - GPJ4_GPIO | GPIO_IN, - GPJ5_GPIO | GPIO_IN, - GPJ6_GPIO | GPIO_IN, - GPJ7_GPIO | GPIO_IN, - GPJ8_GPIO | GPIO_IN, - GPJ9_GPIO | GPIO_IN, - GPJ10_GPIO | GPIO_IN, - GPJ11_GPIO | GPIO_IN, - GPJ12_GPIO | GPIO_IN, - - /* I2C bus */ - GPE14_IICSCL, /* external pull up */ - GPE15_IICSDA, /* external pull up */ - - GPA12_NGCS1, /* CON5, pin 7 */ - GPA13_NGCS2, /* CON5, pin 8 */ - GPA14_NGCS3, /* CON5, pin 9 */ - GPA16_NGCS5, /* CON5, pin 10 */ - - /* UART2 (spare) */ - GPH4_TXD1, - GPH5_RXD1, - - /* UART3 (spare) */ - GPH6_TXD2, - GPH7_RXD2, -}; - -static int mini2440_mem_init(void) -{ - arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size()); - - return 0; -} -mem_initcall(mini2440_mem_init); - -static int mini2440_devices_init(void) -{ - uint32_t reg; - int i; - - /* ----------- configure the access to the outer space ---------- */ - for (i = 0; i < ARRAY_SIZE(pin_usage); i++) - s3c_gpio_mode(pin_usage[i]); - - reg = readl(S3C_BWSCON); - - /* CS#4 to access the network controller */ - reg &= ~0x000f0000; - reg |= 0x000d0000; /* 16 bit */ - writel(0x1f4c, S3C_BANKCON4); - - writel(reg, S3C_BWSCON); - - /* release the reset signal to external devices */ - reg = readl(S3C_MISCCR); - reg |= 0x10000; - writel(reg, S3C_MISCCR); - - s3c24xx_add_nand(&nand_info); - - add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304, - IORESOURCE_MEM_16BIT, &dm9000_data); -#ifdef CONFIG_NAND - /* ----------- add some vital partitions -------- */ - devfs_del_partition("self_raw"); - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_del_partition("env_raw"); - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - s3c24x0_bbu_nand_register_handler(); -#endif - s3c24xx_add_mci(&mci_data); - s3c24xx_add_fb(&s3c24x0_fb_data); - s3c24xx_add_ohci(); - armlinux_set_architecture(MACH_TYPE_MINI2440); - - return 0; -} - -device_initcall(mini2440_devices_init); - -static int mini2440_console_init(void) -{ - /* - * configure the UART1 right now, as barebox will - * start to send data immediately - */ - s3c_gpio_mode(GPH0_NCTS0); - s3c_gpio_mode(GPH1_NRTS0); - s3c_gpio_mode(GPH2_TXD0); - s3c_gpio_mode(GPH3_RXD0); - - barebox_set_model("Friendlyarm mini2440"); - barebox_set_hostname("mini2440"); - - s3c24xx_add_uart1(); - return 0; -} - -console_initcall(mini2440_console_init); diff --git a/arch/arm/boards/friendlyarm-mini6410/Makefile b/arch/arm/boards/friendlyarm-mini6410/Makefile deleted file mode 100644 index c04150e97f..0000000000 --- a/arch/arm/boards/friendlyarm-mini6410/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += mini6410.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-friendlyarm-mini6410 diff --git a/arch/arm/boards/friendlyarm-mini6410/config.h b/arch/arm/boards/friendlyarm-mini6410/config.h deleted file mode 100644 index ee38192041..0000000000 --- a/arch/arm/boards/friendlyarm-mini6410/config.h +++ /dev/null @@ -1,8 +0,0 @@ -/* FriendlyARM Mini6410 specific global settings */ - -#ifndef _MINI6410_CONFIG_H_ -# define _MINI6410_CONFIG_H_ - -#define S3C64XX_CLOCK_REFERENCE 12000000 - -#endif /* _MINI6410_CONFIG_H_ */ diff --git a/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config b/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config deleted file mode 100644 index 924d7b8cc7..0000000000 --- a/arch/arm/boards/friendlyarm-mini6410/defaultenv-friendlyarm-mini6410/config +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/sh - -machine=mini6410 -eth0.serverip=a.b.c.d.e -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d.e -#eth0.netmask=a.b.c.d.e -#eth0.gateway=a.b.c.d.e -#eth0.ethaddr= - -# can be either 'nfs', 'tftp' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${machine}.${rootfs_type} - -# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo -kernelimage=zImage-${machine} -#kernelimage=uImage-$machine -#kernelimage=Image-$machine -#kernelimage=Image-$machine.lzo - -if [ -n $user ]; then - kernelimage="${user}"-"${kernelimage}" - nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}" - rootfsimage="${user}"-"${rootfsimage}" -else - nfsroot="${eth0.serverip}:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -# -# "mini6410" kernel parameter -# 0 .. 9 = screen type -# i = touchscreen with propritary FriendlyARM protocol -# Note: can be "minit6410= " if nothing of these components are connected -# -bootargs="console=ttySAC0,115200 mini6410=0" - -nand_device="nand" -nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)" -rootfs_mtdblock_nand=3 diff --git a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c deleted file mode 100644 index ccbdd13795..0000000000 --- a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c +++ /dev/null @@ -1,11 +0,0 @@ -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/s3c-iomap.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL); -} diff --git a/arch/arm/boards/friendlyarm-mini6410/mini6410.c b/arch/arm/boards/friendlyarm-mini6410/mini6410.c deleted file mode 100644 index 90fb3f5c1e..0000000000 --- a/arch/arm/boards/friendlyarm-mini6410/mini6410.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright (C) 2012 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <common.h> -#include <driver.h> -#include <init.h> -#include <platform_data/eth-dm9000.h> -#include <gpio.h> -#include <envfs.h> -#include <generated/mach-types.h> -#include <asm/armlinux.h> -#include <mach/s3c-iomap.h> -#include <mach/devices-s3c64xx.h> -#include <mach/s3c-generic.h> -#include <mach/iomux.h> - -/* - * dm9000 network controller onboard - * Connected to CS line 1 and interrupt line EINT7, - * data width is 16 bit - * Area 1: Offset 0x300...0x301 - * Area 2: Offset 0x304...0x305 - */ -static struct dm9000_platform_data dm9000_data = { - .srom = 0, /* no serial ROM for the ethernet address */ -}; - -static const unsigned pin_usage[] = { - /* UART2 (spare, 3,3 V TTL level only) */ - GPA4_RXD1 | ENABLE_PU, - GPA5_TXD1, - GPA6_NCTS1 | ENABLE_PU, - GPA7_NRTS1, - /* UART3 (spare, 3,3 V TTL level only) */ - GPB0_RXD2 | ENABLE_PU, - GPB1_TXD2, - /* UART4 (spare, 3,3 V TTL level only) */ - GPB2_RXD3 | ENABLE_PU, - GPB3_TXD3, - - GPB4_GPIO | GPIO_IN | ENABLE_PU, - - /* I2C bus */ - GPB5_IIC0_SCL, /* external PU */ - GPB6_IIC0_SDA, /* external PU */ - - GPC0_SPI0_MISO | ENABLE_PU, - GPC1_SPI0_CLK, - GPC2_SPI0_MOSI, - GPC3_SPI0_NCS, - - GPC4_SPI1_MISO | ENABLE_PU, - GPC5_SPI1_CLK, - GPC6_SPI1_MOSI, - GPC7_SPI1_NCS, - - GPD0_AC97_BITCLK, - GPD1_AC97_NRST, - GPD2_AC97_SYNC, - GPD3_AC97_SDI | ENABLE_PU, - GPD4_AC97_SDO, - - GPE0_GPIO | GPIO_OUT | GPIO_VAL(0), /* LCD backlight off */ - GPE1_GPIO | GPIO_IN | ENABLE_PU, - GPE2_GPIO | GPIO_IN | ENABLE_PU, - GPE3_GPIO | GPIO_IN | ENABLE_PU, - GPE4_GPIO | GPIO_IN | ENABLE_PU, - - /* keep all camera signals at reasonable values */ - GPF0_GPIO | GPIO_IN | ENABLE_PU, - GPF1_GPIO | GPIO_IN | ENABLE_PU, - GPF2_GPIO | GPIO_IN | ENABLE_PU, - GPF3_GPIO | GPIO_IN | ENABLE_PU, - GPF4_GPIO | GPIO_IN | ENABLE_PU, - GPF5_GPIO | GPIO_IN | ENABLE_PU, - GPF6_GPIO | GPIO_IN | ENABLE_PU, - GPF7_GPIO | GPIO_IN | ENABLE_PU, - GPF8_GPIO | GPIO_IN | ENABLE_PU, - GPF9_GPIO | GPIO_IN | ENABLE_PU, - GPF10_GPIO | GPIO_IN | ENABLE_PU, - GPF11_GPIO | GPIO_IN | ENABLE_PU, - GPF12_GPIO | GPIO_IN | ENABLE_PU, - GPF13_GPIO | GPIO_OUT | GPIO_VAL(0), /* USB power off */ -#if 0 - GPF14_CLKOUT, /* for testing purposes, but very noisy */ -#else - GPF14_GPIO | GPIO_OUT | GPIO_VAL(0), /* Buzzer off */ -#endif - GPF15_GPIO | GPIO_OUT | GPIO_VAL(0), /* Backlight PWM inactive */ - - /* SD card slot (all signals have external 10k PU) */ - GPG0_MMC0_CLK, - GPG1_MMC0_CMD, - GPG2_MMC0_DAT0, - GPG3_MMC0_DAT1, - GPG4_MMC0_DAT2, - GPG5_MMC0_DAT3, - GPG6_MMC0_NCD, - - /* SDIO slot (all used signals have external PU) */ - GPH0_GPIO | GPIO_IN, /* CLK */ - GPH1_GPIO | GPIO_IN, /* CMD */ - GPH2_GPIO | GPIO_IN, /* DAT0 */ - GPH3_GPIO | GPIO_IN, /* DAT1 */ - GPH4_GPIO | GPIO_IN, /* DAT2 */ - GPH5_GPIO | GPIO_IN, /* DAT3 */ - GPH6_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */ - GPH7_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */ - GPH8_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */ - GPH9_GPIO | GPIO_IN | ENABLE_PU, /* nowhere connected */ - - /* as long as we are not using the LCD controller, disable the pins */ - GPI0_GPIO | GPIO_IN | ENABLE_PD, - GPI1_GPIO | GPIO_IN | ENABLE_PD, - GPI2_GPIO | GPIO_IN | ENABLE_PD, - GPI3_GPIO | GPIO_IN | ENABLE_PD, - GPI4_GPIO | GPIO_IN | ENABLE_PD, - GPI5_GPIO | GPIO_IN | ENABLE_PD, - GPI6_GPIO | GPIO_IN | ENABLE_PD, - GPI7_GPIO | GPIO_IN | ENABLE_PD, - GPI8_GPIO | GPIO_IN | ENABLE_PD, - GPI9_GPIO | GPIO_IN | ENABLE_PD, - GPI10_GPIO | GPIO_IN | ENABLE_PD, - GPI11_GPIO | GPIO_IN | ENABLE_PD, - GPI12_GPIO | GPIO_IN | ENABLE_PD, - GPI13_GPIO | GPIO_IN | ENABLE_PD, - GPI14_GPIO | GPIO_IN | ENABLE_PD, - GPI15_GPIO | GPIO_IN | ENABLE_PD, - GPJ0_GPIO | GPIO_IN | ENABLE_PD, - GPJ1_GPIO | GPIO_IN | ENABLE_PD, - GPJ2_GPIO | GPIO_IN | ENABLE_PD, - GPJ3_GPIO | GPIO_IN | ENABLE_PD, - GPJ4_GPIO | GPIO_IN | ENABLE_PD, - GPJ5_GPIO | GPIO_IN | ENABLE_PD, - GPJ6_GPIO | GPIO_IN | ENABLE_PD, - GPJ7_GPIO | GPIO_IN | ENABLE_PD, - GPJ8_GPIO | GPIO_IN | ENABLE_PD, - GPJ9_GPIO | GPIO_IN | ENABLE_PD, - GPJ10_GPIO | GPIO_IN | ENABLE_PD, - GPJ11_GPIO | GPIO_IN | ENABLE_PD, - - GPK0_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK1_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK2_GPIO | GPIO_IN, - GPK3_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK4_GPIO | GPIO_OUT | GPIO_VAL(1), /* LED #1 (high = LED off) */ - GPK5_GPIO | GPIO_OUT | GPIO_VAL(1), /* LED #2 (high = LED off) */ - GPK6_GPIO | GPIO_OUT | GPIO_VAL(1), /* LED #3 (high = LED off) */ - GPK7_GPIO | GPIO_OUT | GPIO_VAL(1), /* LED #4 (high = LED off) */ - GPK8_GPIO | GPIO_IN, /* (external PU) */ - GPK9_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK10_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK11_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK12_GPIO | GPIO_IN, /* OCT_DET */ - GPK13_GPIO | GPIO_IN, /* WIFI power (external PU) */ - GPK14_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPK15_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - - GPL0_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL1_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL2_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL3_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL4_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL5_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL6_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL7_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPL8_GPIO | GPIO_IN, /* EINT16 (external PU) */ - GPL9_GPIO | GPIO_IN | ENABLE_PU, /* EINT17 */ - GPL10_GPIO | GPIO_IN | ENABLE_PU, /* EINT18 */ - GPL11_GPIO | GPIO_IN, /* EINT19 + K7 (external PU) */ - GPL12_GPIO | GPIO_IN, /* EINT20 + K6 (external PU) */ - GPL13_GPIO | GPIO_IN, /* SD0 WP (external PU) */ - GPL14_GPIO | GPIO_IN, /* SD1 WP (external PU) */ - - GPM0_GPIO | GPIO_IN, /* (external PU) */ - GPM1_GPIO | GPIO_IN, /* (external PU) */ - GPM2_GPIO | GPIO_IN, /* (external PU) */ - GPM3_GPIO | GPIO_IN, /* (external PU) */ - GPM4_GPIO | GPIO_IN, /* (external PU) */ - GPM5_GPIO | GPIO_IN, /* (external PU) */ - - GPN0_GPIO | GPIO_IN, /* EINT0 (external PU) */ - GPN1_GPIO | GPIO_IN, /* EINT1 (external PU) */ - GPN2_GPIO | GPIO_IN, /* EINT2 (external PU) */ - GPN3_GPIO | GPIO_IN, /* EINT3 (external PU) */ - GPN4_GPIO | GPIO_IN, /* EINT4 (external PU) */ - GPN5_GPIO | GPIO_IN, /* EINT5 (external PU) */ - GPN6_GPIO | GPIO_IN, /* EINT6 (external PU) */ - GPN7_GPIO | GPIO_IN | ENABLE_PU, /* EINT7 DM9000 interrupt */ - GPN8_GPIO | GPIO_IN, /* EINT8 USB detect (external PU) */ - GPN9_GPIO | GPIO_IN, /* EINT9 (external PU) */ - GPN10_GPIO | GPIO_IN, /* SD1 CD (external PU) */ - GPN11_GPIO | GPIO_IN, /* EINT11 (external PU) */ - GPN12_GPIO | GPIO_IN, /* EINT12 IR in (external PU) */ - GPN13_GPIO | GPIO_IN, /* BOOT0/EINT13 (externally fixed) */ - GPN14_GPIO | GPIO_IN, /* BOOT1/EINT14 (externally fixed) */ - GPN15_GPIO | GPIO_IN, /* BOOT2/EINT15 (externally fixed) */ - - GPO0_NCS2, /* NAND */ - GPO1_NCS3, /* NAND */ - GPO2_NCS4, /* CON5 */ - GPO3_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO4_GPIO | GPIO_IN | ENABLE_PU, /* CON5 pin 8 */ - GPO5_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO6_ADDR6, /* CON5 */ - GPO7_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO8_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO9_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO10_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO11_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO12_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO13_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO14_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPO15_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - - GPP0_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPP1_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPP2_NWAIT | ENABLE_PU, /* CON5 */ - GPP3_FALE, /* NAND */ - GPP4_FCLE, /* NAND */ - GPP5_FWE, /* NAND */ - GPP6_FRE, /* NAND */ - GPP7_RNB, /* NAND (external PU) */ - GPP8_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPP9_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPP10_GPIO | GPIO_IN, /* (external PU) */ - GPP11_GPIO | GPIO_IN, /* (external PU) */ - GPP12_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPP13_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - GPP14_GPIO | GPIO_IN | ENABLE_PU, /* not used */ - - GPQ0_GPIO | GPIO_IN | ENABLE_PU, /* not used as LADDR18 */ - GPQ1_GPIO | GPIO_IN, /* (external PU) */ - GPQ2_GPIO | GPIO_IN, /* (external PU) */ - GPQ3_GPIO | GPIO_IN, /* (external PU) */ - GPQ4_GPIO | GPIO_IN, /* (external PU) */ - GPQ5_GPIO | GPIO_IN, /* (external PU) */ - GPQ6_GPIO | GPIO_IN, /* (external PU) */ - GPQ7_GPIO | GPIO_IN | ENABLE_PU, /* not used as LADDR17 */ - GPQ8_GPIO | GPIO_IN | ENABLE_PU, /* not used as LADDR16 */ -}; - -static int mini6410_mem_init(void) -{ - arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size()); - - return 0; -} -mem_initcall(mini6410_mem_init); - -static const struct s3c6410_chipselect dm900_cs = { - .adr_setup_t = 0, - .access_setup_t = 0, - .access_t = 20, - .cs_hold_t = 3, - .adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */ - .width = 16, -}; - -static void mini6410_setup_dm9000_cs(void) -{ - s3c6410_setup_chipselect(1, &dm900_cs); -} - -static int mini6410_devices_init(void) -{ - int i; - - /* ----------- configure the access to the outer space ---------- */ - for (i = 0; i < ARRAY_SIZE(pin_usage); i++) - s3c_gpio_mode(pin_usage[i]); - - mini6410_setup_dm9000_cs(); - add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304, - IORESOURCE_MEM_16BIT, &dm9000_data); - - armlinux_set_architecture(MACH_TYPE_MINI6410); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_friendlyarm_mini6410); - - return 0; -} - -device_initcall(mini6410_devices_init); - -static int mini6410_console_init(void) -{ - s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU); - s3c_gpio_mode(GPA1_TXD0); - s3c_gpio_mode(GPA2_NCTS0 | ENABLE_PU); - s3c_gpio_mode(GPA3_NRTS0); - - barebox_set_model("Friendlyarm mini6410"); - barebox_set_hostname("mini6410"); - - s3c64xx_add_uart1(); - - return 0; -} - -console_initcall(mini6410_console_init); diff --git a/arch/arm/boards/friendlyarm-tiny210/Makefile b/arch/arm/boards/friendlyarm-tiny210/Makefile deleted file mode 100644 index 7deb178739..0000000000 --- a/arch/arm/boards/friendlyarm-tiny210/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += tiny210.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/friendlyarm-tiny210/config.h b/arch/arm/boards/friendlyarm-tiny210/config.h deleted file mode 100644 index 86aedf0a64..0000000000 --- a/arch/arm/boards/friendlyarm-tiny210/config.h +++ /dev/null @@ -1,19 +0,0 @@ -#define S5PCXX_CLOCK_REFERENCE 24000000 - -#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) - -#define BOARD_APLL_VAL set_pll(0x7d, 0x3, 0x1) -#define BOARD_MPLL_VAL set_pll(0x29b, 0xc, 0x1) -#define BOARD_EPLL_VAL set_pll(0x60, 0x6, 0x2) -#define BOARD_VPLL_VAL set_pll(0x6c, 0x6, 0x3) - -#define BOARD_CLK_DIV0_MASK 0xFFFFFFFF -#define BOARD_CLK_DIV0_VAL 0x14131440 -#define BOARD_APLL_LOCKTIME 0x2cf - -#define S5P_DRAM_WR 3 -#define S5P_DRAM_CAS 4 -#define DMC_TIMING_AREF 0x00000618 -#define DMC_TIMING_ROW 0x2B34438A -#define DMC_TIMING_DATA 0x24240000 -#define DMC_TIMING_PWR 0x0BDC0343 diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c deleted file mode 100644 index 17a7cf1591..0000000000 --- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2012 Alexey Galakhov - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <config.h> -#include <common.h> -#include <init.h> -#include <io.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/sections.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c-clocks.h> -#include <mach/s3c-generic.h> - -#define IRAM_CODE_BASE 0xD0020010 - -/* Tiny210 has 4 leds numbered from 0 to 3 at GPJ2 */ -static inline void __bare_init debug_led(int led, bool state) -{ - uint32_t r; - /* GPJ2CON: mode 0001=output */ - r = readl(0xE0200280); - r &= ~(0xF << (4 * led)); - r |= (0x1 << (4 * led)); - writel(r, 0xE0200280); - /* GPJ2DAT: active low */ - r = readl(0xE0200284); - r &= ~(1 << led); - r |= (state ? 0 : 1) << led; - writel(r, 0xE0200284); -} - -/* - * iROM boot from MMC - * TODO: replace this by native boot - */ - -#define ADDR_V210_SDMMC_BASE 0xD0037488 -#define ADDR_CopySDMMCtoMem 0xD0037F98 - -static int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block, - uint16_t block_count) -{ - typedef uint32_t (*func_t) (int32_t, uint32_t, uint16_t, uint32_t*, int8_t); - uint32_t chbase = readl(ADDR_V210_SDMMC_BASE); - func_t func = (func_t)readl(ADDR_CopySDMMCtoMem); - int chan = (chbase - 0xEB000000) >> 20; - if (chan != 0 && chan != 2) - return 0; - return func(chan, start_block, block_count, (uint32_t*)dest, 0) ? 1 : 0; -} - -static __bare_init __naked void jump_sdram(unsigned long offset) -{ - __asm__ __volatile__ ( - "sub lr, lr, %0;" - "mov pc, lr;" : : "r"(offset) - ); -} - -static __bare_init bool load_stage2(void *dest, size_t size) -{ - /* TODO add other ways to boot */ - return s5p_irom_load_mmc(dest, 1, (size+ 511) / 512); -} - -void __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - -#ifdef CONFIG_S3C_PLL_INIT - s5p_init_pll(); -#endif - - debug_led(0, 1); - - if (get_pc() < IRAM_CODE_BASE) /* Are we running from iRAM? */ - /* No, we don't. */ - goto boot; - - s5p_init_dram_bank_ddr2(S5P_DMC0_BASE, 0x20E00323, 0, 0); - - debug_led(1, 1); - - if (! load_stage2((void*)(_text - 16), - barebox_image_size + 16)) { - debug_led(3, 1); - while (1) { } /* hang */ - } - - debug_led(2, 1); - - jump_sdram(IRAM_CODE_BASE - (unsigned long)_text); - - debug_led(1, 0); - -boot: - barebox_arm_entry(S3C_SDRAM_BASE, SZ_256M, NULL); -} diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c deleted file mode 100644 index b40dc98c5b..0000000000 --- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2012 Alexey Galakhov - * Based on Mini6410 code by Juergen Beisert - * - * Copyright (C) 2012 Juergen Beisert, Pengutronix - * - * In some ways inspired by code - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <linux/sizes.h> -#include <generated/mach-types.h> -#include <gpio.h> -#include <led.h> -#include <io.h> -#include <nand.h> -#include <asm/armlinux.h> -#include <mach/iomux.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c-clocks.h> -#include <mach/s3c-generic.h> - - -static const unsigned pin_usage[] = { - /* TODO */ -}; - -static struct gpio_led leds[] = { - { - .gpio = GPJ20, - .led = { - .name = "led1", - } - }, { - .gpio = GPJ21, - .led = { - .name = "led2", - } - }, { - .gpio = GPJ22, - .led = { - .name = "led3", - } - }, { - .gpio = GPJ23, - .led = { - .name = "led4", - } - } -}; - -static int tiny210_mem_init(void) -{ - arm_add_mem_device("ram0", S3C_SDRAM_BASE, s5p_get_memory_size()); - return 0; -} -mem_initcall(tiny210_mem_init); - -static int tiny210_console_init(void) -{ - /* - * configure the UART1 right now, as barebox will - * start to send data immediately - */ - s3c_gpio_mode(GPA00_RXD0 | ENABLE_PU); - s3c_gpio_mode(GPA01_TXD0); - s3c_gpio_mode(GPA02_NCTS0 | ENABLE_PU); - s3c_gpio_mode(GPA03_NRTS0); - - barebox_set_model("Friendlyarm tiny210"); - barebox_set_hostname("tiny210"); - - add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, - S3C_UART1_BASE, S3C_UART1_SIZE, - IORESOURCE_MEM, NULL); - return 0; -} -console_initcall(tiny210_console_init); - -static int tiny210_devices_init(void) -{ - int i; - for (i = 0; i < ARRAY_SIZE(pin_usage); i++) - s3c_gpio_mode(pin_usage[i]); - - for (i = 0; i < ARRAY_SIZE(leds); i++) { - leds[i].active_low = 1; - gpio_direction_output(leds[i].gpio, leds[i].active_low); - led_gpio_register(&leds[i]); - } - - led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); - - armlinux_set_architecture(MACH_TYPE_MINI210); - - return 0; -} -device_initcall(tiny210_devices_init); diff --git a/arch/arm/boards/friendlyarm-tiny6410/Kconfig b/arch/arm/boards/friendlyarm-tiny6410/Kconfig deleted file mode 100644 index 374820f8b3..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -if MACH_TINY6410 - -choice - prompt "FriendlyARM Tiny6410 baseboard" - help - Since the Tiny6410 is a CPU card only, it requires a basebord to make - it work. Select here the baseboard Barebox should expect and - configure. - -config MACH_TINY6410_FA - bool - select HAS_DM9000 - prompt "FA development platform" - help - FriendlyARM's Tiny6410 evaluation board. - -endchoice - -endif diff --git a/arch/arm/boards/friendlyarm-tiny6410/Makefile b/arch/arm/boards/friendlyarm-tiny6410/Makefile deleted file mode 100644 index ba3f3360f8..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += tiny6410.o -lwl-y += lowlevel.o -lwl-$(CONFIG_MACH_TINY6410_FA) += development-board.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-friendlyarm-tiny6410 diff --git a/arch/arm/boards/friendlyarm-tiny6410/config.h b/arch/arm/boards/friendlyarm-tiny6410/config.h deleted file mode 100644 index 04f68579ed..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/config.h +++ /dev/null @@ -1,8 +0,0 @@ -/* FriendlyARM Tiny6410 specific global settings */ - -#ifndef _TINY6410_CONFIG_H_ -# define _TINY6410_CONFIG_H_ - -#define S3C64XX_CLOCK_REFERENCE 12000000 - -#endif /* _TINY6410_CONFIG_H_ */ diff --git a/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config b/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config deleted file mode 100644 index f38535be48..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/defaultenv-friendlyarm-tiny6410/config +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/sh - -machine=tiny6410 -eth0.serverip=a.b.c.d.e -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d.e -#eth0.netmask=a.b.c.d.e -#eth0.gateway=a.b.c.d.e -#eth0.ethaddr= - -# can be either 'nfs', 'tftp' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${machine}.${rootfs_type} - -# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo -kernelimage=zImage-${machine} -#kernelimage=uImage-$machine -#kernelimage=Image-$machine -#kernelimage=Image-$machine.lzo - -if [ -n $user ]; then - kernelimage="${user}"-"${kernelimage}" - nfsroot="${eth0.serverip}:/home/${user}/nfsroot/${machine}" - rootfsimage="${user}"-"${rootfsimage}" -else - nfsroot="${eth0.serverip}:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -# -# "tiny6410" kernel parameter -# 0 .. 9 = screen type -# i = touchscreen with propritary FriendlyARM protocol -# Note: can be "tiny6410= " if nothing of these components are connected -# -bootargs="console=ttySAC0,115200 tiny6410=0" - -nand_device="nand" -nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)" -rootfs_mtdblock_nand=3 diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c b/arch/arm/boards/friendlyarm-tiny6410/development-board.c deleted file mode 100644 index 5dd05e4cc8..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/development-board.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (C) 2012 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * The FriendlyARM's Tiny6410 evaluation board comes with all connectors and - * devices to make the Tiny6410 CPU card work. This includes: - * - * - the DM9000 network controller - * - USB/MCI connectors - * - display connector - * - */ -#include <common.h> -#include <driver.h> -#include <init.h> -#include <gpio.h> -#include <platform_data/eth-dm9000.h> -#include <mach/devices-s3c64xx.h> -#include <mach/s3c-generic.h> -#include <mach/iomux.h> - -#include "tiny6410.h" - -/* - * dm9000 network controller onboard - * Connected to CS line 1 and interrupt line EINT7, - * data width is 16 bit - * Area 1: Offset 0x300...0x301 - * Area 2: Offset 0x304...0x305 - */ -static struct dm9000_platform_data dm9000_data = { - .srom = 0, /* no serial ROM for the ethernet address */ -}; - -static const struct s3c6410_chipselect dm900_cs = { - .adr_setup_t = 0, - .access_setup_t = 0, - .access_t = 20, - .cs_hold_t = 3, - .adr_hold_t = 20, /* CS must be de-asserted for at least 20 ns */ - .width = 16, -}; - -static void tiny6410evk_setup_dm9000_cs(void) -{ - s3c6410_setup_chipselect(1, &dm900_cs); -} - -static const unsigned tiny6410evk_pin_usage[] = { - /* UART1 (V24) */ - GPA4_RXD1 | ENABLE_PU, - GPA5_TXD1, - GPA6_NCTS1 | ENABLE_PU, - GPA7_NRTS1, - /* UART2 (V24) */ - GPB0_RXD2 | ENABLE_PU, - GPB1_TXD2, - /* UART3 (spare, 3,3 V TTL level only) */ - GPB2_RXD3 | ENABLE_PU, - GPB3_TXD3, -}; - -static int tiny6410evk_devices_init(void) -{ - int i; - - /* init CPU card specific devices first */ - tiny6410_init("FA EVK"); - - /* ----------- configure the access to the outer space ---------- */ - for (i = 0; i < ARRAY_SIZE(tiny6410evk_pin_usage); i++) - s3c_gpio_mode(tiny6410evk_pin_usage[i]); - - tiny6410evk_setup_dm9000_cs(); - add_dm9000_device(0, S3C_CS1_BASE + 0x300, S3C_CS1_BASE + 0x304, - IORESOURCE_MEM_16BIT, &dm9000_data); - return 0; -} -device_initcall(tiny6410evk_devices_init); - -static int tiny6410evk_console_init(void) -{ - /* note: UART0 has no RTS/CTS connected */ - s3c_gpio_mode(GPA0_RXD0 | ENABLE_PU); - s3c_gpio_mode(GPA1_TXD0); - - barebox_set_model("Friendlyarm tiny6410"); - barebox_set_hostname("tiny6410"); - - s3c64xx_add_uart1(); - - return 0; -} -console_initcall(tiny6410evk_console_init); diff --git a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c deleted file mode 100644 index ccbdd13795..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c +++ /dev/null @@ -1,11 +0,0 @@ -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/s3c-iomap.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL); -} diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c deleted file mode 100644 index 39179c83d8..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2012 Juergen Beisert - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <common.h> -#include <driver.h> -#include <init.h> -#include <gpio.h> -#include <generated/mach-types.h> -#include <asm/armlinux.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c-generic.h> -#include <mach/iomux.h> - -#include "tiny6410.h" - -static const unsigned tiny6410_pin_usage[] = { - /* UART0 */ - GPA2_GPIO | GPIO_IN | ENABLE_PU, /* CTS not connected */ - GPA3_GPIO | GPIO_IN | ENABLE_PU, /* RTS not connected */ - - /* local bus' D0 ... D15 are always active */ - /* local bus' A0...A5 are always active */ - - /* internal NAND memory */ - GPO0_NCS2, /* NAND's first chip select line */ - /* NAND's second chip select line, not used */ - GPO1_GPIO | GPIO_OUT | GPIO_VAL(1), - GPP3_FALE, - GPP4_FCLE, - GPP5_FWE, - GPP6_FRE, - GPP7_RNB, /* external pull-up */ - - GPF13_GPIO | GPIO_OUT | GPIO_VAL(0), /* OTG power supply, 0 = off */ - - /* nowhere connected */ - GPO2_GPIO | GPIO_IN | ENABLE_PU, - GPO3_GPIO | GPIO_IN | ENABLE_PU, - GPO4_GPIO | GPIO_IN | ENABLE_PU, - GPO5_GPIO | GPIO_IN | ENABLE_PU, - - /* local bus address lines 6...15 are nowhere connected */ - GPO6_GPIO | GPIO_IN | ENABLE_PU, - GPO7_GPIO | GPIO_IN | ENABLE_PU, - GPO8_GPIO | GPIO_IN | ENABLE_PU, - GPO9_GPIO | GPIO_IN | ENABLE_PU, - GPO10_GPIO | GPIO_IN | ENABLE_PU, - GPO11_GPIO | GPIO_IN | ENABLE_PU, - GPO12_GPIO | GPIO_IN | ENABLE_PU, - GPO13_GPIO | GPIO_IN | ENABLE_PU, - GPO14_GPIO | GPIO_IN | ENABLE_PU, - GPO15_GPIO | GPIO_IN | ENABLE_PU, -}; - -static int tiny6410_mem_init(void) -{ - arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c6410_get_memory_size()); - - return 0; -} -mem_initcall(tiny6410_mem_init); - -void tiny6410_init(const char *bb_name) -{ - int i; - - /* ----------- configure the access to the outer space ---------- */ - for (i = 0; i < ARRAY_SIZE(tiny6410_pin_usage); i++) - s3c_gpio_mode(tiny6410_pin_usage[i]); - - armlinux_set_architecture(MACH_TYPE_TINY6410); -} diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h deleted file mode 100644 index 98db422422..0000000000 --- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* to be called by the base board */ -void tiny6410_init(const char*); diff --git a/arch/arm/boards/gateworks-ventana/Makefile b/arch/arm/boards/gateworks-ventana/Makefile index 7d195eebd6..4e1cefbc4c 100644 --- a/arch/arm/boards/gateworks-ventana/Makefile +++ b/arch/arm/boards/gateworks-ventana/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o gsc.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/gateworks-ventana/board.c b/arch/arm/boards/gateworks-ventana/board.c index 6f9e0343be..aa2137a971 100644 --- a/arch/arm/boards/gateworks-ventana/board.c +++ b/arch/arm/boards/gateworks-ventana/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix #include <common.h> #include <environment.h> @@ -19,8 +8,8 @@ #include <linux/marvell_phy.h> #include <linux/pci.h> #include <linux/phy.h> -#include <mach/bbu.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> #include <net.h> #include "gsc.h" @@ -30,9 +19,14 @@ static int gw54xx_wdog_of_fixup(struct device_node *root, void *context) struct device_node *np; /* switch to the watchdog with internal reset capabilities */ - np = of_find_node_by_name(root, "wdog@020c0000"); + np = of_find_node_by_name_address(root, "wdog@020c0000"); + of_device_disable(np); + np = of_find_node_by_name_address(root, "watchdog@20c0000"); of_device_disable(np); - np = of_find_node_by_name(root, "wdog@020bc000"); + + np = of_find_node_by_name_address(root, "wdog@020bc000"); + of_device_enable(np); + np = of_find_node_by_name_address(root, "watchdog@20bc000"); of_device_enable(np); return 0; diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg index b9a6fc12ff..cde49ef029 100644 --- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg +++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> #include "ram-base.imxcfg" #include "quad_128x64.imxcfg" diff --git a/arch/arm/boards/gateworks-ventana/gsc.c b/arch/arm/boards/gateworks-ventana/gsc.c index 92244d12da..ae639bca86 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.c +++ b/arch/arm/boards/gateworks-ventana/gsc.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Gateworks Corporation +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix + /* - * Copyright (C) 2013 Gateworks Corporation - * Copyright (C) 2014 Lucas Stach, Pengutronix * Author: Tim Harvey <tharvey@gateworks.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* diff --git a/arch/arm/boards/gateworks-ventana/gsc.h b/arch/arm/boards/gateworks-ventana/gsc.h index 13f226265c..c2fb535d15 100644 --- a/arch/arm/boards/gateworks-ventana/gsc.h +++ b/arch/arm/boards/gateworks-ventana/gsc.h @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Gateworks Corporation +// SPDX-FileCopyrightText: 2014 Lucas Stach, Pengutronix + /* - * Copyright (C) 2013 Gateworks Corporation - * Copyright (C) 2014 Lucas Stach, Pengutronix * Author: Tim Harvey <tharvey@gateworks.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ /* i2c slave addresses */ diff --git a/arch/arm/boards/gateworks-ventana/lowlevel.c b/arch/arm/boards/gateworks-ventana/lowlevel.c index 0a79d82049..db18b53139 100644 --- a/arch/arm/boards/gateworks-ventana/lowlevel.c +++ b/arch/arm/boards/gateworks-ventana/lowlevel.c @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg b/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg index daf01a8ad1..66a7876649 100644 --- a/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg +++ b/arch/arm/boards/gateworks-ventana/quad_128x64.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00190017 wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00140026 wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x0021001C diff --git a/arch/arm/boards/gateworks-ventana/ram-base.imxcfg b/arch/arm/boards/gateworks-ventana/ram-base.imxcfg index 07dc34c0bb..c482f60b09 100644 --- a/arch/arm/boards/gateworks-ventana/ram-base.imxcfg +++ b/arch/arm/boards/gateworks-ventana/ram-base.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 diff --git a/arch/arm/boards/gk802/Makefile b/arch/arm/boards/gk802/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/gk802/Makefile +++ b/arch/arm/boards/gk802/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/gk802/board.c b/arch/arm/boards/gk802/board.c index 0d1b07b0e0..c4a90306e8 100644 --- a/arch/arm/boards/gk802/board.c +++ b/arch/arm/boards/gk802/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Philipp Zabel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Philipp Zabel #include <asm/armlinux.h> #include <asm/io.h> @@ -20,9 +9,9 @@ #include <envfs.h> #include <gpio.h> #include <init.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> -#include <mach/imx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <linux/sizes.h> #include <of.h> diff --git a/arch/arm/boards/gk802/flash-header.imxcfg b/arch/arm/boards/gk802/flash-header.imxcfg index f26fe77b03..e77f4601cb 100644 --- a/arch/arm/boards/gk802/flash-header.imxcfg +++ b/arch/arm/boards/gk802/flash-header.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 diff --git a/arch/arm/boards/gk802/lowlevel.c b/arch/arm/boards/gk802/lowlevel.c index a41b711e36..7c56a6a1a6 100644 --- a/arch/arm/boards/gk802/lowlevel.c +++ b/arch/arm/boards/gk802/lowlevel.c @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/globalscale-guruplug/Makefile b/arch/arm/boards/globalscale-guruplug/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/globalscale-guruplug/Makefile +++ b/arch/arm/boards/globalscale-guruplug/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/globalscale-guruplug/board.c b/arch/arm/boards/globalscale-guruplug/board.c deleted file mode 100644 index 9c800c5410..0000000000 --- a/arch/arm/boards/globalscale-guruplug/board.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright - * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* empty */ diff --git a/arch/arm/boards/globalscale-guruplug/lowlevel.c b/arch/arm/boards/globalscale-guruplug/lowlevel.c index 92424cbd6b..a54d848c04 100644 --- a/arch/arm/boards/globalscale-guruplug/lowlevel.c +++ b/arch/arm/boards/globalscale-guruplug/lowlevel.c @@ -1,28 +1,15 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_kirkwood_guruplug_server_plus_bb_start[]; -ENTRY_FUNCTION(start_globalscale_guruplug, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_globalscale_guruplug, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/globalscale-mirabox/Makefile b/arch/arm/boards/globalscale-mirabox/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/globalscale-mirabox/Makefile +++ b/arch/arm/boards/globalscale-mirabox/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/globalscale-mirabox/board.c b/arch/arm/boards/globalscale-mirabox/board.c deleted file mode 100644 index 9c800c5410..0000000000 --- a/arch/arm/boards/globalscale-mirabox/board.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright - * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* empty */ diff --git a/arch/arm/boards/globalscale-mirabox/lowlevel.c b/arch/arm/boards/globalscale-mirabox/lowlevel.c index 69786c88fb..da08e80d74 100644 --- a/arch/arm/boards/globalscale-mirabox/lowlevel.c +++ b/arch/arm/boards/globalscale-mirabox/lowlevel.c @@ -1,28 +1,15 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_armada_370_mirabox_bb_start[]; -ENTRY_FUNCTION(start_globalscale_mirabox, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_globalscale_mirabox, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/grinn-liteboard/Makefile b/arch/arm/boards/grinn-liteboard/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/grinn-liteboard/Makefile +++ b/arch/arm/boards/grinn-liteboard/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/grinn-liteboard/board.c b/arch/arm/boards/grinn-liteboard/board.c index 8e5a91e124..6d390a5287 100644 --- a/arch/arm/boards/grinn-liteboard/board.c +++ b/arch/arm/boards/grinn-liteboard/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2018 Grinn - * - * Author: Marcin Niestroj <m.niestroj@grinn-global.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2018 Grinn + +/* Author: Marcin Niestroj <m.niestroj@grinn-global.com> */ #define pr_fmt(fmt) "liteboard: " fmt @@ -19,8 +9,8 @@ #include <common.h> #include <envfs.h> #include <init.h> -#include <mach/bbu.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> #include <malloc.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <of.h> @@ -35,7 +25,7 @@ static void bbu_register_handler_emmc(bool is_boot_source) { int emmc_boot_flag = 0, emmc_flag = 0; const char *bootpart; - struct device_d *dev; + struct device *dev; int ret; if (!is_boot_source) diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg index 1b980c7846..c2d4b2875b 100644 --- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg +++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-256mb.imxcfg @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only #define SETUP_MDASP_MDCTL \ wm 32 0x021B0040 0x00000047; \ diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg index c93a2cc0fa..45bc841ab5 100644 --- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg +++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard-512mb.imxcfg @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only #define SETUP_MDASP_MDCTL \ wm 32 0x021B0040 0x0000004F; \ diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h index 60a39f524b..776a69f8b6 100644 --- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h +++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h @@ -1,7 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/grinn-liteboard/lowlevel.c b/arch/arm/boards/grinn-liteboard/lowlevel.c index bb2e09016e..6851a678bc 100644 --- a/arch/arm/boards/grinn-liteboard/lowlevel.c +++ b/arch/arm/boards/grinn-liteboard/lowlevel.c @@ -1,19 +1,10 @@ -/* - * Copyright (C) 2018 Grinn - * - * Author: Marcin Niestroj <m.niestroj@grinn-global.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2018 Grinn + +/* Author: Marcin Niestroj <m.niestroj@grinn-global.com> */ #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -23,8 +14,8 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/esdctl.h> -#include <mach/imx6.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/imx6.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/guf-cupid/Makefile b/arch/arm/boards/guf-cupid/Makefile deleted file mode 100644 index eaf2a4f407..0000000000 --- a/arch/arm/boards/guf-cupid/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel.o -obj-y += board.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-guf-cupid diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c deleted file mode 100644 index a02cecf6c5..0000000000 --- a/arch/arm/boards/guf-cupid/board.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for the Garz+Fricke Cupid board - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <envfs.h> -#include <mach/imx35-regs.h> -#include <asm/armlinux.h> -#include <io.h> -#include <gpio.h> -#include <partition.h> -#include <nand.h> -#include <generated/mach-types.h> -#include <mach/imx-nand.h> -#include <platform_data/eth-fec.h> -#include <fb.h> -#include <asm/mmu.h> -#include <mach/weim.h> -#include <mach/imx-ipu-fb.h> -#include <mach/imx-pll.h> -#include <mach/iomux-mx35.h> -#include <mach/devices-imx35.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct fb_videomode guf_cupid_fb_mode = { - /* 800x480 @ 70 Hz */ - .name = "CPT CLAA070LC0JCT", - .refresh = 70, - .xres = 800, - .yres = 480, - .pixclock = 30761, - .left_margin = 24, - .right_margin = 47, - .upper_margin = 5, - .lower_margin = 3, - .hsync_len = 24, - .vsync_len = 3, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_CLK_INVERT | - FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, -}; - -#define GPIO_LCD_ENABLE (2 * 32 + 24) -#define GPIO_LCD_BACKLIGHT (0 * 32 + 19) - -static void cupid_fb_enable(int enable) -{ - if (enable) { - gpio_direction_output(GPIO_LCD_ENABLE, 1); - mdelay(100); - gpio_direction_output(GPIO_LCD_BACKLIGHT, 1); - } else { - gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); - mdelay(100); - gpio_direction_output(GPIO_LCD_ENABLE, 0); - } -} - -static struct imx_ipu_fb_platform_data ipu_fb_data = { - .mode = &guf_cupid_fb_mode, - .num_modes = 1, - .bpp = 16, - .enable = cupid_fb_enable, -}; - -static int cupid_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(cupid_mmu_init); - -static int cupid_devices_init(void) -{ - uint32_t reg; - - gpio_direction_output(GPIO_LCD_ENABLE, 0); - gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); - - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); - /* some fuses provide us vital information about connected hardware */ - if (reg & 0x20000000) - nand_info.width = 2; /* 16 bit */ - else - nand_info.width = 1; /* 8 bit */ - - imx35_add_fec(&fec_info); - imx35_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - imx35_add_fb(&ipu_fb_data); - imx35_add_mmc0(NULL); - - armlinux_set_architecture(MACH_TYPE_GUF_CUPID); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_guf_cupid); - - return 0; -} - -device_initcall(cupid_devices_init); - -static iomux_v3_cfg_t cupid_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_LD18__GPIO3_24, /* LCD enable */ - MX35_PAD_CSPI1_SS1__GPIO1_19, /* LCD backligtht PWM */ - /* USB Host*/ - MX35_PAD_MLB_CLK__GPIO3_3, /* USB Host PWR */ - MX35_PAD_MLB_DAT__GPIO3_4, /* USB Host Overcurrent */ - /* USB OTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* SSI */ - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, - MX35_PAD_STXD4__AUDMUX_AUD4_TXD, - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, - MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* UCB1400 IRQ */ - MX35_PAD_ATA_INTRQ__GPIO2_29, - /* Speaker On */ - MX35_PAD_LD20__GPIO3_26, - /* LEDs */ - MX35_PAD_TX1__GPIO1_14, - /* ESDHC1 */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* ESDHC1 CD */ - MX35_PAD_ATA_DATA5__GPIO2_18, - /* ESDHC1 WP */ - MX35_PAD_ATA_DATA6__GPIO2_19, -}; - -static int cupid_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads)); - - barebox_set_model("Garz & Fricke CUPID"); - barebox_set_hostname("cupid"); - - imx35_add_uart0(); - - return 0; -} - -console_initcall(cupid_console_init); - -static int cupid_core_setup(void) -{ - u32 tmp; - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - /* CS0: NOR Flash */ - imx35_setup_weimcs(0, 0x0000DCF6, 0x444A4541, 0x44443302); - - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - writel(0x40, MX35_M3IF_BASE_ADDR); - - return 0; -} - -core_initcall(cupid_core_setup); - -static int do_cpufreq(int argc, char *argv[]) -{ - unsigned long freq; - - if (argc != 2) - return COMMAND_ERROR_USAGE; - - freq = simple_strtoul(argv[1], NULL, 0); - - switch (freq) { - case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - default: - return COMMAND_ERROR_USAGE; - } - - printf("Switched CPU frequency to %luMHz\n", freq); - - return 0; -} - -BAREBOX_CMD_START(cpufreq) - .cmd = do_cpufreq, - BAREBOX_CMD_DESC("adjust CPU frequency") - BAREBOX_CMD_OPTS("399|532") - BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) -BAREBOX_CMD_END diff --git a/arch/arm/boards/guf-cupid/defaultenv-guf-cupid/config b/arch/arm/boards/guf-cupid/defaultenv-guf-cupid/config deleted file mode 100644 index dc289b39f2..0000000000 --- a/arch/arm/boards/guf-cupid/defaultenv-guf-cupid/config +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW" - -nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)" -nand_device=mxc_nand -rootfs_mtdblock_nand=3 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c deleted file mode 100644 index 0d7cfb618c..0000000000 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <mach/imx35-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/cache-l2x0.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/sections.h> -#include <asm-generic/memory_layout.h> -#include <asm/system.h> - -#define SDRAM_MODE_BL_8 0x0003 -#define SDRAM_MODE_BSEQ 0x0000 -#define SDRAM_MODE_CL_3 0x0030 -#define MDDR_DS_HALF 0x20 -#define SDRAM_COMPARE_CONST1 0x55555555 -#define SDRAM_COMPARE_CONST2 0xaaaaaaaa - -static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr) -{ - volatile int loop; - void *r9 = (void *)MX35_CSD0_BASE_ADDR; - u32 r11 = 0xda; /* dummy constant */ - u32 r1, r0; - - /* disable second SDRAM region to save power */ - r1 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - r1 &= ~ESDCTL0_SDE; - writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - - mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST; - writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - - mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST); - writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - - /* wait for esdctl reset */ - for (loop = 0; loop < 0x20000; loop++); - - r1 = ESDCFGx_tXP_4 | ESDCFGx_tWTR_1 | - ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | - ESDCFGx_tWR_1_2 | ESDCFGx_tRAS_6 | - ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | - ESDCFGx_tRCD_3 | ESDCFGx_tRC_20; - - writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - - /* enable SDRAM controller */ - writel(memsize | ESDCTL0_SMODE_NORMAL, - MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - /* Micron Datasheet Initialization Step 3: Wait 200us before first command */ - for (loop = 0; loop < 1000; loop++); - - /* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */ - writel(memsize | ESDCTL0_SMODE_PRECHARGE, - MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(r11, sdram_addr); - - /* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns) - * The CPU is not fast enough to cause a problem here - */ - - /* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP - * (at least 140ns) - */ - writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, - MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(r11, r9); /* AUTO REFRESH #1 */ - - for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ - - writeb(r11, r9); /* AUTO REFRESH #2 */ - - for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ - - /* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */ - writel(memsize | ESDCTL0_SMODE_LOAD_MODE, - MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3)); - - /* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP - * (The memory controller will take care of this delay) - */ - - /* Micron Datasheet Initialization Step 9: LOAD MODE REGISTER EXTENDED */ - writeb(r11, 0x84000000 | MDDR_DS_HALF); /*we assume 14 Rows / 10 Cols here */ - - /* Micron Datasheet Initialization Step 9: tMRD = 2 tCK NOP - * (The memory controller will take care of this delay) - */ - - /* Now configure SDRAM-Controller and check that it works */ - writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, - MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - /* Freescale asks for first access to be a write to properly - * initialize DQS pin-state and keepers - */ - writel(0xdeadbeef, r9); - - /* test that the RAM is in fact working */ - writel(SDRAM_COMPARE_CONST1, r9); - writel(SDRAM_COMPARE_CONST2, r9 + 0x4); - - if (readl(r9) != SDRAM_COMPARE_CONST1) - while (1); - - /* Verify that the correct row and coloumn is selected */ - - /* So far we asssumed that we have 14 rows, verify this */ - writel(SDRAM_COMPARE_CONST1, r9); - writel(SDRAM_COMPARE_CONST2, r9 + (1 << 25)); - - /* if both value are identical, we don't have 14 rows. assume 13 instead */ - if (readl(r9) == readl(r9 + (1 << 25))) { - r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - r0 &= ~ESDCTL0_ROW_MASK; - r0 |= ESDCTL0_ROW13; - writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - } - - /* So far we asssumed that we have 10 columns, verify this */ - writel(SDRAM_COMPARE_CONST1, r9); - writel(SDRAM_COMPARE_CONST2, r9 + (1 << 11)); - - /* if both value are identical, we don't have 10 cols. assume 9 instead */ - if (readl(r9) == readl(r9 + (1 << 11))) { - r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - r0 &= ~ESDCTL0_COL_MASK; - r0 |= ESDCTL0_COL9; - writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - } -} - -#define BRANCH_PREDICTION_ENABLE -#define UNALIGNED_ACCESS_ENABLE -#define LOW_INT_LATENCY_ENABLE - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR; - int i; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(0x10000000 + 128 * 1024); - - /* - * ARM1136 init - * - invalidate I/D cache/TLB and drain write buffer; - * - invalidate L2 cache - * - unaligned access - * - branch predictions - */ -#ifdef TURN_OFF_IMPRECISE_ABORT - __asm__ __volatile__("mrs %0, cpsr":"=r"(r0)); - r0 &= ~0x100; - __asm__ __volatile__("msr cpsr, %0" : : "r"(r0)); -#endif - /* ensure L1 caches and MMU are turned-off for now */ - r1 = get_cr(); - r1 &= ~(CR_I | CR_M | CR_C); - - /* setup core features */ - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1":"=r"(r0)); -#ifdef BRANCH_PREDICTION_ENABLE - r0 |= 7; - r1 |= CR_Z; -#else - r0 &= ~7; - r1 &= ~CR_Z; -#endif - __asm__ __volatile__("mcr p15, 0, r0, c1, c0, 1" : : "r"(r0)); - -#ifdef UNALIGNED_ACCESS_ENABLE - r1 |= CR_U; -#else - r1 &= ~CR_U; -#endif - -#ifdef LOW_INT_LATENCY_ENABLE - r1 |= CR_FI; -#else - r1 &= ~CR_FI; -#endif - set_cr(r1); - - r0 = 0; - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r0)); - - /* invalidate I cache and D cache */ - __asm__ __volatile__("mcr p15, 0, r0, c7, c7, 0" : : "r"(r0)); - /* invalidate TLBs */ - __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0" : : "r"(r0)); - /* Drain the write buffer */ - __asm__ __volatile__("mcr p15, 0, r0, c7, c10, 4" : : "r"(r0)); - - /* Also setup the Peripheral Port Remap register inside the core */ - r0 = 0x40000015; /* start from AIPS 2GB region */ - __asm__ __volatile__("mcr p15, 0, r0, c15, c2, 4" : : "r"(r0)); - -#define WDOG_WMCR 0x8 - /* silence reset WDOG */ - writew(0, MX35_WDOG_BASE_ADDR + WDOG_WMCR); - - /* Skip SDRAM initialization if we run from RAM */ - r0 = get_pc(); - if (r0 > 0x80000000 && r0 < 0x90000000) - goto out; - - /* Configure drive strength */ - - /* Configure DDR-pins to correct mode */ - r0 = 0x00001800; - writel(r0, iomuxc_base + 0x794); - writel(r0, iomuxc_base + 0x798); - writel(r0, iomuxc_base + 0x79c); - writel(r0, iomuxc_base + 0x7a0); - writel(r0, iomuxc_base + 0x7a4); - - /* Set drive strength for DDR-pins */ - for (i = 0x368; i <= 0x4c8; i += 4) { - r0 = readl(iomuxc_base + i); - r0 &= ~0x6; - r0 |= 0x2; - writel(r0, iomuxc_base + i); - if (i == 0x468) - i = 0x4a4; - } - - r0 = readl(iomuxc_base + 0x480); - r0 &= ~0x6; - r0 |= 0x2; - writel(r0, iomuxc_base + 0x480); - - r0 = readl(iomuxc_base + 0x4b8); - r0 &= ~0x6; - r0 |= 0x2; - writel(r0, iomuxc_base + 0x4b8); - - /* Configure static chip-selects */ - r0 = readl(iomuxc_base + 0x000); - r0 &= ~1; /* configure CS2/CSD0 for SDRAM */ - writel(r0, iomuxc_base + 0x000); - - /* start-up code doesn't need any static chip-select. - * Leave their initialization to high-level code that - * can initialize them depending on the baseboard. - */ - - /* Configure clocks */ - - /* setup cpu/bus clocks */ - writel(0x003f4208, MX35_CCM_BASE_ADDR + MX35_CCM_CCMR); - - /* configure MPLL */ - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - - /* configure PPLL */ - writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + MX35_CCM_PPCTL); - - /* configure core dividers */ - r0 = MX35_PDR0_CCM_PER_AHB(1) | MX35_PDR0_HSP_PODF(2); - - writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR0); - - /* configure clock-gates */ - r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - r0 |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; - writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - - r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - r0 |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - r0 |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; - writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - - /* Configure SDRAM */ - /* Try 32-Bit 256 MB DDR memory */ - r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */ - setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* Speed up NAND controller by adjusting the NFC divider */ - r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r0 &= ~(0xf << 28); - r0 |= 0x1 << 28; - writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - imx35_barebox_boot_nand_external(0); - } - -out: - imx35_barebox_entry(NULL); -} diff --git a/arch/arm/boards/guf-neso/Makefile b/arch/arm/boards/guf-neso/Makefile deleted file mode 100644 index af90c36c7e..0000000000 --- a/arch/arm/boards/guf-neso/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -lwl-y += lowlevel.o -obj-y += board.o -obj-y += pll_init.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-guf-neso diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c deleted file mode 100644 index 6846ba5793..0000000000 --- a/arch/arm/boards/guf-neso/board.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (C) 2010 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <platform_data/eth-fec.h> -#include <notifier.h> -#include <partition.h> -#include <gpio.h> -#include <fs.h> -#include <envfs.h> -#include <fcntl.h> -#include <nand.h> -#include <command.h> -#include <spi/spi.h> -#include <usb/ulpi.h> - -#include <io.h> -#include <asm/mmu.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> - -#include <mach/spi.h> -#include <mach/imx27-regs.h> -#include <mach/iomux-mx27.h> -#include <mach/imx-nand.h> -#include <mach/imx-pll.h> -#include <mach/imxfb.h> -#include <mach/devices-imx27.h> - -/* two pins are controlling the CS signals to the USB phys */ -#define USBH2_PHY_CS_GPIO (GPIO_PORTF + 20) -#define OTG_PHY_CS_GPIO (GPIO_PORTF + 19) - -/* two pins are controlling the display and its backlight */ -#define LCD_POWER_GPIO (GPIO_PORTF + 18) -#define BACKLIGHT_POWER_GPIO (GPIO_PORTE + 5) - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 31, -}; - -static struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct fb_videomode imxfb_mode = { - .name = "CPT CLAA070LC0JCT", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(27000), - .hsync_len = 1, /* DE only sync */ - .left_margin = 50, - .right_margin = 50, - .vsync_len = 1, /* DE only sync */ - .upper_margin = 10, - .lower_margin = 10, -}; - -static void neso_fb_enable(int enable) -{ - gpio_direction_output(LCD_POWER_GPIO, enable); - gpio_direction_output(BACKLIGHT_POWER_GPIO, enable); -} - -static struct imx_fb_platform_data neso_fb_data = { - .mode = &imxfb_mode, - .num_modes = 1, - .pwmr = 0x00000000, /* doesn't matter */ - .lscr1 = 0x00120300, /* doesn't matter */ - /* dynamic mode -> using the reset values (as recommended in the datasheet) */ - .dmacr = (0 << 31) | (4 << 16) | 96, - .enable = neso_fb_enable, - .framebuffer_ovl = (void *)0xa7f00000, - /* - * - TFT style panel - * - clk enabled while idle - * - clock inverted - * - data not inverted - * - data enable high active - */ - .pcr = PCR_TFT | - PCR_COLOR | - PCR_PBSIZ_8 | - PCR_BPIX_16 | - PCR_CLKPOL | - PCR_SCLK_SEL | - PCR_LPPOL | - PCR_FLMPOL, - .bpp = 16, /* TODO 32 bit does not work: The 'green' component is lacking in this mode */ -}; - -#if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI) -static void neso_usbh_init(void) -{ - uint32_t temp; - - temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600); - temp &= ~((3 << 21) | 1); - temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11); - writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600); - - temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584); - temp &= ~(3 << 30); - temp |= 2 << 30; - writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584); - - mdelay(10); - - gpio_set_value(USBH2_PHY_CS_GPIO, 0); - mdelay(10); - ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, - MX27_USB_OTG_BASE_ADDR + 0x400, NULL); -} -#else -static void neso_usbh_init(void) { } -#endif - -static int neso_devices_init(void) -{ - int i; - - unsigned int mode[] = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - - /* SSI1 connected in AC97 style */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - - /* LED 1 */ - (GPIO_PORTB | 15 | GPIO_GPIO | GPIO_OUT), - /* LED 2 */ - (GPIO_PORTB | 16 | GPIO_GPIO | GPIO_OUT), - /* CTOUCH reset */ - (GPIO_PORTB | 17 | GPIO_GPIO | GPIO_OUT), - /* CTOUCH IRQ */ - (GPIO_PORTB | 14 | GPIO_GPIO | GPIO_IN), - /* RTC IRQ */ - (GPIO_PORTF | 14 | GPIO_GPIO | GPIO_IN), - /* SD change card detection */ - (GPIO_PORTF | 17 | GPIO_GPIO | GPIO_IN), - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* I2C2, for CTOUCH */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - - /* Connected to: Both USB phys and ethernet phy FIXME 1 = RESET? */ - PE17_PF_RESET_OUT, - - /* USB host */ - (USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT), - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD22_AF_USBH2_DATA0, - PD24_AF_USBH2_DATA1, - PD23_AF_USBH2_DATA2, - PD20_AF_USBH2_DATA3, - PD19_AF_USBH2_DATA4, - PD26_AF_USBH2_DATA5, - PD21_AF_USBH2_DATA6, - PA2_PF_USBH2_DATA7, - - /* USB OTG */ - (OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT), - PE24_PF_USBOTG_CLK, - PE2_PF_USBOTG_DIR, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PC9_PF_USBOTG_DATA0, - PC11_PF_USBOTG_DATA1, - PC10_PF_USBOTG_DATA2, - PC13_PF_USBOTG_DATA3, - PC12_PF_USBOTG_DATA4, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PE25_PF_USBOTG_DATA7, - - /* Display signals */ - (LCD_POWER_GPIO | GPIO_GPIO | GPIO_OUT), /* LCD power: 1 = LCD on */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA31_PF_OE_ACD, /* DE */ - - /* Backlight PWM (Use as gpio) */ - (BACKLIGHT_POWER_GPIO | GPIO_GPIO | GPIO_OUT), - }; - - /* reset the chip select lines to the USB/OTG phys to avoid any hang */ - gpio_direction_output(OTG_PHY_CS_GPIO, 1); - gpio_direction_output(USBH2_PHY_CS_GPIO, 1); - - /* initialize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx27_gpio_mode(mode[i]); - - imx27_add_nand(&nand_info); - imx27_add_fb(&neso_fb_data); - - neso_usbh_init(); - - imx27_add_fec(&fec_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - armlinux_set_architecture(MACH_TYPE_NESO); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_guf_neso); - - return 0; -} - -device_initcall(neso_devices_init); - -static int neso_console_init(void) -{ - barebox_set_model("Garz & Fricke NESO"); - barebox_set_hostname("neso"); - - imx27_add_uart0(); - - return 0; -} - -console_initcall(neso_console_init); - -extern void *neso_pll_init, *neso_pll_init_end; - -static int neso_pll(void) -{ - void *vram = (void *)0xffff4c00; - void (*pllfunc)(void) = vram; - - printf("initialising PLLs\n"); - - memcpy(vram, &neso_pll_init, 0x100); - - console_flush(); - - pllfunc(); - - /* clock gating enable */ - writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); - - writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); - writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); - - /* Clocks have changed. Notify clients */ - clock_notifier_call_chain(); - - return 0; -} - -late_initcall(neso_pll); - diff --git a/arch/arm/boards/guf-neso/defaultenv-guf-neso/config b/arch/arm/boards/guf-neso/defaultenv-guf-neso/config deleted file mode 100644 index bd44a555d9..0000000000 --- a/arch/arm/boards/guf-neso/defaultenv-guf-neso/config +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)" -rootfs_mtdblock_nand=3 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c deleted file mode 100644 index 20f48be7dd..0000000000 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <mach/imx27-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/cache-l2x0.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/system.h> -#include <asm/sections.h> -#include <asm-generic/memory_layout.h> - -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - uint32_t r; - int i; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); - writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); - writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0xa0000000 && r < 0xb0000000) - goto out; - - /* - * DDR on CSD0 - */ - /* Enable DDR SDRAM operation */ - writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - - /* Set the driving strength */ - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); - writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); - writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); - - /* Initial reset */ - writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - - /* precharge CSD0 all banks */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - for (i = 0; i < 8; i++) - writel(0, 0xa0000f00); - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - writeb(0xda, 0xa0000033); - writeb(0xff, 0xa1000000); - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx27_barebox_boot_nand_external(0); - -out: - imx27_barebox_entry(NULL); -} diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S deleted file mode 100644 index 4c6cb67fd4..0000000000 --- a/arch/arm/boards/guf-neso/pll_init.S +++ /dev/null @@ -1,51 +0,0 @@ -#include <config.h> -#include <mach/imx27-regs.h> -#include <mach/imx-pll.h> -#include <linux/linkage.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \ - MX27_CSCR_SD_CNT(3) | \ - MX27_CSCR_MSHC_SEL | \ - MX27_CSCR_H264_SEL | \ - MX27_CSCR_SSI1_SEL | \ - MX27_CSCR_SSI2_SEL | \ - MX27_CSCR_MCU_SEL | \ - MX27_CSCR_ARM_SRC_MPLL | \ - MX27_CSCR_SP_SEL | \ - MX27_CSCR_ARM_DIV(0) | \ - MX27_CSCR_FPM_EN | \ - MX27_CSCR_SPEN | \ - MX27_CSCR_MPEN | \ - MX27_CSCR_AHB_DIV(1) - -ENTRY(neso_pll_init) - - /* 399 MHz */ - writel(IMX_PLL_PD(0) | - IMX_PLL_MFD(51) | - IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) - - /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ - writel(IMX_PLL_PD(1) | - IMX_PLL_MFD(12) | - IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) - - writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, - MX27_CCM_BASE_ADDR + MX27_CSCR) - - ldr r2, =16000 -1: - subs r2, r2, #1 - nop - bcs 1b - - mov pc, lr -ENDPROC(neso_pll_init) - diff --git a/arch/arm/boards/guf-santaro/Makefile b/arch/arm/boards/guf-santaro/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/guf-santaro/Makefile +++ b/arch/arm/boards/guf-santaro/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/guf-santaro/board.c b/arch/arm/boards/guf-santaro/board.c index e54110886b..acc3fc7f07 100644 --- a/arch/arm/boards/guf-santaro/board.c +++ b/arch/arm/boards/guf-santaro/board.c @@ -1,43 +1,32 @@ -/* - * Copyright (C) 2014 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sascha Hauer <s.hauer@pengutronix.de> + #define pr_fmt(fmt) "Santaro: " fmt #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx6-regs.h> +#include <mach/imx/imx6-regs.h> #include <asm/armlinux.h> #include <asm/io.h> #include <asm/mmu.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #include <bootsource.h> #include <bbu.h> -#include <mach/bbu.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> #include <i2c/i2c.h> #include <gpio.h> static int i2c_device_present(struct i2c_adapter *adapter, int addr) { struct i2c_client client = {}; - u8 reg; client.adapter = adapter; client.addr = addr; - return i2c_write_reg(&client, 0x00, ®, 0) < 0 ? false : true; + return i2c_write_reg(&client, 0x00, NULL, 0) < 0 ? false : true; } #define TOUCH_RESET_GPIO IMX_GPIO_NR(1, 20) diff --git a/arch/arm/boards/guf-santaro/flash-header.imxcfg b/arch/arm/boards/guf-santaro/flash-header.imxcfg index 2e85e13ba9..6d5bbae5d8 100644 --- a/arch/arm/boards/guf-santaro/flash-header.imxcfg +++ b/arch/arm/boards/guf-santaro/flash-header.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/guf-santaro/lowlevel.c b/arch/arm/boards/guf-santaro/lowlevel.c index 30c5e9054a..72401eb32c 100644 --- a/arch/arm/boards/guf-santaro/lowlevel.c +++ b/arch/arm/boards/guf-santaro/lowlevel.c @@ -1,14 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <io.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <asm/cache.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6-regs.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <console.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/guf-vincell/Makefile b/arch/arm/boards/guf-vincell/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/guf-vincell/Makefile +++ b/arch/arm/boards/guf-vincell/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c index 007b6dd347..50439b5b78 100644 --- a/arch/arm/boards/guf-vincell/board.c +++ b/arch/arm/boards/guf-vincell/board.c @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2011 Marc Kleine-Budde <mkl@pengutronix.de> #include <common.h> #include <environment.h> @@ -23,11 +11,11 @@ #include <io.h> #include <linux/clk.h> -#include <mach/devices-imx53.h> -#include <mach/generic.h> -#include <mach/iim.h> -#include <mach/bbu.h> -#include <mach/imx5.h> +#include <mach/imx/generic.h> +#include <mach/imx/iim.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx53-regs.h> static int vincell_devices_init(void) { diff --git a/arch/arm/boards/guf-vincell/flash-header.imxcfg b/arch/arm/boards/guf-vincell/flash-header.imxcfg index 8bfb5d0508..f5f2eceb5d 100644 --- a/arch/arm/boards/guf-vincell/flash-header.imxcfg +++ b/arch/arm/boards/guf-vincell/flash-header.imxcfg @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 //============================================================================= //init script for i.MX53 DDR3 diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c index 04060b2003..e691aeca3e 100644 --- a/arch/arm/boards/guf-vincell/lowlevel.c +++ b/arch/arm/boards/guf-vincell/lowlevel.c @@ -1,14 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <io.h> #include <init.h> -#include <mach/imx53-regs.h> -#include <mach/clock-imx51_53.h> -#include <mach/imx5.h> -#include <mach/iomux-v3.h> -#include <mach/esdctl-v4.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/imx5.h> +#include <mach/imx/iomux-v3.h> +#include <mach/imx/esdctl-v4.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> #include <asm/cache.h> diff --git a/arch/arm/boards/haba-knx/Makefile b/arch/arm/boards/haba-knx/Makefile index b1c469dcf9..f2cf1123ed 100644 --- a/arch/arm/boards/haba-knx/Makefile +++ b/arch/arm/boards/haba-knx/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c index 55441b63af..d86e84e71a 100644 --- a/arch/arm/boards/haba-knx/init.c +++ b/arch/arm/boards/haba-knx/init.c @@ -1,43 +1,30 @@ -/* - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD - * Copyright (C) 2014 Gregory Hermant <gregory.hermant@calao-systems.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011-2012 Jean-Christophe PLAGNIOL-VILLARD +// SPDX-FileCopyrightText: 2014 Gregory Hermant <gregory.hermant@calao-systems.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <linux/clk.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> #include <led.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> #include <spi/spi.h> #include <i2c/i2c.h> #include <libfile.h> diff --git a/arch/arm/boards/haba-knx/lowlevel.c b/arch/arm/boards/haba-knx/lowlevel.c index 7f52f824df..f71e0098e8 100644 --- a/arch/arm/boards/haba-knx/lowlevel.c +++ b/arch/arm/boards/haba-knx/lowlevel.c @@ -7,14 +7,12 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_haba_knx_lite, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/highbank/Makefile b/arch/arm/boards/highbank/Makefile deleted file mode 100644 index e5e4536cd1..0000000000 --- a/arch/arm/boards/highbank/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-y += init.o - -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-highbank diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/010-ahci-boot b/arch/arm/boards/highbank/defaultenv-highbank/boot.d/010-ahci-boot deleted file mode 120000 index 3672f0495e..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/010-ahci-boot +++ /dev/null @@ -1 +0,0 @@ -../boot/ahci-boot
\ No newline at end of file diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/011-ahci b/arch/arm/boards/highbank/defaultenv-highbank/boot.d/011-ahci deleted file mode 120000 index 36b3b2815b..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/011-ahci +++ /dev/null @@ -1 +0,0 @@ -../boot/ahci
\ No newline at end of file diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/020-mmc-boot b/arch/arm/boards/highbank/defaultenv-highbank/boot.d/020-mmc-boot deleted file mode 120000 index 85c19bbd66..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/020-mmc-boot +++ /dev/null @@ -1 +0,0 @@ -../boot/mmc-boot
\ No newline at end of file diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/021-mmc b/arch/arm/boards/highbank/defaultenv-highbank/boot.d/021-mmc deleted file mode 120000 index 5af95d0ac7..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/021-mmc +++ /dev/null @@ -1 +0,0 @@ -../boot/mmc
\ No newline at end of file diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/030-net b/arch/arm/boards/highbank/defaultenv-highbank/boot.d/030-net deleted file mode 120000 index 70b8ea3965..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/030-net +++ /dev/null @@ -1 +0,0 @@ -../boot/net
\ No newline at end of file diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/031-net-eth1 b/arch/arm/boards/highbank/defaultenv-highbank/boot.d/031-net-eth1 deleted file mode 120000 index 5a30a308c7..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot.d/031-net-eth1 +++ /dev/null @@ -1 +0,0 @@ -../boot/net-eth1
\ No newline at end of file diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot/ahci b/arch/arm/boards/highbank/defaultenv-highbank/boot/ahci deleted file mode 100644 index 46a8c1b321..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot/ahci +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -path="/mnt/ahci" - -global.bootm.image="${path}/zImage" - -. /env/data/oftree - -oftree=${path}/oftree -if [ -f $oftree ]; then - global.bootm.oftree="$oftree" -fi - -# The rootdevice may actually be mmcblk1p2 if a card -# is inserted to the back MMC slot -global.linux.bootargs.dyn.root="root=/dev/sda2" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot/ahci-boot b/arch/arm/boards/highbank/defaultenv-highbank/boot/ahci-boot deleted file mode 100644 index 919eac54a7..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot/ahci-boot +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -path="/mnt/ahci-boot" - -global.bootm.image="${path}/zImage" - -. /env/data/oftree - -oftree=${path}/oftree -if [ -f $oftree ]; then - global.bootm.oftree="$oftree" -fi - -# The rootdevice may actually be mmcblk1p2 if a card -# is inserted to the back MMC slot -global.linux.bootargs.dyn.root="root=/dev/sda2" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot/mmc b/arch/arm/boards/highbank/defaultenv-highbank/boot/mmc deleted file mode 100644 index 0fff5b4a81..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot/mmc +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -path="/mnt/mmc" - -global.bootm.image="${path}/zimage" - -. /env/data/oftree - -oftree=${path}/oftree -if [ -f $oftree ]; then - global.bootm.oftree="$oftree" -fi - -# The rootdevice may actually be mmcblk1p2 if a card -# is inserted to the back MMC slot -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot/mmc-boot b/arch/arm/boards/highbank/defaultenv-highbank/boot/mmc-boot deleted file mode 100644 index f3ae301e1b..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot/mmc-boot +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -path="/mnt/mmc-boot" - -global.bootm.image="${path}/zimage" - -. /env/data/oftree - -oftree=${path}/oftree -if [ -f $oftree ]; then - global.bootm.oftree="$oftree" -fi - -# The rootdevice may actually be mmcblk1p2 if a card -# is inserted to the back MMC slot -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot/net b/arch/arm/boards/highbank/defaultenv-highbank/boot/net deleted file mode 100644 index 6a700087fb..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot/net +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -ethact eth0 - -path="/mnt/tftp" - -. /env/data/oftree - -global.bootm.image="${path}/${global.user}-linux-${global.hostname}" -#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}" -nfsroot="/home/${global.user}/nfsroot/${global.hostname}" -bootargs-ip -global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/boot/net-eth1 b/arch/arm/boards/highbank/defaultenv-highbank/boot/net-eth1 deleted file mode 100644 index 1c70bdf3f0..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/boot/net-eth1 +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -ethact eth1 - -path="/mnt/tftp" - -. /env/data/oftree - -global.bootm.image="${path}/${global.user}-linux-${global.hostname}" -#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}" -nfsroot="/home/${global.user}/nfsroot/${global.hostname}" -bootargs-ip -global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/data/oftree b/arch/arm/boards/highbank/defaultenv-highbank/data/oftree deleted file mode 100644 index 9a94b310c3..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/data/oftree +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -#device tree provided by the firmware -global.bootm.oftree="/dev/dtb" diff --git a/arch/arm/boards/highbank/defaultenv-highbank/init/001-dtb-probe b/arch/arm/boards/highbank/defaultenv-highbank/init/001-dtb-probe deleted file mode 100644 index 610db1500e..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/init/001-dtb-probe +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -if [ -e /dev/dtb ] -then - oftree -l /dev/dtb - oftree -p -fi diff --git a/arch/arm/boards/highbank/defaultenv-highbank/init/automount b/arch/arm/boards/highbank/defaultenv-highbank/init/automount deleted file mode 100644 index eb5c07a739..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/init/automount +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh - -# automount tftp server based on $eth0.serverip - -mkdir -p /mnt/tftp -automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' - -# SD card slot, boot partition -mkdir -p /mnt/mmc-boot -automount -d /mnt/mmc 'mount /dev/disk0.boot /mnt/mmc-boot' - -# SD card slot, first partition -mkdir -p /mnt/mmc -automount -d /mnt/mmc 'mount /dev/disk0.0 /mnt/mmc' - -# AHCI, boot partition -mkdir -p /mnt/ahci-boot -automount -d /mnt/ahci 'mount /dev/ata0.boot /mnt/ahci-boot' - -# AHCI, first partition -mkdir -p /mnt/ahci -automount -d /mnt/ahci 'mount /dev/ata0.0 /mnt/ahci' diff --git a/arch/arm/boards/highbank/defaultenv-highbank/nv/boot.default b/arch/arm/boards/highbank/defaultenv-highbank/nv/boot.default deleted file mode 100644 index c47e1b2bca..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/nv/boot.default +++ /dev/null @@ -1 +0,0 @@ -/env/boot.d diff --git a/arch/arm/boards/highbank/defaultenv-highbank/nv/bootm.oftree b/arch/arm/boards/highbank/defaultenv-highbank/nv/bootm.oftree deleted file mode 100644 index c373173805..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/nv/bootm.oftree +++ /dev/null @@ -1 +0,0 @@ -/dev/dtb diff --git a/arch/arm/boards/highbank/defaultenv-highbank/nv/linux.bootargs.console b/arch/arm/boards/highbank/defaultenv-highbank/nv/linux.bootargs.console deleted file mode 100644 index 826debe7c2..0000000000 --- a/arch/arm/boards/highbank/defaultenv-highbank/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyAMA0,115200n8 CONSOLE=/dev/ttyAMA0 diff --git a/arch/arm/boards/highbank/init.c b/arch/arm/boards/highbank/init.c deleted file mode 100644 index 32e217321a..0000000000 --- a/arch/arm/boards/highbank/init.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * GPLv2 only - */ - -#include <common.h> -#include <init.h> -#include <asm/armlinux.h> -#include <asm/system_info.h> -#include <generated/mach-types.h> -#include <mach/devices.h> -#include <mach/hardware.h> -#include <mach/sysregs.h> -#include <environment.h> -#include <partition.h> -#include <linux/sizes.h> -#include <io.h> -#include <of.h> -#include <envfs.h> - -#define FIRMWARE_DTB_BASE 0x1000 - -#define HB_OPP_VERSION 0 - -struct fdt_header *fdt = NULL; - -static int hb_fixup(struct device_node *root, void *unused) -{ - struct device_node *node; - u32 reg = readl(sregs_base + HB_SREG_A9_PWRDOM_DATA); - u32 *opp_table = (u32 *)HB_SYSRAM_OPP_TABLE_BASE; - u32 dtb_table[2*10]; - u32 i; - u32 num_opps; - __be32 latency; - - if (!(reg & HB_PWRDOM_STAT_SATA)) { - for_each_compatible_node_from(node, root, NULL, "calxeda,hb-ahci") - of_property_write_string(node, "status", "disabled"); - } - - if (!(reg & HB_PWRDOM_STAT_EMMC)) { - for_each_compatible_node_from(node, root, NULL, "calxeda,hb-sdhci") - of_property_write_string(node, "status", "disabled"); - } - - if ((opp_table[0] >> 16) != HB_OPP_VERSION) - return 0; - - node = of_find_node_by_path("/cpus/cpu@0"); - if (!node) - return 0; - - num_opps = opp_table[0] & 0xff; - - for (i = 0; i < num_opps; i++) { - dtb_table[2 * i] = cpu_to_be32(opp_table[3 + 3 * i]); - dtb_table[2 * i + 1] = cpu_to_be32(opp_table[2 + 3 * i]); - } - - latency = cpu_to_be32(opp_table[1]); - - of_set_property(node, "transition-latency", &latency, 4, 1); - of_set_property(node, "operating-points", dtb_table, 8 * num_opps, 1); - - return 0; -} - -static int highbank_mem_init(void) -{ - struct device_node *root, *np; - int ret; - - /* load by the firmware at 0x1000 */ - fdt = IOMEM(FIRMWARE_DTB_BASE); - - root = of_unflatten_dtb(fdt); - if (IS_ERR(root)) { - pr_warn("no dtb found at 0x1000 use default configuration\n"); - fdt = NULL; - goto not_found; - } - - of_set_root_node(root); - - np = of_find_node_by_path("/memory"); - if (!np) { - pr_warn("no memory node use default configuration\n"); - goto not_found; - } - - ret = of_add_memory(np, true); - if (ret) { - pr_warn("memory node: probe failed use default configuration\n"); - goto not_found; - } - - pr_info("highbank: dtb probed memory size\n"); - - return 0; -not_found: - highbank_add_ddram(4089 << 20); - return 0; -} -mem_initcall(highbank_mem_init); - -static int highbank_devices_init(void) -{ - of_register_fixup(hb_fixup, NULL); - if (!fdt) { - highbank_register_gpio(0); - highbank_register_gpio(1); - highbank_register_gpio(2); - highbank_register_gpio(3); - highbank_register_ahci(); - highbank_register_xgmac(0); - highbank_register_xgmac(1); - } else { - fdt = of_get_fixed_tree(NULL); - add_mem_device("dtb", (unsigned long)fdt, be32_to_cpu(fdt->totalsize), - IORESOURCE_MEM_WRITEABLE); - devfs_add_partition("ram0", FIRMWARE_DTB_BASE, SZ_64K, DEVFS_PARTITION_FIXED, "firmware-dtb"); - } - - devfs_add_partition("nvram", 0x00000, SZ_16K, DEVFS_PARTITION_FIXED, "env0"); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_highbank); - - return 0; -} -device_initcall(highbank_devices_init); - -static int highbank_console_init(void) -{ - barebox_set_model("Calxeda Highbank"); - barebox_set_hostname("highbank"); - - highbank_register_uart(); - - return 0; -} -console_initcall(highbank_console_init); diff --git a/arch/arm/boards/highbank/lowlevel.c b/arch/arm/boards/highbank/lowlevel.c deleted file mode 100644 index 6363ec96df..0000000000 --- a/arch/arm/boards/highbank/lowlevel.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * GPLv2 only - */ - -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <asm/system_info.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - barebox_arm_entry(0x00000000, SZ_512M, NULL); -} diff --git a/arch/arm/boards/imx233-olinuxino/Makefile b/arch/arm/boards/imx233-olinuxino/Makefile index 987b34394a..1288c8c1de 100644 --- a/arch/arm/boards/imx233-olinuxino/Makefile +++ b/arch/arm/boards/imx233-olinuxino/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y = imx23-olinuxino.o lwl-y += lowlevel.o bbenv-y += defaultenv-imx233-olinuxino diff --git a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c index af548b3c53..cf92e2bb63 100644 --- a/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c +++ b/arch/arm/boards/imx233-olinuxino/imx23-olinuxino.c @@ -1,20 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * (C) Copyright 2012 Fadil Berisha, <fadil.r.berisha@gmail.com> * based on falconwing.c & mx23-evk.c * * (C) Copyright 2010 Juergen Beisert - Pengutronix * (C) Copyright 2011 Wolfram Sang - Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <common.h> @@ -27,14 +18,12 @@ #include <mci.h> #include <asm/armlinux.h> #include <asm/barebox-arm.h> -#include <usb/ehci.h> -#include <mach/usb.h> -#include <generated/mach-types.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include <mach/mci.h> -#include <mach/iomux.h> -#include <generated/mach-types.h> +#include <linux/usb/ehci.h> +#include <mach/mxs/usb.h> +#include <asm/mach-types.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/mci.h> +#include <mach/mxs/iomux.h> static struct mxs_mci_platform_data mci_pdata = { .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED, diff --git a/arch/arm/boards/imx233-olinuxino/lowlevel.c b/arch/arm/boards/imx233-olinuxino/lowlevel.c index 253cf1257b..91c1ba3dba 100644 --- a/arch/arm/boards/imx233-olinuxino/lowlevel.c +++ b/arch/arm/boards/imx233-olinuxino/lowlevel.c @@ -1,17 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx23-regs.h> -#include <mach/init.h> +#include <mach/mxs/imx23-regs.h> +#include <mach/mxs/init.h> #include <io.h> #include <debug_ll.h> -#include <mach/iomux.h> -#include <generated/mach-types.h> +#include <mach/mxs/iomux.h> +#include <asm/mach-types.h> + +static noinline void continue_imx_entry(size_t size) +{ + static struct barebox_arm_boarddata boarddata = { + .magic = BAREBOX_ARM_BOARDDATA_MAGIC, + .machine = MACH_TYPE_IMX233_OLINUXINO, + }; + + barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); +} ENTRY_FUNCTION(start_barebox_olinuxino_imx23, r0, r1, r2) { - barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, (void *)MACH_TYPE_IMX233_OLINUXINO); + relocate_to_current_adr(); + setup_c(); + + continue_imx_entry(SZ_64M); } static const uint32_t pad_setup[] = { diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/Makefile b/arch/arm/boards/innocomm-imx8mm-wb15/Makefile new file mode 100644 index 0000000000..10abebc539 --- /dev/null +++ b/arch/arm/boards/innocomm-imx8mm-wb15/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o lpddr4-timing.o +obj-y += board.o diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/board.c b/arch/arm/boards/innocomm-imx8mm-wb15/board.c new file mode 100644 index 0000000000..5bb285b189 --- /dev/null +++ b/arch/arm/boards/innocomm-imx8mm-wb15/board.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/imx/bbu.h> + +static int innocomm_wb15_evk_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", emmc_bbu_flag); + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + + return 0; +} + +static const struct of_device_id innocomm_wb15_evk_of_match[] = { + { .compatible = "innocomm,wb15-evk" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(innocomm_wb15_evk_of_match); + +static struct driver innocomm_wb15_evkboard_driver = { + .name = "board-innocomm-wb15-evk", + .probe = innocomm_wb15_evk_probe, + .of_compatible = DRV_OF_COMPAT(innocomm_wb15_evk_of_match), +}; +coredevice_platform_driver(innocomm_wb15_evkboard_driver); diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg b/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg new file mode 100644 index 0000000000..8aff991618 --- /dev/null +++ b/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mm + +loadaddr 0x007e1000 +max_load_size 0x3f000 +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c new file mode 100644 index 0000000000..a779c1f0ac --- /dev/null +++ b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <asm/barebox-arm.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx8mm.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mfd/bd71837.h> +#include <mach/imx/xload.h> +#include <soc/imx8m/ddr.h> + +#include "lowlevel.h" + +extern char __dtb_z_imx8mm_innocomm_wb15_evk_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mm_setup_pad(IMX8MM_PAD_UART2_TXD_UART2_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + putc_ll('>'); +} + +static struct pmic_config bd71837_cfg[] = { + /* unlock the PMIC regs */ + { BD718XX_REGLOCK, 0x0 }, + /* retry powering up indefinitely every 250ms after VR fault */ + { BD718XX_RCVCFG, 0xfc }, + /* decrease RESET key long push time from the default 10s to 10ms */ + { BD718XX_PWRONCONFIG1, 0x0 }, + /* WDOG_B: Warm Reset */ + { BD718XX_PWRCTRL0, 0xa3 }, + /* READY=>SNVS on PMIC_ON_REQ, SNVS=>RUN on VSYS_UVLO */ + { BD718XX_TRANS_COND0, 0x48 }, + /* WDOG_B: Go to SNVS power state after deassert */ + { BD718XX_TRANS_COND1, 0xc0 }, + /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ + { BD718XX_BUCK1_VOLT_RUN, 0xf }, + /* increase VDD_DRAM to 0.900v for 2400MT/s DDR */ + { BD718XX_1ST_NODVS_BUCK_VOLT, 0x02 }, + /* set BUCK8 to 1.10v */ + { BD718XX_4TH_NODVS_BUCK_VOLT, 0x1e }, + /* lock the PMIC regs */ + { BD718XX_REGLOCK, 0x11 }, +}; + +void innocomm_wb15_power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL); + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MM_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg)); +} + +ENTRY_FUNCTION(start_innocomm_wb15_evk, r0, r1, r2) +{ + imx8mm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + setup_uart(); + + /* + * If we are in EL3 we are running for the first time out of OCRAM, + * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A + * will then jump to DRAM in EL2 + */ + if (current_el() == 3) { + imx8mm_early_clock_init(); + + innocomm_wb15_power_init_board(); + + imx8mm_ddr_init(&innocomm_wb15_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mm_load_and_start_image_via_tfa(); + } + + /* Standard entry we hit once we initialized both DDR and ATF */ + imx8mm_barebox_entry(__dtb_z_imx8mm_innocomm_wb15_evk_start); +} diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h new file mode 100644 index 0000000000..3b0ea9ccc3 --- /dev/null +++ b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef INNOCOMM_WB15_LOWLEVEL_H_ +#define INNOCOMM_WB15_LOWLEVEL_H_ + +void innocomm_wb15_power_init_board(void); +extern struct dram_timing_info innocomm_wb15_dram_timing; + +#endif diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c new file mode 100644 index 0000000000..54c8442673 --- /dev/null +++ b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c @@ -0,0 +1,1132 @@ +/* + * Copyright 2018 InnoComm Mobile Technology Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#define DDR_ONE_RANK +#include <soc/imx8m/lpddr4_define.h> + +#include "lowlevel.h" + +static struct dram_cfg_param ddr_ddrc_cfg_1g_2ch1cs15r10cx32[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa1080020}, + {0x3d400020,0x223}, + {0x3d400024,0x2ee00}, + {0x3d400064,0x49006c}, + {0x3d4000d0,0xc0030495}, + {0x3d4000d4,0x770000}, + {0x3d4000dc,0xc40024}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x1618141a}, + {0x3d400104,0x504a6}, + {0x3d40010c,0x909000}, + {0x3d400110,0xb04060b}, + {0x3d400114,0x2030909}, + {0x3d400118,0x1010006}, + {0x3d40011c,0x301}, + {0x3d400130,0x20500}, + {0x3d400134,0xb100002}, + {0x3d400138,0x71}, + {0x3d400144,0x78003c}, + {0x3d400180,0x2580012}, + {0x3d400184,0x1e0493e}, + {0x3d400188,0x0}, + {0x3d400190,0x4938208}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x1308}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x1}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x60c1514}, + {0x3d400200,0x1f}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0xf070707}, + {0x3d40021c,0xf0f}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x7d00}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc0012}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x13}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d4020f4,0xc99}, + {0x3d403020,0x21}, + {0x3d403024,0x1f40}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30005}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x5}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d4030f4,0xc99}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0xa}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x2}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x258}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg_1g_2ch1cs15r10cx32[] = { + {0xd0000, 0x0}, + {0x54003,0x960}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x24c4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x24c4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xc400}, + {0x54033,0x3124}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xc400}, + {0x54039,0x3124}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg_1g_2ch1cs15r10cx32[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg_1g_2ch1cs15r10cx32[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32[] = { + {0xd0000, 0x0}, + {0x54003,0x960}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x110}, + {0x54019,0x24c4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x24c4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xc400}, + {0x54033,0x3124}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xc400}, + {0x54039,0x3124}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x4b}, + {0x2000c,0x96}, + {0x2000d,0x5dc}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg_1g_2ch1cs15r10cx32[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg_1g_2ch1cs15r10cx32, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1g_2ch1cs15r10cx32), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg_1g_2ch1cs15r10cx32, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1g_2ch1cs15r10cx32), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg_1g_2ch1cs15r10cx32, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1g_2ch1cs15r10cx32), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info innocomm_wb15_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg_1g_2ch1cs15r10cx32, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1g_2ch1cs15r10cx32), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg_1g_2ch1cs15r10cx32, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1g_2ch1cs15r10cx32), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 400, 100, }, +}; diff --git a/arch/arm/boards/kamstrup-mx7-concentrator/Makefile b/arch/arm/boards/kamstrup-mx7-concentrator/Makefile new file mode 100644 index 0000000000..458f520900 --- /dev/null +++ b/arch/arm/boards/kamstrup-mx7-concentrator/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o diff --git a/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg b/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg new file mode 100644 index 0000000000..12e0754912 --- /dev/null +++ b/arch/arm/boards/kamstrup-mx7-concentrator/flash-header-tqma7d.imxcfg @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx7 +loadaddr 0xbfbff000 +ivtofs 0x400 + +#include <mach/imx/imx7-ddr-regs.h> + +wm 32 0x30340004 0x4F400005 /* IOMUXC_GPR_GPR1 */ +/* Clear then set bit30 to ensure exit from DDR retention */ +wm 32 0x30360388 0x40000000 +wm 32 0x30360384 0x40000000 + +/* TQMa7x DRAM Timing REV0100 */ +/* DCD Code i.MX7D/S 528 MHz 1 GByte Samsung K4B4G1646D */ +wm 32 0x30360070 0x0070302C /* CCM_ANALOG_PLL_DDRx */ +wm 32 0x30360090 0x00000000 /* CCM_ANALOG_PLL_NUM */ +wm 32 0x30360070 0x0060302C /* CCM_ANALOG_PLL_DDRx */ +check 32 until_all_bits_set 0x30360070 0x80000000 +wm 32 0x30391000 0x00000002 /* SRC_DDRC_RCR */ + +wm 32 MX7_DDRC_MSTR 0x01040001 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 +wm 32 MX7_DDRC_RFSHTMG 0x00200045 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00020081 +wm 32 MX7_DDRC_INIT1 0x00680000 +wm 32 MX7_DDRC_INIT3 0x09300004 +wm 32 MX7_DDRC_INIT4 0x00480000 +wm 32 MX7_DDRC_INIT5 0x00100004 +wm 32 MX7_DDRC_RANKCTL 0x0000033F +wm 32 MX7_DDRC_DRAMTMG0 0x090E0809 +wm 32 MX7_DDRC_DRAMTMG1 0x0007020E +wm 32 MX7_DDRC_DRAMTMG2 0x03040407 +wm 32 MX7_DDRC_DRAMTMG3 0x00002006 +wm 32 MX7_DDRC_DRAMTMG4 0x04020304 +wm 32 MX7_DDRC_DRAMTMG5 0x03030202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000803 +wm 32 MX7_DDRC_ZQCTL0 0x00800020 +wm 32 MX7_DDRC_DFITMG0 0x02098204 +wm 32 MX7_DDRC_DFITMG1 0x00030303 +wm 32 MX7_DDRC_ADDRMAP0 0x00000016 +wm 32 MX7_DDRC_ADDRMAP1 0x00171717 +wm 32 MX7_DDRC_ADDRMAP4 0x00000F0F +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0F040404 +wm 32 MX7_DDRC_ODTCFG 0x06000604 +wm 32 MX7_DDRC_ODTMAP 0x00000001 +wm 32 0x30391000 0x00000000 /* SRC_DDRC_RCR */ +wm 32 MX7_DDR_PHY_PHY_CON0 0x17420F40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807 +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007E +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000924 +/* DDR_PHY_CMD_DESKEW_CON0 not set */ +/* DDR_PHY_CMD_DESKEW_CON1 not set */ +/* DDR_PHY_CMD_DESKEW_CON2 not set */ +/* DDR_PHY_CMD_DESKEW_CON3 not set */ +/* DDR_PHY_LVL_CON0 not set */ +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x0B0B0B0B +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x06060606 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010 + +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C407304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C447306 +check 32 until_all_bits_set MX7_DDR_PHY_ZQ_CON1 0x1 /* ZQ Calibration is finished */ +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C447304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0C407304 + +wm 32 0x30384130 0x00000000 /* CCM_CCGRn */ +wm 32 0x30340020 0x00000178 /* IOMUXC_GPR_GPR8 */ +wm 32 0x30384130 0x00000002 /* CCM_CCGRn */ +wm 32 0x30790018 0x0000000f /* DDR_PHY_LP_CON0 */ + +/* DDRC_STAT */ +check 32 until_all_bits_set 0x307a0004 0x1 + diff --git a/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c b/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c new file mode 100644 index 0000000000..e1ba327251 --- /dev/null +++ b/arch/arm/boards/kamstrup-mx7-concentrator/lowlevel.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <io.h> +#include <common.h> +#include <linux/sizes.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/imx/imx7-ccm-regs.h> +#include <mach/imx/iomux-mx7.h> +#include <mach/imx/debug_ll.h> +#include <asm/cache.h> +#include <mach/imx/esdctl.h> + +extern char __dtb_z_imx7d_flex_concentrator_mfg_start[]; + +static inline void setup_uart(void) +{ + imx7_early_setup_uart_clock(4); + + imx7_setup_pad(MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX); + + imx7_uart_setup_ll(); + + putc_ll('>'); +} + +ENTRY_FUNCTION(start_kamstrup_mx7_concentrator, r0, r1, r2) +{ + imx7_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + imx7d_barebox_entry(__dtb_z_imx7d_flex_concentrator_mfg_start + get_runtime_offset()); +} diff --git a/arch/arm/boards/karo-qsxp-ml81/Makefile b/arch/arm/boards/karo-qsxp-ml81/Makefile new file mode 100644 index 0000000000..10abebc539 --- /dev/null +++ b/arch/arm/boards/karo-qsxp-ml81/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o lpddr4-timing.o +obj-y += board.o diff --git a/arch/arm/boards/karo-qsxp-ml81/board.c b/arch/arm/boards/karo-qsxp-ml81/board.c new file mode 100644 index 0000000000..e9e3d46bf1 --- /dev/null +++ b/arch/arm/boards/karo-qsxp-ml81/board.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/imx/bbu.h> + +static int karo_qsxp_ml81_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + + return 0; +} + +static const struct of_device_id karo_qsxp_ml81_of_match[] = { + { .compatible = "karo,imx8mp-qsxp-ml81-qsbase4" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(karo_qsxp_ml81_of_match); + +static struct driver karo_qsxp_ml81_board_driver = { + .name = "board-karo-qsxp-ml81", + .probe = karo_qsxp_ml81_probe, + .of_compatible = DRV_OF_COMPAT(karo_qsxp_ml81_of_match), +}; +coredevice_platform_driver(karo_qsxp_ml81_board_driver); diff --git a/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg b/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg new file mode 100644 index 0000000000..da0892e52d --- /dev/null +++ b/arch/arm/boards/karo-qsxp-ml81/flash-header-karo-qsxp-ml81.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mp + +loadaddr 0x00920000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/karo-qsxp-ml81/lowlevel.c b/arch/arm/boards/karo-qsxp-ml81/lowlevel.c new file mode 100644 index 0000000000..506a9c9930 --- /dev/null +++ b/arch/arm/boards/karo-qsxp-ml81/lowlevel.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <asm/barebox-arm.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/atf.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/xload.h> +#include <mfd/pca9450.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <soc/imx8m/ddr.h> + +#include "lowlevel.h" + +extern char __dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_PE | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_DSE6) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +#define pca9450_mV_to_reg(mV) (((mV) - 600) * 10 / 125) +#define pca9450_reg_to_mV(val) (((val) * 125 / 10) + 600) + +#define VDD_SOC_VAL pca9450_mV_to_reg(950) +#define VDD_SOC_SLP_VAL pca9450_mV_to_reg(850) +#define VDD_ARM_VAL pca9450_mV_to_reg(950) +#define VDD_DRAM_VAL pca9450_mV_to_reg(950) + +static struct pmic_config pca9450_cfg[] = { + { PCA9450_BUCK123_DVS, 0x29 }, + { PCA9450_BUCK1OUT_DVS0, VDD_SOC_VAL }, + { PCA9450_BUCK1OUT_DVS1, VDD_SOC_SLP_VAL }, + { PCA9450_BUCK2OUT_DVS0, VDD_ARM_VAL }, + { PCA9450_BUCK3OUT_DVS0, VDD_DRAM_VAL }, + { PCA9450_BUCK1CTRL, 0x59 }, + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +ENTRY_FUNCTION(start_karo_qsxp_ml81, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + setup_uart(); + + /* + * If we are in EL3 we are running for the first time out of OCRAM, + * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A + * will then jump to DRAM in EL2 + */ + if (current_el() == 3) { + imx8mp_early_clock_init(); + + power_init_board(); + + imx8mp_ddr_init(&karo_qsxp_ml81_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); + } + + /* Standard entry we hit once we initialized both DDR and ATF */ + imx8mp_barebox_entry(__dtb_z_imx8mp_karo_qsxp_ml81_qsbase4_start); +} diff --git a/arch/arm/boards/karo-qsxp-ml81/lowlevel.h b/arch/arm/boards/karo-qsxp-ml81/lowlevel.h new file mode 100644 index 0000000000..37e5269653 --- /dev/null +++ b/arch/arm/boards/karo-qsxp-ml81/lowlevel.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef KARO_QSXP_ML81_LOWLEVEL_H_ +#define KARO_QSXP_ML81_LOWLEVEL_H_ + +extern struct dram_timing_info karo_qsxp_ml81_dram_timing; + +#endif diff --git a/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c b/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c new file mode 100644 index 0000000000..e151bcf01a --- /dev/null +++ b/arch/arm/boards/karo-qsxp-ml81/lpddr4-timing.c @@ -0,0 +1,872 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#include <soc/imx8m/lpddr4_define.h> + +#include "lowlevel.h" + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1203 }, + { 0x3d400024, 0x186a000 }, + { 0x3d400064, 0x6100e0 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc003061c }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x210000 }, + { 0x3d4000e8, 0x630048 }, + { 0x3d4000ec, 0x140025 }, + { 0x3d400100, 0x1a201b22 }, + { 0x3d400104, 0x60633 }, + { 0x3d40010c, 0xc0c000 }, + { 0x3d400110, 0xf04080f }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0xe6 }, + { 0x3d400144, 0xa00050 }, + { 0x3d400180, 0x3200018 }, + { 0x3d400184, 0x28061a8 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x1 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x5 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x2 }, + { 0x100a5, 0x4 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x7 }, + { 0x110a1, 0x6 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x5 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x1 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x4 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x2 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x1 }, + { 0x130a1, 0x6 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x0 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x1004d, 0x600 }, + { 0x1014d, 0x600 }, + { 0x1104d, 0x600 }, + { 0x1114d, 0x600 }, + { 0x1204d, 0x600 }, + { 0x1214d, 0x600 }, + { 0x1304d, 0x600 }, + { 0x1314d, 0x600 }, + { 0x10049, 0x69a }, + { 0x10149, 0x69a }, + { 0x11049, 0x69a }, + { 0x11149, 0x69a }, + { 0x12049, 0x69a }, + { 0x12149, 0x69a }, + { 0x13049, 0x69a }, + { 0x13149, 0x69a }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x303c }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x21 }, + { 0x5401b, 0x4863 }, + { 0x5401c, 0x2500 }, + { 0x5401e, 0x14 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x21 }, + { 0x54021, 0x4863 }, + { 0x54022, 0x2500 }, + { 0x54024, 0x14 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x212d }, + { 0x54034, 0x6300 }, + { 0x54035, 0x48 }, + { 0x54036, 0x25 }, + { 0x54037, 0x1400 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x212d }, + { 0x5403a, 0x6300 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x25 }, + { 0x5403d, 0x1400 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x303c }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x21 }, + { 0x5401b, 0x4863 }, + { 0x5401c, 0x2500 }, + { 0x5401e, 0x14 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x21 }, + { 0x54021, 0x4863 }, + { 0x54022, 0x2500 }, + { 0x54024, 0x14 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x212d }, + { 0x54034, 0x6300 }, + { 0x54035, 0x48 }, + { 0x54036, 0x25 }, + { 0x54037, 0x1400 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x212d }, + { 0x5403a, 0x6300 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x25 }, + { 0x5403d, 0x1400 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x384 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info karo_qsxp_ml81_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, }, +}; diff --git a/arch/arm/boards/karo-tx25/Makefile b/arch/arm/boards/karo-tx25/Makefile index 58453b66cd..2960516c5a 100644 --- a/arch/arm/boards/karo-tx25/Makefile +++ b/arch/arm/boards/karo-tx25/Makefile @@ -1,20 +1,5 @@ -# -# (C) Copyright 2011 Sascha Hauer <s.hauer@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de> lwl-y += lowlevel.o obj-y += board.o diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index a4d4af57a3..7e8691ef93 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -1,21 +1,5 @@ -/* - * (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix #define pr_fmt(fmt) "tx25: " fmt @@ -25,20 +9,19 @@ #include <linux/sizes.h> #include <gpio.h> #include <environment.h> -#include <mach/imx25-regs.h> +#include <mach/imx/imx25-regs.h> #include <asm/armlinux.h> #include <asm/sections.h> #include <asm/barebox-arm.h> #include <io.h> -#include <partition.h> -#include <generated/mach-types.h> -#include <mach/imx-nand.h> -#include <mach/iomux-mx25.h> -#include <mach/generic.h> -#include <mach/iim.h> +#include <asm/mach-types.h> +#include <mach/imx/imx-nand.h> +#include <mach/imx/iomux-mx25.h> +#include <mach/imx/generic.h> +#include <mach/imx/iim.h> +#include <platform_data/imxfb.h> #include <linux/err.h> -#include <mach/devices-imx25.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <asm/mmu.h> #define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9) @@ -181,8 +164,8 @@ static int tx25_init_fb(void) mxc_iomux_v3_setup_multiple_pads(tx25_lcdc_gpios, ARRAY_SIZE(tx25_lcdc_gpios)); - imx25_add_fb(&tx25_fb_data); - + add_generic_device("imxfb", -1, NULL, (resource_size_t)MX25_LCDC_BASE_ADDR, 0x1000, + IORESOURCE_MEM, &tx25_fb_data); return 0; } device_initcall(tx25_init_fb); diff --git a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg index 2345f18e93..0786017a85 100644 --- a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg +++ b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg @@ -1,10 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only # # currently unused in barebox, but useful to generate # a imx-image to use with imx-usb-loader # soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8001010 0x00000002 wm 32 0xb8001004 0x00095728 wm 32 0xb8001000 0x92116480 diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index f79cd91640..d6658b535f 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -1,28 +1,13 @@ -/* - * - * (c) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> -#include <mach/imx25-regs.h> -#include <mach/esdctl.h> +#include <mach/imx/imx25-regs.h> +#include <mach/imx/esdctl.h> #include <io.h> #include <linux/sizes.h> -#include <mach/imx-nand.h> +#include <mach/imx/imx-nand.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> #include <asm/system.h> @@ -74,7 +59,24 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, writel(esdctl, esdctlreg); } -static void __bare_init karo_tx25_common_init(void *fdt) +extern char __dtb_imx25_karo_tx25_start[]; + +static void __noreturn karo_tx25_start(void) +{ + void *fdt; + + fdt = __dtb_imx25_karo_tx25_start + get_runtime_offset(); + + imx25_barebox_entry(fdt); +} + +static void __noreturn karo_tx25_load_nand(void) +{ + imx25_nand_load_image(); + karo_tx25_start(); +} + +static void __bare_init karo_tx25_common_init(void) { uint32_t r; @@ -138,7 +140,7 @@ static void __bare_init karo_tx25_common_init(void *fdt) /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0x80000000 && r < 0xa0000000) - goto out; + karo_tx25_start(); /* set to 3.3v SDRAM */ writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454); @@ -156,21 +158,12 @@ static void __bare_init karo_tx25_common_init(void *fdt) setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); - imx25_barebox_boot_nand_external(fdt); - -out: - imx25_barebox_entry(fdt); + imx25_nand_relocate_to_sdram(karo_tx25_load_nand); } -extern char __dtb_imx25_karo_tx25_start[]; - ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE); - fdt = __dtb_imx25_karo_tx25_start + get_runtime_offset(); - - karo_tx25_common_init(fdt); + karo_tx25_common_init(); } diff --git a/arch/arm/boards/karo-tx28/Makefile b/arch/arm/boards/karo-tx28/Makefile index c7d7398cf3..b13ffc8f3c 100644 --- a/arch/arm/boards/karo-tx28/Makefile +++ b/arch/arm/boards/karo-tx28/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += tx28.o obj-$(CONFIG_MACH_TX28STK5) += tx28-stk5.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/karo-tx28/lowlevel.c b/arch/arm/boards/karo-tx28/lowlevel.c index 84cc681816..3be5f521e1 100644 --- a/arch/arm/boards/karo-tx28/lowlevel.c +++ b/arch/arm/boards/karo-tx28/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define pr_fmt(fmt) "KARO TX28: " fmt #define DEBUG @@ -5,17 +7,30 @@ #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx28-regs.h> -#include <mach/init.h> +#include <mach/mxs/imx28-regs.h> +#include <mach/mxs/init.h> #include <io.h> #include <debug_ll.h> -#include <mach/iomux.h> +#include <mach/mxs/iomux.h> #include <stmp-device.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> + +static noinline void continue_imx_entry(size_t size) +{ + static struct barebox_arm_boarddata boarddata = { + .magic = BAREBOX_ARM_BOARDDATA_MAGIC, + .machine = MACH_TYPE_TX28, + }; + + barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); +} ENTRY_FUNCTION(start_barebox_karo_tx28, r0, r1, r2) { - barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, (void *)MACH_TYPE_TX28); + relocate_to_current_adr(); + setup_c(); + + continue_imx_entry(SZ_128M); } static const uint32_t iomux_pads[] = { diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index 8628db2b25..d1fd526c00 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix #include <common.h> #include <init.h> @@ -25,13 +14,14 @@ #include <asm/sections.h> #include <asm/barebox-arm.h> #include <linux/err.h> -#include <mach/imx-regs.h> -#include <mach/clock.h> -#include <mach/mci.h> -#include <mach/fb.h> -#include <mach/ocotp.h> -#include <mach/iomux.h> -#include <generated/mach-types.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/mci.h> +#include <mach/mxs/fb.h> +#include <mach/mxs/ocotp.h> +#include <mach/mxs/iomux.h> +#include <asm/mach-types.h> + +#include "tx28.h" static struct mxs_mci_platform_data mci_pdata = { .caps = MMC_CAP_4_BIT_DATA, @@ -344,9 +334,7 @@ static int register_persistent_environment(void) /* use the full partition as our persistent environment storage */ cdev = devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); - if (IS_ERR(cdev)) - return PTR_ERR(cdev); - return 0; + return PTR_ERR_OR_ZERO(cdev); } static void tx28_get_ethaddr(void) diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c index d99083b190..ef3c42b5f6 100644 --- a/arch/arm/boards/karo-tx28/tx28.c +++ b/arch/arm/boards/karo-tx28/tx28.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2010 Juergen Beisert, Pengutronix <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Juergen Beisert <kernel@pengutronix.de>, Pengutronix #include <common.h> #include <init.h> @@ -20,12 +9,14 @@ #include <asm/armlinux.h> #include <asm/barebox-arm.h> #include <io.h> -#include <generated/mach-types.h> -#include <mach/imx-regs.h> -#include <mach/devices.h> -#include <mach/iomux.h> +#include <asm/mach-types.h> +#include <mach/mxs/imx-regs.h> +#include <mach/mxs/devices.h> +#include <mach/mxs/iomux.h> #include <asm/mmu.h> +#include "tx28.h" + /* setup the CPU card internal signals */ static const uint32_t tx28_pad_setup[] = { /* NAND interface */ @@ -72,8 +63,6 @@ static const uint32_t tx28_pad_setup[] = { }; -extern void base_board_init(void); - static int tx28_devices_init(void) { int i; diff --git a/arch/arm/boards/karo-tx28/tx28.h b/arch/arm/boards/karo-tx28/tx28.h new file mode 100644 index 0000000000..2e14211b7a --- /dev/null +++ b/arch/arm/boards/karo-tx28/tx28.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +void base_board_init(void); + diff --git a/arch/arm/boards/karo-tx51/env/config b/arch/arm/boards/karo-tx51/env/config deleted file mode 100644 index 755eaec2c1..0000000000 --- a/arch/arm/boards/karo-tx51/env/config +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/sh - -machine=tx51 - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.ethaddr=de:ad:be:ef:00:00 -#eth0.netmask=a.b.c.d -#eth0.serverip=a.b.c.d -#eth0.gateway=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-$machine.$rootfs_type - -kernelimage=zImage_$machine -#kernelimage=uImage-$machine -#kernelimage=Image-$machine -#kernelimage=Image-$machine.lzo -kernel_part=nand0.kernel - -#nfsroot="$serverip:/srv/root" - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nand_device=mxc_nand -nand_parts="256k(barebox)ro,256k(bareboxenv),4M@0xc00000(kernel),64M(rootfs),-(rootfs_data)" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31mtx51:\w\e[0m " diff --git a/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg b/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg deleted file mode 100644 index ebb7c4f396..0000000000 --- a/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg +++ /dev/null @@ -1,13 +0,0 @@ -soc imx51 -loadaddr 0x90000000 -dcdofs 0x400 -wm 32 0x83fd9000 0x80000000 -wm 32 0x83fd9014 0x04008008 -wm 32 0x83fd9014 0x00008010 -wm 32 0x83fd9014 0x00008010 -wm 32 0x83fd9014 0x00338018 -wm 32 0x83fd9000 0xb2220000 -wm 32 0x83fd9004 0xb08564a9 -wm 32 0x83fd9034 0x20020000 -wm 32 0x83fd9010 0x000a0080 -wm 32 0x83fd9014 0x00000000 diff --git a/arch/arm/boards/karo-tx51/lowlevel.c b/arch/arm/boards/karo-tx51/lowlevel.c deleted file mode 100644 index 6762fdad4b..0000000000 --- a/arch/arm/boards/karo-tx51/lowlevel.c +++ /dev/null @@ -1,11 +0,0 @@ -#include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> -#include <asm/barebox-arm-head.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - imx5_cpu_lowlevel_init(); - arm_setup_stack(0x20000000); - imx51_barebox_entry(NULL); -} diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c deleted file mode 100644 index 913df68cc9..0000000000 --- a/arch/arm/boards/karo-tx51/tx51.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2012 Christian Kapeller, <christian.kapeller@cmotion.eu> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include <common.h> -#include <init.h> -#include <environment.h> -#include <mach/imx51-regs.h> -#include <platform_data/eth-fec.h> -#include <gpio.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <fs.h> -#include <fcntl.h> -#include <nand.h> -#include <spi/spi.h> -#include <io.h> -#include <asm/mmu.h> -#include <mach/imx5.h> -#include <mach/imx-nand.h> -#include <mach/spi.h> -#include <mach/generic.h> -#include <mach/iomux-mx51.h> -#include <mach/devices-imx51.h> -#include <mach/iim.h> - - -#define STK5_MX51_PAD_DISPB2_SER_RS__GPIO3_8 \ - IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, PAD_CTL_PKE | PAD_CTL_PUE) - -#define STK5_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 \ - IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -struct gpio_led tx51_leds[] = { - { - .led = { .name = "GPIO-LED", }, - .gpio = IMX_GPIO_NR(4,10), - .active_low = 0, - }, -}; - -static iomux_v3_cfg_t tx51_pads[] = { - /*UART1*/ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_CTS__UART1_CTS, - MX51_PAD_UART1_RTS__UART1_RTS, - - /* (e)CSPI */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_RDY__ECSPI1_RDY, - - /* (e)CSPI chip select lines */ - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - -#ifdef CONFIG_MCI_IMX_ESDHC - /* eSDHC 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - /* SD1 card detect */ - STK5_MX51_PAD_DISPB2_SER_RS__GPIO3_8, - - /* eSDHC 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - - /* SD2 card detect */ - STK5_MX51_PAD_DISPB2_SER_DIO__GPIO3_6, -#endif - - /* SW controlled LED on STK5 baseboard */ - MX51_PAD_CSI2_D13__GPIO4_10, - - /* unuseable pads configured as GPIO */ - MX51_PAD_GPIO1_1__GPIO1_1, - MX51_PAD_GPIO1_0__GPIO1_0, -}; - -static int spi_0_cs[] = { - IMX_GPIO_NR(4, 24), - IMX_GPIO_NR(4, 25), -}; - -static struct spi_imx_master tx51_spi_0_data = { - .chipselect = spi_0_cs, - .num_chipselect = ARRAY_SIZE(spi_0_cs), -}; - -static const struct spi_board_info mx51_tx51_spi_board_info[] = {}; - -static struct tx51_fec_gpio_setup { - iomux_v3_cfg_t pad; - unsigned group:4, - shift:5, - level:1; -} tx51_fec_gpios[] = { - { MX51_PAD_EIM_A20__GPIO2_14, 2, 14, 0 }, /* PHY reset */ - { MX51_PAD_GPIO1_3__GPIO1_3, 1, 3, 0 }, /* PHY power enable */ - { MX51_PAD_NANDF_CS3__GPIO3_19, 3, 19, 0 }, /* MDC */ - { MX51_PAD_EIM_EB2__GPIO2_22, 2, 22, 0 }, /* MDIO */ - { MX51_PAD_NANDF_RB3__GPIO3_11, 3, 11, 0 }, /* RX_CLK */ - { MX51_PAD_NANDF_D11__GPIO3_29, 3, 29, 0 }, /* RX_DV */ - { MX51_PAD_NANDF_D9__GPIO3_31, 3, 31, 1 }, /* RXD0/Mode0 */ - { MX51_PAD_EIM_EB3__GPIO2_23, 2, 23, 1 }, /* RXD1/Mode1 */ - { MX51_PAD_EIM_CS2__GPIO2_27, 2, 27, 1 }, /* RXD2/Mode2 */ - { MX51_PAD_EIM_CS3__GPIO2_28, 2, 28, 1 }, /* RXD3/nINTSEL */ - { MX51_PAD_EIM_CS4__GPIO2_29, 2, 29, 0 }, /* RX_ER/RXD4 */ - { MX51_PAD_NANDF_RDY_INT__GPIO3_24, 3, 24, 0 }, /* TX_CLK */ - { MX51_PAD_NANDF_CS7__GPIO3_23, 3, 23, 0 }, /* TX_EN */ - { MX51_PAD_NANDF_D8__GPIO4_0, 4, 0, 0 }, /* TXD0 */ - { MX51_PAD_NANDF_CS4__GPIO3_20, 3, 20, 0 }, /* TXD1 */ - { MX51_PAD_NANDF_CS5__GPIO3_21, 3, 21, 0 }, /* TXD2 */ - { MX51_PAD_NANDF_CS6__GPIO3_22, 3, 22, 0 }, /* TXD3 */ - { MX51_PAD_NANDF_RB2__GPIO3_10, 3, 10, 0 }, /* COL/RMII/CRSDV */ - { MX51_PAD_EIM_CS5__GPIO2_30, 2, 30, 0 }, /* CRS */ - { MX51_PAD_NANDF_CS2__GPIO3_18, 3, 18, 0 }, /* nINT/TX_ER/TXD4 */ -}; - -static iomux_v3_cfg_t tx51_fec_pads[] = { - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDATA1, - MX51_PAD_NANDF_CS5__FEC_TDATA2, - MX51_PAD_NANDF_CS6__FEC_TDATA3, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RX_CLK, - MX51_PAD_NANDF_D8__FEC_TDATA0, - MX51_PAD_NANDF_D9__FEC_RDATA0, - MX51_PAD_NANDF_D11__FEC_RX_DV, - MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDATA1, - MX51_PAD_EIM_CS2__FEC_RDATA2, - MX51_PAD_EIM_CS3__FEC_RDATA3, - MX51_PAD_EIM_CS4__FEC_RX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, -}; - -#define TX51_FEC_PHY_RST IMX_GPIO_NR(2, 14) -#define TX51_FEC_PHY_PWR IMX_GPIO_NR(1, 3) -#define TX51_FEC_PHY_INT IMX_GPIO_NR(3, 18) - -static inline void tx51_fec_init(void) -{ - int i; - - /* Configure LAN8700 pads as GPIO and set up - * necessary strap options for PHY - */ - for (i = 0; i < ARRAY_SIZE(tx51_fec_gpios); i++) { - struct tx51_fec_gpio_setup *gs = &tx51_fec_gpios[i]; - - gpio_direction_output(IMX_GPIO_NR(gs->group, gs->shift ), gs->level); - mxc_iomux_v3_setup_pad(gs->pad); - } - - /* - *Turn on phy power, leave in reset state - */ - gpio_set_value(TX51_FEC_PHY_PWR, 1); - - /* - * Wait some time to let the phy activate the internal regulator - */ - mdelay(10); - - /* - * Deassert reset, phy latches the rest of bootstrap pins - */ - gpio_set_value(TX51_FEC_PHY_RST, 1); - - /* LAN7800 has an internal Power On Reset (POR) signal (OR'ed with - * the external RESET signal) which is deactivated 21ms after - * power on and latches the strap options. - * Delay for 22ms to ensure, that the internal POR is inactive - * before reconfiguring the strap pins. - */ - mdelay(22); - - /* - * The phy is ready, now configure imx51 pads for fec operation - */ - mxc_iomux_v3_setup_multiple_pads(tx51_fec_pads, - ARRAY_SIZE(tx51_fec_pads)); -} - -static void tx51_leds_init(void) -{ - int i; - - for (i = 0 ; i < ARRAY_SIZE(tx51_leds) ; i++) - led_gpio_register(&tx51_leds[i]); -} - -static int tx51_devices_init(void) -{ -#ifdef CONFIG_MCI_IMX_ESDHC - imx51_add_mmc0(NULL); - imx51_add_mmc1(NULL); -#endif - - imx51_add_nand(&nand_info); - - spi_register_board_info(mx51_tx51_spi_board_info, - ARRAY_SIZE(mx51_tx51_spi_board_info)); - imx51_add_spi0(&tx51_spi_0_data); - - imx51_iim_register_fec_ethaddr(); - tx51_fec_init(); - imx51_add_fec(&fec_info); - - tx51_leds_init(); - - //Linux Parameters - armlinux_set_architecture(MACH_TYPE_TX51); - - return 0; -} -device_initcall(tx51_devices_init); - -static int tx51_part_init(void) -{ - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - return 0; -} -late_initcall(tx51_part_init); - -static int tx51_console_init(void) -{ - imx51_init_lowlevel(800); - mxc_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads)); - - barebox_set_model("Ka-Ro TX51"); - barebox_set_hostname("tx51"); - - imx51_add_uart0(); - - return 0; -} -console_initcall(tx51_console_init); diff --git a/arch/arm/boards/karo-tx53/Makefile b/arch/arm/boards/karo-tx53/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/karo-tx53/Makefile +++ b/arch/arm/boards/karo-tx53/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c index 9f1485ad0b..e00378746c 100644 --- a/arch/arm/boards/karo-tx53/board.c +++ b/arch/arm/boards/karo-tx53/board.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2012 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Sascha Hauer, Pengutronix + #include <common.h> #include <bootsource.h> #include <environment.h> @@ -21,21 +10,19 @@ #include <init.h> #include <nand.h> #include <net.h> -#include <partition.h> #include <linux/sizes.h> #include <gpio.h> #include <mci.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> -#include <mach/imx53-regs.h> -#include <mach/iomux-mx53.h> -#include <mach/devices-imx53.h> -#include <mach/generic.h> -#include <mach/imx-nand.h> -#include <mach/iim.h> -#include <mach/imx5.h> -#include <mach/bbu.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/iomux-mx53.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx-nand.h> +#include <mach/imx/iim.h> +#include <mach/imx/imx5.h> +#include <mach/imx/bbu.h> #include <asm/armlinux.h> #include <io.h> diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg index d5e6454b88..158233cc86 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fd406c 0xffffffff wm 32 0x53fd4070 0xffffffff diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg index 6962abd5e6..d7da89beef 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8004 0x00194005 /* set LDO to 1.3V */ diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg index 2b47d63bd4..d516da3770 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fd4068 0xffcc0fff wm 32 0x53fd406c 0x000fffc3 wm 32 0x53fd4070 0x0f3c0000 diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c index 230f60ebd9..914ef69de9 100644 --- a/arch/arm/boards/karo-tx53/lowlevel.c +++ b/arch/arm/boards/karo-tx53/lowlevel.c @@ -1,11 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx5.h> -#include <mach/imx53-regs.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/cache.h> extern char __dtb_imx53_tx53_xx30_start[]; diff --git a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg index 7e244edfd3..bd869ec29e 100644 --- a/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg +++ b/arch/arm/boards/karo-tx6x/1600mhz_4x128mx16.imxcfg @@ -1,12 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* MDMISC mirroring interleaved (row/bank/col) */ wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63 @@ -34,7 +36,7 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000 wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e @@ -62,11 +64,11 @@ wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x80000000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000 wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000 -check 32 until_all_bits_set MX6_MMDC_P0_MPDGCTRL0 0x10001000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 @@ -81,16 +83,16 @@ wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 @@ -98,4 +100,4 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00001006 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P1_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/Makefile b/arch/arm/boards/karo-tx6x/Makefile index 51b7c2d449..bfd7eed20a 100644 --- a/arch/arm/boards/karo-tx6x/Makefile +++ b/arch/arm/boards/karo-tx6x/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o obj-y += pmic-ltc3676.o pmic-rn5t567.o pmic-rn5t618.o diff --git a/arch/arm/boards/karo-tx6x/board.c b/arch/arm/boards/karo-tx6x/board.c index 54b1e248f4..f964ddefd1 100644 --- a/arch/arm/boards/karo-tx6x/board.c +++ b/arch/arm/boards/karo-tx6x/board.c @@ -1,19 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2014 Steffen Trumtrar, Pengutronix * - * * with the PMIC init code taken from u-boot * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #define pr_fmt(fmt) "Karo-tx6: " fmt @@ -25,8 +16,8 @@ #include <linux/clk.h> #include <linux/kernel.h> #include <environment.h> -#include <mach/bbu.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> #include <mfd/imx6q-iomuxc-gpr.h> #include "pmic.h" @@ -121,12 +112,12 @@ static int tx6x_devices_init(void) if (sbmr1 & (1 << 7)) { imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); of_device_enable_and_register_by_name("environment-nand"); - of_device_enable_and_register_by_name("gpmi-nand@00112000"); + of_device_enable_and_register_by_alias("nand"); } else { imx6_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc3.boot0", BBU_HANDLER_FLAG_DEFAULT); of_device_enable_and_register_by_name("environment-emmc"); - of_device_enable_and_register_by_name("usdhc@0219c000"); + of_device_enable_and_register_by_alias("mmc3"); } diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg index b7a914fba5..3d15238c20 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> #include "ram-base.imxcfg" #include "1600mhz_4x128mx16.imxcfg" diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg index 3f6578e19c..bfc9a80a3e 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 0x020e0158 0x00000016 wm 32 0x020e0174 0x00000011 @@ -92,11 +94,10 @@ wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x83190000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333 wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8a63 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -117,7 +118,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -126,14 +127,14 @@ wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x0002556d wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg index 165b69fb19..b05c4a186b 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 0x020e00a4 0x00000016 wm 32 0x020e00c4 0x00000011 @@ -119,11 +121,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x831a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x545a79a4 wm 32 MX6_MMDC_P0_MDCFG1 0xff538e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00dd @@ -145,7 +147,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -159,19 +161,19 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index fc00de957c..bbb9e01022 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -1,9 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 0x020e00a4 0x00000016 wm 32 0x020e00c4 0x00000011 @@ -128,11 +130,11 @@ wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 wm 32 MX6_MMDC_P0_MDMISC 0x00000742 -check 32 until_all_bits_set MX6_MMDC_P0_MDMISC 0x00000002 +check 32 until_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 -check 32 until_any_bit_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000 wm 32 MX6_MMDC_P0_MDCTL 0x841a0000 -check 32 until_any_bit_set MX6_MMDC_P0_MDMISC 0x40000000 +check 32 until_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000 wm 32 MX6_MMDC_P0_MDCFG0 0x898f78f4 wm 32 MX6_MMDC_P0_MDCFG1 0xff328e64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db @@ -155,7 +157,7 @@ wm 32 MX6_MMDC_P0_MAPSR 0x00000001 wm 32 MX6_MMDC_P0_MDSCR 0x04008010 wm 32 MX6_MMDC_P0_MDSCR 0x04008040 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001 -check 32 until_all_bits_set MX6_MMDC_P0_MPZQHWCTRL 0x00010000 +check 32 until_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1380000 wm 32 MX6_MMDC_P0_MDSCR 0x00048033 wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 @@ -169,18 +171,18 @@ wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030 wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f -check 32 until_all_bits_set MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x04008050 wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030 -check 32 until_all_bits_set MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f +check 32 until_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f wm 32 MX6_MMDC_P0_MDSCR 0x00008033 wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b wm 32 MX6_MMDC_P0_MDREF 0x00001800 wm 32 MX6_MMDC_P0_MAPSR 0x00001000 wm 32 MX6_MMDC_P0_MDPDC 0x00025576 wm 32 MX6_MMDC_P0_MDSCR 0x00000000 -check 32 until_all_bits_set MX6_MMDC_P0_MDSCR 0x00004000 +check 32 until_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c index f0ddac284c..082307626b 100644 --- a/arch/arm/boards/karo-tx6x/lowlevel.c +++ b/arch/arm/boards/karo-tx6x/lowlevel.c @@ -1,24 +1,14 @@ -/* - * Copyright (C) 2014 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Steffen Trumtrar, Pengutronix #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <image-metadata.h> -#include <mach/generic.h> -#include <mach/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/esdctl.h> #include <linux/sizes.h> static inline void setup_uart(void) diff --git a/arch/arm/boards/karo-tx6x/pmic-ltc3676.c b/arch/arm/boards/karo-tx6x/pmic-ltc3676.c index 0cddb929fc..4e96fdeca7 100644 --- a/arch/arm/boards/karo-tx6x/pmic-ltc3676.c +++ b/arch/arm/boards/karo-tx6x/pmic-ltc3676.c @@ -1,19 +1,5 @@ -/* - * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lothar Waßmann <LW@KARO-electronics.de> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/karo-tx6x/pmic-rn5t567.c b/arch/arm/boards/karo-tx6x/pmic-rn5t567.c index 5397592c3c..fefb1f74fe 100644 --- a/arch/arm/boards/karo-tx6x/pmic-rn5t567.c +++ b/arch/arm/boards/karo-tx6x/pmic-rn5t567.c @@ -1,19 +1,5 @@ -/* - * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lothar Waßmann <LW@KARO-electronics.de> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/karo-tx6x/pmic-rn5t618.c b/arch/arm/boards/karo-tx6x/pmic-rn5t618.c index d5806d27ff..4154ed23ad 100644 --- a/arch/arm/boards/karo-tx6x/pmic-rn5t618.c +++ b/arch/arm/boards/karo-tx6x/pmic-rn5t618.c @@ -1,19 +1,5 @@ -/* - * Copyright (C) 2014 Lothar Waßmann <LW@KARO-electronics.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lothar Waßmann <LW@KARO-electronics.de> #include <common.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/karo-tx6x/pmic.h b/arch/arm/boards/karo-tx6x/pmic.h index 2427a52e50..5e5616e8c7 100644 --- a/arch/arm/boards/karo-tx6x/pmic.h +++ b/arch/arm/boards/karo-tx6x/pmic.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #include <i2c/i2c.h> diff --git a/arch/arm/boards/karo-tx6x/ram-base.imxcfg b/arch/arm/boards/karo-tx6x/ram-base.imxcfg index e912fb0f2b..9f15806b55 100644 --- a/arch/arm/boards/karo-tx6x/ram-base.imxcfg +++ b/arch/arm/boards/karo-tx6x/ram-base.imxcfg @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + wm 32 MX6_IOM_DRAM_DQM0 0x00020030 wm 32 MX6_IOM_DRAM_DQM1 0x00020030 wm 32 MX6_IOM_DRAM_DQM2 0x00020030 diff --git a/arch/arm/boards/kindle-mx50/Makefile b/arch/arm/boards/kindle-mx50/Makefile index 2cc614a878..14cf83793d 100644 --- a/arch/arm/boards/kindle-mx50/Makefile +++ b/arch/arm/boards/kindle-mx50/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-kindle-mx50 diff --git a/arch/arm/boards/kindle-mx50/board.c b/arch/arm/boards/kindle-mx50/board.c index bfcb9b83be..a5c81ac8e7 100644 --- a/arch/arm/boards/kindle-mx50/board.c +++ b/arch/arm/boards/kindle-mx50/board.c @@ -1,18 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2017 Alexander Kurz <akurz@blala.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2017 Alexander Kurz <akurz@blala.de> #include <common.h> #include <envfs.h> @@ -22,17 +10,16 @@ #include <driver.h> #include <param.h> #include <magicvar.h> -#include <partition.h> #include <libfile.h> #include <globalvar.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <linux/sizes.h> -#include <usb/fsl_usb2.h> -#include <mach/generic.h> -#include <mach/imx50-regs.h> -#include <mach/imx5.h> -#include <mach/revision.h> +#include <linux/usb/fsl_usb2.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx50-regs.h> +#include <mach/imx/imx5.h> +#include <mach/imx/revision.h> /* 16 byte id for serial number */ #define ATAG_SERIAL16 0x5441000a @@ -72,9 +59,9 @@ static const char *get_env_16char_tag(const char *tag) return value; } -BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, +BAREBOX_MAGICVAR(global.board.serial16, "Pass the kindle Serial as vendor-specific ATAG to linux"); -BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, +BAREBOX_MAGICVAR(global.board.revision16, "Pass the kindle BoardId as vendor-specific ATAG to linux"); /* The Kindle Kernel expects two custom ATAGs, ATAG_REVISION16 describing @@ -96,10 +83,9 @@ static char *mac; static void kindle_rev_init(void) { int ret; - size_t size; void *buf; const char userdata[] = "/dev/mmc2.boot0.userdata"; - ret = read_file_2(userdata, &size, &buf, 128); + ret = read_file_2(userdata, NULL, &buf, 128); if (ret && ret != -EFBIG) { pr_err("Could not read board info from %s\n", userdata); return; @@ -154,7 +140,7 @@ mem_initcall(kindle_mx50_mem_init); static int kindle_mx50_devices_init(void) { - struct device_d *dev; + struct device *dev; if (!is_mx50_kindle()) return 0; diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg index fae10423c5..5f1f8ef6b0 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + # DCD i.MX50 SoC setup using 256MiB LPDDR1 # Copyright (C) 2017 Alexander Kurz <akurz@blala.de> # @@ -7,7 +9,7 @@ soc imx50 loadaddr 0x70020000 -dcdofs 0x400 +ivtofs 0x400 # Switch pll1_sw_clk to step_clk wm 32 0x53fd400c 0x00000004 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg index 94436a7b54..520e61be58 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# # DCD i.MX50 SoC setup using 256MiB LPDDR2 # Copyright (C) 2017 Alexander Kurz <akurz@blala.de> # @@ -8,7 +10,7 @@ soc imx50 loadaddr 0x70020000 -dcdofs 0x400 +ivtofs 0x400 # Switch pll1_sw_clk to step_clk wm 32 0x53fd400c 0x00000004 diff --git a/arch/arm/boards/kindle-mx50/lowlevel.c b/arch/arm/boards/kindle-mx50/lowlevel.c index 992d1fd1a8..61d2b037fe 100644 --- a/arch/arm/boards/kindle-mx50/lowlevel.c +++ b/arch/arm/boards/kindle-mx50/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -6,8 +8,8 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx50-regs.h> -#include <mach/generic.h> +#include <mach/imx/imx50-regs.h> +#include <mach/imx/generic.h> extern char __dtb_imx50_kindle_d01100_start[]; extern char __dtb_imx50_kindle_d01200_start[]; diff --git a/arch/arm/boards/kindle3/Makefile b/arch/arm/boards/kindle3/Makefile deleted file mode 100644 index 86c746240e..0000000000 --- a/arch/arm/boards/kindle3/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += kindle3.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/kindle3/env/boot/mmc_kernel b/arch/arm/boards/kindle3/env/boot/mmc_kernel deleted file mode 100644 index c6145b85ac..0000000000 --- a/arch/arm/boards/kindle3/env/boot/mmc_kernel +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh -# Boot the Amazon factory-shipped kernel uimage stored on -# the eMMC at MOVINAND_OFFSET_KERNEL=266240. - -global linux.bootargs.dyn.root="root=/dev/mmcblk0p1 ro" - -bootm -c -a 0x80008000 /dev/disk0.kernel diff --git a/arch/arm/boards/kindle3/env/init/serials b/arch/arm/boards/kindle3/env/init/serials deleted file mode 100644 index 76580aeece..0000000000 --- a/arch/arm/boards/kindle3/env/init/serials +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh - -global board.serial16 -global board.revision16 - -# 16-byte alphanumeric containing the serial number -# SN is the first 16 bytes before the bootloader -if test -b /dev/disk0.serial; then - if memcpy -s /dev/disk0.serial -d tmp_serial16 -b 0 0 16; then - readf tmp_serial16 global.board.serial16 - fi -fi -[ -f tmp_serial16 ] && rm tmp_serial16 - -# 16-byte alphanumeric containing the board revision -if test -b /dev/disk0.imx_header; then - if memcpy -s /dev/disk0.imx_header -d tmp_revision16 -b 2032 0 16; then - readf tmp_revision16 global.board.revision16 - fi -fi -[ -f tmp_revision16 ] && rm tmp_revision16 diff --git a/arch/arm/boards/kindle3/env/init/usbconsole b/arch/arm/boards/kindle3/env/init/usbconsole deleted file mode 100644 index 87a8f9bf8c..0000000000 --- a/arch/arm/boards/kindle3/env/init/usbconsole +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -# Fiveway device select key activates usbserial access for 60s -echo -if gpio_get_value 63; then - usbserial - global.autoboot_timeout=60 -fi diff --git a/arch/arm/boards/kindle3/env/nv/autoboot_timeout b/arch/arm/boards/kindle3/env/nv/autoboot_timeout deleted file mode 100644 index 00750edc07..0000000000 --- a/arch/arm/boards/kindle3/env/nv/autoboot_timeout +++ /dev/null @@ -1 +0,0 @@ -3 diff --git a/arch/arm/boards/kindle3/env/nv/boot.default b/arch/arm/boards/kindle3/env/nv/boot.default deleted file mode 100644 index 3118b7af45..0000000000 --- a/arch/arm/boards/kindle3/env/nv/boot.default +++ /dev/null @@ -1 +0,0 @@ -mmc_kernel diff --git a/arch/arm/boards/kindle3/env/nv/linux.bootargs.base b/arch/arm/boards/kindle3/env/nv/linux.bootargs.base deleted file mode 100644 index 3a940d88fa..0000000000 --- a/arch/arm/boards/kindle3/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -mem=256M ip=none diff --git a/arch/arm/boards/kindle3/env/nv/linux.bootargs.console b/arch/arm/boards/kindle3/env/nv/linux.bootargs.console deleted file mode 100644 index d775310b40..0000000000 --- a/arch/arm/boards/kindle3/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttymxc0,115200 diff --git a/arch/arm/boards/kindle3/env/nv/linux.bootargs.lpj b/arch/arm/boards/kindle3/env/nv/linux.bootargs.lpj deleted file mode 100644 index aa3ba59e55..0000000000 --- a/arch/arm/boards/kindle3/env/nv/linux.bootargs.lpj +++ /dev/null @@ -1 +0,0 @@ -lpj=2555904 diff --git a/arch/arm/boards/kindle3/flash-header.imxcfg b/arch/arm/boards/kindle3/flash-header.imxcfg deleted file mode 100644 index cb56acf9cd..0000000000 --- a/arch/arm/boards/kindle3/flash-header.imxcfg +++ /dev/null @@ -1,24 +0,0 @@ -soc imx35 -loadaddr 0x87eff400 -dcdofs 0x400 - -wm 32 0x53f80004 0x00821000 -wm 32 0x53f80004 0x00821000 -wm 32 0xb8001010 0x00000002 -wm 32 0xb8001010 0x00000004 -wm 32 0xb8001004 0x0019672f -wm 32 0xb8001000 0x93100000 -wm 8 0x80000400 0xda -wm 32 0xb8001000 0xa3100000 -wm 32 0x80000000 0x12344321 -wm 32 0x80000000 0x12344321 -wm 32 0xb8001000 0xb3100000 -wm 8 0x80000033 0xda -wm 8 0x82000000 0xff -wm 32 0xb8001000 0x83226080 -wm 32 0xb8001010 0x0000000c -wm 32 0x80000000 0xdeadbeef -wm 32 0xb8001030 0x00e78000 -wm 32 0x43fac004 0x00000004 -wm 32 0x43fac328 0x00002100 -wm 32 0x43fac7d0 0x00000000 diff --git a/arch/arm/boards/kindle3/kindle3.c b/arch/arm/boards/kindle3/kindle3.c deleted file mode 100644 index 1d966ff55a..0000000000 --- a/arch/arm/boards/kindle3/kindle3.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2016 Alexander Kurz <akurz@blala.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Board support for the Amazon Kindle 3rd generation - */ - -#include <common.h> -#include <command.h> -#include <driver.h> -#include <init.h> -#include <bootsource.h> -#include <io.h> -#include <environment.h> -#include <generated/mach-types.h> -#include <asm/armlinux.h> -#include <asm/mmu.h> -#include <asm/setup.h> -#include <mach/imx35-regs.h> -#include <mach/imx-pll.h> -#include <mach/iomux-mx35.h> -#include <mach/devices-imx35.h> -#include <mach/generic.h> -#include <usb/fsl_usb2.h> -#include <mach/usb.h> -#include <mach/spi.h> -#include <spi/spi.h> -#include <magicvar.h> - -/* 16 byte id for serial number */ -#define ATAG_SERIAL16 0x5441000a -/* 16 byte id for a board revision */ -#define ATAG_REVISION16 0x5441000b - -struct char16_tag { - char data[16]; -}; - -static struct tag *setup_16char_tag(struct tag *params, uint32_t tag, - const char *value) -{ - struct char16_tag *target; - target = ((void *) params) + sizeof(struct tag_header); - params->hdr.tag = tag; - params->hdr.size = tag_size(char16_tag); - memcpy(target->data, value, sizeof target->data); - return tag_next(params); -} - -static const char *get_env_16char_tag(const char *tag) -{ - static const char *default16 = "0000000000000000"; - const char *value; - value = getenv(tag); - if (!value) { - printf("env var %s not found, using default\n", tag); - return default16; - } - if (strlen(value) != 16) { - printf("env var %s: expecting 16 characters, using default\n", - tag); - return default16; - } - printf("%s: %s\n", tag, value); - return value; -} - -BAREBOX_MAGICVAR_NAMED(global_atags_serial16, global.board.serial16, - "Pass the kindle Serial as vendor-specific ATAG to linux"); -BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, - "Pass the kindle BoardId as vendor-specific ATAG to linux"); - -/* The Kindle3 Kernel expects two custom ATAGs, ATAG_REVISION16 describing - * the board and ATAG_SERIAL16 to identify the individual device. - */ -static struct tag *kindle3_append_atags(struct tag *params) -{ - params = setup_16char_tag(params, ATAG_SERIAL16, - get_env_16char_tag("global.board.serial16")); - params = setup_16char_tag(params, ATAG_REVISION16, - get_env_16char_tag("global.board.revision16")); - return params; -} - -static struct fsl_usb2_platform_data kindle3_usb_info = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -/* SPI master devices. */ -static int kindle3_spi0_internal_chipselect[] = { - IMX_GPIO_NR(1, 18), -}; - -static struct spi_imx_master kindle3_spi0_info = { - .chipselect = kindle3_spi0_internal_chipselect, - .num_chipselect = ARRAY_SIZE(kindle3_spi0_internal_chipselect), -}; - -static const struct spi_board_info kindle3_spi_board_info[] = { - { - .name = "mc13892", - .bus_num = 0, - .chip_select = 0, - .mode = SPI_CS_HIGH, - }, -}; - -static int kindle3_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(kindle3_mmu_init); - -static int kindle3_devices_init(void) -{ - imx35_add_mmc0(NULL); - - if (IS_ENABLED(CONFIG_USB_GADGET)) { - unsigned int tmp; - /* Workaround ENGcm09152 */ - tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608); - writel(tmp | (1 << 23), MX35_USB_OTG_BASE_ADDR + 0x608); - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, - MX35_USB_OTG_BASE_ADDR, 0x200, - IORESOURCE_MEM, &kindle3_usb_info); - } - - /* The kindle3 related linux patch published by amazon bluntly - * renamed MACH_MX35_3DS to MACH_MX35_LUIGI - */ - armlinux_set_architecture(MACH_TYPE_MX35_3DS); - - /* Compatibility ATAGs for original kernel */ - armlinux_set_atag_appender(kindle3_append_atags); - return 0; -} -device_initcall(kindle3_devices_init); - -#define FIVEWAY_PAD_CTL (PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS) -static iomux_v3_cfg_t kindle3_pads[] = { - /* UART1 */ - MX35_PAD_RXD1__UART1_RXD_MUX, - MX35_PAD_TXD1__UART1_TXD_MUX, - - /* eMMC */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - - /* USB */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - - /* I2C 1+2 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - MX35_PAD_I2C2_CLK__I2C2_SCL, - MX35_PAD_I2C2_DAT__I2C2_SDA, - - /* SPI */ - MX35_PAD_CSPI1_SS0__GPIO1_18, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY, - - /* fiveway device: up, down, left, right, select */ - IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, FIVEWAY_PAD_CTL), - IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, FIVEWAY_PAD_CTL), - IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, FIVEWAY_PAD_CTL), - IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, FIVEWAY_PAD_CTL), - IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, FIVEWAY_PAD_CTL), - - /* Volume keys: up, down */ - MX35_PAD_SCKR__GPIO1_4, - MX35_PAD_FSR__GPIO1_5, - -}; - -static int kindle3_part_init(void) -{ - devfs_add_partition("disk0", SZ_1K, 2 * SZ_1K, - DEVFS_PARTITION_FIXED, "disk0.imx_header"); - devfs_add_partition("disk0", 4 * SZ_1K, (192 - 1) * SZ_1K, - DEVFS_PARTITION_FIXED, "disk0.self"); - devfs_add_partition("disk0", (192 + 3) * SZ_1K, SZ_64K, - DEVFS_PARTITION_FIXED, "env0"); - devfs_add_partition("disk0", (256 + 3) * SZ_1K, SZ_1K, - DEVFS_PARTITION_FIXED, "disk0.serial"); - devfs_add_partition("disk0", (256 + 4) * SZ_1K, 3407872, - DEVFS_PARTITION_FIXED, "disk0.kernel"); - devfs_add_partition("disk0", 3674112, SZ_256K, - DEVFS_PARTITION_FIXED, "disk0.waveform"); - return 0; -} - -late_initcall(kindle3_part_init); - -static int imx35_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(kindle3_pads, - ARRAY_SIZE(kindle3_pads)); - - barebox_set_model("Kindle3"); - barebox_set_hostname("kindle3"); - - imx35_add_uart0(); - - spi_register_board_info(kindle3_spi_board_info, - ARRAY_SIZE(kindle3_spi_board_info)); - imx35_add_spi0(&kindle3_spi0_info); - - imx35_add_i2c0(NULL); - imx35_add_i2c1(NULL); - return 0; -} -console_initcall(imx35_console_init); - -static int kindle3_core_setup(void) -{ - u32 tmp; - - /* AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - */ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - writel(0x40, MX35_M3IF_BASE_ADDR); - - return 0; -} - -core_initcall(kindle3_core_setup); diff --git a/arch/arm/boards/kindle3/lowlevel.c b/arch/arm/boards/kindle3/lowlevel.c deleted file mode 100644 index 19b95fc376..0000000000 --- a/arch/arm/boards/kindle3/lowlevel.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2016 Alexander Kurz <akurz@blala.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <mach/imx35-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/cache-l2x0.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/sections.h> -#include <asm-generic/memory_layout.h> -#include <asm/system.h> - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - uint32_t r, s; - unsigned long ccm_base = MX35_CCM_BASE_ADDR; - register uint32_t loops = 0x20000; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE); - - r = get_cr(); - r |= CR_Z; /* Flow prediction (Z) */ - r |= CR_U; /* unaligned accesses */ - r |= CR_FI; /* Low Int Latency */ - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(s)); - s |= 0x7; - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); - - set_cr(r); - - r = 0; - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * Branch predicition is now enabled. Flush the BTAC to ensure a valid - * starting point. Don't flush BTAC while it is disabled to avoid - * ARM1136 erratum 408023. - */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); - - /* invalidate I cache and D cache */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); - - /* invalidate TLBs */ - __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); - - /* Drain the write buffer */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); - - /* Also setup the Peripheral Port Remap register inside the core */ - r = 0x40000015; /* start from AIPS 2GB region */ - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * End of ARM1136 init - */ - - writel(0x003F4208, ccm_base + MX35_CCM_CCMR); - - /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - - writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); - writel(0x00001000, ccm_base + MX35_CCM_PDR0); - - r = readl(ccm_base + MX35_CCM_CGR0); - r |= 0x3 << MX35_CCM_CGR0_CSPI1_SHIFT; - r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; - r |= 0x3 << MX35_CCM_CGR0_ESDHC1_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR0); - - r = readl(ccm_base + MX35_CCM_CGR1); - r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_I2C2_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_GPIO1_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_GPIO2_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR1); - - r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - r |= 0x1000; - writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0x90000000) - goto out; - - /* Init Mobile DDR */ - writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - /* ESD_MISC: Enable DDR SDRAM */ - writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); - - writel(0x0019672f, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - /* ESD_ESDCTL0 : select Prechare-All mode */ - writel(0x93220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); - /* ESD_ESDCTL0: Auto Refresh command */ - writel(0xA3220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX35_CSD0_BASE_ADDR); - writeb(0xda, MX35_CSD0_BASE_ADDR); - /* ESD_ESDCTL0: Load Mode Register */ - writel(0xB3220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); - writeb(0xff, MX35_CSD0_BASE_ADDR + 0x2000000); - /* ESD_ESDCTL0: enable Auto-Refresh */ - writel(0x83228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - writel(0x0000000c, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0xdeadbeef, MX35_CSD0_BASE_ADDR); - writel(0x00e78000, MX35_CSD0_BASE_ADDR + 0x1030); - -out: - imx35_barebox_entry(NULL); -} diff --git a/arch/arm/boards/kontron-samx6i/Makefile b/arch/arm/boards/kontron-samx6i/Makefile index 816962241a..d753ff5f18 100644 --- a/arch/arm/boards/kontron-samx6i/Makefile +++ b/arch/arm/boards/kontron-samx6i/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o mem.o lwl-y += lowlevel.o mem.o diff --git a/arch/arm/boards/kontron-samx6i/board.c b/arch/arm/boards/kontron-samx6i/board.c index b4b0eac824..376548f549 100644 --- a/arch/arm/boards/kontron-samx6i/board.c +++ b/arch/arm/boards/kontron-samx6i/board.c @@ -18,8 +18,8 @@ #include <common.h> #include <init.h> #include <of.h> -#include <mach/bbu.h> -#include <mach/esdctl.h> +#include <mach/imx/bbu.h> +#include <mach/imx/esdctl.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg index 9906617083..1ff4caccfa 100644 --- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e0774 0x000c0000 wm 32 0x020e0754 0x00000000 diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg index 7e6ffd7983..a8cc0d512b 100644 --- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e05a8 0x00000030 wm 32 0x020e05b0 0x00000030 diff --git a/arch/arm/boards/kontron-samx6i/lowlevel.c b/arch/arm/boards/kontron-samx6i/lowlevel.c index afb7372323..59694e72f9 100644 --- a/arch/arm/boards/kontron-samx6i/lowlevel.c +++ b/arch/arm/boards/kontron-samx6i/lowlevel.c @@ -10,6 +10,7 @@ */ #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <io.h> #include <asm/barebox-arm-head.h> @@ -17,8 +18,8 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6.h> -#include <mach/esdctl.h> +#include <mach/imx/imx6.h> +#include <mach/imx/esdctl.h> #include "mem.h" diff --git a/arch/arm/boards/kontron-samx6i/mem.c b/arch/arm/boards/kontron-samx6i/mem.c index 3b9fbd464a..19e2ac2dd8 100644 --- a/arch/arm/boards/kontron-samx6i/mem.c +++ b/arch/arm/boards/kontron-samx6i/mem.c @@ -11,13 +11,12 @@ #include <linux/sizes.h> #include <common.h> -#include <mach/iomux-mx6.h> -#include <mach/imx-gpio.h> -#include <mach/imx6.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/imx-gpio.h> +#include <mach/imx/imx6.h> #include "mem.h" -#define PCBVERSION_PIN IMX_GPIO_NR(2, 2) #define PCBID0_PIN IMX_GPIO_NR(6, 7) #define PCBID1_PIN IMX_GPIO_NR(6, 9) @@ -25,62 +24,47 @@ IOMUX_PAD(0x0658, 0x0270, 5, 0x0000, 0, 0) #define MX6S_PAD_NANDF_WP_B__GPIO_6_9 \ IOMUX_PAD(0x0690, 0x02A8, 5, 0x0000, 0, 0) -#define MX6S_PAD_NANDF_D2__GPIO_2_2 \ - IOMUX_PAD(0x028c, 0x0674, 5, 0x0000, 0, 0) resource_size_t samx6i_get_size(void) { resource_size_t size = 0; - int ver, id0, id1; + int id0, id1; int cpu_type = __imx6_cpu_type(); void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); void __iomem *gpio6 = IOMEM(MX6_GPIO6_BASE_ADDR); - void __iomem *gpio2 = IOMEM(MX6_GPIO2_BASE_ADDR); if (cpu_type == IMX6_CPUTYPE_IMX6D || - cpu_type == IMX6_CPUTYPE_IMX6Q) { + cpu_type == IMX6_CPUTYPE_IMX6Q) { imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_CLE__GPIO_6_7); imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_WP_B__GPIO_6_9); - imx_setup_pad(iomuxbase, MX6Q_PAD_NANDF_D2__GPIO_2_2); } else if (cpu_type == IMX6_CPUTYPE_IMX6S || - cpu_type == IMX6_CPUTYPE_IMX6DL) { + cpu_type == IMX6_CPUTYPE_IMX6DL) { imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_CLE__GPIO_6_7); imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_WP_B__GPIO_6_9); - imx_setup_pad(iomuxbase, MX6S_PAD_NANDF_D2__GPIO_2_2); }; - imx6_gpio_direction_input(gpio6, 6); + imx6_gpio_direction_input(gpio6, 7); imx6_gpio_direction_input(gpio6, 9); - imx6_gpio_direction_input(gpio2, 2); - ver = imx6_gpio_val(gpio2, 2); id0 = imx6_gpio_val(gpio6, 7); id1 = imx6_gpio_val(gpio6, 9); - if (cpu_type == IMX6_CPUTYPE_IMX6D || - cpu_type == IMX6_CPUTYPE_IMX6Q) { - if (ver) - size = SZ_1G; - else if (id0 && id1) - size = SZ_2G; - else if (id0) - size = SZ_2G; - else if (id1) - size = SZ_1G; - else - size = SZ_512M; - } else if (cpu_type == IMX6_CPUTYPE_IMX6S || - cpu_type == IMX6_CPUTYPE_IMX6DL) { - if (ver) - size = SZ_512M; - if (id0 && id1) - size = SZ_2G; - else if (id0) - size = SZ_1G; - else if (id1) - size = SZ_512M; + /* Solo/DualLite module sizes */ + if (id0 && id1) + size = SZ_2G; + else if (id0) + size = SZ_1G; + else if (id1) + size = SZ_512M; + else + size = SZ_256M; + + /* Dual/Quad modules always have twice the size */ + if (cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) { + if (size == SZ_2G) + size = 0xf0000000; /* 4G on a 32bit system */ else - size = SZ_128M; + size *= 2; } return size; diff --git a/arch/arm/boards/kontron-samx6i/mem.h b/arch/arm/boards/kontron-samx6i/mem.h index 57e3c0cecc..25faf38490 100644 --- a/arch/arm/boards/kontron-samx6i/mem.h +++ b/arch/arm/boards/kontron-samx6i/mem.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __BOARD_KONTRON_SAMX6I_MEM_H #define __BOARD_KONTRON_SAMX6I_MEM_H diff --git a/arch/arm/boards/lenovo-ix4-300d/Makefile b/arch/arm/boards/lenovo-ix4-300d/Makefile index b08c4a93ca..458f520900 100644 --- a/arch/arm/boards/lenovo-ix4-300d/Makefile +++ b/arch/arm/boards/lenovo-ix4-300d/Makefile @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c index 40145b5cef..d76e4af30d 100644 --- a/arch/arm/boards/lenovo-ix4-300d/lowlevel.c +++ b/arch/arm/boards/lenovo-ix4-300d/lowlevel.c @@ -1,28 +1,15 @@ -/* - * Copyright (C) 2014, 2015 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014, 2015 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> +#include <mach/mvebu/barebox-arm-head.h> #include <linux/sizes.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_armada_xp_lenovo_ix4_300d_bb_start[]; -ENTRY_FUNCTION(start_lenovo_ix4_300d, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_lenovo_ix4_300d, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/ls1021aiot/Makefile b/arch/arm/boards/ls1021aiot/Makefile new file mode 100644 index 0000000000..df69ce814b --- /dev/null +++ b/arch/arm/boards/ls1021aiot/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o +obj-y += board.o +lwl-y += start.o diff --git a/arch/arm/boards/ls1021aiot/board.c b/arch/arm/boards/ls1021aiot/board.c new file mode 100644 index 0000000000..70070a4e75 --- /dev/null +++ b/arch/arm/boards/ls1021aiot/board.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +// SPDX-FileCopyrightText: (C) Copyright 2023 Ametek Inc. +// SPDX-FileCopyrightText: 2023 Renaud Barbier <renaud.barbier@ametek.com>, + +#include <common.h> +#include <init.h> +#include <bbu.h> +#include <net.h> +#include <crc.h> +#include <fs.h> +#include <io.h> +#include <envfs.h> +#include <libfile.h> +#include <asm/memory.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <asm/system.h> +#include <mach/layerscape/layerscape.h> +#include <of_address.h> +#include <soc/fsl/immap_lsch2.h> + +static int iot_mem_init(void) +{ + if (!of_machine_is_compatible("fsl,ls1021a")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, 0x40000000); + + return 0; +} +mem_initcall(iot_mem_init); + +static int iot_postcore_init(void) +{ + struct ls102xa_ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR); + + if (!of_machine_is_compatible("fsl,ls1021a")) + return 0; + + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + + return 0; +} +coredevice_initcall(iot_postcore_init); diff --git a/arch/arm/boards/ls1021aiot/lowlevel.c b/arch/arm/boards/ls1021aiot/lowlevel.c new file mode 100644 index 0000000000..6bba528635 --- /dev/null +++ b/arch/arm/boards/ls1021aiot/lowlevel.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +// SPDX-FileCopyrightText: (C) Copyright 2023 Ametek Inc. +// SPDX-FileCopyrightText: 2023 Renaud Barbier <renaud.barbier@ametek.com> + +/* + * Derived from Freescale LSDK-19.09-update-311219 + */ +#include <common.h> +#include <clock.h> +#include <debug_ll.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/syscounter.h> +#include <asm/system.h> +#include <asm/cache.h> +#include <linux/sizes.h> +#include <mach/layerscape/errata.h> +#include <mach/layerscape/lowlevel.h> +#include <mach/layerscape/xload.h> +#include <mach/layerscape/layerscape.h> + +static struct fsl_ddr_controller ddrc[] = { + { + .memctl_opts.ddrtype = SDRAM_TYPE_DDR3, + .base = IOMEM(LSCH2_DDR_ADDR), + .ddr_freq = LS1021A_DDR_FREQ, + .erratum_A009942 = 1, + .chip_selects_per_ctrl = 4, + .fsl_ddr_config_reg = { + .cs[0].bnds = 0x008000bf, + .cs[0].config = 0x80014302, + .cs[0].config_2 = 0x00000000, + .cs[1].bnds = 0x00000000, + .cs[1].config = 0x00000000, + .cs[1].config_2 = 0x00000000, + .cs[2].bnds = 0x00000000, + .cs[2].config = 0x00000000, + .cs[2].config_2 = 0x00000000, + .cs[3].bnds = 0x00000000, + .cs[3].config = 0x00000000, + .cs[3].config_2 = 0x00000000, + .timing_cfg_3 = 0x010e1000, + .timing_cfg_0 = 0x50550004, + .timing_cfg_1 = 0xbcb38c56, + .timing_cfg_2 = 0x0040d120, + .ddr_sdram_cfg = 0x470c0008, + .ddr_sdram_cfg_2 = 0x00401010, + .ddr_sdram_mode = 0x00061c60, + .ddr_sdram_mode_2 = 0x00180000, + .ddr_sdram_interval = 0x18600618, + .ddr_data_init = 0xDEADBEEF, + .ddr_sdram_clk_cntl = 0x02000000, + .ddr_init_addr = 0x00000000, + .ddr_init_ext_addr = 0x00000000, + .timing_cfg_4 = 0x00000001, + .timing_cfg_5 = 0x03401400, + .ddr_zq_cntl = 0x89080600, + .ddr_wrlvl_cntl = 0x8655f605, + .ddr_wrlvl_cntl_2 = 0x05060607, + .ddr_wrlvl_cntl_3 = 0x05050505, + .ddr_sr_cntr = 0x00000000, + .ddr_sdram_rcw_1 = 0x00000000, + .ddr_sdram_rcw_2 = 0x00000000, + .ddr_sdram_rcw_3 = 0x00000000, + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x000000C0, + .dq_map_0 = 0x00000000, + .dq_map_1 = 0x00000000, + .dq_map_2 = 0x00000000, + .dq_map_3 = 0x00000000, + .debug[28] = 0x00700046, + }, + }, +}; + +extern char __dtb_fsl_ls1021a_iot_start[]; + +static noinline __noreturn void ls1021aiot_r_entry(void) +{ + unsigned long membase = LS1021A_DDR_SDRAM_BASE; + + if (get_pc() >= membase) { + barebox_arm_entry(membase, SZ_1G - SZ_64M, + __dtb_fsl_ls1021a_iot_start); + } + + ls102xa_init_lowlevel(); + ls102xa_debug_ll_init(); + + udelay(500); + putc_ll('>'); + + fsl_ddr_set_memctl_regs(&ddrc[0], 0, false); + + ls1021a_errata_post_ddr(); + + ls1021a_xload_start_image(SZ_1G, 0, 0); + + pr_err("Booting failed\n"); + + while (1) + ; +} + +void ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2); + +__noreturn void +ls1021aiot_entry(unsigned long r0, unsigned long r1, unsigned long r2) +{ + relocate_to_current_adr(); + setup_c(); + + ls1021aiot_r_entry(); +} diff --git a/arch/arm/boards/ls1021aiot/ls102xa_pbi.cfg b/arch/arm/boards/ls1021aiot/ls102xa_pbi.cfg new file mode 100644 index 0000000000..840299be8d --- /dev/null +++ b/arch/arm/boards/ls1021aiot/ls102xa_pbi.cfg @@ -0,0 +1,11 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/arch/arm/boards/ls1021aiot/ls102xa_rcw_sd_qspi.cfg b/arch/arm/boards/ls1021aiot/ls102xa_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..3b5300501d --- /dev/null +++ b/arch/arm/boards/ls1021aiot/ls102xa_rcw_sd_qspi.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +20000000 08407900 e0025a00 21046000 +00000000 00000000 00000000 20038000 +20024800 881b1340 00000000 00000000 diff --git a/arch/arm/boards/ls1021aiot/start.S b/arch/arm/boards/ls1021aiot/start.S new file mode 100644 index 0000000000..c907777ca1 --- /dev/null +++ b/arch/arm/boards/ls1021aiot/start.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +#define STACK_TOP 0x10020000 + +ENTRY_PROC(start_ls1021aiot) + ldr r3, =STACK_TOP + mov sp, r3 + b ls1021aiot_entry +ENTRY_PROC_END(start_ls1021aiot) diff --git a/arch/arm/boards/ls1028ardb/Makefile b/arch/arm/boards/ls1028ardb/Makefile new file mode 100644 index 0000000000..df60a21844 --- /dev/null +++ b/arch/arm/boards/ls1028ardb/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +lwl-y += start.o +obj-y += board.o diff --git a/arch/arm/boards/ls1028ardb/board.c b/arch/arm/boards/ls1028ardb/board.c new file mode 100644 index 0000000000..094d72e6fc --- /dev/null +++ b/arch/arm/boards/ls1028ardb/board.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <deep-probe.h> +#include <bootsource.h> +#include <driver.h> +#include <init.h> +#include <of.h> +#include <asm/memory.h> +#include <mach/layerscape/layerscape.h> +#include <mach/layerscape/bbu.h> +#include <linux/sizes.h> + +static int ls1028ardb_probe(struct device *dev) +{ + unsigned long sd_bbu_flags = 0; + unsigned long emmc_bbu_flags = 0; + + arm_add_mem_device("ram1", LS1028A_DDR_SDRAM_HIGHMEM_BASE, SZ_2G); + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 0) { + sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-sd"); + } else { + emmc_bbu_flags = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-emmc"); + } + + ls1028a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", sd_bbu_flags); + ls1028a_bbu_mmc_register_handler("emmc", "/dev/mmc1.barebox", emmc_bbu_flags); + + return 0; +} + +static const struct of_device_id ls1028a_of_match[] = { + { .compatible = "fsl,ls1028a-rdb" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(ls1028a_of_match); + +static struct driver ls1028ardb_board_driver = { + .name = "ls1028a-rdb", + .probe = ls1028ardb_probe, + .of_compatible = ls1028a_of_match, +}; +device_platform_driver(ls1028ardb_board_driver); diff --git a/arch/arm/boards/ls1028ardb/lowlevel.c b/arch/arm/boards/ls1028ardb/lowlevel.c new file mode 100644 index 0000000000..00db0b1cf8 --- /dev/null +++ b/arch/arm/boards/ls1028ardb/lowlevel.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <debug_ll.h> +#include <ddr_spd.h> +#include <image-metadata.h> +#include <platform_data/mmc-esdhc-imx.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <soc/fsl/immap_lsch2.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/syscounter.h> +#include <asm/cache.h> +#include <mach/layerscape/lowlevel.h> +#include <mach/layerscape/xload.h> +#include <mach/layerscape/errata.h> +#include <mach/layerscape/layerscape.h> +#include <linux/bitfield.h> + +static struct fsl_ddr_controller ddrc = { + .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, + .base = IOMEM(LSCH2_DDR_ADDR), + .ddr_freq = 1600000000, + .erratum_A009942 = 1, + .erratum_A009663 = 1, + .chip_selects_per_ctrl = 4, + .fsl_ddr_config_reg = { + .cs[0].bnds = 0x000000ff, + .cs[0].config = 0x80040422, + .cs[0].config_2 = 0, + .cs[1].bnds = 0, + .cs[1].config = 0, + .cs[1].config_2 = 0, + + .timing_cfg_3 = 0x01111000, + .timing_cfg_0 = 0xd0550018, + .timing_cfg_1 = 0xFAFC0C42, + .timing_cfg_2 = 0x0048c114, + .ddr_sdram_cfg = 0xe50c000c, + .ddr_sdram_cfg_2 = 0x00401110, + .ddr_sdram_mode = 0x01010230, + .ddr_sdram_mode_2 = 0x0, + + .ddr_sdram_md_cntl = 0x0600001f, + .ddr_sdram_interval = 0x18600618, + .ddr_data_init = 0xdeadbeef, + + .ddr_sdram_clk_cntl = 0x02000000, + .ddr_init_addr = 0, + .ddr_init_ext_addr = 0, + + .timing_cfg_4 = 0x00000002, + .timing_cfg_5 = 0x07401400, + .timing_cfg_6 = 0x0, + .timing_cfg_7 = 0x23300000, + + .ddr_zq_cntl = 0x8A090705, + .ddr_wrlvl_cntl = 0x86550607, + .ddr_sr_cntr = 0, + .ddr_sdram_rcw_1 = 0, + .ddr_sdram_rcw_2 = 0, + .ddr_wrlvl_cntl_2 = 0x0708080A, + .ddr_wrlvl_cntl_3 = 0x0A0B0C09, + + .ddr_sdram_mode_9 = 0x00000400, + .ddr_sdram_mode_10 = 0x04000000, + + .timing_cfg_8 = 0x06115600, + + .dq_map_0 = 0x5b65b658, + .dq_map_1 = 0xd96d8000, + .dq_map_2 = 0, + .dq_map_3 = 0x01600000, + + .ddr_cdr1 = 0x80040000, + .ddr_cdr2 = 0x000000C1 + }, +}; + +extern char __dtb_z_fsl_ls1028a_rdb_start[]; + +#define MEM_PLL_RAT GENMASK(15, 10) + +static unsigned long get_ddr_freq(void) +{ + unsigned long freq = 100000000; + u32 rcwsr1 = readl(0x1e00100); + u32 mult; + + mult = FIELD_GET(MEM_PLL_RAT, rcwsr1); + + return freq * mult; +} + +struct dram_regions_info dram_info = { + .num_dram_regions = 2, + .total_dram_size = SZ_4G, + .region = { + { + .addr = LS1028A_DDR_SDRAM_BASE, + .size = SZ_2G, + }, { + .addr = LS1028A_DDR_SDRAM_HIGHMEM_BASE, + .size = SZ_2G, + }, + }, +}; + +static noinline __noreturn void ls1028ardb_r_entry(unsigned long memsize) +{ + unsigned long membase = LS1028A_DDR_SDRAM_BASE; + + if (get_pc() >= membase) + barebox_arm_entry(membase, SZ_2G - LS1028A_TFA_RESERVED_SIZE, + __dtb_z_fsl_ls1028a_rdb_start); + + arm_cpu_lowlevel_init(); + ls1028a_init_lowlevel(); + ddrc.ddr_freq = get_ddr_freq(); + + fsl_ddr_set_memctl_regs(&ddrc, 0, true); + + ls1028a_tzc400_init(SZ_4G); + + ls1028a_errata_post_ddr(); + + ls1028a_esdhc1_start_image(&dram_info); + + hang(); +} + +void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2); + +__noreturn void ls1028ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2) +{ + ls1028a_uart_setup(IOMEM(LSCH2_NS16550_COM1)); + + relocate_to_current_adr(); + setup_c(); + + ls1028ardb_r_entry(r0); +} diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg new file mode 100644 index 0000000000..53cfb20327 --- /dev/null +++ b/arch/arm/boards/ls1028ardb/ls1028ardb_pbi.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +31e00400 18010000 +31e00404 00000000 +33400890 00800401 +33500890 00800401 +334008bc 00000001 +33400154 47474747 +33400158 47474747 +335008bc 00000001 +33500154 47474747 +33500158 47474747 +334008bc 00000000 +335008bc 00000000 diff --git a/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg new file mode 100644 index 0000000000..2183991112 --- /dev/null +++ b/arch/arm/boards/ls1028ardb/ls1028ardb_rcw_sd.cfg @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +#PBL preamble and RCW header +aa55aa55 80100000 +# RCW +34004010 00000030 00000000 00000000 +00000000 00bf0000 0030c000 00000000 +01e03150 00002580 00000000 00003496 +00000000 00000010 00000000 00000000 +00000000 00000000 00000000 00000000 +00000000 00000000 00000000 00000000 +00000000 00000000 200e705a 00000000 +bb580000 00000000 00000000 00000000 + diff --git a/arch/arm/boards/ls1028ardb/start.S b/arch/arm/boards/ls1028ardb/start.S new file mode 100644 index 0000000000..fd410b744a --- /dev/null +++ b/arch/arm/boards/ls1028ardb/start.S @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> +#include <asm/assembler64.h> + +#define STACK_TOP 0x18040000 + +ENTRY_PROC(start_ls1028ardb) + switch_el x3, 3f, 2f, 1f +3: + mov x3, #STACK_TOP + mov sp, x3 + b ls1028ardb_entry +2: +1: + mov x3, 0x90000000 + mov sp, x3 + b ls1028ardb_entry +ENTRY_PROC_END(start_ls1028ardb) diff --git a/arch/arm/boards/ls1046ardb/Makefile b/arch/arm/boards/ls1046ardb/Makefile index 03ac4ecca3..829be5327a 100644 --- a/arch/arm/boards/ls1046ardb/Makefile +++ b/arch/arm/boards/ls1046ardb/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o lwl-y += start.o diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c index 0846df9fad..ee70171ca3 100644 --- a/arch/arm/boards/ls1046ardb/board.c +++ b/arch/arm/boards/ls1046ardb/board.c @@ -2,13 +2,134 @@ #include <common.h> #include <init.h> +#include <bbu.h> +#include <net.h> +#include <crc.h> +#include <fs.h> #include <envfs.h> +#include <libfile.h> #include <asm/memory.h> #include <linux/sizes.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <asm/system.h> -#include <mach/layerscape.h> +#include <mach/layerscape/layerscape.h> +#include <mach/layerscape/bbu.h> +#include <of_address.h> +#include <linux/fsl_ifc.h> + +#define MAX_NUM_PORTS 16 +struct nxid { + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ + u8 sn[12]; /* 0x04 - 0x0F Serial Number */ + u8 errata[5]; /* 0x10 - 0x14 Errata Level */ + u8 date[6]; /* 0x15 - 0x1a Build Date */ + u8 res_0; /* 0x1b Reserved */ + u32 version; /* 0x1c - 0x1f NXID Version */ + u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */ + u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */ + u8 tempcalflags; /* 0x2a Temperature Calibration Flags */ + u8 res_1[21]; /* 0x2b - 0x3f Reserved */ + u8 mac_count; /* 0x40 Number of MAC addresses */ + u8 mac_flag; /* 0x41 MAC table flags */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */ + u8 res_2[90]; /* 0xa2 - 0xfb Reserved */ + u32 crc; /* 0xfc - 0xff CRC32 checksum */ +} __packed; + +static int nxid_is_valid(struct nxid *nxid) +{ + unsigned char id[] = { 'N', 'X', 'I', 'D' }; + int i; + + for (i = 0; i < ARRAY_SIZE(id); i++) + if (nxid->id[i] != id[i]) + return false; + return true; +} + +static struct nxid *nxp_nxid_read(const char *filename, unsigned int offset) +{ + struct nxid *nxid; + int fd, ret, i, n; + struct device_node *root; + u32 crc, crc_expected; + + nxid = xzalloc(sizeof(*nxid)); + + fd = open(filename, O_RDONLY); + if (fd < 0) { + ret = -errno; + goto out; + } + + ret = pread(fd, nxid, sizeof(*nxid), offset); + if (ret < 0) { + close(fd); + goto out; + } + + if (!nxid_is_valid(nxid)) { + ret = -ENODEV; + goto out; + } + + crc = crc32(0, nxid, 256 - 4); + crc_expected = be32_to_cpu(nxid->crc); + if (crc != crc_expected) { + pr_err("CRC mismatch (%08x != %08x)\n", crc, crc_expected); + ret = -EINVAL; + goto out; + } + + root = of_get_root_node(); + + i = n = 0; + + /* + * The MAC addresses in the nxid structure are in the order of enabled + * network interfaces. We have to find the network interfaces by their + * aliases and skip assigning MAC addresses to disabled devices. + */ + while (1) { + struct device_node *np; + char alias[sizeof("ethernetxxx")]; + + sprintf(alias, "ethernet%d", n); + + np = of_find_node_by_alias(root, alias); + if (!np) + goto out; + + n++; + if (!of_device_is_available(np)) + continue; + + of_eth_register_ethaddr(np, (char *)nxid->mac[i]); + + i++; + + if (i == nxid->mac_count) + break; + } + + ret = 0; +out: + if (ret) { + free(nxid); + nxid = ERR_PTR(ret); + } + + return nxid; +} + +static int rdb_late_init(void) +{ + nxp_nxid_read("/dev/eeprom", 256); + + return 0; +} +late_initcall(rdb_late_init); static int rdb_mem_init(void) { @@ -28,6 +149,40 @@ static int rdb_mem_init(void) } mem_initcall(rdb_mem_init); +static int rdb_nand_init(void) +{ + struct device_node *np; + void __iomem *ifc; + + np = of_find_compatible_node(NULL, NULL, "fsl,ifc"); + if (!np) + return -EINVAL; + + ifc = of_iomap(np, 0); + if (!ifc) + return -EINVAL; + + set_ifc_cspr(ifc, IFC_CS0, CSPR_PHYS_ADDR(0x7e800000) | + CSPR_PORT_SIZE_8 | CSPR_MSEL_NAND | CSPR_V); + set_ifc_csor(ifc, IFC_CS0, CSOR_NAND_ECC_ENC_EN | CSOR_NAND_ECC_DEC_EN | + CSOR_NAND_ECC_MODE_8 | + CSOR_NAND_RAL_3 | CSOR_NAND_PGS_4K | + CSOR_NAND_SPRZ_224 | CSOR_NAND_PB(64) | + CSOR_NAND_TRHZ_20); + set_ifc_amask(ifc, IFC_CS0, IFC_AMASK(64*1024)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM0, FTIM0_NAND_TCCST(0x07) | + FTIM0_NAND_TWP(0x18) | FTIM0_NAND_TWCHT(0x07) | + FTIM0_NAND_TWH(0x0a)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM1, FTIM1_NAND_TADLE(0x32) | + FTIM1_NAND_TWBE(0x39) | FTIM1_NAND_TRR(0x0e)| + FTIM1_NAND_TRP(0x18)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM2, FTIM2_NAND_TRAD(0xf) | + FTIM2_NAND_TREH(0xa) | FTIM2_NAND_TWHRE(0x1e)); + set_ifc_ftim(ifc, IFC_CS0, IFC_FTIM3, 0); + + return 0; +} + static int rdb_postcore_init(void) { if (!of_machine_is_compatible("fsl,ls1046a-rdb")) @@ -35,7 +190,10 @@ static int rdb_postcore_init(void) defaultenv_append_directory(defaultenv_ls1046ardb); - return 0; + ls1046a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + return rdb_nand_init(); } postcore_initcall(rdb_postcore_init); diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c index 0a30f05aa2..408e6017f6 100644 --- a/arch/arm/boards/ls1046ardb/lowlevel.c +++ b/arch/arm/boards/ls1046ardb/lowlevel.c @@ -5,17 +5,17 @@ #include <ddr_spd.h> #include <image-metadata.h> #include <platform_data/mmc-esdhc-imx.h> -#include <i2c/i2c-early.h> +#include <pbl/i2c.h> #include <soc/fsl/fsl_ddr_sdram.h> #include <soc/fsl/immap_lsch2.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <asm/syscounter.h> #include <asm/cache.h> -#include <mach/errata.h> -#include <mach/lowlevel.h> -#include <mach/xload.h> -#include <mach/layerscape.h> +#include <mach/layerscape/errata.h> +#include <mach/layerscape/lowlevel.h> +#include <mach/layerscape/xload.h> +#include <mach/layerscape/layerscape.h> struct board_specific_parameters { u32 n_ranks; @@ -147,7 +147,7 @@ found: popts->cpo_sample = 0x61; } -extern char __dtb_fsl_ls1046a_rdb_start[]; +extern char __dtb_z_fsl_ls1046a_rdb_start[]; static struct spd_eeprom spd_eeprom[] = { { @@ -187,7 +187,7 @@ static struct fsl_ddr_info ls1046a_info = { static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize) { unsigned long membase = LS1046A_DDR_SDRAM_BASE; - struct fsl_i2c *i2c; + struct pbl_i2c *i2c; int ret; if (get_pc() >= membase) { @@ -195,23 +195,21 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize) memsize = 0x100000000 - membase; barebox_arm_entry(membase, 0x80000000 - SZ_64M, - __dtb_fsl_ls1046a_rdb_start); + __dtb_z_fsl_ls1046a_rdb_start); } arm_cpu_lowlevel_init(); - debug_ll_init(); + ls1046a_debug_ll_init(); ls1046a_init_lowlevel(); - IMD_USED_OF(fsl_ls1046a_rdb); - i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR)); - ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom); + ret = spd_read_eeprom(i2c, 0x51, &spd_eeprom, SPD_MEMTYPE_DDR4); if (ret) { pr_err("Cannot read SPD EEPROM: %d\n", ret); goto err; } - memsize = fsl_ddr_sdram(&ls1046a_info); + memsize = fsl_ddr_sdram(&ls1046a_info, false); ls1046a_errata_post_ddr(); diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg index 5478217524..0ed997031e 100644 --- a/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #Configure Scratch register 09570600 00000000 09570604 10000000 diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg index 735d46c9f9..b9e455da9e 100644 --- a/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #QSPI clk 0957015c 40100000 #Configure Scratch register diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg index ccedf87e84..debb6479a8 100644 --- a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #PBL preamble and RCW header aa55aa55 01ee0100 # RCW diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg index 7b9be0ad3f..2167a71b7f 100644 --- a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #PBL preamble and RCW header aa55aa55 01ee0100 # RCW diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg index d3b152282f..ec18028c4b 100644 --- a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #PBL preamble and RCW header aa55aa55 01ee0100 # RCW diff --git a/arch/arm/boards/lubbock/Makefile b/arch/arm/boards/lubbock/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/lubbock/Makefile +++ b/arch/arm/boards/lubbock/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c index c2a0db7bd8..af046e110a 100644 --- a/arch/arm/boards/lubbock/board.c +++ b/arch/arm/boards/lubbock/board.c @@ -1,44 +1,28 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> #include <driver.h> #include <environment.h> #include <fs.h> #include <init.h> -#include <partition.h> #include <led.h> #include <gpio.h> #include <pwm.h> #include <linux/sizes.h> -#include <mach/devices.h> -#include <mach/mfp-pxa27x.h> -#include <mach/pxa-regs.h> -#include <mach/udc_pxa2xx.h> -#include <mach/mci_pxa2xx.h> +#include <mach/pxa/devices.h> +#include <mach/pxa/mfp-pxa27x.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/udc_pxa2xx.h> +#include <mach/pxa/mci_pxa2xx.h> #include <platform_data/eth-smc91111.h> #include <asm/armlinux.h> #include <asm/io.h> #include <asm/mmu.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #define ECOR 0x8000 #define ECOR_RESET 0x80 diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c index abf9e7a98a..ef6b544a26 100644 --- a/arch/arm/boards/lubbock/lowlevel.c +++ b/arch/arm/boards/lubbock/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> @@ -5,8 +7,8 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <linux/sizes.h> -#include <mach/pxa-regs.h> -#include <mach/regs-ost.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/regs-ost.h> /* * Memory settings diff --git a/arch/arm/boards/lxa-mc1/Makefile b/arch/arm/boards/lxa-mc1/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/lxa-mc1/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/lxa-mc1/board.c b/arch/arm/boards/lxa-mc1/board.c new file mode 100644 index 0000000000..8be265b0fc --- /dev/null +++ b/arch/arm/boards/lxa-mc1/board.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <mach/stm32mp/bbu.h> +#include <bootsource.h> +#include <deep-probe.h> +#include <of.h> + +static int of_fixup_regulator_supply_disable(struct device_node *root, void *path) +{ + struct device_node *node; + struct property *prop; + + node = of_find_node_by_path_from(root, path); + if (!node) { + pr_warn("fixup for %s failed: not found\n", (const char *)path); + return -ENOENT; + } + + if (!of_property_read_bool(node, "regulator-always-on")) + return 0; + + prop = of_find_property(node, "vin-supply", NULL); + if (prop) + of_delete_property(prop); + + return 0; +} + +static int mc1_probe(struct device *dev) +{ + struct device_node *state_node, *state_backend; + int flags; + + flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); + + flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("emmc", "/dev/mmc1.ssbl", flags); + + + if (bootsource_get_instance() == 0) { + of_device_enable_path("/chosen/environment-sd"); + state_backend = of_find_node_by_alias(NULL, "mmc0"); + } else { + of_device_enable_path("/chosen/environment-emmc"); + state_backend = of_find_node_by_alias(NULL, "mmc1"); + } + + state_node = of_find_node_by_alias(NULL, "state"); + if (state_node) + of_property_write_u32(state_node, "backend", + of_node_create_phandle(state_backend)); + + barebox_set_hostname("lxa-mc1"); + + /* The regulator is powered by the PMIC, but is always on as far as + * software is concerned. Break the reference to the PMIC, so the OS + * doesn't need to defer SDMMC/Ethernet peripherals till after the PMIC + * is up. + */ + return of_register_fixup(of_fixup_regulator_supply_disable, "/regulator_3v3"); +} + +static const struct of_device_id mc1_of_match[] = { + { .compatible = "lxa,stm32mp157c-mc1" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(mc1_of_match); + +static struct driver mc1_board_driver = { + .name = "board-lxa-mc1", + .probe = mc1_probe, + .of_compatible = mc1_of_match, +}; +device_platform_driver(mc1_board_driver); diff --git a/arch/arm/boards/lxa-mc1/lowlevel.c b/arch/arm/boards/lxa-mc1/lowlevel.c new file mode 100644 index 0000000000..86211bf9d8 --- /dev/null +++ b/arch/arm/boards/lxa-mc1/lowlevel.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/stm32mp/entry.h> +#include <debug_ll.h> + +extern char __dtb_z_stm32mp157c_lxa_mc1_start[]; + +static void setup_uart(void) +{ + /* first stage has set up the UART, so nothing to do here */ + putc_ll('>'); +} + +ENTRY_FUNCTION(start_stm32mp157c_lxa_mc1, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_z_stm32mp157c_lxa_mc1_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} diff --git a/arch/arm/boards/mainstone/Makefile b/arch/arm/boards/mainstone/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/mainstone/Makefile +++ b/arch/arm/boards/mainstone/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/mainstone/board.c b/arch/arm/boards/mainstone/board.c index 0e48e79967..979a4f3609 100644 --- a/arch/arm/boards/mainstone/board.c +++ b/arch/arm/boards/mainstone/board.c @@ -1,44 +1,28 @@ -/* - * (C) 2015 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> #include <driver.h> #include <environment.h> #include <fs.h> #include <init.h> -#include <partition.h> #include <led.h> #include <gpio.h> #include <pwm.h> #include <linux/sizes.h> -#include <mach/devices.h> -#include <mach/mfp-pxa27x.h> -#include <mach/pxa-regs.h> -#include <mach/udc_pxa2xx.h> -#include <mach/mci_pxa2xx.h> +#include <mach/pxa/devices.h> +#include <mach/pxa/mfp-pxa27x.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/udc_pxa2xx.h> +#include <mach/pxa/mci_pxa2xx.h> #include <platform_data/eth-smc91111.h> #include <asm/armlinux.h> #include <asm/io.h> #include <asm/mmu.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> static struct smc91c111_pdata smsc91x_pdata = { .word_aligned_short_writes = true, diff --git a/arch/arm/boards/mainstone/lowlevel.c b/arch/arm/boards/mainstone/lowlevel.c index 31f9d76513..29d12f7424 100644 --- a/arch/arm/boards/mainstone/lowlevel.c +++ b/arch/arm/boards/mainstone/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> @@ -5,8 +7,8 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> #include <linux/sizes.h> -#include <mach/pxa-regs.h> -#include <mach/regs-ost.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/regs-ost.h> /* * Memory settings diff --git a/arch/arm/boards/marvell-armada-xp-db/Makefile b/arch/arm/boards/marvell-armada-xp-db/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/marvell-armada-xp-db/Makefile +++ b/arch/arm/boards/marvell-armada-xp-db/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/marvell-armada-xp-db/lowlevel.c b/arch/arm/boards/marvell-armada-xp-db/lowlevel.c index 4752bbf1b4..14059fe8c5 100644 --- a/arch/arm/boards/marvell-armada-xp-db/lowlevel.c +++ b/arch/arm/boards/marvell-armada-xp-db/lowlevel.c @@ -7,13 +7,13 @@ #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> #include <io.h> extern char __dtb_armada_xp_db_bb_start[]; -ENTRY_FUNCTION(start_marvell_armada_xp_db, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_marvell_armada_xp_db, r0, r1, r2) { void *fdt; uint32_t reg; diff --git a/arch/arm/boards/marvell-armada-xp-gp/Makefile b/arch/arm/boards/marvell-armada-xp-gp/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/marvell-armada-xp-gp/Makefile +++ b/arch/arm/boards/marvell-armada-xp-gp/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/marvell-armada-xp-gp/board.c b/arch/arm/boards/marvell-armada-xp-gp/board.c deleted file mode 100644 index 9c800c5410..0000000000 --- a/arch/arm/boards/marvell-armada-xp-gp/board.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright - * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* empty */ diff --git a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c index e62627c324..ae5ad2822a 100644 --- a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c +++ b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c @@ -1,28 +1,15 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_armada_xp_gp_bb_start[]; -ENTRY_FUNCTION(start_marvell_armada_xp_gp, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_marvell_armada_xp_gp, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/meerkat96/Makefile b/arch/arm/boards/meerkat96/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/meerkat96/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/meerkat96/board.c b/arch/arm/boards/meerkat96/board.c new file mode 100644 index 0000000000..49e9c06f78 --- /dev/null +++ b/arch/arm/boards/meerkat96/board.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <of.h> +#include <deep-probe.h> + +static const struct of_device_id meerkat96_match[] = { + { .compatible = "novtech,imx7d-meerkat96" }, + { /* Sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(meerkat96_match); diff --git a/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg b/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg new file mode 100644 index 0000000000..a49b816178 --- /dev/null +++ b/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +soc imx7 +loadaddr 0x80000000 +ivtofs 0x400 + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable OCRAM EPDC */ +wm 32 0x30340004 0x4F400005 + +/* ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Memory type: DDR3 + * Manufacturer: ISSI + * Device Part Number: IS43TR16256AL-125KBL + * Clock Freq.: 533MHz + * Density per CS in Gb: 4 + * Chip Selects used: 1 + * Number of Banks: 8 + * Row address: 15 + * Column address: 10 + * Data bus width: 16 + * ROW-BANK interleave: ENABLED + * ============================================================================= + */ + +wm 32 0x30391000 0x00000002 // deassert presetn +wm 32 0x307A0000 0x01041001 // DDRC_MSTR +wm 32 0x307A0064 0x00400046 // DDRC_RFSHTMG +wm 32 0x307a0490 0x00000001 // DDRC_PCTRL_0 +wm 32 0x307A00D4 0x00690000 // DDRC_INIT1 +wm 32 0x307A00D0 0x00020083 // DDRC_INIT0 +wm 32 0x307A00DC 0x09300004 // DDRC_INIT3 +wm 32 0x307A00E0 0x04080000 // DDRC_INIT4 +wm 32 0x307A00E4 0x00100004 // DDRC_INIT5 +wm 32 0x307A00F4 0x0000033F // DDRC_RANKCTL +wm 32 0x307A0100 0x090B1109 // DDRC_DRAMTMG0 +wm 32 0x307A0104 0x0007020D // DDRC_DRAMTMG1 +wm 32 0x307A0108 0x03040407 // DDRC_DRAMTMG2 +wm 32 0x307A010C 0x00002006 // DDRC_DRAMTMG3 +wm 32 0x307A0110 0x04020205 // DDRC_DRAMTMG4 +wm 32 0x307A0114 0x03030202 // DDRC_DRAMTMG5 +wm 32 0x307A0120 0x00000803 // DDRC_DRAMTMG8 +wm 32 0x307A0180 0x00800020 // DDRC_ZQCTL0 +wm 32 0x307A0190 0x02098204 // DDRC_DFITMG0 +wm 32 0x307A0194 0x00030303 // DDRC_DFITMG1 +wm 32 0x307A01A0 0x80400003 // DDRC_DFIUPD0 +wm 32 0x307A01A4 0x00100020 // DDRC_DFIUPD1 +wm 32 0x307A01A8 0x80100004 // DDRC_DFIUPD2 +wm 32 0x307A0200 0x00000015 // DDRC_ADDRMAP0 +wm 32 0x307A0204 0x00070707 // DDRC_ADDRMAP1 +wm 32 0x307A0210 0x00000F0F // DDRC_ADDRMAP4 +wm 32 0x307A0214 0x06060606 // DDRC_ADDRMAP5 +wm 32 0x307A0218 0x0F060606 // DDRC_ADDRMAP6 +wm 32 0x307A0240 0x06000604 // DDRC_ODTCFG +wm 32 0x307A0244 0x00000001 // DDRC_ODTMAP + + +/* ============================================================================= + * PHY Control Register + * ============================================================================= + */ + +wm 32 0x30391000 0x00000000 // deassert presetn +wm 32 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0 +wm 32 0x30790004 0x10210100 // DDR_PHY_PHY_CON1 +wm 32 0x30790010 0x00060807 // DDR_PHY_PHY_CON4 +wm 32 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0 +wm 32 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0 +wm 32 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0 +wm 32 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0 +wm 32 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0 +wm 32 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0 +wm 32 0x30790018 0x0000000F // DDR_PHY_LP_CON0 +wm 32 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ +wm 32 0x307900C0 0x0E447304 +wm 32 0x307900C0 0x0E447306 +wm 32 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point. +wm 32 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ + + +/* ============================================================================= + * Final Initialization start sequence + * ============================================================================= + */ + +wm 32 0x30384130 0x00000000 // Disable Clock +wm 32 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY +wm 32 0x30384130 0x00000002 // Enable Clock +/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */ diff --git a/arch/arm/boards/meerkat96/lowlevel.c b/arch/arm/boards/meerkat96/lowlevel.c new file mode 100644 index 0000000000..03a1a11466 --- /dev/null +++ b/arch/arm/boards/meerkat96/lowlevel.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <debug_ll.h> +#include <io.h> +#include <linux/sizes.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/iomux-mx7.h> +#include <mach/imx/imx7-ccm-regs.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/cache.h> +extern char __dtb_z_imx7d_meerkat96_start[]; + +static void setup_uart(void) +{ + /* FIXME: Below UART6 is muxed, not UART1 */ + imx7_early_setup_uart_clock(1); + imx7_setup_pad(MX7D_PAD_SD1_WP__UART6_DCE_TX); + imx7_uart_setup_ll(); + putc_ll('>'); +} + +ENTRY_FUNCTION_WITHSTACK(start_imx7d_meerkat96, 0, r0, r1, r2) +{ + void *fdt; + + imx7_cpu_lowlevel_init(); + + setup_uart(); + + fdt = __dtb_z_imx7d_meerkat96_start + get_runtime_offset(); + + barebox_arm_entry(0x80000000, SZ_512M, fdt); +} diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile index b08c4a93ca..458f520900 100644 --- a/arch/arm/boards/microchip-ksz9477-evb/Makefile +++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c index 30a5760da6..aa2161daee 100644 --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c @@ -8,20 +8,16 @@ #include <init.h> #include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/at91_pmc_ll.h> - -#include <mach/hardware.h> -#include <mach/iomux.h> #include <debug_ll.h> -#include <mach/at91_dbgu.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/iomux.h> +#include <mach/at91/sama5d3.h> +#include <mach/at91/sama5d3-xplained-ddramc.h> +#include <mach/at91/xload.h> /* PCK = 528MHz, MCK = 132MHz */ #define MASTER_CLOCK 132000000 -#define sama5d3_pmc_enable_periph_clock(clk) \ - at91_pmc_enable_periph_clock(IOMEM(SAMA5D3_BASE_PMC), clk) - static void dbgu_init(void) { void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB); @@ -36,20 +32,31 @@ static void dbgu_init(void) putc_ll('>'); } +SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071_xload_mmc, r4) +{ + sama5d3_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + sama5d3_udelay_init(MASTER_CLOCK); + sama5d3_xplained_ddrconf(); + if (IS_ENABLED(CONFIG_DEBUG_LL)) + dbgu_init(); + + sama5d3_atmci_start_image(0, MASTER_CLOCK, 0); +} + extern char __dtb_z_at91_microchip_ksz9477_evb_start[]; -ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2) +SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r4) { void *fdt; - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); - if (IS_ENABLED(CONFIG_DEBUG_LL)) dbgu_init(); fdt = __dtb_z_at91_microchip_ksz9477_evb_start + get_runtime_offset(); - barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt); + sama5d3_barebox_entry(r4, fdt); } diff --git a/arch/arm/boards/microchip-sama5d3-eds/Makefile b/arch/arm/boards/microchip-sama5d3-eds/Makefile new file mode 100644 index 0000000000..458f520900 --- /dev/null +++ b/arch/arm/boards/microchip-sama5d3-eds/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o diff --git a/arch/arm/boards/microchip-sama5d3-eds/lowlevel.c b/arch/arm/boards/microchip-sama5d3-eds/lowlevel.c new file mode 100644 index 0000000000..79346a9b6a --- /dev/null +++ b/arch/arm/boards/microchip-sama5d3-eds/lowlevel.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause +/* + * Copyright (C) 2014, Atmel Corporation + * Copyright (C) 2018 Ahmad Fatoum, Pengutronix + */ + +#include <common.h> +#include <init.h> + +#include <asm/barebox-arm-head.h> +#include <debug_ll.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/iomux.h> +#include <mach/at91/sama5d3.h> +#include <mach/at91/sama5d3-xplained-ddramc.h> +#include <mach/at91/xload.h> + +/* PCK = 528MHz, MCK = 132MHz */ +#define MASTER_CLOCK 132000000 + +static void dbgu_init(void) +{ + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB); + + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB); + + at91_mux_pio3_pin(pio, pin_to_mask(AT91_PIN_PB31), AT91_MUX_PERIPH_A, 0); + + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU); + at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), MASTER_CLOCK, 115200); + + putc_ll('>'); +} + +SAMA5D3_ENTRY_FUNCTION(start_microchip_sama5d3_eds_xload_mmc, r4) +{ + sama5d3_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + sama5d3_udelay_init(MASTER_CLOCK); + sama5d3_xplained_ddrconf(); + if (IS_ENABLED(CONFIG_DEBUG_LL)) + dbgu_init(); + + sama5d3_atmci_start_image(0, MASTER_CLOCK, 0); +} + +extern char __dtb_z_at91_microchip_sama5d3_eds_start[]; + +SAMA5D3_ENTRY_FUNCTION(start_microchip_sama5d3_eds, r4) +{ + void *fdt; + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + dbgu_init(); + + fdt = __dtb_z_at91_microchip_sama5d3_eds_start + get_runtime_offset(); + + sama5d3_barebox_entry(r4, fdt); +} diff --git a/arch/arm/boards/mioa701/Makefile b/arch/arm/boards/mioa701/Makefile index 3072706237..bf17869fb2 100644 --- a/arch/arm/boards/mioa701/Makefile +++ b/arch/arm/boards/mioa701/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o gpio0_poweroff.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c index cdb86fc36e..685c78611b 100644 --- a/arch/arm/boards/mioa701/board.c +++ b/arch/arm/boards/mioa701/board.c @@ -1,40 +1,24 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> #include <driver.h> #include <environment.h> #include <fs.h> #include <init.h> -#include <partition.h> #include <led.h> #include <gpio.h> #include <pwm.h> -#include <mach/devices.h> -#include <mach/mfp-pxa27x.h> -#include <mach/pxa-regs.h> -#include <mach/udc_pxa2xx.h> -#include <mach/mci_pxa2xx.h> +#include <mach/pxa/devices.h> +#include <mach/pxa/mfp-pxa27x.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/udc_pxa2xx.h> +#include <mach/pxa/mci_pxa2xx.h> #include <asm/armlinux.h> #include <asm/io.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <asm/mmu.h> #include "mioa701.h" diff --git a/arch/arm/boards/mioa701/gpio0_poweroff.c b/arch/arm/boards/mioa701/gpio0_poweroff.c index 01a5d0cc6e..41d886d74b 100644 --- a/arch/arm/boards/mioa701/gpio0_poweroff.c +++ b/arch/arm/boards/mioa701/gpio0_poweroff.c @@ -1,20 +1,5 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> #include <clock.h> #include <common.h> @@ -76,7 +61,7 @@ static struct poller_struct gpio0_poller = { static int gpio0_poweroff_probe(void) { - return poller_register(&gpio0_poller); + return poller_register(&gpio0_poller, "power-button"); } device_initcall(gpio0_poweroff_probe); diff --git a/arch/arm/boards/mioa701/lowlevel.c b/arch/arm/boards/mioa701/lowlevel.c index ee0546ea63..6116990402 100644 --- a/arch/arm/boards/mioa701/lowlevel.c +++ b/arch/arm/boards/mioa701/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> diff --git a/arch/arm/boards/mioa701/mioa701.h b/arch/arm/boards/mioa701/mioa701.h index 20b9b51af2..5f6d5e65f7 100644 --- a/arch/arm/boards/mioa701/mioa701.h +++ b/arch/arm/boards/mioa701/mioa701.h @@ -1,20 +1,6 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> + #ifndef _MIOA701_H_ #define _MIOA701_H_ diff --git a/arch/arm/boards/mnt-reform/Makefile b/arch/arm/boards/mnt-reform/Makefile new file mode 100644 index 0000000000..35d8640087 --- /dev/null +++ b/arch/arm/boards/mnt-reform/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/mnt-reform/board.c b/arch/arm/boards/mnt-reform/board.c new file mode 100644 index 0000000000..8b56d108e6 --- /dev/null +++ b/arch/arm/boards/mnt-reform/board.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Lucas Stach <dev@lynxeye.de> + */ + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/imx/bbu.h> + +static int mnt_reform_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", emmc_bbu_flag); + + return 0; +} + +static const struct of_device_id mnt_reform_of_match[] = { + { .compatible = "mntre,reform2"}, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(mnt_reform_of_match); + +static struct driver mnt_reform_board_driver = { + .name = "board-mnt-reform", + .probe = mnt_reform_probe, + .of_compatible = DRV_OF_COMPAT(mnt_reform_of_match), +}; +device_platform_driver(mnt_reform_board_driver); diff --git a/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg b/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg new file mode 100644 index 0000000000..f82759f849 --- /dev/null +++ b/arch/arm/boards/mnt-reform/flash-header-mnt-reform.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mq + +loadaddr 0x007E1000 +max_load_size 0x3F000 +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/mnt-reform/lowlevel.c b/arch/arm/boards/mnt-reform/lowlevel.c new file mode 100644 index 0000000000..9f951508df --- /dev/null +++ b/arch/arm/boards/mnt-reform/lowlevel.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Lucas Stach <dev@lynxeye.de> + */ + +#include <asm/barebox-arm.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx-gpio.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/imx8mq-regs.h> +#include <mach/imx/iomux-mx8mq.h> +#include <mach/imx/xload.h> +#include <soc/imx8m/ddr.h> + +extern char __dtb_z_imx8mq_mnt_reform2_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MQ_PAD_CTL_DSE_65R) + +static void mnt_reform_setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static void i2c_mux_set(struct pbl_i2c *i2c, u8 channel) +{ + int ret; + u8 buf[1]; + struct i2c_msg msgs[] = { + { + .addr = 0x70, + .buf = buf, + .len = 1, + }, + }; + + buf[0] = 1 << channel; + + ret = pbl_i2c_xfer(i2c, msgs, ARRAY_SIZE(msgs)); + if (ret != 1) + pr_err("failed to set i2c mux\n"); +} + +static void i2c_regulator_set_voltage(struct pbl_i2c *i2c, u8 reg, u8 voffs) +{ + pmic_reg_write8(i2c, 0x60, reg, 0x80 + voffs); +} + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MQ_PAD_CTL_DSE_45R | \ + MX8MQ_PAD_CTL_HYS | \ + MX8MQ_PAD_CTL_PUE) + +static void mnt_reform_init_power(void) +{ + struct pbl_i2c *i2c; + + imx8mq_setup_pad(IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR)); + + /* de-assert i2c mux reset */ + imx8m_gpio_direction_output(IOMEM(MX8MQ_GPIO1_BASE_ADDR), 4, 1); + /* ARM/DRAM_CORE VSEL */ + imx8m_gpio_direction_output(IOMEM(MX8MQ_GPIO3_BASE_ADDR), 24, 0); + /* DRAM VSEL */ + imx8m_gpio_direction_output(IOMEM(MX8MQ_GPIO2_BASE_ADDR), 11, 0); + /* SOC/GPU/VPU VSEL */ + imx8m_gpio_direction_output(IOMEM(MX8MQ_GPIO2_BASE_ADDR), 20, 0); + + /* enable I2C1A, ARM/DRAM */ + i2c_mux_set(i2c, 0); + /* .6 + .40 = 1.00V */ + i2c_regulator_set_voltage(i2c, 0, 40); + i2c_regulator_set_voltage(i2c, 1, 40); + + /* enable I2C1B, DRAM 1.1V */ + i2c_mux_set(i2c, 1); + /* .6 + .50 = 1.10V */ + i2c_regulator_set_voltage(i2c, 0, 50); + i2c_regulator_set_voltage(i2c, 1, 50); + + /* enable I2C1C, SOC/GPU/VPU */ + i2c_mux_set(i2c, 2); + /*.6 + .30 = .90V */ + i2c_regulator_set_voltage(i2c, 0, 30); + i2c_regulator_set_voltage(i2c, 1, 30); + + /* enable I2C1D */ + i2c_mux_set(i2c, 3); +} + +extern struct dram_timing_info mnt_reform_dram_timing; + +static __noreturn noinline void mnt_reform_start(void) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the power supplies, DRAM and run TF-A (BL31). + * The TF-A will then jump to DRAM in EL2. + */ + if (current_el() == 3) { + mnt_reform_setup_uart(); + + mnt_reform_init_power(); + + imx8mq_ddr_init(&mnt_reform_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mq_load_and_start_image_via_tfa(); + } + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mq_barebox_entry(__dtb_z_imx8mq_mnt_reform2_start); +} + +ENTRY_FUNCTION(start_mnt_reform, r0, r1, r2) +{ + imx8mq_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + mnt_reform_start(); +} diff --git a/arch/arm/boards/mnt-reform/lpddr4-timing.c b/arch/arm/boards/mnt-reform/lpddr4-timing.c new file mode 100644 index 0000000000..0b5853000d --- /dev/null +++ b/arch/arm/boards/mnt-reform/lpddr4-timing.c @@ -0,0 +1,1012 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param mnt_reform_lpddr4_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { DDRC_DBG1(0), 1 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 1 }, + { DDRC_MSTR(0), 0xa0080020 | (LPDDR4_CS << 24) }, + { DDRC_MSTR2(0), 0 }, + { DDRC_DERATEEN(0), 0x0203 }, + { DDRC_DERATEINT(0), 0x0003e800 }, + { DDRC_RFSHTMG(0), 0x006100e0 }, + { DDRC_INIT0(0), 0xc003061c }, + { DDRC_INIT1(0), 0x009e0000 }, + { DDRC_INIT3(0), 0x00d4002d }, + { DDRC_INIT4(0), ((LPDDR4_MR3 << 16) | 8) }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0016004a }, + { DDRC_DRAMTMG0(0), 0x1a201b22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00c0c000 }, + { DDRC_DRAMTMG4(0), 0x0f04080f }, + { DDRC_DRAMTMG5(0), 0x02040c0c }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x0401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0c100002 }, + { DDRC_DRAMTMG14(0), 0xe6 }, + { DDRC_DRAMTMG17(0), 0x00a00050 }, + { DDRC_ZQCTL0(0), 0xc3200018 }, + { DDRC_ZQCTL1(0), 0x028061a8 }, + { DDRC_ZQCTL2(0), 0 }, + { DDRC_DFITMG0(0), 0x0497820a }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xe0400018 }, + { DDRC_DFIUPD1(0), 0x00df00e4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x11 }, + { DDRC_DFITMG2(0), 0x170a }, + { DDRC_DBICTL(0), 1 }, + { DDRC_DFIPHYMSTR(0), 1 }, + { DDRC_RANKCTL(0), 0x0639 }, + { DDRC_DRAMTMG2(0), 0x070e1617 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000017 }, + { DDRC_ADDRMAP3(0), 0 }, + /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x1f1f }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x07070707 }, + { DDRC_ADDRMAP7(0), 0x0f0f }, + { DDRC_FREQ1_DERATEEN(0), 1 }, + { DDRC_FREQ1_DERATEINT(0), 0xd0c0 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x0014002f }, + { DDRC_FREQ1_INIT3(0), 0x00940009 }, + { DDRC_FREQ1_INIT4(0), ((LPDDR4_MR3 << 16) | 8) }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0016004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x0003040b }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0301 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x00020300 }, + { DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x31 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ1_DFITMG2(0), 0x0502 }, + { DDRC_ODTMAP(0), 0 }, + { DDRC_SCHED(0), 0x29001505 }, + { DDRC_SCHED1(0), 0x2c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + { DDRC_PERFLPR1(0), 0x90000096 }, + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x16 }, + { DDRC_DBG1(0), 0 }, + { DDRC_DBGCMD(0), 0 }, + { DDRC_SWCTL(0), 1 }, + { DDRC_POISONCFG(0), 0x11 }, + { DDRC_PCCFG(0), 0x0111 }, + { DDRC_PCFGR_0(0), 0x10f3 }, + { DDRC_PCFGW_0(0), 0x72ff }, + { DDRC_PCTRL_0(0), 1 }, + { DDRC_PCFGQOS0_0(0), 0x0e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + { DDRC_PCFGWQOS0_0(0), 0x0e00 }, + { DDRC_PCFGWQOS1_0(0), 0xffff }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param mnt_reform_lpddr4_ddrphy_cfg[] = { + { 0x100a0, 0 }, + { 0x100a1, 1 }, + { 0x100a2, 2 }, + { 0x100a3, 3 }, + { 0x100a4, 4 }, + { 0x100a5, 5 }, + { 0x100a6, 6 }, + { 0x100a7, 7 }, + { 0x110a0, 0 }, + { 0x110a1, 1 }, + { 0x110a2, 2 }, + { 0x110a3, 3 }, + { 0x110a4, 4 }, + { 0x110a5, 5 }, + { 0x110a6, 6 }, + { 0x110a7, 7 }, + { 0x120a0, 0 }, + { 0x120a1, 1 }, + { 0x120a2, 2 }, + { 0x120a3, 3 }, + { 0x120a4, 4 }, + { 0x120a5, 5 }, + { 0x120a6, 6 }, + { 0x120a7, 7 }, + { 0x130a0, 0 }, + { 0x130a1, 1 }, + { 0x130a2, 2 }, + { 0x130a3, 3 }, + { 0x130a4, 4 }, + { 0x130a5, 5 }, + { 0x130a6, 6 }, + { 0x130a7, 7 }, + { 0x1005f, 0x01ff }, + { 0x1015f, 0x01ff }, + { 0x1105f, 0x01ff }, + { 0x1115f, 0x01ff }, + { 0x1205f, 0x01ff }, + { 0x1215f, 0x01ff }, + { 0x1305f, 0x01ff }, + { 0x1315f, 0x01ff }, + { 0x11005f, 0x01ff }, + { 0x11015f, 0x01ff }, + { 0x11105f, 0x01ff }, + { 0x11115f, 0x01ff }, + { 0x11205f, 0x01ff }, + { 0x11215f, 0x01ff }, + { 0x11305f, 0x01ff }, + { 0x11315f, 0x01ff }, + { 0x0055, 0x01ff }, + { 0x1055, 0x01ff }, + { 0x2055, 0x01ff }, + { 0x3055, 0x01ff }, + { 0x4055, 0x01ff }, + { 0x5055, 0x01ff }, + { 0x6055, 0x01ff }, + { 0x7055, 0x01ff }, + { 0x8055, 0x01ff }, + { 0x9055, 0x01ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 7 }, + { 0x2002e, 2 }, + { 0x12002e, 1 }, + { 0x90204, 0 }, + { 0x190204, 0 }, + { 0x20024, 0x01ab }, + { 0x2003a, 0 }, + { 0x120024, 0x01ab }, + { 0x2003a, 0 }, + { 0x20056, 3 }, + { 0x120056, 3 }, + { 0x1004d, 0x0e00 }, + { 0x1014d, 0x0e00 }, + { 0x1104d, 0x0e00 }, + { 0x1114d, 0x0e00 }, + { 0x1204d, 0x0e00 }, + { 0x1214d, 0x0e00 }, + { 0x1304d, 0x0e00 }, + { 0x1314d, 0x0e00 }, + { 0x11004d, 0x0e00 }, + { 0x11014d, 0x0e00 }, + { 0x11104d, 0x0e00 }, + { 0x11114d, 0x0e00 }, + { 0x11204d, 0x0e00 }, + { 0x11214d, 0x0e00 }, + { 0x11304d, 0x0e00 }, + { 0x11314d, 0x0e00 }, + { 0x10049, 0x0eba }, + { 0x10149, 0x0eba }, + { 0x11049, 0x0eba }, + { 0x11149, 0x0eba }, + { 0x12049, 0x0eba }, + { 0x12149, 0x0eba }, + { 0x13049, 0x0eba }, + { 0x13149, 0x0eba }, + { 0x110049, 0x0eba }, + { 0x110149, 0x0eba }, + { 0x111049, 0x0eba }, + { 0x111149, 0x0eba }, + { 0x112049, 0x0eba }, + { 0x112149, 0x0eba }, + { 0x113049, 0x0eba }, + { 0x113149, 0x0eba }, + { 0x0043, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 3 }, + { 0x20075, 4 }, + { 0x20050, 0 }, + { 0x20008, 0x0320 }, + { 0x120008, 0xa7 }, + { 0x20088, 9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x05a1 }, + { 0x10143, 0x05a1 }, + { 0x11043, 0x05a1 }, + { 0x11143, 0x05a1 }, + { 0x12043, 0x05a1 }, + { 0x12143, 0x05a1 }, + { 0x13043, 0x05a1 }, + { 0x13143, 0x05a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x05a1 }, + { 0x110143, 0x05a1 }, + { 0x111043, 0x05a1 }, + { 0x111143, 0x05a1 }, + { 0x112043, 0x05a1 }, + { 0x112143, 0x05a1 }, + { 0x113043, 0x05a1 }, + { 0x113143, 0x05a1 }, + { 0x200fa, 1 }, + { 0x1200fa, 1 }, + { 0x20019, 1 }, + { 0x120019, 1 }, + { 0x200f0, 0 }, + { 0x200f1, 0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0 }, + { 0x200f6, 0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0 }, + { 0x2002d, 0 }, + { 0x12002d, 0 }, + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x200ca, 0x0106 }, + { 0x1200ca, 0x0106 }, + { 0x20110, 2 }, + { 0x20111, 3 }, + { 0x20112, 4 }, + { 0x20113, 5 }, + { 0x20114, 0 }, + { 0x20115, 1 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0 }, + { 0x54003, 0x0c80 }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x54012, 0x10 | (LPDDR4_CS << 8) }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0 }, + { 0x54002, 1 }, + { 0x54003, 0x029c }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x121f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x54012, 0x10 | (LPDDR4_CS << 8) }, + { 0x54019, 0x0994 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x0994 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x54032, 0x9400 }, + { 0x54033, 0x3109 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0x9400 }, + { 0x54039, 0x3109 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0 }, + { 0x54003, 0x0c80 }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x5400d, 0x0100 }, + { 0x5400f, 0x0100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x10 | (LPDDR4_CS << 8) }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param mnt_reform_lpddr4_phy_pie[] = { + { 0xd0000, 0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x0400 }, + { 0x90002, 0x010e }, + { 0x90003, 0 }, + { 0x90004, 0 }, + { 0x90005, 8 }, + { 0x90029, 0x0b }, + { 0x9002a, 0x0480 }, + { 0x9002b, 0x0109 }, + { 0x9002c, 8 }, + { 0x9002d, 0x0448 }, + { 0x9002e, 0x0139 }, + { 0x9002f, 8 }, + { 0x90030, 0x0478 }, + { 0x90031, 0x0109 }, + { 0x90032, 0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x0109 }, + { 0x90035, 2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x0139 }, + { 0x90038, 0x0f }, + { 0x90039, 0x07c0 }, + { 0x9003a, 0x0139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x0630 }, + { 0x9003d, 0x0159 }, + { 0x9003e, 0x014f }, + { 0x9003f, 0x0630 }, + { 0x90040, 0x0159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x0630 }, + { 0x90043, 0x0149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x0630 }, + { 0x90046, 0x0179 }, + { 0x90047, 8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x0109 }, + { 0x9004a, 0 }, + { 0x9004b, 0x07c8 }, + { 0x9004c, 0x0109 }, + { 0x9004d, 0 }, + { 0x9004e, 1 }, + { 0x9004f, 8 }, + { 0x90050, 0 }, + { 0x90051, 0x045a }, + { 0x90052, 9 }, + { 0x90053, 0 }, + { 0x90054, 0x0448 }, + { 0x90055, 0x0109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x0630 }, + { 0x90058, 0x0179 }, + { 0x90059, 1 }, + { 0x9005a, 0x0618 }, + { 0x9005b, 0x0109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x0630 }, + { 0x9005e, 0x0149 }, + { 0x9005f, 8 }, + { 0x90060, 4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x0630 }, + { 0x90064, 0x0149 }, + { 0x90065, 0 }, + { 0x90066, 4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x0630 }, + { 0x9006a, 0x0149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0 }, + { 0x9006f, 4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x0549 }, + { 0x90072, 0x0630 }, + { 0x90073, 0x0159 }, + { 0x90074, 0x0d49 }, + { 0x90075, 0x0630 }, + { 0x90076, 0x0159 }, + { 0x90077, 0x094a }, + { 0x90078, 0x0630 }, + { 0x90079, 0x0159 }, + { 0x9007a, 0x0441 }, + { 0x9007b, 0x0630 }, + { 0x9007c, 0x0149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x0630 }, + { 0x9007f, 0x0149 }, + { 0x90080, 1 }, + { 0x90081, 0x0630 }, + { 0x90082, 0x0149 }, + { 0x90083, 0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x0109 }, + { 0x90086, 0x0a }, + { 0x90087, 0x10 }, + { 0x90088, 0x0109 }, + { 0x90089, 9 }, + { 0x9008a, 0x03c0 }, + { 0x9008b, 0x0149 }, + { 0x9008c, 9 }, + { 0x9008d, 0x03c0 }, + { 0x9008e, 0x0159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x0109 }, + { 0x90092, 0 }, + { 0x90093, 0x03c0 }, + { 0x90094, 0x0109 }, + { 0x90095, 0x18 }, + { 0x90096, 4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0x0a }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x0109 }, + { 0x9009e, 2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x0109 }, + { 0x900a1, 5 }, + { 0x900a2, 0x07c0 }, + { 0x900a3, 0x0109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x0109 }, + { 0x40000, 0x0811 }, + { 0x40020, 0x0880 }, + { 0x40040, 0 }, + { 0x40060, 0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0 }, + { 0x40003, 0x0811 }, + { 0x40023, 0x0880 }, + { 0x40043, 0 }, + { 0x40063, 0 }, + { 0x40004, 0x0720 }, + { 0x40024, 0x0f }, + { 0x40044, 0x1740 }, + { 0x40064, 0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0 }, + { 0x40006, 0x0716 }, + { 0x40026, 0x0f }, + { 0x40046, 0x2001 }, + { 0x40066, 0 }, + { 0x40007, 0x0716 }, + { 0x40027, 0x0f }, + { 0x40047, 0x2800 }, + { 0x40067, 0 }, + { 0x40008, 0x0716 }, + { 0x40028, 0x0f }, + { 0x40048, 0x0f00 }, + { 0x40068, 0 }, + { 0x40009, 0x0720 }, + { 0x40029, 0x0f }, + { 0x40049, 0x1400 }, + { 0x40069, 0 }, + { 0x4000a, 0x0e08 }, + { 0x4002a, 0x0c15 }, + { 0x4004a, 0 }, + { 0x4006a, 0 }, + { 0x4000b, 0x0623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0 }, + { 0x4006b, 0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0 }, + { 0x4006c, 0 }, + { 0x4000d, 0x0e08 }, + { 0x4002d, 0x0c1a }, + { 0x4004d, 0 }, + { 0x4006d, 0 }, + { 0x4000e, 0x0623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0 }, + { 0x4006e, 0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0 }, + { 0x4006f, 0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0 }, + { 0x40070, 0 }, + { 0x40011, 0x0708 }, + { 0x40031, 5 }, + { 0x40051, 0 }, + { 0x40071, 0x2002 }, + { 0x40012, 8 }, + { 0x40032, 0x80 }, + { 0x40052, 0 }, + { 0x40072, 0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0 }, + { 0x40073, 0 }, + { 0x40014, 0x0708 }, + { 0x40034, 0x0a }, + { 0x40054, 0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0 }, + { 0x40075, 0 }, + { 0x40016, 0x060a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0 }, + { 0x40017, 0x061a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0 }, + { 0x40018, 0x060a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0 }, + { 0x40019, 0x0642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x0880 }, + { 0x4005a, 0 }, + { 0x4007a, 0 }, + { 0x900a7, 0 }, + { 0x900a8, 0x0790 }, + { 0x900a9, 0x011a }, + { 0x900aa, 8 }, + { 0x900ab, 0x07aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x07b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0 }, + { 0x900b1, 0x07c8 }, + { 0x900b2, 0x0109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x02a8 }, + { 0x900b5, 0x0129 }, + { 0x900b6, 8 }, + { 0x900b7, 0x0370 }, + { 0x900b8, 0x0129 }, + { 0x900b9, 0x0a }, + { 0x900ba, 0x03c8 }, + { 0x900bb, 0x01a9 }, + { 0x900bc, 0x0c }, + { 0x900bd, 0x0408 }, + { 0x900be, 0x0199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x0790 }, + { 0x900c1, 0x011a }, + { 0x900c2, 8 }, + { 0x900c3, 4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0x0e }, + { 0x900c6, 0x0408 }, + { 0x900c7, 0x0199 }, + { 0x900c8, 8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x0108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x0790 }, + { 0x900cd, 0x016a }, + { 0x900ce, 8 }, + { 0x900cf, 0x01d8 }, + { 0x900d0, 0x0169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x0168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x0788 }, + { 0x900d6, 0x016a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x01e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x0798 }, + { 0x900dc, 0x016a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x07a0 }, + { 0x900df, 0x016a }, + { 0x900e0, 8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x0168 }, + { 0x900e3, 8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x0168 }, + { 0x900e6, 0x0a }, + { 0x900e7, 0x0408 }, + { 0x900e8, 0x0169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0 }, + { 0x900ed, 0x0408 }, + { 0x900ee, 0x0169 }, + { 0x900ef, 0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x0168 }, + { 0x900f2, 0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x0168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x01e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x0798 }, + { 0x900fa, 0x016a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x07a0 }, + { 0x900fd, 0x016a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x0790 }, + { 0x90100, 0x016a }, + { 0x90101, 8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x0168 }, + { 0x90104, 8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x0168 }, + { 0x90107, 0x0a }, + { 0x90108, 0x0408 }, + { 0x90109, 0x0169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0 }, + { 0x9010e, 0x0408 }, + { 0x9010f, 0x0169 }, + { 0x90110, 0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x0168 }, + { 0x90113, 0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x0168 }, + { 0x90116, 0 }, + { 0x90117, 0x01d8 }, + { 0x90118, 0x0169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x0790 }, + { 0x9011b, 0x016a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x07aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0x0a }, + { 0x90120, 0 }, + { 0x90121, 0x01e9 }, + { 0x90122, 8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x0108 }, + { 0x90125, 0x0f }, + { 0x90126, 0x0408 }, + { 0x90127, 0x0169 }, + { 0x90128, 0x0c }, + { 0x90129, 0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 9 }, + { 0x9012c, 0 }, + { 0x9012d, 0x01a9 }, + { 0x9012e, 0 }, + { 0x9012f, 0x0408 }, + { 0x90130, 0x0169 }, + { 0x90131, 0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x0108 }, + { 0x90134, 8 }, + { 0x90135, 0x07aa }, + { 0x90136, 0x6a }, + { 0x90137, 0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x0108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x0790 }, + { 0x9013c, 0x016a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0 }, + { 0x9013f, 0x68 }, + { 0x90140, 8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x0168 }, + { 0x90143, 0x0f }, + { 0x90144, 0x0408 }, + { 0x90145, 0x0169 }, + { 0x90146, 0x0c }, + { 0x90147, 0 }, + { 0x90148, 0x68 }, + { 0x90149, 0 }, + { 0x9014a, 0x0408 }, + { 0x9014b, 0x0169 }, + { 0x9014c, 0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x0168 }, + { 0x9014f, 8 }, + { 0x90150, 0x03c8 }, + { 0x90151, 0x01a9 }, + { 0x90152, 3 }, + { 0x90153, 0x0370 }, + { 0x90154, 0x0129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x02aa }, + { 0x90157, 9 }, + { 0x90158, 0 }, + { 0x90159, 0x0400 }, + { 0x9015a, 0x010e }, + { 0x9015b, 8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x0109 }, + { 0x9015e, 0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x010c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x010c }, + { 0x90164, 8 }, + { 0x90165, 0x07c8 }, + { 0x90166, 0x0101 }, + { 0x90167, 8 }, + { 0x90168, 0 }, + { 0x90169, 8 }, + { 0x9016a, 8 }, + { 0x9016b, 0x0448 }, + { 0x9016c, 0x0109 }, + { 0x9016d, 0x0f }, + { 0x9016e, 0x07c0 }, + { 0x9016f, 0x0109 }, + { 0x90170, 0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x0109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x0630 }, + { 0x90175, 0x0109 }, + { 0x90176, 8 }, + { 0x90177, 0x0618 }, + { 0x90178, 0x0109 }, + { 0x90179, 8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x0109 }, + { 0x9017c, 0 }, + { 0x9017d, 0x07c8 }, + { 0x9017e, 0x0109 }, + { 0x9017f, 8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x010c }, + { 0x90182, 0 }, + { 0x90183, 1 }, + { 0x90184, 8 }, + { 0x90185, 8 }, + { 0x90186, 4 }, + { 0x90187, 8 }, + { 0x90188, 8 }, + { 0x90189, 0x07c8 }, + { 0x9018a, 0x0101 }, + { 0x90006, 0 }, + { 0x90007, 0 }, + { 0x90008, 8 }, + { 0x90009, 0 }, + { 0x9000a, 0 }, + { 0x9000b, 0 }, + { 0xd00e7, 0x0400 }, + { 0x90017, 0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0 }, + { 0x400d1, 0x0101 }, + { 0x400d2, 0x0105 }, + { 0x400d3, 0x0107 }, + { 0x400d4, 0x010f }, + { 0x400d5, 0x0202 }, + { 0x400d6, 0x020a }, + { 0x400d7, 0x020b }, + { 0x2003a, 2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x07d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x01a1 }, + { 0x12000e, 0x10 }, + { 0x9000c, 0 }, + { 0x9000d, 0x0173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x400fd, 0x0f }, + { 0x10011, 1 }, + { 0x10012, 1 }, + { 0x10013, 0x0180 }, + { 0x10018, 1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 1 }, + { 0x101b4, 1 }, + { 0x102b4, 1 }, + { 0x103b4, 1 }, + { 0x104b4, 1 }, + { 0x105b4, 1 }, + { 0x106b4, 1 }, + { 0x107b4, 1 }, + { 0x108b4, 1 }, + { 0x11011, 1 }, + { 0x11012, 1 }, + { 0x11013, 0x0180 }, + { 0x11018, 1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 1 }, + { 0x111b4, 1 }, + { 0x112b4, 1 }, + { 0x113b4, 1 }, + { 0x114b4, 1 }, + { 0x115b4, 1 }, + { 0x116b4, 1 }, + { 0x117b4, 1 }, + { 0x118b4, 1 }, + { 0x12011, 1 }, + { 0x12012, 1 }, + { 0x12013, 0x0180 }, + { 0x12018, 1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 1 }, + { 0x121b4, 1 }, + { 0x122b4, 1 }, + { 0x123b4, 1 }, + { 0x124b4, 1 }, + { 0x125b4, 1 }, + { 0x126b4, 1 }, + { 0x127b4, 1 }, + { 0x128b4, 1 }, + { 0x13011, 1 }, + { 0x13012, 1 }, + { 0x13013, 0x0180 }, + { 0x13018, 1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 1 }, + { 0x131b4, 1 }, + { 0x132b4, 1 }, + { 0x133b4, 1 }, + { 0x134b4, 1 }, + { 0x135b4, 1 }, + { 0x136b4, 1 }, + { 0x137b4, 1 }, + { 0x138b4, 1 }, + { 0x2003a, 2 }, + { 0xc0080, 2 }, + { 0xd0000, 1 } +}; + +static struct dram_fsp_msg mnt_reform_lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info mnt_reform_dram_timing = { + .ddrc_cfg = mnt_reform_lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(mnt_reform_lpddr4_ddrc_cfg), + .ddrphy_cfg = mnt_reform_lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(mnt_reform_lpddr4_ddrphy_cfg), + .fsp_msg = mnt_reform_lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(mnt_reform_lpddr4_dram_fsp_msg), + .ddrphy_pie = mnt_reform_lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(mnt_reform_lpddr4_phy_pie), + .fsp_table = { 3200, 667, }, +}; diff --git a/arch/arm/boards/module-mb7707/Makefile b/arch/arm/boards/module-mb7707/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/module-mb7707/Makefile +++ b/arch/arm/boards/module-mb7707/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/module-mb7707/board.c b/arch/arm/boards/module-mb7707/board.c index 7ffad6e62a..366baddf81 100644 --- a/arch/arm/boards/module-mb7707/board.c +++ b/arch/arm/boards/module-mb7707/board.c @@ -1,25 +1,13 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #include <common.h> #include <init.h> #include <driver.h> -#include <usb/ehci.h> -#include <mach/hardware.h> +#include <linux/usb/ehci.h> +#include <mach/uemd/hardware.h> static int hostname_init(void) { diff --git a/arch/arm/boards/module-mb7707/lowlevel.c b/arch/arm/boards/module-mb7707/lowlevel.c index fc102e26e1..3b529d1232 100644 --- a/arch/arm/boards/module-mb7707/lowlevel.c +++ b/arch/arm/boards/module-mb7707/lowlevel.c @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #define __LOWLEVEL_INIT__ diff --git a/arch/arm/boards/mx31moboard/Makefile b/arch/arm/boards/mx31moboard/Makefile deleted file mode 100644 index 83a6016b22..0000000000 --- a/arch/arm/boards/mx31moboard/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel.o -obj-y += mx31moboard.o diff --git a/arch/arm/boards/mx31moboard/env/boot/nor b/arch/arm/boards/mx31moboard/env/boot/nor deleted file mode 100644 index f584307d7a..0000000000 --- a/arch/arm/boards/mx31moboard/env/boot/nor +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nor0.kernel" -global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro" diff --git a/arch/arm/boards/mx31moboard/env/boot/sd b/arch/arm/boards/mx31moboard/env/boot/sd deleted file mode 100644 index a0c4da9e78..0000000000 --- a/arch/arm/boards/mx31moboard/env/boot/sd +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -boot mci0 diff --git a/arch/arm/boards/mx31moboard/env/boot/usbmsd b/arch/arm/boards/mx31moboard/env/boot/usbmsd deleted file mode 100644 index 208921da26..0000000000 --- a/arch/arm/boards/mx31moboard/env/boot/usbmsd +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -boot ehci0 diff --git a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor b/arch/arm/boards/mx31moboard/env/init/mtdparts-nor deleted file mode 100644 index ab5b175c37..0000000000 --- a/arch/arm/boards/mx31moboard/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nor0.barebox)ro,256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/mx31moboard/env/nv/boot.default b/arch/arm/boards/mx31moboard/env/nv/boot.default deleted file mode 100644 index 7957ab340c..0000000000 --- a/arch/arm/boards/mx31moboard/env/nv/boot.default +++ /dev/null @@ -1 +0,0 @@ -usbmsd sd nor diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c deleted file mode 100644 index 307975d78c..0000000000 --- a/arch/arm/boards/mx31moboard/lowlevel.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (c) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <io.h> -#include <asm/barebox-arm.h> -#include <asm/system.h> -#include <asm-generic/memory_layout.h> -#include <asm-generic/sections.h> -#include <asm/barebox-arm-head.h> -#include <mach/imx31-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> - -static noinline __noreturn void mx31moboard_startup(void) -{ - uint32_t r; - volatile int c; - - /* Enable IPU Display interface */ - writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); - - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); - - for (c = 0; c < 0x4000; c++) ; - - writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + - MX31_CCM_CCMR); - writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, - MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); - - writel(MX31_PDR0_CSI_PODF(0x1ff) | \ - MX31_PDR0_PER_PODF(7) | \ - MX31_PDR0_HSP_PODF(3) | \ - MX31_PDR0_NFC_PODF(5) | \ - MX31_PDR0_IPG_PODF(1) | \ - MX31_PDR0_MAX_PODF(3) | \ - MX31_PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) | - IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C), - MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | - IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + - MX31_CCM_SPCTL); - - /* - * Configure IOMUXC - * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, - * except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) - * and 0x43fa_c280 (untouched) - * (behaviour copied by sha, source unknown) - */ - writel(0, 0x43fac26c); /* SDCLK */ - writel(0, 0x43fac270); /* CAS */ - writel(0, 0x43fac274); /* RAS */ - - writel(0x1000, 0x43fac27c); /* CSD0 */ - - /* DQM3, DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 */ - for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) - writel(0, r); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0xa0000000) - imx31_barebox_entry(NULL); - - writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x00695727, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(0x92100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); - writel(0xa2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x12344321, MX31_CSD0_BASE_ADDR); - writel(0x12344321, MX31_CSD0_BASE_ADDR); - writel(0xb2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); - writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); - writel(0x82226080, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); - - imx31_barebox_entry(NULL); - -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - - /* Temporary stack location in internal SRAM */ - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE); - - mx31moboard_startup(); -} diff --git a/arch/arm/boards/mx31moboard/mx31moboard.c b/arch/arm/boards/mx31moboard/mx31moboard.c deleted file mode 100644 index 2ec1f4ff8b..0000000000 --- a/arch/arm/boards/mx31moboard/mx31moboard.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for EPFL's, i.MX31 based CPU card - * - * Based on: - * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <fs.h> -#include <gpio.h> -#include <led.h> -#include <environment.h> -#include <usb/ulpi.h> -#include <mach/imx31-regs.h> -#include <mach/iomux-mx31.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <mach/weim.h> -#include <io.h> -#include <asm/mmu.h> -#include <partition.h> -#include <generated/mach-types.h> -#include <asm/barebox-arm.h> -#include <mach/devices-imx31.h> - -#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) -#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) - -static void mx31moboard_usb_init(void) -{ - u32 tmp; - - if (!IS_ENABLED(CONFIG_USB)) - return; - - /* enable clock */ - tmp = readl(0x53f80000); - tmp |= (1 << 9); - writel(tmp, 0x53f80000); - - /* Host 2 */ - tmp = readl(MX31_IOMUXC_GPR); - tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */ - writel(tmp, MX31_IOMUXC_GPR); - - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ - | PAD_CTL_ODE_CMOS) - imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG | PAD_CTL_100K_PU); - imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG | PAD_CTL_100K_PU); - imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG | PAD_CTL_100K_PU); - imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG | PAD_CTL_100K_PU); - imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - - gpio_request(USB_RESET_B, "usb-reset"); - gpio_direction_output(USB_RESET_B, 0); - mdelay(5); - gpio_set_value(USB_RESET_B, 1); - mdelay(10); - - gpio_request(USBH2_EN_B, "usbh2-en"); - gpio_direction_output(USBH2_EN_B, 0); - udelay(900); - gpio_set_value(USBH2_EN_B, 1); - udelay(200); - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~((3 << 21) | 1); - tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584); - tmp &= ~(3 << 30); - tmp |= 2 << 30; - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584); - - gpio_set_value(USBH2_EN_B, 0); - - mdelay(50); - - ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1); - - /* Set to Host mode */ - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8); - writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8); - -} - -static struct gpio_led mx31moboard_leds[] = { - { - .led = { - .name = "coreboard-led-0:red:running" - }, - .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), - }, { - .led = { - .name = "coreboard-led-1:red", - }, - .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), - }, { - .led = { - .name = "coreboard-led-2:red", - }, - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0), - }, { - .led = { - .name = "coreboard-led-3:red", - }, - .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0), - }, -}; - -static void mx31moboard_add_leds(void) -{ - int i; - - if (!IS_ENABLED(CONFIG_LED_GPIO)) - return; - - for (i = 0; i < ARRAY_SIZE(mx31moboard_leds); i++) { - led_gpio_register(&mx31moboard_leds[i]); - led_set(&mx31moboard_leds[i].led, 0); - } - - led_set_trigger(LED_TRIGGER_HEARTBEAT, &mx31moboard_leds[0].led); -} - -static int mx31moboard_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(mx31moboard_mmu_init); - -static const struct devfs_partition mx31moboard_nor0_partitions[] = { - { - .offset = 0, - .size = SZ_512K, - .flags = DEVFS_PARTITION_FIXED, - .name = "self0", - }, { - .offset = DEVFS_PARTITION_APPEND, - .size = SZ_256K, - .name = "env0", - }, { - /* Sentinel */ - } -}; - -static int mx31moboard_devices_init(void) -{ - /* CS0: Nor Flash */ - imx31_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800); - - /* - * Up to 32MiB NOR type flash, connected to - * CS line 0, data width is 16 bit - */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, SZ_32M, 0); - - imx31_add_mmc0(NULL); - - /* - * Create partitions that should be - * not touched by any regular user - */ - devfs_create_partitions("nor0", mx31moboard_nor0_partitions); - protect_file("/dev/env0", 1); - - mx31moboard_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, - MX31_USB_HS2_BASE_ADDR, NULL); - - mx31moboard_add_leds(); - - armlinux_set_architecture(MACH_TYPE_MX31MOBOARD); - - return 0; -} - -device_initcall(mx31moboard_devices_init); - -static unsigned int mx31moboard_iomux[] = { - /* UART1 */ - MX31_PIN_RXD1__RXD1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_CTS1__GPIO2_7, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, - /* LEDS */ - MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, - MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, -}; - -static int imx31_console_init(void) -{ - imx_iomux_setup_multiple_pins(mx31moboard_iomux, - ARRAY_SIZE(mx31moboard_iomux)); - - gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - - barebox_set_model("EPFL mx31moboard"); - barebox_set_hostname("mx31moboard"); - - imx31_add_uart0(); - - return 0; -} - -console_initcall(imx31_console_init); diff --git a/arch/arm/boards/myirtech-x335x/Makefile b/arch/arm/boards/myirtech-x335x/Makefile new file mode 100644 index 0000000000..05d9fc7bc3 --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o +obj-y += board.o +bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-myirtech-x335x diff --git a/arch/arm/boards/myirtech-x335x/board.c b/arch/arm/boards/myirtech-x335x/board.c new file mode 100644 index 0000000000..82bb612032 --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/board.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */ + +#include <bootsource.h> +#include <common.h> +#include <driver.h> +#include <envfs.h> +#include <init.h> +#include <linux/sizes.h> +#include <mach/omap/am33xx-generic.h> + +static struct omap_barebox_part myir_barebox_part = { + .nand_offset = SZ_128K * 4, + .nand_size = SZ_1M, +}; + +static __init int myir_devices_init(void) +{ + if (!of_machine_is_compatible("myir,myc-am335x")) + return 0; + + am33xx_register_ethaddr(0, 0); + am33xx_register_ethaddr(1, 1); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + omap_set_bootmmc_devname("mmc0"); + break; + case BOOTSOURCE_NAND: + omap_set_barebox_part(&myir_barebox_part); + break; + default: + break; + } + + if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT)) + defaultenv_append_directory(defaultenv_myirtech_x335x); + + if (IS_ENABLED(CONFIG_SHELL_NONE)) + return am33xx_of_register_bootdevice(); + + return 0; +} +coredevice_initcall(myir_devices_init); diff --git a/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand new file mode 100644 index 0000000000..c000041095 --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/boot/nand @@ -0,0 +1,4 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.system.ubi.kernel" +global.linux.bootargs.dyn.root="ubi.mtd=system ubi.block=0,root root=fe00 ro" diff --git a/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default new file mode 100644 index 0000000000..026a25cc7e --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/defaultenv-myirtech-x335x/nv/boot.default @@ -0,0 +1 @@ +nand diff --git a/arch/arm/boards/myirtech-x335x/lowlevel.c b/arch/arm/boards/myirtech-x335x/lowlevel.c new file mode 100644 index 0000000000..0ac2370e57 --- /dev/null +++ b/arch/arm/boards/myirtech-x335x/lowlevel.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-FileCopyrightText: Alexander Shiyan <shc_work@mail.ru> */ + +#include <common.h> +#include <io.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <mach/omap/debug_ll.h> +#include <init.h> +#include <linux/sizes.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/am33xx-mux.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> + +#define AM335X_ZCZ_1000 0x1c2f + +static const struct am33xx_ddr_data ddr3_data = { + .rd_slave_ratio0 = 0x38, + .wr_dqs_slave_ratio0 = 0x44, + .fifo_we_slave_ratio0 = 0x94, + .wr_slave_ratio0 = 0x7d, + .use_rank0_delay = 0x01, + .dll_lock_diff0 = 0x00, +}; + +static const struct am33xx_cmd_control ddr3_cmd_ctrl = { + .slave_ratio0 = 0x80, + .dll_lock_diff0 = 0x01, + .invert_clkout0 = 0x00, + .slave_ratio1 = 0x80, + .dll_lock_diff1 = 0x01, + .invert_clkout1 = 0x00, + .slave_ratio2 = 0x80, + .dll_lock_diff2 = 0x01, + .invert_clkout2 = 0x00, +}; + +/* CPU module contains 512MB (2*256MB) DDR3 SDRAM (2*128MB compatible), + * so we configure EMIF for 512MB then detect real size of memory. + */ +static struct am33xx_emif_regs ddr3_regs = { + .emif_read_latency = 0x00100007, + .emif_tim1 = 0x0aaad4db, + .emif_tim2 = 0x266b7fda, + .emif_tim3 = 0x501f867f, + .zq_config = 0x50074be4, + /* MT41K256M8DA */ + .sdram_config = 0x61c05332, + .sdram_config2 = 0x00, + .sdram_ref_ctrl = 0xc30, +}; + +extern char __dtb_z_am335x_myirtech_myd_start[]; + +ENTRY_FUNCTION(start_am33xx_myirtech_sram, bootinfo, r1, r2) +{ + int mpupll; + void *fdt; + + am33xx_save_bootinfo((void *)bootinfo); + + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + fdt = __dtb_z_am335x_myirtech_myd_start; + + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); + + mpupll = MPUPLL_M_800; + if (am33xx_get_cpu_rev() == AM335X_ES2_1) { + u32 deviceid = readl(AM33XX_EFUSE_SMA) & 0x1fff; + if (deviceid == AM335X_ZCZ_1000) + mpupll = MPUPLL_M_1000; + } + + am33xx_pll_init(mpupll, DDRPLL_M_400); + + am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); + + if (get_ram_size((void *)AM33XX_DRAM_ADDR_SPACE_START, SZ_512M) < SZ_512M) { + /* MT41K128M8DA */ + ddr3_regs.sdram_config = 0x61c04ab2; + am335x_sdram_init(0x18b, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); + } + + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + am33xx_uart_soft_reset(IOMEM(AM33XX_UART0_BASE)); + am33xx_enable_uart0_pin_mux(); + omap_debug_ll_init(); + putc_ll('>'); + } + + am335x_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_am33xx_myirtech_sdram, r0, r1, r2) +{ + void *fdt; + + fdt = __dtb_z_am335x_myirtech_myd_start; + + fdt += get_runtime_offset(); + + am335x_barebox_entry(fdt); +} diff --git a/arch/arm/boards/netgear-rn104/Makefile b/arch/arm/boards/netgear-rn104/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/netgear-rn104/Makefile +++ b/arch/arm/boards/netgear-rn104/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/netgear-rn104/board.c b/arch/arm/boards/netgear-rn104/board.c deleted file mode 100644 index 40a8c178f1..0000000000 --- a/arch/arm/boards/netgear-rn104/board.c +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/boards/netgear-rn104/lowlevel.c b/arch/arm/boards/netgear-rn104/lowlevel.c index 8a53615018..e693d13993 100644 --- a/arch/arm/boards/netgear-rn104/lowlevel.c +++ b/arch/arm/boards/netgear-rn104/lowlevel.c @@ -1,15 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only + /* * Copyright (C) 2014 Uwe Kleine-Koenig <uwe@kleine-koenig.org> */ #include <common.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_armada_370_rn104_bb_start[]; -ENTRY_FUNCTION(start_netgear_rn104, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_netgear_rn104, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/netgear-rn2120/Makefile b/arch/arm/boards/netgear-rn2120/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/netgear-rn2120/Makefile +++ b/arch/arm/boards/netgear-rn2120/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/netgear-rn2120/board.c b/arch/arm/boards/netgear-rn2120/board.c index caf106af50..8689202ba6 100644 --- a/arch/arm/boards/netgear-rn2120/board.c +++ b/arch/arm/boards/netgear-rn2120/board.c @@ -1,11 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <clock.h> #include <init.h> #include <of.h> #include <gpio.h> -#include <printk.h> +#include <linux/printk.h> #include <linux/kernel.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> static int rn2120_init(void) { diff --git a/arch/arm/boards/netgear-rn2120/lowlevel.c b/arch/arm/boards/netgear-rn2120/lowlevel.c index e05f2f4c17..f923be5a27 100644 --- a/arch/arm/boards/netgear-rn2120/lowlevel.c +++ b/arch/arm/boards/netgear-rn2120/lowlevel.c @@ -1,26 +1,16 @@ -/* - * Copyright (C) 2015 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2015 Uwe Kleine-König <kernel@pengutronix.de>, Pengutronix #include <common.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> +#include <mach/mvebu/barebox-arm-head.h> #include <asm/io.h> -#include <mach/lowlevel.h> -#include <mach/common.h> +#include <mach/mvebu/lowlevel.h> +#include <mach/mvebu/common.h> extern char __dtb_armada_xp_rn2120_bb_start[]; -ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_netgear_rn2120, r0, r1, r2) { void *fdt; void __iomem *base = mvebu_get_initial_int_reg_base(); diff --git a/arch/arm/boards/nhk8815/Makefile b/arch/arm/boards/nhk8815/Makefile index 56f2013e22..0367fa7dd5 100644 --- a/arch/arm/boards/nhk8815/Makefile +++ b/arch/arm/boards/nhk8815/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += setup.o lwl-y += lowlevel.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-nhk8815 diff --git a/arch/arm/boards/nhk8815/lowlevel.c b/arch/arm/boards/nhk8815/lowlevel.c index a9ccf1fff5..9ba5bbffad 100644 --- a/arch/arm/boards/nhk8815/lowlevel.c +++ b/arch/arm/boards/nhk8815/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c index 0b6901001a..c7a2afdbfe 100644 --- a/arch/arm/boards/nhk8815/setup.c +++ b/arch/arm/boards/nhk8815/setup.c @@ -1,34 +1,20 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> #include <common.h> #include <init.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> -#include <partition.h> #include <nand.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> -#include <mach/board.h> -#include <mach/nand.h> -#include <mach/fsmc.h> +#include <mach/nomadik/hardware.h> +#include <mach/nomadik/board.h> +#include <mach/nomadik/nand.h> +#include <mach/nomadik/fsmc.h> static int nhk8815_nand_init(void) { @@ -66,7 +52,7 @@ static struct resource nhk8815_nand_resources[] = { } }; -static struct device_d nhk8815_nand_device = { +static struct device nhk8815_nand_device = { .id = DEVICE_ID_DYNAMIC, .name = "nomadik_nand", .num_resources = ARRAY_SIZE(nhk8815_nand_resources), diff --git a/arch/arm/boards/novena/Makefile b/arch/arm/boards/novena/Makefile new file mode 100644 index 0000000000..3111392bf9 --- /dev/null +++ b/arch/arm/boards/novena/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/novena/board.c b/arch/arm/boards/novena/board.c new file mode 100644 index 0000000000..b6c59aff44 --- /dev/null +++ b/arch/arm/boards/novena/board.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2023 John Watts <contact@jookia.org> + +#include <common.h> +#include <deep-probe.h> +#include <fs.h> +#include <libfile.h> +#include <net.h> + +struct novena_eeprom { + uint8_t signature[6]; /* 'Novena' */ + uint8_t version; /* 1 or 2, not checked */ + uint8_t page_size; /* v2 only: EEPROM read/write page */ + uint32_t serial; /* 32-bit serial number */ + uint8_t mac[6]; /* Gigabit MAC address */ + uint16_t features; /* features */ + /* ... extra fields omitted ... */ +} __packed; + +static void power_on_audio_codec(void) +{ + int rc = of_devices_ensure_probed_by_name("regulator-audio-codec"); + + if (rc < 0) + pr_err("Unable to power on audio codec: %s\n", strerror(-rc)); +} + +static struct novena_eeprom *novena_read_eeprom(void) +{ + size_t read; + loff_t max = sizeof(struct novena_eeprom); + void *eeprom; + int rc; + + /* + * When powered off the audio codec pulls down the EEPROM's I2C line. + * Power it on so we can actually read data. + */ + power_on_audio_codec(); + + rc = of_device_ensure_probed_by_alias("eeprom0"); + if (rc < 0) { + pr_err("Unable to probe eeprom0: %s\n", strerror(-rc)); + return NULL; + } + + rc = read_file_2("/dev/eeprom0", &read, &eeprom, max); + + if (rc < 0 && rc != -EFBIG) { + pr_err("Unable to read Novena EEPROM: %s\n", strerror(-rc)); + return NULL; + } else if (read != max) { + pr_err("Short read from Novena EEPROM?\n"); + free(eeprom); + return NULL; + } + + return eeprom; +} + +static bool novena_check_eeprom(struct novena_eeprom *eeprom) +{ + char *sig = eeprom->signature; + size_t size = sizeof(eeprom->signature); + + if (memcmp("Novena", sig, size) != 0) { + pr_err("Unknown Novena EEPROM signature\n"); + return false; + } + + return true; +} + +static void novena_set_mac(struct novena_eeprom *eeprom) +{ + struct device_node *dnode; + + dnode = of_find_node_by_alias(of_get_root_node(), "ethernet0"); + if (dnode) + of_eth_register_ethaddr(dnode, eeprom->mac); + else + pr_err("Unable to find ethernet node\n"); +} + +static int novena_probe(struct device *dev) +{ + struct novena_eeprom *eeprom = novena_read_eeprom(); + + if (eeprom && novena_check_eeprom(eeprom)) + novena_set_mac(eeprom); + + free(eeprom); + + return 0; +} + +static const struct of_device_id novena_of_match[] = { + { .compatible = "kosagi,imx6q-novena", }, + { /* sentinel */ } +}; + +static struct driver novena_board_driver = { + .name = "board-novena", + .probe = novena_probe, + .of_compatible = novena_of_match, +}; +coredevice_platform_driver(novena_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(novena_of_match); diff --git a/arch/arm/boards/novena/ddr_regs.h b/arch/arm/boards/novena/ddr_regs.h new file mode 100644 index 0000000000..5f18d5e0e4 --- /dev/null +++ b/arch/arm/boards/novena/ddr_regs.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2014 Marek Vasut <marex@denx.de> */ + +#ifndef NOVENA_DDR_REGS_H +#define NOVENA_DDR_REGS_H + +/* MEMORY CONTROLLER CONFIGURATION */ + +static struct mx6dq_iomux_ddr_regs novena_ddr_regs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020038, + .dram_sdclk_1 = 0x00020038, + .dram_cas = 0x00000038, + .dram_ras = 0x00000038, + .dram_reset = 0x00000038, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00000038, + .dram_sdodt1 = 0x00000038, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000038, + .dram_sdqs2 = 0x00000038, + .dram_sdqs3 = 0x00000038, + .dram_sdqs4 = 0x00000038, + .dram_sdqs5 = 0x00000038, + .dram_sdqs6 = 0x00000038, + .dram_sdqs7 = 0x00000038, + + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00000038, + .dram_dqm1 = 0x00000038, + .dram_dqm2 = 0x00000038, + .dram_dqm3 = 0x00000038, + .dram_dqm4 = 0x00000038, + .dram_dqm5 = 0x00000038, + .dram_dqm6 = 0x00000038, + .dram_dqm7 = 0x00000038, +}; + +static struct mx6dq_iomux_grp_regs novena_grp_regs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* Disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000038, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000038, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000038, + .grp_b1ds = 0x00000038, + .grp_b2ds = 0x00000038, + .grp_b3ds = 0x00000038, + .grp_b4ds = 0x00000038, + .grp_b5ds = 0x00000038, + .grp_b6ds = 0x00000038, + .grp_b7ds = 0x00000038, +}; + +/* MEMORY STICK CONFIGURATION */ + +static struct mx6_mmdc_calibration novena_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00420048, + .p0_mpwldectrl1 = 0x006f0059, + .p1_mpwldectrl0 = 0x005a0104, + .p1_mpwldectrl1 = 0x01070113, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x437c040b, + .p0_mpdgctrl1 = 0x0413040e, + .p1_mpdgctrl0 = 0x444f0446, + .p1_mpdgctrl1 = 0x044d0422, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4c424249, + .p1_mprddlctl = 0x4e48414f, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x42414641, + .p1_mpwrdlctl = 0x46374b43, +}; + +static struct mx6_ddr_sysinfo novena_ddr_info = { + /* Width of data bus: 0=16, 1=32, 2=64 */ + .dsize = 2, + /* Config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* Single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 3, /* Write additional latency */ + .ralat = 7, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 0, /* Bank interleaving disabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +static struct mx6_ddr3_cfg novena_ddr_cfg = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 16, + .coladdr = 10, + .pagesz = 1, + .trcd = 1300, + .trcmin = 4900, + .trasmin = 3590, +}; + +#endif diff --git a/arch/arm/boards/novena/flash-header-novena.imxcfg b/arch/arm/boards/novena/flash-header-novena.imxcfg new file mode 100644 index 0000000000..0612542c19 --- /dev/null +++ b/arch/arm/boards/novena/flash-header-novena.imxcfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +loadaddr 0x00907000 +soc imx6 +max_load_size 0x11000 +ivtofs 0x400 diff --git a/arch/arm/boards/novena/lowlevel.c b/arch/arm/boards/novena/lowlevel.c new file mode 100644 index 0000000000..70aa92d5b4 --- /dev/null +++ b/arch/arm/boards/novena/lowlevel.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2023 John Watts <contact@jookia.org> + +#include <asm/barebox-arm.h> +#include <common.h> +#include <ddr_dimms.h> +#include <ddr_spd.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/xload.h> +#include <pbl/i2c.h> +#include <soc/fsl/fsl_udc.h> +#include "ddr_regs.h" + +#define STACK_TOP (MX6_OCRAM_BASE_ADDR + MX6_OCRAM_MAX_SIZE) + +extern char __dtb_z_imx6q_novena_start[]; + +static struct spd_eeprom spd_eeprom; +static struct dimm_params dimm_params; + +static struct pbl_i2c *setup_spd_i2c(void) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *i2c1base = IOMEM(MX6_I2C1_BASE_ADDR); + + imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT8__I2C1_SDA); + imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT9__I2C1_SCL); + + return imx6_i2c_early_init(i2c1base); +} + +static struct spd_eeprom *read_spd(void) +{ + struct spd_eeprom *eeprom = &spd_eeprom; + struct pbl_i2c *i2c = setup_spd_i2c(); + int rc; + + rc = spd_read_eeprom(i2c, 0x50, eeprom, SPD_MEMTYPE_DDR3); + if (rc < 0) { + pr_err("Couldn't read SPD EEPROM: %i\n", rc); + return NULL; + } + + rc = ddr3_spd_check(&eeprom->ddr3); + if (rc < 0) { + pr_err("Couldn't verify SPD data: %i\n", rc); + return NULL; + } + + return eeprom; +} + +static void setup_dimm_settings(struct dimm_params *params, + struct mx6_ddr_sysinfo *info, + struct mx6_ddr3_cfg *cfg) +{ + int capacity_gbit = params->capacity / 0x8000000; + int density_rank = capacity_gbit / params->n_ranks; + + info->ncs = params->n_ranks; + info->cs_density = density_rank; + cfg->mem_speed = params->tckmin_x_ps; + cfg->density = density_rank / params->n_banks_per_sdram_device; + cfg->width = params->data_width; + cfg->banks = params->n_banks_per_sdram_device; + cfg->rowaddr = params->n_row_addr; + cfg->coladdr = params->n_col_addr; + cfg->trcd = params->trcd_ps / 10; + cfg->trcmin = params->trc_ps / 10; + cfg->trasmin = params->tras_ps / 10; + cfg->SRT = params->extended_op_srt; + + if (params->device_width >= 16) + cfg->pagesz = 2; +} + +static void read_dimm_settings(void) +{ + struct spd_eeprom *eeprom = read_spd(); + struct dimm_params *params = &dimm_params; + int rc; + + if (!eeprom) { + pr_err("Couldn't read SPD EEPROM, using default settings\n"); + return; + } + + rc = ddr3_compute_dimm_parameters(&eeprom->ddr3, params); + if (rc < 0) { + pr_err("Couldn't compute DIMM params: %i\n", rc); + return; + } + + pr_info("Found DIMM: %s\n", params->mpart); + + if (params->primary_sdram_width != 64) { + pr_err("ERROR: DIMM stick memory width is not 64 bits\n"); + hang(); + } + + setup_dimm_settings(params, &novena_ddr_info, &novena_ddr_cfg); +} + +static bool running_from_ram(void) +{ + return (get_pc() >= MX6_MMDC_PORT01_BASE_ADDR); +} + +static void setup_uart(void) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *uart2base = IOMEM(MX6_UART2_BASE_ADDR); + + /* NOTE: RX is needed for TX to work on this board */ + imx_setup_pad(iomuxbase, MX6Q_PAD_EIM_D26__UART2_RXD); + imx_setup_pad(iomuxbase, MX6Q_PAD_EIM_D27__UART2_TXD); + + imx6_uart_setup(uart2base); + pbl_set_putc(imx_uart_putc, uart2base); + + pr_debug(">"); +} + +static void setup_ram(void) +{ + read_dimm_settings(); + + mx6dq_dram_iocfg(64, &novena_ddr_regs, &novena_grp_regs); + mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &novena_ddr_cfg); + + mmdc_do_write_level_calibration(); + mmdc_do_dqs_calibration(); +} + +static void load_barebox(void) +{ + enum bootsource bootsrc; + int bootinstance; + + imx6_get_boot_source(&bootsrc, &bootinstance); + + if (bootsrc == BOOTSOURCE_SERIAL) + imx6_barebox_start_usb(IOMEM(MX6_MMDC_PORT01_BASE_ADDR)); + else if (bootsrc == BOOTSOURCE_MMC) + imx6_esdhc_start_image(bootinstance); + + pr_err("Unsupported boot source %i instance %i\n", + bootsrc, bootinstance); + hang(); +} + +ENTRY_FUNCTION_WITHSTACK(start_imx6q_novena, STACK_TOP, r0, r1, r2) +{ + imx6_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + + imx6_ungate_all_peripherals(); + setup_uart(); + + if (!running_from_ram()) { + setup_ram(); + load_barebox(); + } else { + imx6q_barebox_entry(__dtb_z_imx6q_novena_start); + } +} diff --git a/arch/arm/boards/nvidia-beaver/Makefile b/arch/arm/boards/nvidia-beaver/Makefile index 7ade54e854..6485e5d2da 100644 --- a/arch/arm/boards/nvidia-beaver/Makefile +++ b/arch/arm/boards/nvidia-beaver/Makefile @@ -1,6 +1,6 @@ -CFLAGS_pbl-entry.o := \ - -mcpu=arm7tdmi -march=armv4t \ - -fno-tree-switch-conversion -fno-jump-tables +# SPDX-License-Identifier: GPL-2.0-only + +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t soc := tegra30 lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/nvidia-beaver/board.c b/arch/arm/boards/nvidia-beaver/board.c index bab0238779..2537e75337 100644 --- a/arch/arm/boards/nvidia-beaver/board.c +++ b/arch/arm/boards/nvidia-beaver/board.c @@ -1,25 +1,12 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <gpio.h> #include <i2c/i2c.h> #include <init.h> -#include <mach/tegra-bbu.h> +#include <mach/tegra/tegra-bbu.h> static int nvidia_beaver_fs_init(void) { diff --git a/arch/arm/boards/nvidia-beaver/entry.c b/arch/arm/boards/nvidia-beaver/entry.c index 0f487bbd67..c79057cd9d 100644 --- a/arch/arm/boards/nvidia-beaver/entry.c +++ b/arch/arm/boards/nvidia-beaver/entry.c @@ -1,22 +1,9 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> -#include <mach/lowlevel.h> -#include <mach/lowlevel-dvc.h> +#include <mach/tegra/lowlevel.h> +#include <mach/tegra/lowlevel-dvc.h> extern char __dtb_tegra30_beaver_start[]; diff --git a/arch/arm/boards/nvidia-jetson-tk1/Makefile b/arch/arm/boards/nvidia-jetson-tk1/Makefile index 16b203f9f3..7d9402f9b3 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/Makefile +++ b/arch/arm/boards/nvidia-jetson-tk1/Makefile @@ -1,6 +1,6 @@ -CFLAGS_pbl-entry.o := \ - -mcpu=arm7tdmi -march=armv4t \ - -fno-tree-switch-conversion -fno-jump-tables +# SPDX-License-Identifier: GPL-2.0-only + +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t soc := tegra124 lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/nvidia-jetson-tk1/board.c b/arch/arm/boards/nvidia-jetson-tk1/board.c index 939d18419a..6f72466d76 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/board.c +++ b/arch/arm/boards/nvidia-jetson-tk1/board.c @@ -1,25 +1,12 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <dt-bindings/gpio/tegra-gpio.h> #include <gpio.h> #include <i2c/i2c.h> #include <init.h> -#include <mach/tegra-bbu.h> +#include <mach/tegra/tegra-bbu.h> #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) diff --git a/arch/arm/boards/nvidia-jetson-tk1/entry.c b/arch/arm/boards/nvidia-jetson-tk1/entry.c index da40f74e85..db9b1d9ebf 100644 --- a/arch/arm/boards/nvidia-jetson-tk1/entry.c +++ b/arch/arm/boards/nvidia-jetson-tk1/entry.c @@ -1,22 +1,9 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> -#include <mach/lowlevel.h> -#include <mach/lowlevel-dvc.h> +#include <mach/tegra/lowlevel.h> +#include <mach/tegra/lowlevel-dvc.h> extern char __dtb_tegra124_jetson_tk1_start[]; diff --git a/arch/arm/boards/nxp-imx6ull-evk/Makefile b/arch/arm/boards/nxp-imx6ull-evk/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/Makefile +++ b/arch/arm/boards/nxp-imx6ull-evk/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/nxp-imx6ull-evk/board.c b/arch/arm/boards/nxp-imx6ull-evk/board.c index a0ca268f82..fb168662b9 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/board.c +++ b/arch/arm/boards/nxp-imx6ull-evk/board.c @@ -1,25 +1,9 @@ -/* - * Copyright (C) 2017 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <linux/phy.h> #include <linux/micrel_phy.h> diff --git a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg index a507ab3e24..2538caea8a 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg +++ b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg @@ -9,7 +9,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c index cc0b98e1d8..0a12eb9b68 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c @@ -1,23 +1,15 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-regs.h> +#include <mach/imx/imx6-regs.h> #include <io.h> #include <debug_ll.h> -#include <mach/esdctl.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> #include <asm/cache.h> #include <asm/sections.h> #include <image-metadata.h> diff --git a/arch/arm/boards/nxp-imx8mm-evk/Makefile b/arch/arm/boards/nxp-imx8mm-evk/Makefile new file mode 100644 index 0000000000..35d8640087 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mm-evk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/nxp-imx8mm-evk/board.c b/arch/arm/boards/nxp-imx8mm-evk/board.c new file mode 100644 index 0000000000..c8e17570ca --- /dev/null +++ b/arch/arm/boards/nxp-imx8mm-evk/board.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Sascha Hauer, Pengutronix + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/imx/bbu.h> +#include <deep-probe.h> + +#include <envfs.h> + +#define PHY_ID_AR8031 0x004dd074 +#define AR_PHY_ID_MASK 0xffffffff + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, 0x1d, 0x1f); + phy_write(phydev, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, 0x1d, 0x05); + phy_write(phydev, 0x1e, 0x100); + + return 0; +} + +static int imx8mm_evk_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + barebox_set_hostname("imx8mm-evk"); + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", "/dev/m25p0.barebox", 0); + + phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, + ar8031_phy_fixup); + return 0; +} + +static const struct of_device_id imx8mm_evk_of_match[] = { + { .compatible = "fsl,imx8mm-evk", }, + { .compatible = "fsl,imx8mm-evkb", }, + { /* sentinel */ } +}; + +static struct driver imx8mm_evk_board_driver = { + .name = "board-imx8mm-evk", + .probe = imx8mm_evk_probe, + .of_compatible = imx8mm_evk_of_match, +}; +coredevice_platform_driver(imx8mm_evk_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(imx8mm_evk_of_match); diff --git a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg new file mode 100644 index 0000000000..d1d223a8ee --- /dev/null +++ b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mm + +loadaddr 0x007e1000 +max_load_size 0x3f000 +ivtofs 0x400 + +#include <mach/imx/flexspi-imx8mm-cfg.h> +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c new file mode 100644 index 0000000000..881d8285b6 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <linux/sizes.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8mm-regs.h> +#include <mach/imx/iomux-mx8mm.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mfd/bd71837.h> +#include <mfd/pca9450.h> +#include <mach/imx/xload.h> +#include <soc/imx8m/ddr.h> + +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mm_setup_pad(IMX8MM_PAD_UART2_TXD_UART2_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + + /* Buck 1 DVS control through PMIC_STBY_REQ */ + { PCA9450_BUCK1CTRL, 0x59 }, + + /* Set DVS1 to 0.8v for suspend */ + { PCA9450_BUCK1OUT_DVS1, 0x10 }, + + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + { PCA9450_BUCK3OUT_DVS0, 0x1c }, + + /* + * VDD_DRAM needs off in suspend, set B1_ENMODE=10 + * (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) + */ + { PCA9450_BUCK3CTRL, 0x4a }, + + /* set VDD_SNVS_0V8 from default 0.85V */ + { PCA9450_LDO2CTRL, 0xc0 }, + + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xa1 }, +}; + +static struct pmic_config bd71837_cfg[] = { + /* decrease RESET key long push time from the default 10s to 10ms */ + { BD718XX_PWRONCONFIG1, 0x0 }, + /* unlock the PMIC regs */ + { BD718XX_REGLOCK, 0x1 }, + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + { BD718XX_BUCK1_VOLT_RUN, 0x0f }, + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + { BD718XX_1ST_NODVS_BUCK_VOLT, 0x83 }, + /* lock the PMIC regs */ + { BD718XX_REGLOCK, 0x11 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL); + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR)); + + if (i2c_dev_probe(i2c, 0x25, true) == 0) + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); + else + pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg)); +} + +extern struct dram_timing_info imx8mm_evk_dram_timing; + +static void start_atf(void) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mm_early_clock_init(); + power_init_board(); + imx8mm_ddr_init(&imx8mm_evk_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mm_load_and_start_image_via_tfa(); +} + +/* + * Power-on execution flow of start_nxp_imx8mm_evk() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void nxp_imx8mm_evk_start(void) +{ + extern char __dtb_z_imx8mm_evk_start[], __dtb_z_imx8mm_evkb_start[]; + struct pbl_i2c *i2c; + void *fdt; + + setup_uart(); + + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF. I2C pad + * and clock setup already done during power_init_board(). + */ + i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR)); + + if (i2c_dev_probe(i2c, 0x25, true) == 0) + fdt = __dtb_z_imx8mm_evkb_start; + else + fdt = __dtb_z_imx8mm_evk_start; + + imx8mm_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_nxp_imx8mm_evk, r0, r1, r2) +{ + imx8mm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + nxp_imx8mm_evk_start(); +} diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c new file mode 100644 index 0000000000..c9d11a2408 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c @@ -0,0 +1,1254 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#define DDR_ONE_RANK +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa1080020 }, + { DDRC_RFSHTMG(0), 0x005b00d2 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + { DDRC_DBICTL(0), 0x00000001 }, + + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x0000001f }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x07070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x04000030 }, + { DDRC_PERFLPR1(0), 0x900093e7 }, + { DDRC_PERFWR1(0), 0x20005574 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCFGQOS0_0(0), 0x02100e07 }, + { DDRC_PCFGQOS1_0(0), 0x00620096 }, + { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, + { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + + /* frequency P1&P2 */ + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310000 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, + + /* boot start point */ + { DDRC_MSTR2(0), 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + + { 0x200b2, 0x1d4 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + + { 0x20025, 0x0 }, + { 0x2002d, LPDDR4_PHY_DMIPinPresent }, + { 0x12002d, LPDDR4_PHY_DMIPinPresent }, + { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info imx8mm_evk_dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/nxp-imx8mn-evk/Makefile b/arch/arm/boards/nxp-imx8mn-evk/Makefile new file mode 100644 index 0000000000..d74c5845ef --- /dev/null +++ b/arch/arm/boards/nxp-imx8mn-evk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o ddr4-timing.o lpddr4-timing.o diff --git a/arch/arm/boards/nxp-imx8mn-evk/board.c b/arch/arm/boards/nxp-imx8mn-evk/board.c new file mode 100644 index 0000000000..3e90ba284c --- /dev/null +++ b/arch/arm/boards/nxp-imx8mn-evk/board.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/imx/bbu.h> +#include <envfs.h> + +#define PHY_ID_AR8031 0x004dd074 +#define AR_PHY_ID_MASK 0xffffffff + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + /* + * Enable 1.8V(SEL_1P5_1P8_POS_REG) on + * Phy control debug reg 0 + */ + phy_write(phydev, 0x1d, 0x1f); + phy_write(phydev, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, 0x1d, 0x05); + phy_write(phydev, 0x1e, 0x100); + + return 0; +} + +static int imx8mn_evk_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", "/dev/m25p0.barebox", 0); + + phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, + ar8031_phy_fixup); + + return 0; +} + +static const struct of_device_id imx8mn_evk_of_match[] = { + { .compatible = "fsl,imx8mn-evk" }, + { .compatible = "fsl,imx8mn-ddr4-evk" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(imx8mn_evk_of_match); + +static struct driver imx8mn_evkboard_driver = { + .name = "board-imx8mn-evk", + .probe = imx8mn_evk_probe, + .of_compatible = DRV_OF_COMPAT(imx8mn_evk_of_match), +}; +coredevice_platform_driver(imx8mn_evkboard_driver); diff --git a/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c b/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c new file mode 100644 index 0000000000..626d7e1c08 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x92014a }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x7070d0c }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1809010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + + /* performance setting */ + { 0x3d400250, 0x00001f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x900003ff }, + { 0x3d40026c, 0x200003ff }, + { 0x3d400494, 0x01000e00 }, + { 0x3d400498, 0x03ff0000 }, + { 0x3d40049c, 0x01000e00 }, + { 0x3d4004a0, 0x03ff0000 }, + + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3848204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x404 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000600 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info imx8mn_evk_ddr4_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; diff --git a/arch/arm/boards/nxp-imx8mn-evk/flash-header-imx8mn-evk.imxcfg b/arch/arm/boards/nxp-imx8mn-evk/flash-header-imx8mn-evk.imxcfg new file mode 100644 index 0000000000..f47ea08266 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mn-evk/flash-header-imx8mn-evk.imxcfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mn + +loadaddr 0x912000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/flexspi-imx8mp-cfg.h> +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c new file mode 100644 index 0000000000..a1a501b1d9 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <image-metadata.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <linux/sizes.h> +#include <mach/imx/atf.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8mn-regs.h> +#include <mach/imx/iomux-mx8mn.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mfd/pca9450.h> +#include <mfd/bd71837.h> +#include <soc/imx8m/ddr.h> + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mn_setup_pad(IMX8MN_PAD_UART2_TXD__UART2_DCE_TX); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + /* Set DVS1 to 0.85v for suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* set VDD_SNVS_0V8 from default 0.85V */ + { PCA9450_LDO2CTRL, 0xC0 }, + /* enable LDO4 to 1.2v */ + { PCA9450_LDO4CTRL, 0x44 }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static struct pmic_config bd71837_cfg[] = { + /* decrease RESET key long push time from the default 10s to 10ms */ + { BD718XX_PWRONCONFIG1, 0x0 }, + /* unlock the PMIC regs */ + { BD718XX_REGLOCK, 0x1 }, + /* Set VDD_ARM to typical value 0.85v for 1.2Ghz */ + { BD718XX_BUCK2_VOLT_RUN, 0xf }, + /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ + { BD718XX_BUCK1_VOLT_RUN, 0xf }, + /* Set VDD_SOC 0.85v for suspend */ + { BD718XX_BUCK1_VOLT_SUSP, 0xf }, + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + { BD718XX_4TH_NODVS_BUCK_CTRL, 0x28 }, + /* lock the PMIC regs */ + { BD718XX_REGLOCK, 0x11 }, +}; + +extern struct dram_timing_info imx8mn_evk_ddr4_timing, imx8mn_evk_lpddr4_timing; + +static void start_atf(void) +{ + struct pbl_i2c *i2c; + + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mn_early_clock_init(); + + imx8mn_setup_pad(IMX8MN_PAD_I2C1_SCL__I2C1_SCL); + imx8mn_setup_pad(IMX8MN_PAD_I2C1_SDA__I2C1_SDA); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MN_I2C1_BASE_ADDR)); + + if (i2c_dev_probe(i2c, 0x25, true) == 0) { + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); + imx8mn_ddr_init(&imx8mn_evk_lpddr4_timing, DRAM_TYPE_LPDDR4); + } else { + pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg)); + imx8mn_ddr_init(&imx8mn_evk_ddr4_timing, DRAM_TYPE_DDR4); + } + + imx8mn_load_and_start_image_via_tfa(); +} + +/* + * Power-on execution flow of start_nxp_imx8mn_evk() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void nxp_imx8mn_evk_start(void) +{ + extern char __dtb_z_imx8mn_evk_start[], __dtb_z_imx8mn_ddr4_evk_start[]; + void *fdt; + + setup_uart(); + + start_atf(); + + /* Check if we configured DDR4 in EL3 */ + if (readl(MX8M_DDRC_CTL_BASE_ADDR) & BIT(4)) + fdt = __dtb_z_imx8mn_ddr4_evk_start; + else + fdt = __dtb_z_imx8mn_evk_start; + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mn_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_nxp_imx8mn_evk, r0, r1, r2) +{ + imx8mn_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + nxp_imx8mn_evk_start(); +} diff --git a/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c new file mode 100644 index 0000000000..902c607a82 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c @@ -0,0 +1,1185 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#define DDR_ONE_RANK +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000d0000, 0x00000000}, + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, + {0x00020060, 0x00000002}, + {0x000d0000, 0x00000001}, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info imx8mn_evk_lpddr4_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/arch/arm/boards/nxp-imx8mp-evk/Makefile b/arch/arm/boards/nxp-imx8mp-evk/Makefile new file mode 100644 index 0000000000..35d8640087 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/nxp-imx8mp-evk/board.c b/arch/arm/boards/nxp-imx8mp-evk/board.c new file mode 100644 index 0000000000..2aa551e504 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/board.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Oleksij Rempel, Pengutronix + */ + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iomux-mx8mp.h> +#include <gpio.h> +#include <envfs.h> + +static int nxp_imx8mp_evk_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + u32 val; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + imx8m_bbu_internal_flexspi_nor_register_handler("QSPI", "/dev/m25p0.barebox", 0); + + /* Enable RGMII TX clk output */ + val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN; + writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + + return 0; +} + +static const struct of_device_id nxp_imx8mp_evk_of_match[] = { + { .compatible = "fsl,imx8mp-evk" }, + { /* Sentinel */ } +}; +BAREBOX_DEEP_PROBE_ENABLE(nxp_imx8mp_evk_of_match); + +static struct driver nxp_imx8mp_evk_board_driver = { + .name = "board-nxp-imx8mp-evk", + .probe = nxp_imx8mp_evk_probe, + .of_compatible = nxp_imx8mp_evk_of_match, +}; +coredevice_platform_driver(nxp_imx8mp_evk_board_driver); diff --git a/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg new file mode 100644 index 0000000000..c896c9f248 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/flexspi-imx8mp-cfg.h> +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c new file mode 100644 index 0000000000..969947d2ec --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <linux/sizes.h> +#include <mach/imx/atf.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mfd/pca9450.h> +#include <soc/imx8m/ddr.h> +#include <soc/fsl/fsl_udc.h> + +extern char __dtb_z_imx8mp_evk_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* + * Increase VDD_ARM to 0.95V to avoid issues in case software after + * Barebox switches to the OD ARM frequency without reprogramming the + * PMIC first. + */ + { PCA9450_BUCK2OUT_DVS0, 0x1C }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +extern struct dram_timing_info imx8mp_evk_dram_timing; + +static void start_atf(void) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mp_early_clock_init(); + + power_init_board(); + + imx8mp_ddr_init(&imx8mp_evk_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); +} + +/* + * Power-on execution flow of start_nxp_imx8mp_evk() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void nxp_imx8mp_evk_start(void) +{ + setup_uart(); + + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(__dtb_z_imx8mp_evk_start); +} + +ENTRY_FUNCTION(start_nxp_imx8mp_evk, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + nxp_imx8mp_evk_start(); +} diff --git a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c new file mode 100644 index 0000000000..d929890e15 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x460048 }, + { 0x3d4000ec, 0x150048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x21 }, + { 0x3d403024, 0x30d400 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x478 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info imx8mp_evk_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/nxp-imx8mq-evk/.gitignore b/arch/arm/boards/nxp-imx8mq-evk/.gitignore index ef13747c92..cafa52b207 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/.gitignore +++ b/arch/arm/boards/nxp-imx8mq-evk/.gitignore @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + *.ddr-phy-fw* diff --git a/arch/arm/boards/nxp-imx8mq-evk/Makefile b/arch/arm/boards/nxp-imx8mq-evk/Makefile index 2995f06f0f..17d769f330 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/Makefile +++ b/arch/arm/boards/nxp-imx8mq-evk/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o ddr_init.o ddrphy_train.o diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c index 299d056e27..d86666958a 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/board.c +++ b/arch/arm/boards/nxp-imx8mq-evk/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2018 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Sascha Hauer, Pengutronix #include <asm/memory.h> #include <bootsource.h> @@ -23,7 +7,7 @@ #include <init.h> #include <linux/phy.h> #include <linux/sizes.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <envfs.h> @@ -56,12 +40,10 @@ static int nxp_imx8mq_evk_init(void) barebox_set_hostname("imx8mq-evk"); flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; - imx8mq_bbu_internal_mmc_register_handler("eMMC", - "/dev/mmc0.barebox", flags); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags); flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; - imx8mq_bbu_internal_mmc_register_handler("SD", - "/dev/mmc1.barebox", flags); + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flags); if (bootsource_get_instance() == 0) of_device_enable_path("/chosen/environment-emmc"); diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr.h b/arch/arm/boards/nxp-imx8mq-evk/ddr.h index 65115dba1e..fd09ad6bf1 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr.h +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr.h @@ -8,7 +8,7 @@ */ #include <common.h> #include <io.h> -#include <mach/imx8-ddrc.h> +#include <soc/imx8m/ddr.h> /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -20,10 +20,3 @@ void nxp_imx8mq_evk_ddr_init(void); void nxp_imx8mq_evk_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin - - diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c index 39addea973..b1f752c4cb 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x15); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x48080707); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c index 1b30ff7257..bac7d0a517 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c @@ -11,6 +11,8 @@ void ddr_cfg_phy(void) { unsigned int tmp, tmp_t; + ddr_get_firmware(DRAM_TYPE_LPDDR4); + //Init DDRPHY register... reg32_write(0x3c080440,0x2); reg32_write(0x3c080444,0x3); @@ -142,7 +144,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); //configure DDRPHY-FW DMEM structure @clock0... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -187,7 +189,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //configure DDRPHY-FW DMEM structure @clock1... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -256,7 +258,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //set the PHY input clock to the desired frequency for pstate 0 reg32_write(0x3038a088,0x7070000); @@ -289,7 +291,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(FW_2D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); @@ -330,7 +332,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //Halt MPU reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -932,4 +934,4 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); //disable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg index 11463fe850..f82759f849 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg @@ -1,6 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 -#include <mach/habv4-imx8-gencsf.h> +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 9d060fb589..d1a517dddb 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -1,91 +1,63 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0 #include <common.h> +#include <firmware.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx8-ccm-regs.h> -#include <mach/iomux-mx8.h> -#include <mach/imx8-ddrc.h> -#include <mach/xload.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mq.h> +#include <soc/imx8m/ddr.h> +#include <mach/imx/xload.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/mmu.h> -#include <mach/atf.h> -#include <mach/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> #include "ddr.h" -extern char __dtb_imx8mq_evk_start[]; +extern char __dtb_z_imx8mq_evk_start[]; #define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); - imx8_uart_setup_ll(); + pbl_set_putc(imx_uart_putc, uart); putc_ll('>'); } -static void nxp_imx8mq_evk_sram_setup(void) -{ - ddr_init(); -} - /* * Power-on execution flow of start_nxp_imx8mq_evk() might not be * obvious for a very first read, so here's, hopefully helpful, * summary: * * 1. MaskROM uploads PBL into OCRAM and that's where this function is - * executed for the first time - * - * 2. DDR is initialized and the TF-A trampoline is installed in the - * DRAM. + * executed for the first time. At entry the exception level is EL3. * - * 3. TF-A is executed and exits into the trampoline in RAM, which enters the - * PBL for the second time. DRAM setup done is indicated by a one in register - * x0 by the trampoline + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. * - * 4. The piggydata is loaded from the SD card and copied to the expected - * location in the DRAM. + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. * - * 5. Standard barebox boot flow continues + * 4. Standard barebox boot flow continues */ static __noreturn noinline void nxp_imx8mq_evk_start(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - int ret = -ENOTSUPP; - const u8 *bl31; - size_t bl31_size; - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + setup_uart(); /* * If we are in EL3 we are running for the first time and need to @@ -93,27 +65,15 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void) * to DRAM in EL2. */ if (current_el() == 3) { - nxp_imx8mq_evk_sram_setup(); - get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); - /* - * On completion the TF-A will jump to MX8MQ_ATF_BL33_BASE_ADDR in - * EL2. Copy ourselves there. - */ - memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR, _text, __bss_start - _text); - imx8mq_atf_load_bl31(bl31, bl31_size); - /* not reached */ - } + ddr_init(); - imx8_get_boot_source(&src, &instance); + imx8mq_load_and_start_image_via_tfa(); + } - if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_load_piggy(instance); - else - BUG_ON(ret); /* * Standard entry we hit once we initialized both DDR and ATF */ - imx8mq_barebox_entry(__dtb_imx8mq_evk_start); + imx8mq_barebox_entry(__dtb_z_imx8mq_evk_start); } ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) diff --git a/arch/arm/boards/omap343xdsp/Makefile b/arch/arm/boards/omap343xdsp/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/omap343xdsp/Makefile +++ b/arch/arm/boards/omap343xdsp/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c index 2fd0dee194..ca1cf9c58c 100644 --- a/arch/arm/boards/omap343xdsp/board.c +++ b/arch/arm/boards/omap343xdsp/board.c @@ -1,19 +1,5 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2006-2008 Nishanth Menon <x0nishan@ti.com>, Texas Instruments (http://www.ti.com/) #include <common.h> #include <console.h> @@ -21,9 +7,9 @@ #include <driver.h> #include <io.h> #include <asm/armlinux.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-devices.h> -#include <mach/gpmc.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-devices.h> +#include <mach/omap/gpmc.h> #include <errno.h> /** diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c index fb99ea9278..3a8165f885 100644 --- a/arch/arm/boards/omap343xdsp/lowlevel.c +++ b/arch/arm/boards/omap343xdsp/lowlevel.c @@ -1,17 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/generic.h> -#include <mach/omap3-mux.h> -#include <mach/sdrc.h> -#include <mach/control.h> -#include <mach/syslib.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> -#include <mach/sys_info.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap3-mux.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/control.h> +#include <mach/omap/syslib.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/sys_info.h> /** * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0 diff --git a/arch/arm/boards/omap3evm/Makefile b/arch/arm/boards/omap3evm/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/omap3evm/Makefile +++ b/arch/arm/boards/omap3evm/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c index eefb540fc1..37dbc0044e 100644 --- a/arch/arm/boards/omap3evm/board.c +++ b/arch/arm/boards/omap3evm/board.c @@ -1,3 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2009 Sanjeev Premi <premi@ti.com>, Texas Instruments Incorporated (http://www.ti.com/) + /** * @file * @brief Board Initialization routines for OMAP3EVM. @@ -22,22 +25,6 @@ * Originally from arch/arm/boards/omap/board-beagle.c */ -/* - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * Sanjeev Premi <premi@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - - #include <common.h> #include <console.h> #include <init.h> @@ -45,12 +32,12 @@ #include <io.h> #include <linux/sizes.h> #include <asm/armlinux.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-mux.h> -#include <mach/gpmc.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-mux.h> +#include <mach/omap/gpmc.h> #include <errno.h> -#include <generated/mach-types.h> -#include <mach/omap3-devices.h> +#include <asm/mach-types.h> +#include <mach/omap/omap3-devices.h> /** * @brief Initialize the serial port to be used as console. diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c index e06ece2560..5797acc14e 100644 --- a/arch/arm/boards/omap3evm/lowlevel.c +++ b/arch/arm/boards/omap3evm/lowlevel.c @@ -1,16 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <io.h> #include <init.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/generic.h> -#include <mach/omap3-mux.h> -#include <mach/sdrc.h> -#include <mach/control.h> -#include <mach/syslib.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> -#include <mach/sys_info.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap3-mux.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/control.h> +#include <mach/omap/syslib.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/sys_info.h> /* diff --git a/arch/arm/boards/panda/Makefile b/arch/arm/boards/panda/Makefile index 5d4eb10b9b..3bd91350ce 100644 --- a/arch/arm/boards/panda/Makefile +++ b/arch/arm/boards/panda/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o mux.o diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c index a0a00782d3..55836d2331 100644 --- a/arch/arm/boards/panda/board.c +++ b/arch/arm/boards/panda/board.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <console.h> #include <init.h> @@ -5,14 +7,14 @@ #include <io.h> #include <gpio.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-devices.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/control.h> -#include <usb/ehci.h> +#include <asm/mach-types.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-devices.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/control.h> +#include <linux/usb/ehci.h> #include <linux/err.h> #include <linux/sizes.h> #include <asm/mmu.h> diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c index 006fb627dd..f535e7f9a4 100644 --- a/arch/arm/boards/panda/lowlevel.c +++ b/arch/arm/boards/panda/lowlevel.c @@ -1,37 +1,22 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) + #include <common.h> #include <init.h> #include <io.h> #include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-generic.h> -#include <mach/omap4-clock.h> -#include <mach/syslib.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-generic.h> +#include <mach/omap/omap4-clock.h> +#include <mach/omap/syslib.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#define TPS62361_VSEL0_GPIO 7 +#include "mux.h" -void set_muxconf_regs(void); +#define TPS62361_VSEL0_GPIO 7 static const struct ddr_regs ddr_regs_400_mhz_2cs = { /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ @@ -69,7 +54,7 @@ static void noinline panda_init_lowlevel(void) /* Enable all clocks */ omap4_enable_all_clocks(); - set_muxconf_regs(); + panda_set_muxconf_regs(); omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c index 8225aa615d..b5e1e79c8f 100644 --- a/arch/arm/boards/panda/mux.c +++ b/arch/arm/boards/panda/mux.c @@ -1,9 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-clock.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-clock.h> + +#include "mux.h" static const struct pad_conf_entry core_padconf_array[] = { { GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0 */ }, @@ -239,7 +243,7 @@ static const struct pad_conf_entry wkup_padconf_array[] = { { FREF_CLK4_OUT, M3 /* gpio_wk8 */ }, }; -void set_muxconf_regs(void) +void panda_set_muxconf_regs(void) { omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, ARRAY_SIZE(core_padconf_array)); diff --git a/arch/arm/boards/panda/mux.h b/arch/arm/boards/panda/mux.h new file mode 100644 index 0000000000..540d4e5d34 --- /dev/null +++ b/arch/arm/boards/panda/mux.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BOARD_MUX_H +#define __BOARD_MUX_H + +void panda_set_muxconf_regs(void); + +#endif /* __BOARD_MUX_H */ diff --git a/arch/arm/boards/phytec-phycard-imx27/Makefile b/arch/arm/boards/phytec-phycard-imx27/Makefile index 34492bb127..0e6411d588 100644 --- a/arch/arm/boards/phytec-phycard-imx27/Makefile +++ b/arch/arm/boards/phytec-phycard-imx27/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only lwl-y += lowlevel.o obj-y += pca100.o diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c index bd46df0962..a43406e1a2 100644 --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + /* * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia * Applications Processor Reference Manual, Rev. 0.2". @@ -10,10 +12,10 @@ #include <config.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <mach/imx27-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <mach/imx-nand.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/imx-pll.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/imx-nand.h> enum { PHYCARD_MICRON_64MB, @@ -77,7 +79,24 @@ static void sdram_init(int sdram) MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } -static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) +extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[]; + +static void __noreturn phytec_phycard_imx27_start(void) +{ + void *fdt; + + fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); + + imx27_barebox_entry(fdt); +} + +static void __noreturn phytec_phycard_imx27_load_nand(void) +{ + imx27_nand_load_image(); + phytec_phycard_imx27_start(); +} + +static noinline void __bare_init phytec_phycard_imx27_common_init(int sdram) { unsigned long r; @@ -92,7 +111,7 @@ static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0xa0000000 && r < 0xc0000000) - imx27_barebox_entry(fdt); + phytec_phycard_imx27_start(); /* 399 MHz */ writel(IMX_PLL_PD(0) | @@ -117,29 +136,20 @@ static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram_init(sdram); - imx27_barebox_boot_nand_external(fdt); + imx27_nand_relocate_to_sdram(phytec_phycard_imx27_load_nand); + phytec_phycard_imx27_start(); } -extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[]; - ENTRY_FUNCTION(start_phytec_phycard_imx27_64mb, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); - - phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_64MB); + phytec_phycard_imx27_common_init(PHYCARD_MICRON_64MB); } ENTRY_FUNCTION(start_phytec_phycard_imx27_128mb, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); - - phytec_phycard_imx27_common_init(fdt, PHYCARD_MICRON_128MB); + phytec_phycard_imx27_common_init(PHYCARD_MICRON_128MB); } diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c index 7184a59c71..d3a5598e96 100644 --- a/arch/arm/boards/phytec-phycard-imx27/pca100.c +++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c @@ -1,43 +1,28 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> #include <init.h> #include <environment.h> -#include <mach/imx27-regs.h> +#include <mach/imx/imx27-regs.h> #include <gpio.h> #include <linux/sizes.h> #include <asm/armlinux.h> #include <asm/sections.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <nand.h> #include <spi/spi.h> #include <io.h> -#include <mach/imx-nand.h> -#include <mach/imx-pll.h> -#include <mach/imxfb.h> +#include <mach/imx/imx-nand.h> +#include <mach/imx/imx-pll.h> +#include <platform_data/imxfb.h> #include <asm/mmu.h> -#include <usb/ulpi.h> -#include <mach/bbu.h> -#include <mach/iomux-mx27.h> -#include <mach/devices-imx27.h> +#include <linux/usb/ulpi.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iomux-mx27.h> #if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI) static void pca100_usb_register(void) diff --git a/arch/arm/boards/phytec-phycard-omap3/Makefile b/arch/arm/boards/phytec-phycard-omap3/Makefile index a71feec396..16f198b38c 100644 --- a/arch/arm/boards/phytec-phycard-omap3/Makefile +++ b/arch/arm/boards/phytec-phycard-omap3/Makefile @@ -1,18 +1,5 @@ -# (C) Copyright 2011 Juergen Kilb <j.kilb@phytec.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Juergen Kilb <j.kilb@phytec.de> obj-y += pca-a-l1.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c index 54d8eaaddf..56fbdf12ad 100644 --- a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c @@ -1,17 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <io.h> #include <init.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/omap3-mux.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/control.h> -#include <mach/syslib.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> -#include <mach/sys_info.h> +#include <mach/omap/omap3-mux.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/control.h> +#include <mach/omap/syslib.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/sys_info.h> /* Slower full frequency range default timings for x32 operation */ #define SDP_SDRC_SHARING 0x00000100 @@ -98,7 +100,7 @@ static void config_sdram_ddr(u8 cs, u8 cfg) static void pcaal1_sdrc_init(void) { u32 test0, test1; - char cfg; + signed char cfg; init_sdram_ddr(); diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c index 930f3b9c7c..d878dba082 100644 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + /** * @file * @brief Board Initialization routines for the phyCARD-A-L1 @@ -27,15 +29,6 @@ * based on code from Texas Instruments / board-beagle.c * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ * Sanjeev Premi <premi@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> @@ -44,19 +37,18 @@ #include <errno.h> #include <init.h> #include <nand.h> -#include <partition.h> #include <linux/sizes.h> #include <asm/armlinux.h> #include <asm/io.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <linux/err.h> -#include <mach/gpmc.h> -#include <mach/gpmc_nand.h> -#include <mach/omap_hsmmc.h> -#include <mach/sdrc.h> -#include <mach/omap3-silicon.h> -#include <mach/sys_info.h> -#include <mach/omap3-devices.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/gpmc_nand.h> +#include <mach/omap/omap_hsmmc.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/omap3-devices.h> #define SMC911X_BASE 0x2c000000 diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h index f6f8996697..7e7dadc587 100644 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h @@ -1,22 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) + /** * @file * @brief exported generic APIs which various board files implement * * This file will not contain any board specific implementations. - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef __BOARD_OMAP_H_ diff --git a/arch/arm/boards/phytec-phycard-omap4/Makefile b/arch/arm/boards/phytec-phycard-omap4/Makefile index 0fec0c7f53..0ac095becc 100644 --- a/arch/arm/boards/phytec-phycard-omap4/Makefile +++ b/arch/arm/boards/phytec-phycard-omap4/Makefile @@ -1,18 +1,6 @@ -# (C) Copyright 2012 Jan Weitzel <j.weitzel@phytec.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jan Weitzel <j.weitzel@phytec.de> + obj-y += pca-a-xl2.o lwl-y += mux.o lowlevel.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-phytec-phycard-omap4 diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c index c49c4ca841..b5906234d3 100644 --- a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c @@ -1,37 +1,22 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) + #include <common.h> #include <init.h> #include <io.h> #include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-generic.h> -#include <mach/omap4-clock.h> -#include <mach/syslib.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-generic.h> +#include <mach/omap/omap4-clock.h> +#include <mach/omap/syslib.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#define TPS62361_VSEL0_GPIO 7 +#include "mux.h" -void set_muxconf_regs(void); +#define TPS62361_VSEL0_GPIO 7 static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { .tim1 = 0x0EEB0662, @@ -57,7 +42,7 @@ static noinline void pcaaxl2_init_lowlevel(void) struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; unsigned int rev = omap4_revision(); - set_muxconf_regs(); + phycard_omap4_set_muxconf_regs(); omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.c b/arch/arm/boards/phytec-phycard-omap4/mux.c index a31d995767..a545ca5948 100644 --- a/arch/arm/boards/phytec-phycard-omap4/mux.c +++ b/arch/arm/boards/phytec-phycard-omap4/mux.c @@ -1,9 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-clock.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-clock.h> + +#include "mux.h" static const struct pad_conf_entry core_padconf_array[] = { {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ @@ -236,7 +240,7 @@ static const struct pad_conf_entry wkup_padconf_array[] = { {SYS_BOOT7, (M0)}, /* sys_boot7 */ }; -void set_muxconf_regs(void) +void phycard_omap4_set_muxconf_regs(void) { omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, ARRAY_SIZE(core_padconf_array)); diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.h b/arch/arm/boards/phytec-phycard-omap4/mux.h new file mode 100644 index 0000000000..46a2434ad0 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/mux.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BOARD_MUX_H +#define __BOARD_MUX_H + +void phycard_omap4_set_muxconf_regs(void); + +#endif /* __BOARD_MUX_H */ diff --git a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c index c0e4448a00..f18f11c331 100644 --- a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c +++ b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix #include <common.h> #include <console.h> @@ -21,21 +8,20 @@ #include <io.h> #include <gpio.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/omap4-silicon.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/control.h> +#include <asm/mach-types.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/control.h> #include <linux/err.h> #include <linux/sizes.h> -#include <partition.h> #include <nand.h> #include <asm/mmu.h> -#include <mach/gpmc.h> -#include <mach/gpmc_nand.h> -#include <mach/omap_hsmmc.h> -#include <mach/omap4-devices.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/gpmc_nand.h> +#include <mach/omap/omap_hsmmc.h> +#include <mach/omap/omap4-devices.h> #include <i2c/i2c.h> static int pcaaxl2_console_init(void) diff --git a/arch/arm/boards/phytec-phycore-imx27/Makefile b/arch/arm/boards/phytec-phycore-imx27/Makefile index 4723c77818..ce7b990407 100644 --- a/arch/arm/boards/phytec-phycore-imx27/Makefile +++ b/arch/arm/boards/phytec-phycore-imx27/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += pcm038.o pcm970.o lwl-y += lowlevel.o bbenv-y += defaultenv-pcm038 diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c index a9e296a0af..a42b30a7bb 100644 --- a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c @@ -1,28 +1,13 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + #include <common.h> #include <init.h> -#include <mach/imx27-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/imx-pll.h> +#include <mach/imx/esdctl.h> #include <io.h> -#include <mach/imx-nand.h> +#include <mach/imx/imx-nand.h> #include <asm/barebox-arm.h> #include <asm/system.h> #include <asm-generic/memory_layout.h> @@ -33,7 +18,24 @@ #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) -static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void *fdt) +extern char __dtb_imx27_phytec_phycore_rdk_start[]; + +static void __noreturn phytec_phycore_imx27_start(void) +{ + void *fdt; + + fdt = __dtb_imx27_phytec_phycore_rdk_start + get_runtime_offset(); + + imx27_barebox_entry(fdt); +} + +static void __noreturn phytec_phycore_imx27_load_nand(void) +{ + imx27_nand_load_image(); + phytec_phycore_imx27_start(); +} + +static void __bare_init noinline phytec_phycore_imx27_common_init(void) { uint32_t r; int i; @@ -49,7 +51,7 @@ static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); if (r > 0xa0000000 && r < 0xb0000000) - goto out; + phytec_phycore_imx27_start(); /* re-program the PLL prior(!) starting the SDRAM controller */ writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0); @@ -93,22 +95,13 @@ static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx27_barebox_boot_nand_external(fdt); - -out: - imx27_barebox_entry(fdt); + imx27_nand_relocate_to_sdram(phytec_phycore_imx27_load_nand); + phytec_phycore_imx27_start(); } -extern char __dtb_imx27_phytec_phycore_rdk_start[]; - ENTRY_FUNCTION(start_phytec_phycore_imx27, r0, r1, r2) { - void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); - fdt = __dtb_imx27_phytec_phycore_rdk_start + get_runtime_offset(); - - phytec_phycorce_imx27_common_init(fdt); + phytec_phycore_imx27_common_init(); } diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.c b/arch/arm/boards/phytec-phycore-imx27/pcm038.c index 008346faf1..879e94293c 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pcm038.c +++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #define pr_fmt(fmt) "pcm038: " fmt @@ -22,13 +11,12 @@ #include <notifier.h> #include <linux/sizes.h> #include <envfs.h> -#include <mach/devices-imx27.h> -#include <mach/imx-pll.h> -#include <mach/imx27-regs.h> -#include <mach/imxfb.h> -#include <mach/iomux-mx27.h> +#include <mach/imx/imx-pll.h> +#include <mach/imx/imx27-regs.h> +#include <platform_data/imxfb.h> +#include <mach/imx/iomux-mx27.h> #include <mfd/mc13xxx.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include "pll.h" @@ -117,7 +105,8 @@ static int pcm038_init(void) for (i = 0; i < ARRAY_SIZE(pcm038_pins); i++) imx27_gpio_mode(pcm038_pins[i]); - imx27_add_fb(&pcm038_fb_data); + add_generic_device("imxfb", -1, NULL, (resource_size_t)MX27_LCDC_BASE_ADDR, 0x1000, + IORESOURCE_MEM, &pcm038_fb_data); switch (bootsource_get()) { case BOOTSOURCE_NAND: diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm970.c b/arch/arm/boards/phytec-phycore-imx27/pcm970.c index b8faec0384..1e466e0ec8 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pcm970.c +++ b/arch/arm/boards/phytec-phycore-imx27/pcm970.c @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <gpio.h> @@ -17,8 +6,8 @@ #include <io.h> #include <platform_data/ide.h> #include <linux/sizes.h> -#include <mach/imx27-regs.h> -#include <mach/iomux-mx27.h> +#include <mach/imx/imx27-regs.h> +#include <mach/imx/iomux-mx27.h> #define GPIO_IDE_POWER (GPIO_PORTE + 18) #define GPIO_IDE_PCOE (GPIO_PORTF + 7) @@ -39,7 +28,7 @@ static struct ide_port_info pcm970_ide_pdata = { .reset = &pcm970_ide_reset, }; -static struct device_d pcm970_ide_device = { +static struct device pcm970_ide_device = { .id = DEVICE_ID_DYNAMIC, .name = "ide_intf", .num_resources = ARRAY_SIZE(pcm970_ide_resources), diff --git a/arch/arm/boards/phytec-phycore-imx27/pll.h b/arch/arm/boards/phytec-phycore-imx27/pll.h index 8bdb76d111..cb34de1136 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pll.h +++ b/arch/arm/boards/phytec-phycore-imx27/pll.h @@ -1,15 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later /** * @file diff --git a/arch/arm/boards/phytec-phycore-imx31/Makefile b/arch/arm/boards/phytec-phycore-imx31/Makefile deleted file mode 100644 index 6c9ca6942f..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel.o -obj-y += pcm037.o diff --git a/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi deleted file mode 100644 index d555a538d1..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand deleted file mode 100644 index 540277cdeb..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor deleted file mode 100644 index 940eb86c95..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c deleted file mode 100644 index b5f333987a..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/system.h> -#include <asm-generic/memory_layout.h> -#include <asm-generic/sections.h> -#include <asm/barebox-arm-head.h> -#include <mach/imx31-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> - -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - uint32_t r; - volatile int v; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE); - - writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); - - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); - - for (v = 0; v < 0x4000; v++); - - writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + - MX31_CCM_CCMR); - writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, - MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); - - writel(MX31_PDR0_CSI_PODF(0xff1) | \ - MX31_PDR0_PER_PODF(7) | \ - MX31_PDR0_HSP_PODF(3) | \ - MX31_PDR0_NFC_PODF(5) | \ - MX31_PDR0_IPG_PODF(1) | \ - MX31_PDR0_MAX_PODF(3) | \ - MX31_PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | - IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), - MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | - IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + - MX31_CCM_SPCTL); - - /* - * Configure IOMUXC - * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), - * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) - * (behaviour copied by sha, source unknown) - */ - writel(0, 0x43fac26c); - writel(0, 0x43fac270); - writel(0, 0x43fac274); - - writel(0x1000, 0x43fac27c); - - for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) - writel(0, r); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0xa0000000) - imx31_barebox_entry(NULL); - -#if defined CONFIG_PCM037_SDRAM_BANK0_128MB -#define ROWS0 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB -#define ROWS0 ESDCTL0_ROW14 -#endif - writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); - writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x12344321, MX31_CSD0_BASE_ADDR); - writel(0x12344321, MX31_CSD0_BASE_ADDR); - writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); - writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); - writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); - -#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE -#if defined CONFIG_PCM037_SDRAM_BANK1_128MB -#define ROWS1 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB -#define ROWS1 ESDCTL0_ROW14 -#endif - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1); - writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00); - writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writel(0x12344321, MX31_CSD1_BASE_ADDR); - writel(0x12344321, MX31_CSD1_BASE_ADDR); - writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33); - writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000); - writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR); - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); -#endif - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) - imx31_barebox_boot_nand_external(0); - else - imx31_barebox_entry(NULL); -} diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.c b/arch/arm/boards/phytec-phycore-imx31/pcm037.c deleted file mode 100644 index 39e7838be0..0000000000 --- a/arch/arm/boards/phytec-phycore-imx31/pcm037.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 - */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <fs.h> -#include <gpio.h> -#include <environment.h> -#include <usb/ulpi.h> -#include <mach/imx31-regs.h> -#include <mach/iomux-mx31.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <mach/weim.h> -#include <io.h> -#include <platform_data/eth-smc911x.h> -#include <asm/mmu.h> -#include <partition.h> -#include <generated/mach-types.h> -#include <asm/barebox-arm.h> -#include <mach/imx-nand.h> -#include <mach/devices-imx31.h> - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#ifdef CONFIG_USB -static void pcm037_usb_init(void) -{ - u32 tmp; - - /* enable clock */ - tmp = readl(0x53f80000); - tmp |= (1 << 9); - writel(tmp, 0x53f80000); - - /* Host 1 */ - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~((3 << 21) | 1); - tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184); - tmp &= ~(3 << 30); - tmp |= 2 << 30; - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184); - - imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0); - imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1); - imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2); - imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3); - imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4); - imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5); - imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6); - imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7); - imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK); - imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR); - imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT); - imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP); - - mdelay(50); - ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1); - - /* Host 2 */ - tmp = readl(MX31_IOMUXC_GPR); - tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */ - writel(tmp, MX31_IOMUXC_GPR); - - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~((3 << 21) | 1); - tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584); - tmp &= ~(3 << 30); - tmp |= 2 << 30; - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584); - - mdelay(50); - ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1); - - /* Set to Host mode */ - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8); - writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8); - -} -#endif - -static int pcm037_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(pcm037_mmu_init); - -static struct smc911x_plat smsc9217_pdata = { - .flags = SMC911X_FORCE_INTERNAL_PHY, -}; - -static int pcm037_devices_init(void) -{ - /* CS0: Nor Flash */ - imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - /* CS1: Network Controller */ - imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302); - /* CS4: SRAM */ - imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00); - /* CS5: SJA1000 */ - imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); - - /* - * Up to 32MiB NOR type flash, connected to - * CS line 0, data width is 16 bit - */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); - - imx31_add_mmc0(NULL); - - /* - * Create partitions that should be - * not touched by any regular user - */ - devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */ - devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */ - - protect_file("/dev/env0", 1); - - /* - * up to 2MiB static RAM type memory, connected - * to CS4, data width is 16 bit - */ - add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */ - IORESOURCE_MEM_WRITEABLE); - imx31_add_nand(&nand_info); - - /* - * SMSC 9217 network controller - * connected to CS line 1 and interrupt line - * GPIO3, data width is 16 bit - */ - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR, - MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata); - -#ifdef CONFIG_USB - pcm037_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL); -#endif - armlinux_set_architecture(MACH_TYPE_PCM037); - - return 0; -} - -device_initcall(pcm037_devices_init); - -static unsigned int pcm037_iomux[] = { - /* UART1 */ - MX31_PIN_RXD1__RXD1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - /* I2C */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - MX31_PIN_CSPI2_SS2__I2C3_SDA, - MX31_PIN_CSPI2_SCLK__I2C3_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ - /* SPI1 */ - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* UART2 */ - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - /* UART3 */ - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, -}; - -static int imx31_console_init(void) -{ - imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux)); - - barebox_set_model("Phytec phyCORE-i.MX31"); - barebox_set_hostname("phycore-imx31"); - - imx31_add_uart0(); - return 0; -} - -console_initcall(imx31_console_init); diff --git a/arch/arm/boards/phytec-phycore-imx35/Makefile b/arch/arm/boards/phytec-phycore-imx35/Makefile deleted file mode 100644 index 72275ead78..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel.o -obj-y += pcm043.o diff --git a/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi deleted file mode 100644 index d555a538d1..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand deleted file mode 100644 index c7185db7f7..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nand0.barebox),256k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor deleted file mode 100644 index 09c3ba9842..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg b/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg deleted file mode 100644 index 36b68cd7ee..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg +++ /dev/null @@ -1,37 +0,0 @@ -soc imx35 -dcdofs 0x400 -loadaddr 0x80000000 -wm 32 0x53f80004 0x00821000 -wm 32 0x53f80004 0x00821000 - -wm 32 0x43fac794 0x00000800 -wm 32 0x43fac798 0x00000800 -wm 32 0x43fac79c 0x00000800 -wm 32 0x43fac7a0 0x00000800 -wm 32 0x43fac7a4 0x00000800 - -wm 32 0xb8001010 0x00000304 -wm 32 0xb8001004 0x0025541f -wm 32 0xb8001000 0x92220000 -wm 32 0x80000400 0x12345678 - -wm 32 0xb8001000 0xb8001000 -wm 8 0x84000000 0xda -wm 8 0x86000000 0xda -wm 8 0x82000400 0xda -wm 8 0x80000333 0xda - -wm 32 0xb8001000 0x92220000 -wm 32 0x80000400 0x12345678 - -wm 32 0xb8001000 0xa2220000 -wm 32 0x80000000 0x12344321 -wm 32 0x80000000 0x12344321 -wm 32 0xb8001000 0xb2220000 -wm 8 0x80000233 0xda -wm 8 0x82000780 0xda -wm 8 0x82000400 0xda -wm 32 0xb8001000 0x82220080 -wm 32 0xb8001000 0x82228080 -wm 32 0xb8001008 0x00002000 - diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c deleted file mode 100644 index b80dafec16..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <common.h> -#include <init.h> -#include <mach/imx35-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/cache-l2x0.h> -#include <io.h> -#include <mach/imx-nand.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <asm/sections.h> -#include <asm-generic/memory_layout.h> -#include <asm/system.h> - -#define IMX35_CHIP_REVISION_2_1 0x11 - -#define CCM_PDR0_399 0x00011000 -#define CCM_PDR0_532 0x00001000 - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - uint32_t r, s; - unsigned long ccm_base = MX35_CCM_BASE_ADDR; - unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; - unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE); - - r = get_cr(); - r |= CR_Z; /* Flow prediction (Z) */ - r |= CR_U; /* unaligned accesses */ - r |= CR_FI; /* Low Int Latency */ - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); - s |= 0x7; - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); - - set_cr(r); - - r = 0; - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * Branch predicition is now enabled. Flush the BTAC to ensure a valid - * starting point. Don't flush BTAC while it is disabled to avoid - * ARM1136 erratum 408023. - */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); - - /* invalidate I cache and D cache */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); - - /* invalidate TLBs */ - __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); - - /* Drain the write buffer */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); - - /* Also setup the Peripheral Port Remap register inside the core */ - r = 0x40000015; /* start from AIPS 2GB region */ - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * End of ARM1136 init - */ - - writel(0x003F4208, ccm_base + MX35_CCM_CCMR); - - /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - - writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); - - /* Check silicon revision and use 532MHz if >=2.1 */ - r = readl(MX35_IIM_BASE_ADDR + 0x24); - if (r >= IMX35_CHIP_REVISION_2_1) - writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0); - else - writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); - - r = readl(ccm_base + MX35_CCM_CGR0); - r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR0); - - r = readl(ccm_base + MX35_CCM_CGR1); - r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; - writel(r, ccm_base + MX35_CCM_CGR1); - - r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - r |= 0x1000; - writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0x90000000) - goto out; - - /* Set DDR Type to SDRAM, drive strength workaround * - * 0x00000000 MDDR * - * 0x00000800 3,3V SDRAM */ - - r = 0x00000800; - writel(r, iomuxc_base + 0x794); - writel(r, iomuxc_base + 0x798); - writel(r, iomuxc_base + 0x79c); - writel(r, iomuxc_base + 0x7a0); - writel(r, iomuxc_base + 0x7a4); - - /* MDDR init, enable mDDR*/ - writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */ - - /* set timing paramters */ - writel(0x0025541F, esdctl_base + IMX_ESDCFG0); - /* select Precharge-All mode */ - writel(0x92220000, esdctl_base + IMX_ESDCTL0); - /* Precharge-All */ - writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); - - /* select Load-Mode-Register mode */ - writel(0xB8001000, esdctl_base + IMX_ESDCTL0); - /* Load reg EMR2 */ - writeb(0xda, 0x84000000); - /* Load reg EMR3 */ - writeb(0xda, 0x86000000); - /* Load reg EMR1 -- enable DLL */ - writeb(0xda, 0x82000400); - /* Load reg MR -- reset DLL */ - writeb(0xda, 0x80000333); - - /* select Precharge-All mode */ - writel(0x92220000, esdctl_base + IMX_ESDCTL0); - /* Precharge-All */ - writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); - - /* select Manual-Refresh mode */ - writel(0xA2220000, esdctl_base + IMX_ESDCTL0); - /* Manual-Refresh 2 times */ - writel(0x87654321, MX35_CSD0_BASE_ADDR); - writel(0x87654321, MX35_CSD0_BASE_ADDR); - - /* select Load-Mode-Register mode */ - writel(0xB2220000, esdctl_base + IMX_ESDCTL0); - /* Load reg MR -- CL3, BL8, end DLL reset */ - writeb(0xda, 0x80000233); - /* Load reg EMR1 -- OCD default */ - writeb(0xda, 0x82000780); - /* Load reg EMR1 -- OCD exit */ - writeb(0xda, 0x82000400); - - /* select normal-operation mode - * DSIZ32-bit, BL8, COL10-bit, ROW13-bit - * disable PWT & PRCT - * disable Auto-Refresh */ - writel(0x82220080, esdctl_base + IMX_ESDCTL0); - - /* enable Auto-Refresh */ - writel(0x82228080, esdctl_base + IMX_ESDCTL0); - /* enable Auto-Refresh */ - writel(0x00002000, esdctl_base + IMX_ESDCTL1); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - imx35_barebox_boot_nand_external(0); - } - -out: - imx35_barebox_entry(NULL); -} diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.c b/arch/arm/boards/phytec-phycore-imx35/pcm043.c deleted file mode 100644 index 65b592d0b5..0000000000 --- a/arch/arm/boards/phytec-phycore-imx35/pcm043.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for Phytec's, i.MX35 based CPU card, called: PCM043 - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <gpio.h> -#include <linux/sizes.h> -#include <mach/imx35-regs.h> -#include <asm/armlinux.h> -#include <io.h> -#include <partition.h> -#include <nand.h> -#include <generated/mach-types.h> -#include <mach/imx-nand.h> -#include <fb.h> -#include <led.h> -#include <bootsource.h> -#include <asm/mmu.h> -#include <mach/weim.h> -#include <mach/imx-ipu-fb.h> -#include <mach/imx-pll.h> -#include <mach/iomux-mx35.h> -#include <mach/devices-imx35.h> -#include <mach/generic.h> -#include <mach/bbu.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct fb_videomode pcm043_fb_mode[] = { - { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - }, { - /* 240x320 @ 60 Hz */ - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | \ - FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - } -}; - -static struct imx_ipu_fb_platform_data ipu_fb_data = { - .mode = pcm043_fb_mode, - .num_modes = ARRAY_SIZE(pcm043_fb_mode), - .framebuffer_ovl = (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M), - .bpp = 16, -}; - -static int pcm043_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(pcm043_mmu_init); - -struct gpio_led led0 = { - .gpio = 1 * 32 + 6, -}; - -static int pcm043_devices_init(void) -{ - uint32_t reg; - char *envstr; - unsigned long bbu_nand_flags = 0; - - /* CS0: Nor Flash */ - imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900); - - led_gpio_register(&led0); - - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); - /* some fuses provide us vital information about connected hardware */ - if (reg & 0x20000000) - nand_info.width = 2; /* 16 bit */ - else - nand_info.width = 1; /* 8 bit */ - - imx35_add_fec(&fec_info); - /* - * This platform supports NOR and NAND - */ - imx35_add_nand(&nand_info); - /* - * Up to 32MiB NOR type flash, connected to - * CS line 0, data width is 16 bit - */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); - - switch (bootsource_get()) { - case BOOTSOURCE_NAND: - devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - envstr = "NAND"; - bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT; - break; - case BOOTSOURCE_NOR: - default: - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */ - devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */ - protect_file("/dev/env0", 1); - envstr = "NOR"; - break; - } - - pr_info("using environment from %s flash\n", envstr); - - imx35_add_fb(&ipu_fb_data); - - armlinux_set_architecture(MACH_TYPE_PCM043); - - imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox", - bbu_nand_flags); - - return 0; -} - -device_initcall(pcm043_devices_init); - -static iomux_v3_cfg_t pcm043_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - MX35_PAD_RXD1__UART1_RXD_MUX, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - MX35_PAD_ATA_CS0__GPIO2_6, /* LED */ -}; - -static int imx35_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - - barebox_set_model("Phytec phyCORE-i.MX35"); - barebox_set_hostname("phycore-imx35"); - - imx35_add_uart0(); - - return 0; -} - -console_initcall(imx35_console_init); - -static int pcm043_core_setup(void) -{ - u32 tmp; - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - writel(0x40, MX35_M3IF_BASE_ADDR); - - return 0; -} - -core_initcall(pcm043_core_setup); - -static int do_cpufreq(int argc, char *argv[]) -{ - unsigned long freq; - - if (argc != 2) - return COMMAND_ERROR_USAGE; - - freq = simple_strtoul(argv[1], NULL, 0); - - switch (freq) { - case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - default: - return COMMAND_ERROR_USAGE; - } - - printf("Switched CPU frequency to %luMHz\n", freq); - - return 0; -} - -BAREBOX_CMD_START(cpufreq) - .cmd = do_cpufreq, - BAREBOX_CMD_DESC("adjust CPU frequency") - BAREBOX_CMD_OPTS("399|532") - BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) -BAREBOX_CMD_END - diff --git a/arch/arm/boards/phytec-phycore-imx7/Makefile b/arch/arm/boards/phytec-phycore-imx7/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/phytec-phycore-imx7/Makefile +++ b/arch/arm/boards/phytec-phycore-imx7/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phycore-imx7/board.c b/arch/arm/boards/phytec-phycore-imx7/board.c index c3ebd1fadf..4d8b938f17 100644 --- a/arch/arm/boards/phytec-phycore-imx7/board.c +++ b/arch/arm/boards/phytec-phycore-imx7/board.c @@ -1,29 +1,17 @@ -/* - * Copyright (C) 2017 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Sascha Hauer, Pengutronix #include <common.h> #include <init.h> #include <environment.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <mach/generic.h> +#include <asm/mach-types.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #include <asm/psci.h> #include <io.h> -#include <mach/imx7-regs.h> +#include <mach/imx/imx7-regs.h> #include <serial/imx-uart.h> #include <asm/secure.h> diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index 6e08b6c1b1..03cdbe8bc8 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -11,9 +11,9 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx7-ddr-regs.h> +#include <mach/imx/imx7-ddr-regs.h> wm 32 0x30340004 0x4F400005 /* Clear then set bit30 to ensure exit from DDR retention */ diff --git a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c index 3d2038e4a8..1f3c08ac62 100644 --- a/arch/arm/boards/phytec-phycore-imx7/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx7/lowlevel.c @@ -1,11 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #define DEBUG #include <io.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> extern char __dtb_imx7d_phyboard_zeta_start[]; diff --git a/arch/arm/boards/phytec-phycore-omap4460/Makefile b/arch/arm/boards/phytec-phycore-omap4460/Makefile index 5e78e11ec1..c5d3950bc3 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/Makefile +++ b/arch/arm/boards/phytec-phycore-omap4460/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o mux.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-phytec-phycore-omap4460 diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c index b7aeeca6df..2a176f156e 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/board.c +++ b/arch/arm/boards/phytec-phycore-omap4460/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix #include <common.h> #include <console.h> @@ -22,22 +9,21 @@ #include <io.h> #include <envfs.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-devices.h> -#include <mach/omap4-clock.h> -#include <mach/omap-fb.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/control.h> +#include <asm/mach-types.h> +#include <mach/omap/devices.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-devices.h> +#include <mach/omap/omap4-clock.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/control.h> #include <linux/err.h> #include <linux/sizes.h> -#include <partition.h> #include <nand.h> #include <asm/mmu.h> -#include <mach/gpmc.h> -#include <mach/gpmc_nand.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/gpmc_nand.h> #include <i2c/i2c.h> static int pcm049_console_init(void) @@ -305,8 +291,7 @@ static int pcm049_devices_init(void) armlinux_set_architecture(MACH_TYPE_PCM049); - if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP)) - omap_add_display(&pcm049_fb_data); + omap_add_display(&pcm049_fb_data); if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) defaultenv_append_directory(defaultenv_phytec_phycore_omap4460); diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c index 6511dae9d4..17194c6562 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -1,34 +1,21 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) + #include <common.h> #include <init.h> #include <io.h> #include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-generic.h> -#include <mach/omap4-clock.h> -#include <mach/syslib.h> +#include <mach/omap/generic.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-generic.h> +#include <mach/omap/omap4-clock.h> +#include <mach/omap/syslib.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> +#include "mux.h" + #define TPS62361_VSEL0_GPIO 182 #define LPDDR2_2G 0x5 #define LPDDR2_4G 0x6 @@ -38,8 +25,6 @@ #define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050 #define EMIF_LPDDR2_MODE_REG_DATA 0x0040 -void set_muxconf_regs(void); - /* 512MB */ static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { .tim1 = 0x0EEB0662, @@ -94,7 +79,7 @@ static void noinline pcm049_init_lowlevel(void) struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; unsigned int rev = omap4_revision(); - set_muxconf_regs(); + phycore_omap4460_set_muxconf_regs(); if (IS_ENABLED(CONFIG_1024MB_DDR2RAM)) { omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.c b/arch/arm/boards/phytec-phycore-omap4460/mux.c index fda4c519b8..287c2a4826 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/mux.c +++ b/arch/arm/boards/phytec-phycore-omap4460/mux.c @@ -1,9 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-mux.h> -#include <mach/omap4-clock.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/omap4-clock.h> + +#include "mux.h" static const struct pad_conf_entry core_padconf_array[] = { {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ @@ -236,7 +240,7 @@ static const struct pad_conf_entry wkup_padconf_array[] = { {SYS_BOOT7, (M0)}, /* sys_boot7 */ }; -void set_muxconf_regs(void) +void phycore_omap4460_set_muxconf_regs(void) { omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, ARRAY_SIZE(core_padconf_array)); diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.h b/arch/arm/boards/phytec-phycore-omap4460/mux.h new file mode 100644 index 0000000000..c84ecd32c8 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/mux.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BOARD_MUX_H +#define __BOARD_MUX_H + +void phycore_omap4460_set_muxconf_regs(void); + +#endif /* __BOARD_MUX_H */ diff --git a/arch/arm/boards/phytec-phycore-pxa270/Makefile b/arch/arm/boards/phytec-phycore-pxa270/Makefile index 040cf93944..e00d1cfd7f 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/Makefile +++ b/arch/arm/boards/phytec-phycore-pxa270/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/phytec-phycore-pxa270/board.c b/arch/arm/boards/phytec-phycore-pxa270/board.c index 1424c9c937..0283659a4e 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/board.c +++ b/arch/arm/boards/phytec-phycore-pxa270/board.c @@ -1,40 +1,23 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * 2010 by Marc Kleine-Budde <kernel@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix +// SPDX-FileCopyrightText: 2010 Marc Kleine-Budde <kernel@pengutronix.de> #include <common.h> #include <driver.h> #include <environment.h> #include <fs.h> #include <init.h> -#include <partition.h> #include <linux/sizes.h> #include <gpio.h> -#include <mach/mfp-pxa27x.h> -#include <mach/pxa-regs.h> -#include <mach/pxafb.h> -#include <mach/devices.h> +#include <mach/pxa/mfp-pxa27x.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/pxafb.h> +#include <mach/pxa/devices.h> #include <asm/armlinux.h> #include <asm/io.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <asm/mmu.h> #define PCM990_CTRL_PHYS (void *)PXA_CS1_PHYS diff --git a/arch/arm/boards/phytec-phycore-pxa270/config.h b/arch/arm/boards/phytec-phycore-pxa270/config.h index ca02b1140b..6aba53edea 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/config.h +++ b/arch/arm/boards/phytec-phycore-pxa270/config.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Copyright (C) 2005 Phytec Messtechnik GmbH * Juergen Kilb, H. Klaholz <armlinux@phytec.de> @@ -5,18 +7,6 @@ * Copyright (C) 2006 Pengutronix * Sascha Hauer <s.hauer@pengutronix.de> * Robert Schwebel <r.schwebel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #ifndef __CONFIG_H diff --git a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S index 39af00b54b..f8f1a037e0 100644 --- a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S +++ b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * This was originally from the Lubbock u-boot port. * @@ -7,28 +9,15 @@ * running. See hal_platform_setup.h for the source. See * board/cradle/lowlevel_init.S for another PXA250 setup that is * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <config.h> #include <linux/sizes.h> -#include <mach/pxa-regs.h> -#include <mach/regs-ost.h> -#include <mach/regs-intc.h> +#include <mach/pxa/pxa-regs.h> +#include <mach/pxa/regs-ost.h> +#include <mach/pxa/regs-intc.h> #include <asm/barebox-arm-head.h> +#include "config.h" #define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO <31:00> */ #define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO <63:32> */ diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/Makefile b/arch/arm/boards/phytec-phycore-stm32mp1/Makefile new file mode 100644 index 0000000000..1d052d28c9 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-stm32mp1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/board.c b/arch/arm/boards/phytec-phycore-stm32mp1/board.c new file mode 100644 index 0000000000..6690e36ca7 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-stm32mp1/board.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include <common.h> +#include <driver.h> +#include <bootsource.h> +#include <mach/stm32mp/bbu.h> + +static int phycore_stm32mp1_probe(struct device *dev) +{ + int sd_bbu_flags = 0, emmc_bbu_flags = 0; + + if (bootsource_get_instance() == 0) { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flags = BBU_HANDLER_FLAG_DEFAULT; + } + + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", sd_bbu_flags); + stm32mp_bbu_mmc_fip_register("emmc", "/dev/mmc1", emmc_bbu_flags); + + barebox_set_hostname("phyCORE-STM32MP1"); + + return 0; +} + +static const struct of_device_id phycore_stm32mp1_of_match[] = { + { .compatible = "phytec,phycore-stm32mp1-3" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, phycore_stm32mp1_of_match); + +static struct driver phycore_stm32mp1_board_driver = { + .name = "board-phycore-stm32mp1", + .probe = phycore_stm32mp1_probe, + .of_compatible = phycore_stm32mp1_of_match, +}; +device_platform_driver(phycore_stm32mp1_board_driver); diff --git a/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c b/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c new file mode 100644 index 0000000000..8174e060af --- /dev/null +++ b/arch/arm/boards/phytec-phycore-stm32mp1/lowlevel.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/stm32mp/entry.h> +#include <debug_ll.h> + +extern char __dtb_z_stm32mp157c_phycore_stm32mp1_3_start[]; + +ENTRY_FUNCTION(start_phycore_stm32mp1_3, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + putc_ll('>'); + + fdt = __dtb_z_stm32mp157c_phycore_stm32mp1_3_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} diff --git a/arch/arm/boards/phytec-som-am335x/Kconfig b/arch/arm/boards/phytec-som-am335x/Kconfig index 52fa723a21..054a1d219f 100644 --- a/arch/arm/boards/phytec-som-am335x/Kconfig +++ b/arch/arm/boards/phytec-som-am335x/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only if MACH_PHYTEC_SOM_AM335X diff --git a/arch/arm/boards/phytec-som-am335x/Makefile b/arch/arm/boards/phytec-som-am335x/Makefile index 78397bd59f..82dd631c9f 100644 --- a/arch/arm/boards/phytec-som-am335x/Makefile +++ b/arch/arm/boards/phytec-som-am335x/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o bbenv-y += defaultenv-physom-am335x diff --git a/arch/arm/boards/phytec-som-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c index c25f33ae20..f3caa5d50a 100644 --- a/arch/arm/boards/phytec-som-am335x/board.c +++ b/arch/arm/boards/phytec-som-am335x/board.c @@ -1,21 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Wadim Egorov, PHYTEC Messtechnik GmbH + /* - * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH - * * Device initialization for the following modules and board variants: * - phyCORE: PCM-953, phyBOARD-MAIA, phyBOARD-WEGA * - phyFLEX: PBA-B-01 * - phyCARD: PCA-A-XS1 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <bootsource.h> @@ -28,12 +18,12 @@ #include <envfs.h> #include <state.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <linux/phy.h> #include <linux/micrel_phy.h> -#include <mach/am33xx-generic.h> -#include <mach/am33xx-silicon.h> -#include <mach/bbu.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/bbu.h> static int physom_coredevice_init(void) { diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index a028449fc0..267f30b638 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Wadim Egorov, PHYTEC Messtechnik GmbH #include <common.h> #include <linux/sizes.h> @@ -19,16 +7,16 @@ #include <init.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/am33xx-mux.h> -#include <mach/am33xx-generic.h> -#include <mach/wdt.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/am33xx-mux.h> +#include <mach/omap/am33xx-generic.h> #include <debug_ll.h> +#include <mach/omap/debug_ll.h> #include "ram-timings.h" @@ -148,15 +136,7 @@ static noinline void physom_board_init(void *fdt, int sdram, int module_family) struct am335x_sdram_timings *timing = NULL; u32 ramsize; - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - - writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400); @@ -184,7 +164,7 @@ static noinline void physom_board_init(void *fdt, int sdram, int module_family) am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); am33xx_enable_uart0_pin_mux(); - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); + omap_debug_ll_init(); putc_ll('>'); am335x_barebox_entry(fdt); diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h index d1947b588e..8a9bd32beb 100644 --- a/arch/arm/boards/phytec-som-am335x/ram-timings.h +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2015 Wadim Egorov, PHYTEC Messtechnik GmbH #ifndef __RAM_TIMINGS_H #define __RAM_TIMINGS_H diff --git a/arch/arm/boards/phytec-som-imx6/Makefile b/arch/arm/boards/phytec-som-imx6/Makefile index 73456aed8b..0780da79b9 100644 --- a/arch/arm/boards/phytec-som-imx6/Makefile +++ b/arch/arm/boards/phytec-som-imx6/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-physom-imx6 diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 27a1ad4f66..2db3fa1db8 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -1,23 +1,9 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * Copyright (C) 2015 PHYTEC Messtechnik GmbH, - * Author: Stefan Christ <s.christ@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2015 PHYTEC Messtechnik GmbH + +/* Author: Stefan Christ <s.christ@phytec.de> */ + #define pr_fmt(fmt) "phySOM-i.MX6: " fmt #include <malloc.h> @@ -28,16 +14,17 @@ #include <gpio.h> #include <init.h> #include <of.h> +#include <deep-probe.h> #include <i2c/i2c.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <platform_data/eth-fec.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <linux/micrel_phy.h> #include <globalvar.h> -#include <mach/iomux-mx6.h> -#include <mach/imx6.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/imx6.h> #define PHYFLEX_MODULE_REV_1 0x1 #define PHYFLEX_MODULE_REV_2 0x2 @@ -120,10 +107,14 @@ static int phycore_da9062_setup_buck_mode(void) unsigned char value; int ret; - pmic_np = of_find_node_by_name(NULL, "pmic@58"); + pmic_np = of_find_node_by_name_address(NULL, "pmic@58"); if (!pmic_np) return -ENODEV; + ret = of_device_ensure_probed(pmic_np); + if (ret) + return ret; + adapter = of_find_i2c_adapter_by_node(pmic_np->parent); if (!adapter) return -ENODEV; @@ -155,15 +146,29 @@ err_out: return ret; } -static int physom_imx6_devices_init(void) +#define IS_PHYFLEX BIT(0) +#define IS_PHYCORE BIT(1) +#define IS_PHYCARD BIT(2) +#define IS_PHYCORE_UL BIT(3) +#define HAS_MMC3 BIT(4) +#define HAS_MMC1 BIT(5) + +struct board_data { + unsigned flags; +}; + +static int physom_imx6_probe(struct device *dev) { int ret; char *environment_path, *default_environment_path; char *envdev, *default_envdev; + const struct board_data *brd = device_get_match_data(dev); + unsigned flags = brd->flags; - if (of_machine_is_compatible("phytec,imx6q-pfla02") - || of_machine_is_compatible("phytec,imx6dl-pfla02") - || of_machine_is_compatible("phytec,imx6s-pfla02")) { + if (flags & IS_PHYFLEX) { + ret = of_devices_ensure_probed_by_property("gpio-controller"); + if (ret) + return ret; phyflex_err006282_workaround(); @@ -175,18 +180,17 @@ static int physom_imx6_devices_init(void) default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; - } else if (of_machine_is_compatible("phytec,imx6q-pcaaxl3")) { + imx6_bbu_internal_mmc_register_handler("mmc2", + "/dev/mmc2", 0); + } else if (flags & IS_PHYCARD) { barebox_set_hostname("phyCARD-i.MX6"); default_environment_path = "/chosen/environment-nand"; default_envdev = "NAND flash"; - } else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") - || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") - || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") - || of_machine_is_compatible("phytec,imx6qp-pcm058-nand") - || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { - + imx6_bbu_internal_mmc_register_handler("mmc2", + "/dev/mmc2", 0); + } else if (flags & IS_PHYCORE) { if (phycore_da9062_setup_buck_mode()) pr_err("Setting PMIC BUCK mode failed\n"); @@ -194,8 +198,10 @@ static int physom_imx6_devices_init(void) default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; - } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand") - || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) { + imx6_bbu_internal_mmc_register_handler("mmc0", + "/dev/mmc0", 0); + + } else if (flags & IS_PHYCORE_UL) { barebox_set_hostname("phyCORE-i.MX6UL"); default_environment_path = "/chosen/environment-nand"; default_envdev = "NAND flash"; @@ -203,8 +209,12 @@ static int physom_imx6_devices_init(void) phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, ksz8081_phy_fixup); - } else - return 0; + imx6_bbu_internal_mmc_register_handler("mmc0", + "/dev/mmc0", 0); + + } else { + return -EINVAL; + } switch (bootsource_get()) { case BOOTSOURCE_MMC: @@ -221,7 +231,7 @@ static int physom_imx6_devices_init(void) envdev = "SPI NOR flash"; break; default: - environment_path = basprintf(default_environment_path); + environment_path = strdup(default_environment_path); envdev = default_envdev; break; } @@ -236,15 +246,18 @@ static int physom_imx6_devices_init(void) pr_notice("Using environment in %s\n", envdev); - if (of_machine_is_compatible("phytec,imx6q-pcm058-emmc") - || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { + if (flags & HAS_MMC3) { imx6_bbu_internal_mmc_register_handler("mmc3", "/dev/mmc3", BBU_HANDLER_FLAG_DEFAULT); - } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) { + imx6_bbu_internal_mmcboot_register_handler("mmc3-boot", + "mmc3", 0); + } else if (flags & HAS_MMC1) { imx6_bbu_internal_mmc_register_handler("mmc1", "/dev/mmc1", BBU_HANDLER_FLAG_DEFAULT); + imx6_bbu_internal_mmcboot_register_handler("mmc1-boot", + "mmc1", 0); } else { imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); } @@ -252,23 +265,107 @@ static int physom_imx6_devices_init(void) defaultenv_append_directory(defaultenv_physom_imx6); /* Overwrite file /env/init/automount */ - if (of_machine_is_compatible("phytec,imx6q-pfla02") - || of_machine_is_compatible("phytec,imx6dl-pfla02") - || of_machine_is_compatible("phytec,imx6s-pfla02") - || of_machine_is_compatible("phytec,imx6q-pcaaxl3")) { + if (flags & IS_PHYCARD || flags & IS_PHYFLEX) { defaultenv_append_directory(defaultenv_physom_imx6); - } else if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand") - || of_machine_is_compatible("phytec,imx6q-pcm058-nand") - || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") - || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") - || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { + } else if (flags & IS_PHYCORE) { defaultenv_append_directory(defaultenv_physom_imx6); defaultenv_append_directory(defaultenv_physom_imx6_phycore); - } else if (of_machine_is_compatible("phytec,imx6ul-pcl063-nand") - || of_machine_is_compatible("phytec,imx6ul-pcl063-emmc")) { + } else if (flags & IS_PHYCORE_UL) { defaultenv_append_directory(defaultenv_physom_imx6ul_phycore); } return 0; } -device_initcall(physom_imx6_devices_init); + +static struct board_data imx6q_pfla02 = { + .flags = IS_PHYFLEX, +}; + +static struct board_data imx6dl_pfla02 = { + .flags = IS_PHYFLEX, +}; + +static struct board_data imx6s_pfla02 = { + .flags = IS_PHYFLEX, +}; + +static struct board_data imx6q_pcaaxl3 = { + .flags = IS_PHYCARD, +}; + +static struct board_data imx6q_pcm058_nand = { + .flags = IS_PHYCORE, +}; + +static struct board_data imx6q_pcm058_emmc = { + .flags = IS_PHYCORE | HAS_MMC3, +}; + +static struct board_data imx6dl_pcm058_nand = { + .flags = IS_PHYCORE, +}; + +static struct board_data imx6qp_pcm058_nand = { + .flags = IS_PHYCORE, +}; + +static struct board_data imx6dl_pcm058_emmc = { + .flags = IS_PHYCORE | HAS_MMC3, +}; + +static struct board_data imx6ul_pcl063_nand = { + .flags = IS_PHYCORE_UL, +}; + +static struct board_data imx6ul_pcl063_emmc = { + .flags = IS_PHYCORE_UL | HAS_MMC1, +}; + + +static const struct of_device_id physom_imx6_match[] = { + { + .compatible = "phytec,imx6q-pfla02", + .data = &imx6q_pfla02, + }, { + .compatible = "phytec,imx6dl-pfla02", + .data = &imx6dl_pfla02, + }, { + .compatible = "phytec,imx6s-pfla02", + .data = &imx6s_pfla02, + }, { + .compatible = "phytec,imx6q-pcaaxl3", + .data = &imx6q_pcaaxl3, + }, { + .compatible = "phytec,imx6q-pcm058-nand", + .data = &imx6q_pcm058_nand, + }, { + .compatible = "phytec,imx6q-pcm058-emmc", + .data = &imx6q_pcm058_emmc, + }, { + .compatible = "phytec,imx6dl-pcm058-nand", + .data = &imx6dl_pcm058_nand, + }, { + .compatible = "phytec,imx6qp-pcm058-nand", + .data = &imx6qp_pcm058_nand, + }, { + .compatible = "phytec,imx6dl-pcm058-emmc", + .data = &imx6dl_pcm058_emmc, + }, { + .compatible = "phytec,imx6ul-pcl063-nand", + .data = &imx6ul_pcl063_nand, + }, { + .compatible = "phytec,imx6ul-pcl063-emmc", + .data = &imx6ul_pcl063_emmc, + }, + { /* Sentinel */ }, +}; + +static struct driver physom_imx6_driver = { + .name = "physom-imx6", + .probe = physom_imx6_probe, + .of_compatible = physom_imx6_match, +}; + +postcore_platform_driver(physom_imx6_driver); + +BAREBOX_DEEP_PROBE_ENABLE(physom_imx6_match); diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource index 515613b041..fa5f7f26c5 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource @@ -12,7 +12,7 @@ if [ $bootsource = mmc ]; then fi elif [ $bootsource = nand ]; then global.boot.default="nand spi emmc mmc net" -elif [ $bootsource = spi ]; then +elif [ $bootsource = spi-nor ]; then global.boot.default="spi nand emmc mmc net" elif [ $bootsource = net ]; then global.boot.default="net nand spi emmc mmc" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi index 2000a16a12..8fb71f569b 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi @@ -1,5 +1,5 @@ #!/bin/sh -global.bootm.image="/dev/m25p0.kernel" -global.bootm.oftree="/dev/m25p0.oftree" +global.bootm.image="/dev/m25p0.nor.kernel" +global.bootm.oftree="/dev/m25p0.nor.oftree" global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource index 3f2ff4bcc8..9c9f0ec381 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource @@ -8,7 +8,7 @@ if [ $bootsource = mmc ]; then global.boot.default="mmc nand spi net" elif [ $bootsource = nand ]; then global.boot.default="nand spi mmc net" -elif [ $bootsource = spi ]; then +elif [ $bootsource = spi-nor ]; then global.boot.default="spi nand mmc net" elif [ $bootsource = net ]; then global.boot.default="net nand spi mmc" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg index 62a24ed0df..3b3e290fbe 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x54597955; \ @@ -7,3 +9,4 @@ wm 32 0x021b0000 0x831a0000 #include "flash-header-phytec-pcaaxl3.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg index bab726d147..4c8c527043 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x3a3f7975; \ @@ -7,3 +9,4 @@ wm 32 0x021b0000 0xc21a0000 #include "flash-header-phytec-pcaaxl3.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg index 512f6cbd47..a2f932e12a 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x54597955; \ @@ -7,3 +9,4 @@ wm 32 0x021b0000 0xc31a0000 #include "flash-header-phytec-pcaaxl3.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h index 06ba308fb8..c6cd180176 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h index c4122d245d..c7ee1aaeeb 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ #define SETUP_MDCFG0 \ wm 32 0x021B000C 0x676B52F3 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h index 5401e4243e..9847954693 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h @@ -1,7 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 + +wm 32 0x020c8140 0x00580012 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg new file mode 100644 index 0000000000..1a987c2c1f --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ul-512mb.imxcfg @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "flash-header-phytec-pcl063-512mb.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg index 4a827e4dfa..f519abf1a0 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-256mb.imxcfg @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only #define SETUP_MDCFG0 \ wm 32 0x021B000C 0x676B52F3 @@ -7,3 +8,4 @@ wm 32 0x021B0000 0x83180000 #include "flash-header-phytec-pcl063.h" +#include <mach/imx/habv4-imx6ull-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg new file mode 100644 index 0000000000..6935bd2ef3 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063ull-512mb.imxcfg @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +#include "flash-header-phytec-pcl063-512mb.h" +#include <mach/imx/habv4-imx6ull-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg index 5df46b9ff4..131e08cf4b 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x555A7955 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x831A0000 #include "flash-header-phytec-pcm058.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg index 54c9e41d28..be638ab1c1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x8c929b85 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x841A0000 #include "flash-header-phytec-pcm058.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h index 8b83aeae63..eaa2a3da6e 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg index bf95d0f6ae..83f8480bfe 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x8c929b85 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x84190000 #include "flash-header-phytec-pcm058dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg index f047253084..708e5bb21d 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x555A7955 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x831A0000 #include "flash-header-phytec-pcm058dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg index bf50190c78..be3cd5a20d 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x3c409b85 @@ -6,3 +8,5 @@ wm 32 0x021b0000 0x82190000 #include "flash-header-phytec-pcm058dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> + diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg new file mode 100644 index 0000000000..4fcf36990d --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-512mb.imxcfg @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3c409b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0x83190000 + +#include "flash-header-phytec-pcm058dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h index da4708e4e3..2d90faad4c 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg index bf85f0a19c..e15d220428 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x555A7955 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x831A0000 #include "flash-header-phytec-pcm058qp.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h index 6e7b740a6f..aae646e75c 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 /* NOC setup */ wm 32 0x00bb0008 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg index 75dc982432..48b1321b51 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x565c9b85 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x831a0000 #include "flash-header-phytec-pfla02.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg index 1f1fbe542c..8bd6a83786 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x3c409b85 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0xc21a0000 #include "flash-header-phytec-pfla02.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg index aa01c056be..fe2fa2c637 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x565c9b85 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0xC31A0000 #include "flash-header-phytec-pfla02.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg index c8d33cfacc..6f8645c4e6 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x8c929b85 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0xC41A0000 #include "flash-header-phytec-pfla02.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg index d6bbe1f1c3..edafe2d47c 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x555a7975 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x821a0000 #include "flash-header-phytec-pfla02.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h index c5ed9b759f..26a9341dda 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg index 7b64e5d2fd..553ba8d40a 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x41447525 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x831a0000 #include "flash-header-phytec-pfla02dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg index 04c489d7e8..5c37061853 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x2d307525 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0xc21a0000 #include "flash-header-phytec-pfla02dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index b0f3faa0b7..537a93eda9 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg index ebe5a968b1..331692af49 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x2D307525 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x82180000 #include "flash-header-phytec-pfla02dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg index 5f1585a40b..bd830865ec 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x2D307525 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x82190000 #include "flash-header-phytec-pfla02dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg index 5ff3ec69d7..7e57e7cd9e 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x41447525 @@ -6,3 +8,4 @@ wm 32 0x021b0000 0x83190000 #include "flash-header-phytec-pfla02dl.h" +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 2de84169c6..da5665a716 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -1,20 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> +// SPDX-FileCopyrightText: 2015 PHYTEC Messtechnik GmbH + /* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * Copyright (C) 2015 PHYTEC Messtechnik GmbH, * Author: Stefan Christ <s.christ@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -24,7 +16,7 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6.h> +#include <mach/imx/imx6.h> static inline void setup_uart(void) { @@ -84,15 +76,14 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, extern char __dtb_##fdt_name##_start[]; \ \ IMD_USED(physom_mx6_memsize_##memory_size); \ - IMD_USED_OF(fdt_name); \ \ start_imx6_phytec_common(memory_size, do_early_uart_config, \ __dtb_##fdt_name##_start); \ } -PHYTEC_ENTRY(start_phytec_pbaa03_1gib, imx6q_phytec_pbaa03, SZ_1G, true); -PHYTEC_ENTRY(start_phytec_pbaa03_1gib_1bank, imx6q_phytec_pbaa03, SZ_1G, true); -PHYTEC_ENTRY(start_phytec_pbaa03_2gib, imx6q_phytec_pbaa03, SZ_2G, true); +PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib, imx6q_phytec_phycard, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycard_imx6q_1gib_1bank, imx6q_phytec_phycard, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycard_imx6q_2gib, imx6q_phytec_phycard, SZ_2G, true); PHYTEC_ENTRY(start_phytec_pbab01_512mb_1bank, imx6q_phytec_pbab01, SZ_512M, true); PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true); @@ -111,6 +102,7 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_nand_256mb, imx6dl_phytec_phycore_som_lc_nand, SZ_256M, true); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib, imx6dl_phytec_phycore_som_nand, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_512mb, imx6dl_phytec_phycore_som_emmc, SZ_512M, true); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_lc_emmc_1gib, imx6dl_phytec_phycore_som_lc_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true); @@ -118,6 +110,7 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_so PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_emmc_512mb, imx6ul_phytec_phycore_som_emmc, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_nand_512mb, imx6ul_phytec_phycore_som_nand, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_nand_256mb, imx6ull_phytec_phycore_som_lc_nand, SZ_256M, false); PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_nand_512mb, imx6ull_phytec_phycore_som_nand, SZ_512M, false); diff --git a/arch/arm/boards/phytec-som-imx8mm/Makefile b/arch/arm/boards/phytec-som-imx8mm/Makefile new file mode 100644 index 0000000000..10abebc539 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mm/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o lpddr4-timing.o +obj-y += board.o diff --git a/arch/arm/boards/phytec-som-imx8mm/board.c b/arch/arm/boards/phytec-som-imx8mm/board.c new file mode 100644 index 0000000000..52f821f5fa --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mm/board.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/imx/bbu.h> + +static int phyboard_polis_rdk_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + + return 0; +} + +static const struct of_device_id phyboard_polis_rdk_of_match[] = { + { .compatible = "phytec,imx8mm-phyboard-polis-rdk" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(phyboard_polis_rdk_of_match); + +static struct driver phyboard_polis_rdkboard_driver = { + .name = "board-phyboard-polis-rdk", + .probe = phyboard_polis_rdk_probe, + .of_compatible = DRV_OF_COMPAT(phyboard_polis_rdk_of_match), +}; +coredevice_platform_driver(phyboard_polis_rdkboard_driver); diff --git a/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg new file mode 100644 index 0000000000..8aff991618 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mm + +loadaddr 0x007e1000 +max_load_size 0x3f000 +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.c b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c new file mode 100644 index 0000000000..26f0f4d3e1 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <asm/barebox-arm.h> +#include <boards/phytec/phytec-som-imx8m-detection.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/atf.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mm.h> +#include <mach/imx/xload.h> +#include <mfd/bd71837.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <soc/imx8m/ddr.h> + +#include "lowlevel.h" + +extern char __dtb_z_imx8mm_phyboard_polis_rdk_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART3_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mm_setup_pad(IMX8MM_PAD_UART3_TXD_UART3_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + putc_ll('>'); +} + +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 + +static void phyboard_polis_rdk_ddr_init(enum phytec_imx8m_ddr_size size) +{ + int ret; + + if (size == PHYTEC_IMX8M_DDR_AUTODETECT) { + struct pbl_i2c *i2c; + + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL); + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + i2c = imx8m_i2c_early_init(IOMEM(MX8MM_I2C1_BASE_ADDR)); + + ret = phytec_eeprom_data_setup(i2c, NULL, EEPROM_ADDR, + EEPROM_ADDR_FALLBACK, IMX_CPU_IMX8MM); + if (ret) { + pr_err("Could not detect correct RAM size. Fallback to default.\n"); + } else { + phytec_print_som_info(NULL); + size = phytec_get_imx8m_ddr_size(NULL); + } + } + + switch (size) { + case PHYTEC_IMX8M_DDR_1G: + phyboard_polis_rdk_dram_timing.ddrc_cfg[5].val = 0x2d0087; + phyboard_polis_rdk_dram_timing.ddrc_cfg[21].val = 0x8d; + phyboard_polis_rdk_dram_timing.ddrc_cfg[42].val = 0xf070707; + phyboard_polis_rdk_dram_timing.ddrc_cfg[58].val = 0x60012; + phyboard_polis_rdk_dram_timing.ddrc_cfg[73].val = 0x13; + phyboard_polis_rdk_dram_timing.ddrc_cfg[83].val = 0x30005; + phyboard_polis_rdk_dram_timing.ddrc_cfg[98].val = 0x5; + break; + default: + case PHYTEC_IMX8M_DDR_AUTODETECT: + case PHYTEC_IMX8M_DDR_2G: + break; + case PHYTEC_IMX8M_DDR_4G: + phyboard_polis_rdk_dram_timing.ddrc_cfg[2].val = 0xa3080020; + phyboard_polis_rdk_dram_timing.ddrc_cfg[37].val = 0x17; + phyboard_polis_rdk_dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x310; + phyboard_polis_rdk_dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x3; + phyboard_polis_rdk_dram_timing.fsp_msg[1].fsp_cfg[9].val = 0x310; + phyboard_polis_rdk_dram_timing.fsp_msg[1].fsp_cfg[21].val = 0x3; + phyboard_polis_rdk_dram_timing.fsp_msg[2].fsp_cfg[9].val = 0x310; + phyboard_polis_rdk_dram_timing.fsp_msg[2].fsp_cfg[21].val = 0x3; + phyboard_polis_rdk_dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x310; + phyboard_polis_rdk_dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x3; + break; + } + + imx8mm_ddr_init(&phyboard_polis_rdk_dram_timing, DRAM_TYPE_LPDDR4); +} + +static void start_phyboard_polis_rdk_common(enum phytec_imx8m_ddr_size size) +{ + imx8mm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + setup_uart(); + + /* + * If we are in EL3 we are running for the first time out of OCRAM, + * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A + * will then jump to DRAM in EL2 + */ + if (current_el() == 3) { + imx8mm_early_clock_init(); + + phyboard_polis_rdk_ddr_init(size); + + imx8mm_load_and_start_image_via_tfa(); + } + + /* Standard entry we hit once we initialized both DDR and ATF */ + imx8mm_barebox_entry(__dtb_z_imx8mm_phyboard_polis_rdk_start); +} + +ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_autodetect, r0, r1, r2) +{ + start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_AUTODETECT); +} + +ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_1g, r0, r1, r2) +{ + start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_1G); +} + +ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_2g, r0, r1, r2) +{ + start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_1G); +} + +ENTRY_FUNCTION(start_phyboard_polis_rdk_ddr_4g, r0, r1, r2) +{ + start_phyboard_polis_rdk_common(PHYTEC_IMX8M_DDR_4G); +} diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.h b/arch/arm/boards/phytec-som-imx8mm/lowlevel.h new file mode 100644 index 0000000000..9982a822b7 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PHYBOARD_POLIS_RDK_LOWLEVEL_H_ +#define PHYBOARD_POLIS_RDK_LOWLEVEL_H_ + +extern struct dram_timing_info phyboard_polis_rdk_dram_timing; + +#endif diff --git a/arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c b/arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c new file mode 100644 index 0000000000..7d01c181c0 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c @@ -0,0 +1,1125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * + * Generated code from MX8M_DDR_tool + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#define DDR_ONE_RANK +#include <soc/imx8m/lpddr4_define.h> + +#include "lowlevel.h" + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x222 }, + { 0x3d400024, 0x3a980 }, + { 0x3d400064, 0x2d00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e0c20 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x402 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x20 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0x6001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040105 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x302 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x20 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x302 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0x599 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info phyboard_polis_rdk_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100,}, +}; diff --git a/arch/arm/boards/phytec-som-imx8mq/.gitignore b/arch/arm/boards/phytec-som-imx8mq/.gitignore index ef13747c92..cafa52b207 100644 --- a/arch/arm/boards/phytec-som-imx8mq/.gitignore +++ b/arch/arm/boards/phytec-som-imx8mq/.gitignore @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + *.ddr-phy-fw* diff --git a/arch/arm/boards/phytec-som-imx8mq/Makefile b/arch/arm/boards/phytec-som-imx8mq/Makefile index 2995f06f0f..17d769f330 100644 --- a/arch/arm/boards/phytec-som-imx8mq/Makefile +++ b/arch/arm/boards/phytec-som-imx8mq/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o ddr_init.o ddrphy_train.o diff --git a/arch/arm/boards/phytec-som-imx8mq/board.c b/arch/arm/boards/phytec-som-imx8mq/board.c index 4fd098c5f6..45ed9cf5ad 100644 --- a/arch/arm/boards/phytec-som-imx8mq/board.c +++ b/arch/arm/boards/phytec-som-imx8mq/board.c @@ -9,10 +9,47 @@ #include <common.h> #include <init.h> #include <linux/sizes.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> +#include <mfd/pfuze.h> +#include <linux/regmap.h> #include <envfs.h> +#define PFUZE100_DEVICEID 0x0 +#define PFUZE100_REVID 0x3 + +#define PFUZE100_SW1ABMODE 0x23 +#define PFUZE100_SW2MODE 0x38 +#define PFUZE100_SW1CMODE 0x31 +#define PFUZE100_SW3AVOL 0x3c + +#define APS_PFM 0xc + +static void imx8mq_setup_pmic_voltages(struct regmap *map) +{ + int offset = PFUZE100_SW1CMODE; + int switch_num = 6; + int val, i; + + regmap_read(map, PFUZE100_SW3AVOL, &val); + + /* ensure the correct VDD_DRAM_0V9 output voltage */ + regmap_write_bits(map, PFUZE100_SW3AVOL, 0x3f, 0x18); + + /* pfuze200 */ + regmap_read(map, PFUZE100_DEVICEID, &val); + if (val & 0xf) { + offset = PFUZE100_SW2MODE; + switch_num = 4; + } + + /* set all switches APS in normal and PFM mode in standby */ + regmap_write(map, PFUZE100_SW1ABMODE, APS_PFM); + + for (i = 0; i < switch_num - 1; i++) + regmap_write(map, offset + i * 7, APS_PFM); +} + static int physom_imx8mq_devices_init(void) { int flag_emmc = 0; @@ -23,6 +60,8 @@ static int physom_imx8mq_devices_init(void) barebox_set_hostname("phycore-imx8mq"); + pfuze_register_init_callback(imx8mq_setup_pmic_voltages); + switch (bootsource_get_instance()) { case 0: flag_emmc = BBU_HANDLER_FLAG_DEFAULT; @@ -35,10 +74,8 @@ static int physom_imx8mq_devices_init(void) break; } - imx8mq_bbu_internal_mmc_register_handler("eMMC", - "/dev/mmc0.barebox", flag_emmc); - imx8mq_bbu_internal_mmc_register_handler("SD", - "/dev/mmc1.barebox", flag_sd); + imx8m_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0.barebox", flag_emmc); + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flag_sd); return 0; diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr.h b/arch/arm/boards/phytec-som-imx8mq/ddr.h index 18ae6e9022..e125feaaf0 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddr.h +++ b/arch/arm/boards/phytec-som-imx8mq/ddr.h @@ -7,7 +7,7 @@ */ #include <common.h> #include <io.h> -#include <mach/imx8-ddrc.h> +#include <soc/imx8m/ddr.h> /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -19,8 +19,3 @@ void phytec_imx8mq_phycore_ddr_init(void); void phytec_imx8mq_phycore_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin diff --git a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c index aa327d3fb0..c6812e3efa 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddr_init.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddr_init.c @@ -84,6 +84,7 @@ void ddr_init(void) reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0xf070707); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d402020,0x1); reg32_write(0x3d402024,0x518b00); reg32_write(0x3d402050,0x20d040); diff --git a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c index 56af647821..fac9e184ae 100644 --- a/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c +++ b/arch/arm/boards/phytec-som-imx8mq/ddrphy_train.c @@ -9,10 +9,11 @@ #include "ddr.h" -extern void wait_ddrphy_training_complete(void); void ddr_cfg_phy(void) { unsigned int tmp, tmp_t; + ddr_get_firmware(DRAM_TYPE_LPDDR4); + //Init DDRPHY register... reg32_write(0x3c080440,0x2); reg32_write(0x3c080444,0x3); @@ -147,7 +148,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); @@ -189,7 +190,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //configure DDRPHY-FW DMEM structure @clock1... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -223,7 +224,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x29c); @@ -266,7 +267,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //set the PHY input clock to the desired frequency for pstate 0 reg32_write(0x3038a088,0x7070000); @@ -299,7 +300,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(FW_2D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); @@ -342,7 +343,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //Halt MPU reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); diff --git a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg index aff8321b9a..f82759f849 100644 --- a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg +++ b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg @@ -1,5 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index 4e52b92ad3..362b3ed823 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -4,67 +4,48 @@ */ #include <common.h> +#include <firmware.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx8-ccm-regs.h> -#include <mach/iomux-mx8.h> -#include <mach/imx8-ddrc.h> -#include <mach/xload.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mq.h> +#include <soc/imx8m/ddr.h> +#include <mach/imx/xload.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/mmu.h> -#include <mach/atf.h> -#include <mach/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> #include "ddr.h" -extern char __dtb_imx8mq_phytec_phycore_som_start[]; +extern char __dtb_z_imx8mq_phytec_phycore_som_start[]; #define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); - imx8_uart_setup_ll(); + imx8m_uart_setup(uart); - putc_ll('>'); -} - -static void phytec_imx8mq_som_sram_setup(void) -{ - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - int ret = -ENOTSUPP; - - ddr_init(); + pbl_set_putc(imx_uart_putc, uart); - imx8_get_boot_source(&src, &instance); - - if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_start_image(instance); - - BUG_ON(ret); + putc_ll('>'); } static __noreturn noinline void phytec_phycore_imx8mq_start(void) { - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); + setup_uart(); if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { /* @@ -73,7 +54,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * that means DDR needs to be initialized for the * first time. */ - phytec_imx8mq_som_sram_setup(); + ddr_init(); } /* * Straight from the power-on we are at EL3, so the following @@ -83,18 +64,13 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * initialization routine, it is EL2 which means we'll skip * loadting ATF blob again */ - if (current_el() == 3) { - const u8 *bl31; - size_t bl31_size; - - get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); - imx8mq_atf_load_bl31(bl31, bl31_size); - } + if (current_el() == 3) + imx8mq_load_and_start_image_via_tfa(); /* * Standard entry we hit once we initialized both DDR and ATF */ - imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start); + imx8mq_barebox_entry(__dtb_z_imx8mq_phytec_phycore_som_start); } /* @@ -112,7 +88,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void) * * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR, * executing start_phytec_phycore_imx8mq() the third time * * 6. Standard barebox boot flow continues diff --git a/arch/arm/boards/phytec-som-rk3288/Makefile b/arch/arm/boards/phytec-som-rk3288/Makefile index 6f34c9a2f2..e4ba704dea 100644 --- a/arch/arm/boards/phytec-som-rk3288/Makefile +++ b/arch/arm/boards/phytec-som-rk3288/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-physom-rk3288 diff --git a/arch/arm/boards/phytec-som-rk3288/board.c b/arch/arm/boards/phytec-som-rk3288/board.c index 8ea6c6c47c..43ed465f21 100644 --- a/arch/arm/boards/phytec-som-rk3288/board.c +++ b/arch/arm/boards/phytec-som-rk3288/board.c @@ -1,17 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2016 PHYTEC Messtechnik GmbH + /* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH, * Author: Wadim Egorov <w.egorov@phytec.de> * * Device initialization for the phyCORE-RK3288 SoM - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <common.h> diff --git a/arch/arm/boards/phytec-som-rk3288/lowlevel.c b/arch/arm/boards/phytec-som-rk3288/lowlevel.c index 9def80ddb8..12044b6039 100644 --- a/arch/arm/boards/phytec-som-rk3288/lowlevel.c +++ b/arch/arm/boards/phytec-som-rk3288/lowlevel.c @@ -1,25 +1,17 @@ -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH, - * Author: Wadim Egorov <w.egorov@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2016 PHYTEC Messtechnik GmbH + +/* Author: Wadim Egorov <w.egorov@phytec.de> */ #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/rk3288-regs.h> -#include <mach/grf_rk3288.h> -#include <mach/hardware.h> +#include <mach/rockchip/rk3288-regs.h> +#include <mach/rockchip/grf_rk3288.h> +#include <mach/rockchip/hardware.h> #include <debug_ll.h> +#include <mach/rockchip/debug_ll.h> extern char __dtb_rk3288_phycore_som_start[]; @@ -35,7 +27,7 @@ ENTRY_FUNCTION(start_rk3288_phycore_som, r0, r1, r2) GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); - INIT_LL(); + rockchip_debug_ll_init(); } fdt = __dtb_rk3288_phycore_som_start + get_runtime_offset(); diff --git a/arch/arm/boards/pine64-quartz64/.gitignore b/arch/arm/boards/pine64-quartz64/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/pine64-quartz64/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/pine64-quartz64/Makefile b/arch/arm/boards/pine64-quartz64/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/pine64-quartz64/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/pine64-quartz64/board.c b/arch/arm/boards/pine64-quartz64/board.c new file mode 100644 index 0000000000..1573dd8674 --- /dev/null +++ b/arch/arm/boards/pine64-quartz64/board.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <init.h> + +struct quartz64_model { + const char *name; + const char *shortname; +}; + +static int quartz64_probe(struct device *dev) +{ + const struct quartz64_model *model; + + model = device_get_match_data(dev); + + barebox_set_model(model->name); + barebox_set_hostname(model->shortname); + + return 0; +} + +static const struct quartz64_model quartz64a = { + .name = "Pine64 Quartz64 Model A", + .shortname = "quartz64a", +}; + +static const struct of_device_id quartz64_of_match[] = { + { + .compatible = "pine64,quartz64-a", + .data = &quartz64a, + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, quartz64_of_match); + +static struct driver quartz64_board_driver = { + .name = "board-quartz64", + .probe = quartz64_probe, + .of_compatible = quartz64_of_match, +}; +coredevice_platform_driver(quartz64_board_driver); diff --git a/arch/arm/boards/pine64-quartz64/lowlevel.c b/arch/arm/boards/pine64-quartz64/lowlevel.c new file mode 100644 index 0000000000..7723d47860 --- /dev/null +++ b/arch/arm/boards/pine64-quartz64/lowlevel.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3566_quartz64_a_start[]; + +ENTRY_FUNCTION(start_quartz64a, r0, r1, r2) +{ + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3566_quartz64_a_start); +} diff --git a/arch/arm/boards/plathome-openblocks-a6/Makefile b/arch/arm/boards/plathome-openblocks-a6/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/plathome-openblocks-a6/Makefile +++ b/arch/arm/boards/plathome-openblocks-a6/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/plathome-openblocks-a6/board.c b/arch/arm/boards/plathome-openblocks-a6/board.c deleted file mode 100644 index 40a8c178f1..0000000000 --- a/arch/arm/boards/plathome-openblocks-a6/board.c +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c index 31a28c8916..8a58d692d8 100644 --- a/arch/arm/boards/plathome-openblocks-a6/lowlevel.c +++ b/arch/arm/boards/plathome-openblocks-a6/lowlevel.c @@ -1,25 +1,14 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_kirkwood_openblocks_a6_bb_start[]; -ENTRY_FUNCTION(start_plathome_openblocks_a6, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_plathome_openblocks_a6, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/plathome-openblocks-ax3/Makefile b/arch/arm/boards/plathome-openblocks-ax3/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/plathome-openblocks-ax3/Makefile +++ b/arch/arm/boards/plathome-openblocks-ax3/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/plathome-openblocks-ax3/board.c b/arch/arm/boards/plathome-openblocks-ax3/board.c deleted file mode 100644 index 9c800c5410..0000000000 --- a/arch/arm/boards/plathome-openblocks-ax3/board.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright - * (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* empty */ diff --git a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c index f029bd1ba6..35888a0b83 100644 --- a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c +++ b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c @@ -1,28 +1,15 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_armada_xp_openblocks_ax3_4_bb_start[]; -ENTRY_FUNCTION(start_plathome_openblocks_ax3, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_plathome_openblocks_ax3, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile index e9bf1212fe..5b501a548f 100644 --- a/arch/arm/boards/pm9261/Makefile +++ b/arch/arm/boards/pm9261/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c index 33c2a542b2..e87c8ad27b 100644 --- a/arch/arm/boards/pm9261/init.c +++ b/arch/arm/boards/pm9261/init.c @@ -1,20 +1,6 @@ -/* - * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> @@ -22,19 +8,19 @@ #include <gpio.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/mtd/nand.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/iomux.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91sam9_smc.h> #include <platform_data/eth-dm9000.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c index b18cd067b7..6a44981cc1 100644 --- a/arch/arm/boards/pm9261/lowlevel_init.c +++ b/arch/arm/boards/pm9261/lowlevel_init.c @@ -4,10 +4,9 @@ * Under GPLv2 */ -#include <asm/barebox-arm.h> - -#include <mach/at91sam926x_board_init.h> -#include <mach/at91sam9261_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9261_matrix.h> #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 @@ -111,7 +110,7 @@ static void __bare_init pm9261_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_pm9261, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/pm9263/Makefile b/arch/arm/boards/pm9263/Makefile index 68bfbfa926..7220ee11f3 100644 --- a/arch/arm/boards/pm9263/Makefile +++ b/arch/arm/boards/pm9263/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c index 30b3d26fbf..026a8bfe8d 100644 --- a/arch/arm/boards/pm9263/init.c +++ b/arch/arm/boards/pm9263/init.c @@ -1,39 +1,25 @@ -/* - * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <gpio.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/mtd/nand.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/iomux.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c index 8f44adee99..d06573d1cc 100644 --- a/arch/arm/boards/pm9263/lowlevel_init.c +++ b/arch/arm/boards/pm9263/lowlevel_init.c @@ -6,10 +6,9 @@ #include <linux/sizes.h> -#include <asm/barebox-arm.h> - -#include <mach/at91sam926x_board_init.h> -#include <mach/at91sam9263_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9263_matrix.h> #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 @@ -132,7 +131,7 @@ static void __bare_init pm9263_board_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_pm9263, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/pm9g45/Makefile b/arch/arm/boards/pm9g45/Makefile index abf50243e5..148ae4a252 100644 --- a/arch/arm/boards/pm9g45/Makefile +++ b/arch/arm/boards/pm9g45/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c index 0565657a8c..ee60cf8f00 100644 --- a/arch/arm/boards/pm9g45/init.c +++ b/arch/arm/boards/pm9g45/init.c @@ -1,40 +1,26 @@ -/* - * Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <gpio.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/mtd/nand.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/iomux.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91sam9_smc.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c index fc0bfe405b..9cdc2711e6 100644 --- a/arch/arm/boards/pm9g45/lowlevel.c +++ b/arch/arm/boards/pm9g45/lowlevel.c @@ -7,13 +7,11 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_pm9g45, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c b/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c new file mode 100644 index 0000000000..db75a424b7 --- /dev/null +++ b/arch/arm/boards/polyhex-debix/8g-lpddr4-timing.c @@ -0,0 +1,1125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a017c }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x184 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x18 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0026 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x27 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x3000a }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0xa }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info imx8mp_debix_8g_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/polyhex-debix/Makefile b/arch/arm/boards/polyhex-debix/Makefile new file mode 100644 index 0000000000..725cb1f8b5 --- /dev/null +++ b/arch/arm/boards/polyhex-debix/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o 8g-lpddr4-timing.o diff --git a/arch/arm/boards/polyhex-debix/board.c b/arch/arm/boards/polyhex-debix/board.c new file mode 100644 index 0000000000..ea4fc26a0c --- /dev/null +++ b/arch/arm/boards/polyhex-debix/board.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <envfs.h> +#include <init.h> +#include <io.h> +#include <linux/nvmem-consumer.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iomux-mx8mp.h> +#include <net.h> + +struct debix_polyhex_machine_data { + void (*ethernet_setup)(void); +}; + +#define ETH_ALEN_ASCII 12 + +static int polyhex_debix_eth_register_ethaddr(struct device_node *np) +{ + u8 mac[ETH_ALEN]; + u8 *data; + int ret; + + data = nvmem_cell_get_and_read(np, "mac-address", ETH_ALEN_ASCII); + if (IS_ERR(data)) + return PTR_ERR(data); + + ret = hex2bin(mac, data, ETH_ALEN); + if (ret) + goto err; + + of_eth_register_ethaddr(np, mac); +err: + free(data); + + return ret; +} + +static void polyhex_debix_ethernet_init(void) +{ + static const char * const aliases[] = { "ethernet0", "ethernet1" }; + struct device_node *np, *root; + unsigned int i; + + root = of_get_root_node(); + + for (i = 0; i < ARRAY_SIZE(aliases); i++) { + const char *alias = aliases[i]; + int ret; + + np = of_find_node_by_alias(root, alias); + if (!np) { + pr_warn("Failed to find %s\n", alias); + continue; + } + + ret = polyhex_debix_eth_register_ethaddr(np); + if (ret) { + pr_warn("Failed to register MAC for %s\n", alias); + continue; + } + } +} + +static int polyhex_debix_probe(struct device *dev) +{ + const struct debix_polyhex_machine_data *machine_data; + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + u32 val; + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + + /* Enable RGMII TX clk output */ + val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN | + MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN; + writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + + machine_data = device_get_match_data(dev); + if (machine_data && machine_data->ethernet_setup) + machine_data->ethernet_setup(); + + return 0; +} + +static const struct debix_polyhex_machine_data debix_som_a_bmb_08 = { + .ethernet_setup = polyhex_debix_ethernet_init, +}; + +static const struct of_device_id polyhex_debix_of_match[] = { + { .compatible = "polyhex,imx8mp-debix" }, + { .compatible = "polyhex,imx8mp-debix-som-a-bmb-08", .data = &debix_som_a_bmb_08 }, + { /* Sentinel */ } +}; +BAREBOX_DEEP_PROBE_ENABLE(polyhex_debix_of_match); + +static struct driver polyhex_debix_board_driver = { + .name = "board-imx8mp-debix", + .probe = polyhex_debix_probe, + .of_compatible = polyhex_debix_of_match, +}; +coredevice_platform_driver(polyhex_debix_board_driver); diff --git a/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg new file mode 100644 index 0000000000..6ea2e6c68e --- /dev/null +++ b/arch/arm/boards/polyhex-debix/flash-header-polyhex-debix.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/polyhex-debix/lowlevel.c b/arch/arm/boards/polyhex-debix/lowlevel.c new file mode 100644 index 0000000000..fa49fcb5c1 --- /dev/null +++ b/arch/arm/boards/polyhex-debix/lowlevel.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/xload.h> +#include <mfd/pca9450.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <soc/imx8m/ddr.h> + +extern char __dtb_z_imx8mp_debix_model_a_start[]; +extern char __dtb_z_imx8mp_debix_som_a_bmb_08_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* + * Increase VDD_ARM to 0.95V to avoid issues in case software after + * Barebox switches to the OD ARM frequency without reprogramming the + * PMIC first. + */ + { PCA9450_BUCK2OUT_DVS0, 0x1C }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +extern struct dram_timing_info imx8mp_debix_dram_timing; +extern struct dram_timing_info imx8mp_debix_8g_dram_timing; + +static void start_atf(struct dram_timing_info *dram_timing) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mp_early_clock_init(); + + power_init_board(); + + imx8mp_ddr_init(dram_timing, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); +} + +/* + * Power-on execution flow of start_imx8mp_debix() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void +imx8mp_debix_start(struct dram_timing_info *dram_timing, void *dtb) +{ + setup_uart(); + + start_atf(dram_timing); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(dtb); +} + +ENTRY_FUNCTION(start_polyhex_debix, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + imx8mp_debix_start(&imx8mp_debix_dram_timing, + __dtb_z_imx8mp_debix_model_a_start); +} + +ENTRY_FUNCTION(start_polyhex_debix_som_a_8g, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + imx8mp_debix_start(&imx8mp_debix_8g_dram_timing, + __dtb_z_imx8mp_debix_som_a_bmb_08_start); +} diff --git a/arch/arm/boards/polyhex-debix/lpddr4-timing.c b/arch/arm/boards/polyhex-debix/lpddr4-timing.c new file mode 100644 index 0000000000..2724b893d6 --- /dev/null +++ b/arch/arm/boards/polyhex-debix/lpddr4-timing.c @@ -0,0 +1,1123 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1c61a00 }, + { 0x3d400064, 0x710105 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc003071a }, + { 0x3d4000d4, 0xb70000 }, + { 0x3d4000dc, 0xe40036 }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x1e261f28 }, + { 0x3d400104, 0x7073b }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x11040a11 }, + { 0x3d400114, 0x2050e0e }, + { 0x3d400118, 0x1010008 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20700 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x10c }, + { 0x3d400144, 0xba005d }, + { 0x3d400180, 0x3a2001c }, + { 0x3d400184, 0x2f07187 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49b820c }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1b0c }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x810191a }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3a2 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe88 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe88 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3336 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3336 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x74 }, + { 0x2000c, 0xe8 }, + { 0x2000d, 0x915 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3720mts 1D */ + .drate = 3720, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3720mts 2D */ + .drate = 3720, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* Samsung K4F6E3S4HM-MGCJ ddr timing config params */ +struct dram_timing_info imx8mp_debix_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3720, 400, 100, }, +}; diff --git a/arch/arm/boards/protonic-imx6/Makefile b/arch/arm/boards/protonic-imx6/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/protonic-imx6/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/protonic-imx6/board.c b/arch/arm/boards/protonic-imx6/board.c new file mode 100644 index 0000000000..9e62dc1544 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/board.c @@ -0,0 +1,1282 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix +// SPDX-FileCopyrightText: 2014 Protonic Holland +// SPDX-FileCopyrightText: 2020 Oleksij Rempel, Pengutronix + +#include <bbu.h> +#include <boot.h> +#include <bootm.h> +#include <common.h> +#include <deep-probe.h> +#include <environment.h> +#include <fcntl.h> +#include <globalvar.h> +#include <gpio.h> +#include <i2c/i2c.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> +#include <mach/imx/ocotp-fusemap.h> +#include <mfd/imx6q-iomuxc-gpr.h> +#include <mfd/syscon.h> +#include <net.h> +#include <of_device.h> +#include <linux/regmap.h> +#include <sys/mount.h> +#include <sys/stat.h> +#include <unistd.h> +#include <linux/usb/usb.h> + +#define GPIO_HW_REV_ID {\ + {IMX_GPIO_NR(2, 8), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id0"}, \ + {IMX_GPIO_NR(2, 9), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id1"}, \ + {IMX_GPIO_NR(2, 10), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "rev_id2"} \ +} + +#define GPIO_HW_TYPE_ID {\ + {IMX_GPIO_NR(2, 11), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id0"}, \ + {IMX_GPIO_NR(2, 12), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id1"}, \ + {IMX_GPIO_NR(2, 13), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id2"}, \ + {IMX_GPIO_NR(2, 14), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id3"}, \ + {IMX_GPIO_NR(2, 15), GPIOF_DIR_IN | GPIOF_ACTIVE_LOW, "hw_id4"} \ +} + +enum { + HW_TYPE_PRTI6Q = 0, + HW_TYPE_PRTWD2 = 1, + HW_TYPE_ALTI6S = 2, + HW_TYPE_VICUT1 = 4, + HW_TYPE_ALTI6P = 6, + HW_TYPE_PRTMVT = 8, + HW_TYPE_PRTI6G = 10, + HW_TYPE_PRTRVT = 12, + HW_TYPE_VICUT2 = 16, + HW_TYPE_PLYM2M = 20, + HW_TYPE_PRTVT7 = 22, + HW_TYPE_LANMCU = 23, + HW_TYPE_PLYBAS = 24, + HW_TYPE_VICTGO = 28, + HW_TYPE_JOZACP = 30, + HW_TYPE_JOZACPP = 31, +}; + +enum prt_imx6_kvg_pw_mode { + PW_MODE_KVG_WITH_YACO = 0, + PW_MODE_KVG_NEW = 1, + PW_MODE_KUBOTA = 2, +}; + +/* board specific flags */ +#define PRT_IMX6_BOOTCHOOSER BIT(3) +#define PRT_IMX6_USB_LONG_DELAY BIT(2) +#define PRT_IMX6_BOOTSRC_EMMC BIT(1) +#define PRT_IMX6_BOOTSRC_SPI_NOR BIT(0) + +static struct prt_imx6_priv *prt_priv; +struct prt_machine_data { + unsigned int hw_id; + unsigned int hw_rev; + unsigned int i2c_addr; + unsigned int i2c_adapter; + unsigned int emmc_usdhc; + unsigned int sd_usdhc; + unsigned int flags; + int (*init)(struct prt_imx6_priv *priv); +}; + +struct prt_imx6_priv { + struct device *dev; + const struct prt_machine_data *dcfg; + unsigned int hw_id; + unsigned int hw_rev; + const char *name; + unsigned int no_usb_check; + char *ocotp_serial; +}; + +struct prti6q_rfid_contents { + u8 mac[6]; + char serial[10]; + u8 cs; +} __attribute__ ((packed)); + +#define GPIO_DIP1_FB IMX_GPIO_NR(4, 18) +#define GPIO_FORCE_ON1 IMX_GPIO_NR(2, 30) +#define GPIO_ON1_CTRL IMX_GPIO_NR(4, 21) +#define GPIO_ON2_CTRL IMX_GPIO_NR(4, 22) + +static const struct gpio prt_imx6_kvg_gpios[] = { + { + .gpio = GPIO_DIP1_FB, + .flags = GPIOF_IN, + .label = "DIP1_FB", + }, + { + .gpio = GPIO_FORCE_ON1, + .flags = GPIOF_OUT_INIT_HIGH, + .label = "FORCE_ON1", + }, + { + .gpio = GPIO_ON1_CTRL, + .flags = GPIOF_IN, + .label = "ON1_CTRL", + }, + { + .gpio = GPIO_ON2_CTRL, + .flags = GPIOF_IN, + .label = "ON2_CTRL", + }, +}; + +static int prt_of_fixup_hwrev(struct prt_imx6_priv *priv) +{ + const char *compat; + char *buf; + + compat = of_device_get_match_compatible(priv->dev); + + buf = xasprintf("%s-m%u-r%u", compat, priv->hw_id, + priv->hw_rev); + barebox_set_of_machine_compatible(buf); + + free(buf); + + return 0; +} + +static int prt_imx6_read_rfid(struct prt_imx6_priv *priv, void *buf, + size_t size) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + struct device *dev = priv->dev; + struct i2c_client cl; + int ret; + + cl.addr = dcfg->i2c_addr; + cl.adapter = i2c_get_adapter(dcfg->i2c_adapter); + if (!cl.adapter) { + dev_err(dev, "i2c bus not found\n"); + return -ENODEV; + } + + /* 0x6000 user storage in the RFID tag */ + ret = i2c_read_reg(&cl, 0x6000 | I2C_ADDR_16_BIT, buf, size); + if (ret < 0) { + dev_err(dev, "Failed to read the RFID: %pe\n", ERR_PTR(ret)); + return ret; + } + + return 0; +} + +static u8 prt_imx6_calc_rfid_cs(void *buf, size_t size) +{ + unsigned int cs = 0; + u8 *dat = buf; + int t; + + for (t = 0; t < size - 1; t++) { + cs += dat[t]; + } + + cs ^= 0xff; + + return cs & 0xff; + +} + +static int prt_imx6_set_mac(struct prt_imx6_priv *priv, + struct prti6q_rfid_contents *rfid) +{ + struct device *dev = priv->dev; + struct device_node *node; + + node = of_find_node_by_alias(of_get_root_node(), "ethernet0"); + if (!node) { + dev_err(dev, "Cannot find FEC!\n"); + return -ENODEV; + } + + if (!of_device_is_available(node)) + return 0; + + if (!is_valid_ether_addr(&rfid->mac[0])) { + dev_err(dev, "bad MAC addr: %pM\n", &rfid->mac[0]); + + return -EILSEQ; + } + + of_eth_register_ethaddr(node, &rfid->mac[0]); + + return 0; +} + +static int prt_imx6_set_serial(struct prt_imx6_priv *priv, char *serial) +{ + serial[9] = 0; /* Failsafe */ + dev_info(priv->dev, "Serial number: %s\n", serial); + barebox_set_serial_number(serial); + + return 0; +} + +static int prt_imx6_read_i2c_mac_serial(struct prt_imx6_priv *priv) +{ + struct device *dev = priv->dev; + struct prti6q_rfid_contents rfid; + int ret; + + ret = prt_imx6_read_rfid(priv, &rfid, sizeof(rfid)); + if (ret) + return ret; + + if (rfid.cs != prt_imx6_calc_rfid_cs(&rfid, sizeof(rfid))) { + dev_err(dev, "RFID: bad checksum!\n"); + return -EBADMSG; + } + + ret = prt_imx6_set_mac(priv, &rfid); + if (ret) + return ret; + + ret = prt_imx6_set_serial(priv, rfid.serial); + if (ret) + return ret; + + return 0; +} + +#define PRT_IMX6_GP1_FMT_DEC BIT(31) + +static int prt_imx6_read_ocotp_serial(struct prt_imx6_priv *priv) +{ + int ret; + unsigned val; + + ret = imx_ocotp_read_field(OCOTP_GP1, &val); + if (ret) { + dev_err(priv->dev, "Failed to read ocotp serial (%i)\n", ret); + return ret; + } + + if (!(val & PRT_IMX6_GP1_FMT_DEC)) + return -EINVAL; + val &= PRT_IMX6_GP1_FMT_DEC - 1; + + priv->ocotp_serial = xasprintf("%u", val); + + return prt_imx6_set_serial(priv, priv->ocotp_serial); +} + +static int prt_imx6_set_ocotp_serial(struct param_d *param, void *driver_priv) +{ + struct prt_imx6_priv *priv = driver_priv; + int ret; + unsigned val; + + ret = kstrtouint(priv->ocotp_serial, 10, &val); + if (ret) + return ret; + + if (val & PRT_IMX6_GP1_FMT_DEC) + return -ERANGE; + val |= PRT_IMX6_GP1_FMT_DEC; + + ret = imx_ocotp_write_field(OCOTP_GP1, val); + if (ret) + return ret; + + barebox_set_serial_number(priv->ocotp_serial); + return 0; +} + +static int prt_imx6_usb_mount(struct prt_imx6_priv *priv) +{ + struct device *dev = priv->dev; + const char *path; + struct stat s; + int ret; + + ret = mkdir("/usb", 0); + if (ret) { + dev_err(dev, "Cannot mkdir /usb\n"); + return ret; + } + + path = "/dev/disk0.0"; + ret = stat(path, &s); + if (!ret) { + ret = mount(path, NULL, "usb", NULL); + if (ret) + goto exit_usb_mount; + return 0; + } + + path = "/dev/disk0"; + ret = stat(path, &s); + if (!ret) { + ret = mount(path, NULL, "usb", NULL); + if (ret) + goto exit_usb_mount; + return 0; + } + +exit_usb_mount: + dev_err(dev, "Failed to mount %s with error (%i)\n", path, ret); + return ret; +} + +#define OTG_PORTSC1 (MX6_OTG_BASE_ADDR+0x184) + +static int prt_imx6_usb_boot(struct bootentry *entry, int verbose, int dryrun) +{ + struct prt_imx6_priv *priv = prt_priv; + struct device *dev = priv->dev; + char *second_word; + char buf[sizeof("vicut1q recovery")] = {}; + struct bootm_data bootm_data = {}; + ssize_t size; + int fd, ret; + + usb_rescan(); + + ret = prt_imx6_usb_mount(priv); + if (ret) + return ret; + + fd = open("/usb/boot_target", O_RDONLY); + if (fd < 0) { + dev_warn(dev, "Can't open /usb/boot_target file, continue with normal boot\n"); + ret = fd; + goto exit_usb_boot; + } + + size = read(fd, buf, sizeof(buf) - 1); + close(fd); + if (size < 0) { + ret = size; + goto exit_usb_boot; + } + + /* Length of "vicut1 usb", the shortest possible target. */ + if (size < strlen("vicut1 usb")) { + dev_err(dev, "Invalid boot target file!\n"); + ret = -EINVAL; + goto exit_usb_boot; + } + + second_word = strchr(buf, ' '); + if (!second_word) { + dev_err(dev, "Cant find boot target in the boot target file!\n"); + ret = -ENODEV; + goto exit_usb_boot; + } + + *second_word = 0; + + if (strcmp(buf, priv->name)) { + dev_err(dev, "Boot target for a different board! (got: %s expected: %s)\n", + buf, priv->name); + ret = -EINVAL; + goto exit_usb_boot; + } + + bootm_data_init_defaults(&bootm_data); + + second_word++; + if (strncmp(second_word, "usb", 3) == 0) { + dev_info(dev, "Booting from USB drive\n"); + bootm_data.os_file = "/usb/linuximage.fit"; + } else if (strncmp(second_word, "recovery", 8) == 0) { + dev_info(dev, "Booting internal recovery OS\n"); + bootm_data.os_file = "/dev/mmc2.5"; + } else { + dev_err(dev, "Unknown boot target!\n"); + ret = -ENODEV; + goto exit_usb_boot; + } + + ret = globalvar_add_simple("linux.bootargs.root", + "root=/dev/ram rw rootwait ramdisk_size=196608"); + if (ret) + goto exit_usb_boot; + + if (verbose) + bootm_data.verbose = verbose; + if (dryrun) + bootm_data.dryrun = dryrun; + + ret = bootm_boot(&bootm_data); + if (ret) + goto exit_usb_boot; + + return 0; + +exit_usb_boot: + dev_err(dev, "Failed to run usb boot: %s\n", strerror(-ret)); + + return ret; +} + +static void prt_imx6_bootentry_release(struct bootentry *entry) +{ + free(entry); +} + +static int prt_imx6_bootentry_create(struct bootentries *bootentries, const char *name) +{ + struct bootentry *entry; + + entry = xzalloc(sizeof(*entry)); + if (!entry) + return -ENOMEM; + + entry->me.type = MENU_ENTRY_NORMAL; + entry->release = prt_imx6_bootentry_release; + entry->boot = prt_imx6_usb_boot; + entry->title = xstrdup(name); + entry->description = xstrdup("Boot FIT image of a USB drive"); + bootentries_add_entry(bootentries, entry); + + return 0; +} + +static int prt_imx6_bootentry_provider(struct bootentries *bootentries, + const char *name) +{ + int found = 0; + unsigned int v; + + if (strncmp(name, "prt-usb", 7)) + return found; + + v = readl(OTG_PORTSC1); + if ((v & 0x0c00) == 0) /* No usb device detected */ + return found; + + if (!prt_imx6_bootentry_create(bootentries, name)) + found = 1; + + return found; +} + +static int prt_imx6_env_init(struct prt_imx6_priv *priv) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + struct device *dev = priv->dev; + char *delay, *bootsrc, *boot_targets; + unsigned int autoboot_timeout; + int ret; + + ret = setenv("global.linux.bootargs.base", "consoleblank=0 vt.color=0x00"); + if (ret) + goto exit_env_init; + + if (priv->no_usb_check) { + set_autoboot_state(AUTOBOOT_BOOT); + } else { + if (dcfg->flags & PRT_IMX6_USB_LONG_DELAY) + autoboot_timeout = 4; + else + autoboot_timeout = 1; + + /* the usb_delay value is used for poller_call_async() */ + delay = basprintf("%d", autoboot_timeout); + ret = setenv("global.autoboot_timeout", delay); + free(delay); + if (ret) + goto exit_env_init; + } + + if (dcfg->flags & PRT_IMX6_BOOTCHOOSER) + bootsrc = "bootchooser"; + else + bootsrc = "mmc2"; + + if (!priv->no_usb_check) + boot_targets = xasprintf("prt-usb %s", bootsrc); + else + boot_targets = xstrdup(bootsrc); + + ret = setenv("global.boot.default", boot_targets); + free(boot_targets); + if (ret) + goto exit_env_init; + + dev_info(dev, "Board specific env init is done\n"); + return 0; + +exit_env_init: + dev_err(dev, "Failed to set env: %pe\n", ERR_PTR(ret)); + + return ret; +} + +static int prt_imx6_bbu(struct prt_imx6_priv *priv) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + u32 emmc_flags = 0; + char *devicefile; + int ret; + + if (dcfg->flags & PRT_IMX6_BOOTSRC_SPI_NOR) { + ret = imx6_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + if (ret) + goto exit_bbu; + } else { + emmc_flags = BBU_HANDLER_FLAG_DEFAULT; + } + + devicefile = basprintf("/dev/mmc%d", dcfg->emmc_usdhc); + if (!devicefile) { + ret = -ENOMEM; + goto exit_bbu; + } + ret = imx6_bbu_internal_mmcboot_register_handler("eMMC", devicefile, + emmc_flags); + if (ret) + goto exit_bbu; + + devicefile = basprintf("/dev/mmc%d", dcfg->sd_usdhc); + if (!devicefile) { + ret = -ENOMEM; + goto exit_bbu; + } + + ret = imx6_bbu_internal_mmc_register_handler("SD", devicefile, 0); + if (ret) + goto exit_bbu; + + return 0; +exit_bbu: + dev_err(priv->dev, "Failed to register bbu: %pe\n", ERR_PTR(ret)); + return ret; +} + +static int prt_imx6_devices_init(void) +{ + struct prt_imx6_priv *priv = prt_priv; + struct device *ocotp_dev; + struct param_d *p; + + if (!priv) + return 0; + + if (priv->dcfg->init) + priv->dcfg->init(priv); + + prt_imx6_bbu(priv); + + /* + * Read serial number from fuses. On success we'll assume the imx_ocotp + * driver takes care of providing the mac address if needed. On + * failure we'll fallback to reading and setting serial and mac from an + * attached RFID eeprom. + */ + if (prt_imx6_read_ocotp_serial(priv) != 0) + prt_imx6_read_i2c_mac_serial(priv); + + bootentry_register_provider(prt_imx6_bootentry_provider); + + prt_imx6_env_init(priv); + + ocotp_dev = get_device_by_name("ocotp0"); + if (ocotp_dev) { + p = dev_add_param_string(ocotp_dev, "serial_number", + prt_imx6_set_ocotp_serial, NULL, + &priv->ocotp_serial, priv); + if (IS_ERR(p)) + return PTR_ERR(p); + } + + return 0; +} +late_initcall(prt_imx6_devices_init); + +static int prt_imx6_init_kvg_set_ctrl(struct prt_imx6_priv *priv, bool val) +{ + int ret; + + ret = gpio_direction_output(GPIO_ON1_CTRL, val); + if (ret) + return ret; + + ret = gpio_direction_output(GPIO_ON2_CTRL, val); + if (ret) + return ret; + + return 0; +} + +static int prt_imx6_yaco_set_kvg_power_mode(struct prt_imx6_priv *priv, + const char *serial) +{ + static const char command[] = "{\"command\":\"mode\",\"value\":\"kvg\",\"on2\":true}"; + struct device *dev = priv->dev; + struct console_device *yccon; + int ret; + + yccon = of_console_get_by_alias(serial); + if (!yccon) { + dev_dbg(dev, "Cant find the %s node, try later\n", serial); + return -EPROBE_DEFER; + } + + ret = console_set_baudrate(yccon, 115200); + if (ret) + goto exit_yaco_set_kvg_power_mode; + + yccon->puts(yccon, command, sizeof(command)); + + dev_info(dev, "Send YaCO power init sequence to %s\n", serial); + return 0; + +exit_yaco_set_kvg_power_mode: + dev_err(dev, "Failed to set YaCO pw mode: %pe", ERR_PTR(ret)); + + return ret; +} + +static int prt_imx6_init_kvg_power(struct prt_imx6_priv *priv, + enum prt_imx6_kvg_pw_mode pw_mode) +{ + const char *mode; + int ret; + + ret = gpio_request_array(prt_imx6_kvg_gpios, + ARRAY_SIZE(prt_imx6_kvg_gpios)); + if (ret) + goto exit_init_kvg_vicut; + + mdelay(1); + + if (!gpio_get_value(GPIO_DIP1_FB)) + pw_mode = PW_MODE_KUBOTA; + + switch (pw_mode) { + case PW_MODE_KVG_WITH_YACO: + mode = "KVG (with YaCO)"; + + /* GPIO_ON1_CTRL and GPIO_ON2_CTRL are N.C. on the SoC for + * older revisions */ + + /* Inform YaCO of power mode */ + ret = prt_imx6_yaco_set_kvg_power_mode(priv, "serial0"); + break; + case PW_MODE_KVG_NEW: + mode = "KVG (new)"; + + ret = prt_imx6_init_kvg_set_ctrl(priv, true); + if (ret) + goto exit_init_kvg_vicut; + break; + case PW_MODE_KUBOTA: + mode = "Kubota"; + ret = prt_imx6_init_kvg_set_ctrl(priv, false); + if (ret) + goto exit_init_kvg_vicut; + break; + default: + ret = -ENODEV; + goto exit_init_kvg_vicut; + } + + dev_info(priv->dev, "Power mode: %s\n", mode); + + return 0; + +exit_init_kvg_vicut: + dev_err(priv->dev, "KvG power init failed: %i\n", ret); + + return ret; +} + +static int prt_imx6_init_victgo(struct prt_imx6_priv *priv) +{ + int ret = 0; + + /* Bit 1 of HW-REV is pulled low by 2k2, but must be high on some + * revisions + */ + if (priv->hw_rev & 2) { + ret = gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + if (ret) { + dev_err(priv->dev, "Failed to set gpio up\n"); + return ret; + } + } + + return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_NEW); +} + +static int prt_imx6_init_prti6g(struct prt_imx6_priv *priv) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + int ret; + + /* Configure FEC1 to use 50MHz clock provided by the PHY */ + ret = regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6UL_GPR1_ENET1_CLK_DIR | IMX6UL_GPR1_ENET1_CLK_SEL, + IMX6UL_GPR1_ENET1_CLK_SEL); + if (ret) + dev_err(priv->dev, "regmap error\n"); + } else { + dev_err(priv->dev, "failed to find fsl,imx6ul-iomux-gpr regmap\n"); + } + + return 0; +} + +static int prt_imx6_init_kvg_new(struct prt_imx6_priv *priv) +{ + return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_NEW); +} + +static int prt_imx6_init_kvg_yaco(struct prt_imx6_priv *priv) +{ + return prt_imx6_init_kvg_power(priv, PW_MODE_KVG_WITH_YACO); +} + +#define GPIO_KEY_F6 (0xe0 + 5) +#define GPIO_KEY_CYCLE (0xe0 + 2) + +static int prt_imx6_init_prtvt7(struct prt_imx6_priv *priv) +{ + /* This function relies heavely on the gpio-pca9539 driver */ + + gpio_direction_input(GPIO_KEY_F6); + gpio_direction_input(GPIO_KEY_CYCLE); + + if (gpio_get_value(GPIO_KEY_CYCLE) && gpio_get_value(GPIO_KEY_F6)) + priv->no_usb_check = 1; + + return 0; +} + +static int prt_imx6_init_prtwd3(struct prt_imx6_priv *priv) +{ + void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; + uint32_t val; + + val = readl(iomux + IOMUXC_GPR1); + val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; + writel(val, iomux + IOMUXC_GPR1); + + return 0; +} + +static int prt_imx6_rfid_fixup(struct prt_imx6_priv *priv, + struct device_node *root) +{ + const struct prt_machine_data *dcfg = priv->dcfg; + struct device_node *node, *i2c_node; + char *eeprom_node_name, *alias; + int na, ns, len = 0; + int ret; + u8 *tmp; + + alias = basprintf("i2c%d", dcfg->i2c_adapter); + if (!alias) { + ret = -ENOMEM; + goto exit_error; + } + + i2c_node = of_find_node_by_alias(root, alias); + kfree(alias); + if (!i2c_node) { + dev_err(priv->dev, "Unsupported i2c adapter\n"); + return -ENODEV; + } + + eeprom_node_name = basprintf("/eeprom@%x", dcfg->i2c_addr); + if (!eeprom_node_name) { + return -ENOMEM; + } + + node = of_create_node(i2c_node, eeprom_node_name); + if (!node) { + dev_err(priv->dev, "Failed to create node %s\n", + eeprom_node_name); + return -ENOMEM; + } + + ret = of_property_write_string(node, "compatible", "atmel,24c256"); + if (ret) + goto free_eeprom; + + na = of_n_addr_cells(node); + ns = of_n_size_cells(node); + tmp = xzalloc((na + ns) * 4); + + of_write_number(tmp + len, dcfg->i2c_addr, na); + len += na * 4; + of_write_number(tmp + len, 0, ns); + len += ns * 4; + + ret = of_set_property(node, "reg", tmp, len, 1); + kfree(tmp); + if (ret) + goto free_eeprom; + + return 0; +free_eeprom: + kfree(eeprom_node_name); +exit_error: + dev_err(priv->dev, "Failed to apply fixup: %pe\n", ERR_PTR(ret)); + return ret; +} + +static int prt_imx6_of_fixup(struct device_node *root, void *data) +{ + struct prt_imx6_priv *priv = data; + int ret; + + if (!root) { + dev_err(priv->dev, "Unable to find the root node\n"); + dump_stack(); + return -ENODEV; + } + + ret = prt_imx6_rfid_fixup(priv, root); + if (ret) + goto exit_of_fixups; + + return 0; +exit_of_fixups: + dev_err(priv->dev, "Failed to apply OF fixups: %pe\n", ERR_PTR(ret)); + return ret; +} + +static int prt_imx6_get_id(struct prt_imx6_priv *priv) +{ + struct gpio gpios_type[] = GPIO_HW_TYPE_ID; + struct gpio gpios_rev[] = GPIO_HW_REV_ID; + struct device_node *gpio_np = NULL; + int ret; + + gpio_np = of_find_node_by_name_address(NULL, "gpio@20a0000"); + if (!gpio_np) + return -ENODEV; + + ret = of_device_ensure_probed(gpio_np); + if (ret) + return ret; + + ret = gpio_array_to_id(gpios_type, ARRAY_SIZE(gpios_type), &priv->hw_id); + if (ret) + goto exit_get_id; + + ret = gpio_array_to_id(gpios_rev, ARRAY_SIZE(gpios_rev), &priv->hw_rev); + if (ret) + goto exit_get_id; + + return 0; +exit_get_id: + dev_err(priv->dev, "Failed to read gpio ID: %pe\n", ERR_PTR(ret)); + return ret; +} + +static int prt_imx6_get_dcfg(struct prt_imx6_priv *priv) +{ + const struct prt_machine_data *dcfg, *found = NULL; + int ret; + + dcfg = of_device_get_match_data(priv->dev); + if (!dcfg) { + ret = -EINVAL; + goto exit_get_dcfg; + } + + for (; dcfg->hw_id != UINT_MAX; dcfg++) { + if (dcfg->hw_id != priv->hw_id) + continue; + if (dcfg->hw_rev > priv->hw_rev) + break; + found = dcfg; + } + + if (!found) { + ret = -ENODEV; + goto exit_get_dcfg; + } + + priv->dcfg = found; + + return 0; +exit_get_dcfg: + dev_err(priv->dev, "Failed to get dcfg: %i\n", ret); + return ret; +} + +static int prt_imx6_probe(struct device *dev) +{ + struct prt_imx6_priv *priv; + struct param_d *p; + int ret; + + priv = xzalloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->name = of_get_machine_compatible(); + + pr_info("Detected machine type: %s\n", priv->name); + + ret = prt_imx6_get_id(priv); + if (ret) + goto free_priv; + + pr_info(" HW type: %d\n", priv->hw_id); + pr_info(" HW revision: %d\n", priv->hw_rev); + prt_of_fixup_hwrev(priv); + + ret = prt_imx6_get_dcfg(priv); + if (ret) + goto free_priv; + + p = dev_add_param_uint32_ro(dev, "boardrev", &priv->hw_rev, "%u"); + if (IS_ERR(p)) { + ret = PTR_ERR(p); + goto free_priv; + } + + p = dev_add_param_uint32_ro(dev, "boardid", &priv->hw_id, "%u"); + if (IS_ERR(p)) { + ret = PTR_ERR(p); + goto free_priv; + } + + ret = prt_imx6_of_fixup(of_get_root_node(), priv); + if (ret) + goto free_priv; + + prt_priv = priv; + + return 0; +free_priv: + kfree(priv); + return ret; +} + +static const struct prt_machine_data prt_imx6_cfg_alti6p[] = { + { + .hw_id = HW_TYPE_ALTI6P, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_victgo[] = { + { + .hw_id = HW_TYPE_VICTGO, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_victgo, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_vicut1[] = { + { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 0, + .i2c_addr = 0x50, + .i2c_adapter = 1, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_kvg_yaco, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_kvg_new, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_vicut1q[] = { + { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 0, + .i2c_addr = 0x50, + .i2c_adapter = 1, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT1, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_kvg_yaco, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_kvg_yaco, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_kvg_new, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_vicutp[] = { + { + .hw_id = HW_TYPE_VICUT2, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_kvg_new, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_lanmcu[] = { + { + .hw_id = HW_TYPE_LANMCU, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_plybas[] = { + { + .hw_id = HW_TYPE_PLYBAS, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR | PRT_IMX6_USB_LONG_DELAY, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_plym2m[] = { + { + .hw_id = HW_TYPE_PLYM2M, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR | PRT_IMX6_USB_LONG_DELAY, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prti6g[] = { + { + .hw_id = HW_TYPE_PRTI6G, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 1, + .sd_usdhc = 0, + .init = prt_imx6_init_prti6g, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prti6q[] = { + { + .hw_id = HW_TYPE_PRTI6Q, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 2, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = HW_TYPE_PRTI6Q, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtmvt[] = { + { + .hw_id = HW_TYPE_PRTMVT, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtrvt[] = { + { + .hw_id = HW_TYPE_PRTRVT, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_SPI_NOR, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtvt7[] = { + { + .hw_id = HW_TYPE_PRTVT7, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_prtvt7, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER | + PRT_IMX6_USB_LONG_DELAY, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtwd2[] = { + { + .hw_id = HW_TYPE_PRTWD2, + .hw_rev = 0, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_prtwd3[] = { + { + .hw_id = HW_TYPE_PRTWD2, + .hw_rev = 2, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 2, + .sd_usdhc = 0, + .init = prt_imx6_init_prtwd3, + .flags = PRT_IMX6_BOOTSRC_EMMC, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct prt_machine_data prt_imx6_cfg_jozacp[] = { + { + .hw_id = HW_TYPE_JOZACP, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 0, + .sd_usdhc = 2, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER, + }, { + .hw_id = HW_TYPE_JOZACPP, + .hw_rev = 1, + .i2c_addr = 0x51, + .i2c_adapter = 0, + .emmc_usdhc = 0, + .sd_usdhc = 2, + .flags = PRT_IMX6_BOOTSRC_EMMC | PRT_IMX6_BOOTCHOOSER, + }, { + .hw_id = UINT_MAX + }, +}; + +static const struct of_device_id prt_imx6_of_match[] = { + { .compatible = "alt,alti6p", .data = &prt_imx6_cfg_alti6p }, + { .compatible = "kvg,victgo", .data = &prt_imx6_cfg_victgo }, + { .compatible = "kvg,vicut1", .data = &prt_imx6_cfg_vicut1 }, + { .compatible = "kvg,vicut1q", .data = &prt_imx6_cfg_vicut1q }, + { .compatible = "kvg,vicutp", .data = &prt_imx6_cfg_vicutp }, + { .compatible = "vdl,lanmcu", .data = &prt_imx6_cfg_lanmcu }, + { .compatible = "ply,plybas", .data = &prt_imx6_cfg_plybas }, + { .compatible = "ply,plym2m", .data = &prt_imx6_cfg_plym2m }, + { .compatible = "prt,prti6g", .data = &prt_imx6_cfg_prti6g }, + { .compatible = "prt,prti6q", .data = &prt_imx6_cfg_prti6q }, + { .compatible = "prt,prtmvt", .data = &prt_imx6_cfg_prtmvt }, + { .compatible = "prt,prtrvt", .data = &prt_imx6_cfg_prtrvt }, + { .compatible = "prt,prtvt7", .data = &prt_imx6_cfg_prtvt7 }, + { .compatible = "prt,prtwd2", .data = &prt_imx6_cfg_prtwd2 }, + { .compatible = "prt,prtwd3", .data = &prt_imx6_cfg_prtwd3 }, + { .compatible = "joz,jozacp", .data = &prt_imx6_cfg_jozacp }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(prt_imx6_of_match); + +static struct driver prt_imx6_board_driver = { + .name = "board-protonic-imx6", + .probe = prt_imx6_probe, + .of_compatible = DRV_OF_COMPAT(prt_imx6_of_match), +}; +postcore_platform_driver(prt_imx6_board_driver); diff --git a/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg new file mode 100644 index 0000000000..5bcd6c5f3c --- /dev/null +++ b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg @@ -0,0 +1,352 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Timing configuration: + * + * MDCFG0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRFC 2Gb 400MHz 0x3f (64) 24 0x3f000000 + * 4Gb 400MHz 0x77 (120) 24 0x77000000 + * 8Gb 400MHz 0x8b (140) 24 0x8b000000 + * 2Gb 533MHz 0x55 (86) 24 0x55000000 + * 4Gb 533MHz 0x9f (160) 24 0x9f000000 + * 8Gb 533MHz 0xba (187) 24 0xba000000 + * tXS 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * tXP * 400MHz 0x2 (3) 13 0x00004000 + * * 533MHz 0x3 (4) 13 0x00006000 + * tXPDLL * 400MHz 0x9 (10) 9 0x00001200 + * * 533MHz 0xc (13) 9 0x00001800 + * tFAW * 400MHz 0x13 (20) 4 0x00000130 + * * 533MHz 0x1a (27) 4 0x000001a0 + * tCL * 400MHz 0x3 (6) 0 0x00000003 + * * 533MHz-CL7 0x4 (7) 0 0x00000004 + * * 533MHz-CL8 0x5 (8) 0 0x00000005 + * ---------------------------------------------------------------- + */ +#define MDCFG0_2G_400MHZ 0x3f435333 +#define MDCFG0_4G_400MHZ 0x777b5333 +#define MDCFG0_8G_400MHZ 0x8b8f5333 +#define MDCFG0_2G_533MHZ_CL8 0x555b79a5 +#define MDCFG0_2G_533MHZ_CL7 0x555b79a4 +#define MDCFG0_4G_533MHZ_CL8 0x9fa579a5 +#define MDCFG0_4G_533MHZ_CL7 0x9fa579a4 +#define MDCFG0_8G_533MHZ_CL8 0xbac079a5 +#define MDCFG0_8G_533MHZ_CL7 0xbac079a4 + +/* + * MDCFG1: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRCD * 400MHz 0x5 (6) 28 0xa0000000 + * * 533MHz 0x7 (8) 28 0xe0000000 + * tRP * 400MHz 0x5 (6) 26 0x14000000 + * * 533MHz 0x7 (8) 26 0x1c000000 + * tRC * 400MHz 0x14 (21) 21 0x02800000 + * * 533MHz 0x1b (28) 21 0x03600000 + * tRAS * 400MHz 0x0e (15) 16 0x000e0000 + * * 533MHz 0x13 (20) 16 0x00130000 + * tRPA * 0x1 (tRP+1) 15 0x00008000 + * tWR * 400MHz 0x5 (6) 9 0x00000a00 + * * 533MHz 0x7 (8) 9 0x00000e00 + * tMRD * 0xb (12) 5 0x00000160 + * tCWL * 400MHz 0x3 (5) 0 0x00000003 + * * 533MHz 0x4 (6) 0 0x00000004 + * ---------------------------------------------------------------- + */ +#define MDCFG1_400MHZ 0xb68e8b63 +#define MDCFG1_533MHZ 0xff738f64 + +/* + * MDCFG2: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tDLLK * 0x1ff (512) 16 0x01ff0000 + * tRTP * 0x3 (4) 6 0x000000c0 + * tWTR * 0x3 (4) 3 0x00000018 + * tRRD * 400MHz 0x3 (4) 0 0x00000003 + * * 533MHz 0x5 (6) 0 0x00000005 + * ---------------------------------------------------------------- + */ +#define MDCFG2_400MHZ 0x01ff00db +#define MDCFG2_533MHZ 0x01ff00dd + +/* + * MDOR: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tXPR 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * SDE_to_RST * 0x10 (14) 8 0x00001000 + * RST_to_CKE * 0x23 (33) 0 0x00000023 + * ---------------------------------------------------------------- + */ +#define MDOR_2G_400MHZ 0x00431023 +#define MDOR_4G_400MHZ 0x007b1023 +#define MDOR_8G_400MHZ 0x008f1023 +#define MDOR_2G_533MHZ 0x005b1023 +#define MDOR_4G_533MHZ 0x00a51023 +#define MDOR_8G_533MHZ 0x00c01023 + +/* + * MDOTC ODT delays: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tAOFPD * 400MHz 0x0 (1) 27 0x00000000 + * * 533MHz 0x1 (2) 27 0x08000000 + * tAONPD * 400MHz 0x0 (1) 24 0x00000000 + * * 533MHz 0x1 (2) 24 0x01000000 + * tANPD * 400MHz 0x3 (4) 20 0x00300000 + * * 533MHz 0x4 (5) 20 0x00400000 + * tAXPD * 400MHz 0x3 (4) 16 0x00030000 + * * 533MHz 0x4 (5) 16 0x00040000 + * tODTLon * 400MHz 0x3 (3) 12 0x00003000 + * * 533MHz 0x4 (4) 12 0x00004000 + * tODTidle_off * 400MHz 0x3 (3) 4 0x00000030 + * * 533MHz 0x4 (4) 4 0x00000040 + * ---------------------------------------------------------------- + */ +#define MDOTC_400MHZ 0x00333030 +#define MDOTC_533MHZ 0x09444040 + +/* + * MDPDC: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * PRCT_1 * 0x0 28 0x00000000 + * PRCT_0 * 0x0 24 0x00000000 + * tCKE * 0x2 (3) 16 0x00020000 + * PWDT_1 * 0x5 (256) 12 0x00005000 + * PWDT_0 * 0x5 (256) 8 0x00000500 + * SLOW_PD * 0x0 (0) 7 0x00000000 + * BOTH_CS_PD * 0x1 (1) 6 0x00000040 + * tCKSRX * 400MHz 0x5 (5) 3 0x00000028 + * * 533MHz 0x6 (6) 3 0x00000030 + * tCKSRE * 400MHz 0x5 (5) 0 0x00000005 + * * 533MHz 0x6 (6) 0 0x00000006 + * ---------------------------------------------------------------- + */ +#define MDPDC_400MHZ 0x0002556d +#define MDPDC_533MHZ 0x00025576 + +/* + * MDCTL: + * 2Gb: CS0 enable, 14bit ROW, 10bit COL, BL=8, 64bit data + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * SDE_0 * 0x1 (1) 31 0x80000000 + * SDE_1 * 0x0 (0) 30 0x00000000 + * ROW 2Gb * 0x3 (14) 24 0x03000000 + * 4Gb * 0x4 (15) 24 0x04000000 + * 8Gb * 0x5 (16) 24 0x05000000 + * COL * 0x1 (10) 20 0x00100000 + * BL * 0x1 (8) 19 0x00080000 + * DSIZ 64bit 0x2 (64) 16 0x00020000 + * DSIZ 32bit 0x1 (32) 16 0x00010000 + * DSIZ 16bit 0x0 (16) 16 0x00000000 + * ---------------------------------------------------------------- + */ +#define MDCTL_2G_16BIT 0x83180000 +#define MDCTL_2G_32BIT 0x83190000 +#define MDCTL_2G 0x831a0000 +#define MDCTL_4G_16BIT 0x84180000 +#define MDCTL_4G_32BIT 0x84190000 +#define MDCTL_4G 0x841a0000 +#define MDCTL_8G 0x851a0000 + +/* + * MDASP Address space partitioning: + * + * At 0.25GiB, internal address space ends. Above that DDR3 should be + * located. The CS1/CS0 split-line determines where: + * + * For 1x2Gb chips (0.25GiB total on CS0): 0.5GiB + * For 2x4Gb chips (1GiB total on CS0): 1.25GiB + * For 4x2Gb chips (1GiB total on CS0): 1.25GiB + * For 4x4Gb chips (2GiB total on CS0): 2.25GiB + * For 4x8Gb chips (4GiB total on CS0): 4.00GiB (maximum possible, + * shadowed partially by internal address space). + * + * Register value Split + * --------------------------- + * 0x0000000f 0.5GiB + * 0x00000017 0.75GiB + * 0x00000027 1.25GiB + * 0x00000047 2.25GiB + * 0x0000007f 4.00GiB + */ +#define MDASP_512MIB 0x0000000f +#define MDASP_768MIB 0x00000017 +#define MDASP_1GIB25 0x00000027 +#define MDASP_2GIB25 0x00000047 +#define MDASP_4GIB00 0x0000007f + +/* + * Initialize DDR3 chips + * MDSCR: Value = 0xvvvv803n, with 0xvvvv = value, n = Reg. number (BA) + */ +/* + * DDR3 chip MR2, n = 2: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Rtt(wr) * 0x0 (disabled) 10, 9 0x0000 + * SR-Temp. * 0x1 (Extended) 7 0x0080 + * Auto-SR * 0x0 (Manual) 6 0x0000 + * CWL * 400MHz 0x0 (5tCK) 5, 4, 3 0x0000 + * * 533MHz 0x1 (6tCK) 5, 4, 3 0x0008 + * ---------------------------------------------------------------- + */ +#define DDR3_MR2_400MHZ_RTT_OFF 0x00808032 +#define DDR3_MR2_533MHZ_RTT_OFF 0x00888032 +#define DDR3_MR2_400MHZ_RTT_120 0x04808032 +#define DDR3_MR2_533MHZ_RTT_120 0x04888032 + +/* + * DDR3 chip MR1, n = 1: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Qoff * 0x0 (enabled) 12 0x0000 + * TDQS * 0x0 (disabled) 11 0x0000 + * Rtt * 0x0 (disabled) 9, 6, 2 0x0000 + * Write-levelling * 0x0 (disable) 7 0x0000 + * ODS * 0x0 (RZQ/6=40) 5, 1 0x0000 + * DLL * 0x0 (enable) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR1_RTT_OFF_ODS_40 0x00008031 +#define DDR3_MR1_RTT_120_ODS_40 0x00408031 +#define DDR3_MR1_RTT_60_ODS_40 0x00048031 +#define DDR3_MR1_RTT_OFF_ODS_34 0x00028031 +#define DDR3_MR1_RTT_120_ODS_34 0x00428031 +#define DDR3_MR1_RTT_60_ODS_34 0x00068031 + +/* + * DDR3 chip MR0, n = 0: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Precharge PD * 0x1 (fast exit) 12 0x1000 + * WR 400MHz 0x2 (6) 11,10,9 0x0400 + * 533MHz 0x4 (8) 11,10,9 0x0800 + * DLL reset * 0x1 (Yes) 8 0x0100 + * CL 400MHz 0x4 (6) 6,5,4,2 0x0020 + * 533MHz 0x6 (7) 6,5,4,2 0x0030 + * 533MHz 0x8 (8) 6,5,4,2 0x0040 + * RD burst type * 0x0 (seq.) 3 0x0000 + * BL * 0x0 (BL8) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR0_400MHZ 0x15208030 +#define DDR3_MR0_533MHZ_CL7 0x19308030 +#define DDR3_MR0_533MHZ_CL8 0x19408030 + + +/* + * MDREF: + * REF_SEL (bit 14,15): 0 (64kHz, needed for high-temp.) + * REFR (bit 11, 12, 13): 0x3 (4 refreshes) -> 0x00001800 + * 0x7 (8 refreshes) -> 0x00003800 + */ +#define MDREF_64KHZ 0x00001800 +#define MDREF_32KHZ 0x00007800 + +/* MPODTCTRL */ +#define MPODTCTRL_ODT_OFF 0x00000007 +#define MPODTCTRL_ODT_120 0x00011117 +#define MPODTCTRL_ODT_60 0x00022227 +#define MPODTCTRL_ODT_40 0x00033337 + +/* + * MPDGCTRL0: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * RST_RD_FIFO * 0 31 0x00000000 + * DG_CMP_CYC * 1 30 0x40000000 + * DG_DIS * 0 29 0x00000000 + * HW_DG_EN * 0 28 0x00000000 + * DG_HC_DEL1 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_EXT_UP * 0 23 0x00000000 + * DG_DL_ABS_OFFS1 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH0_400MHZ 0x42350231 +#define MPDGCTRL0_CH0_533MHZ 0x434b0350 +/* + * + * Channel 1: + * + * DG_HC_DEL1 (5) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS1 (5) 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 (4) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 (4) 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH1_400MHZ 0x42350231 +#define MPDGCTRL0_CH1_533MHZ 0x434b0350 + +/* + * MPDGCTRL1: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * DG_HC_DEL3 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x4c 16 0x004c0000 + * DG_HC_DEL2 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 400MHz 0x18 0 0x00000018 + * 533MHz 0x59 0 0x00000059 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH0_400MHZ 0x021a0218 +#define MPDGCTRL1_CH0_533MHZ 0x034c0359 +/* + * + * Channel 1: + * + * DG_HC_DEL3 (7) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 (7) 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x65 16 0x00650000 + * DG_HC_DEL2 (6) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 (6) 400MHz 0x18 0 0x00000018 + * 533MHz 0x48 0 0x00000048 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH1_400MHZ 0x021a0218 +#define MPDGCTRL1_CH1_533MHZ 0x03650348 diff --git a/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg new file mode 100644 index 0000000000..4e71e493ae --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: ALTI6P doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-jozacp.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-jozacp.imxcfg new file mode 100644 index 0000000000..472767611d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-jozacp.imxcfg @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x80000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" +#include "padsetup-ul.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 0x00000047 /* MDASP_512MIB */ +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000117 /* MPODTCTRL_ODT_120 */ + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b0850 0x40404040 /* For now set all to 50%. */ + +/* MPWLDECTRL0 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff diff --git a/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg new file mode 100644 index 0000000000..7deaaa9b7b --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug 0 LED */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e060c 0x000130b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg new file mode 100644 index 0000000000..c9c9d076f5 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg new file mode 100644 index 0000000000..71df95b968 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg new file mode 100644 index 0000000000..472767611d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x80000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" +#include "padsetup-ul.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 0x00000047 /* MDASP_512MIB */ +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000117 /* MPODTCTRL_ODT_120 */ + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b0850 0x40404040 /* For now set all to 50%. */ + +/* MPWLDECTRL0 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg new file mode 100644 index 0000000000..deced6901b --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +wm 32 0x020e0244 0x00000005 +wm 32 0x020e05f8 0x000130b0 +wm 32 0x020e0614 0x0001b0b0 + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00000742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_8G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_4GIB00 +wm 32 0x021b0000 MDCTL_8G + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg new file mode 100644 index 0000000000..58530910fc --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg new file mode 100644 index 0000000000..c9c9d076f5 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg new file mode 100644 index 0000000000..5073458a03 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug 0 LED */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e060c 0x000130b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_768MIB +wm 32 0x021b0000 MDCTL_2G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg new file mode 100644 index 0000000000..035b5f1315 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "lpddr2-defines.imxcfg" + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* Set DDR clk to 400MHz. */ +wm 32 0x020c4018 0x00060324 + +/* #include "padsetup-q.imxcfg" */ + +/* LPDDR2 i.MX6D/Q pad setup */ +wm 32 0x020e0798 0x00080000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00003030 +wm 32 0x020e05b0 0x00003030 +wm 32 0x020e0524 0x00003030 +wm 32 0x020e051c 0x00003030 +wm 32 0x020e0518 0x00003030 +wm 32 0x020e050c 0x00003030 +wm 32 0x020e05b8 0x00003030 +wm 32 0x020e05c0 0x00003030 + +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 +wm 32 0x021b401c 0x00008000 +/* check 32 until_any_bit_set 0x021b401c 0x00004000 */ + + +wm 32 0x021b085c 0x1b4700c7 +wm 32 0x021b485c 0x1b4700c7 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0890 0x00400000 +wm 32 0x021b4890 0x00400000 + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +wm 32 0x021b083c 0x20000000 +wm 32 0x021b0840 0x00000000 +wm 32 0x021b483c 0x20000000 +wm 32 0x021b4840 0x00000000 + + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* Set Write data delay 3 delay units for all bits */ +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b0834 0xf3333333 +wm 32 0x021b0838 0xf3333333 +wm 32 0x021b482c 0xf3333333 +wm 32 0x021b4830 0xf3333333 +wm 32 0x021b4834 0xf3333333 +wm 32 0x021b4838 0xf3333333 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* + * Configure MMDC Channel 0 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b0018 0x00001602 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b000c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b0010 MDCFG1_LPDDR2 +wm 32 0x021b0014 MDCFG2_LPDDR2 + +wm 32 0x021b0018 0x0000174c +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b0030 MDOR_LPDDR2 +wm 32 0x021b0038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b0040 0x0000004f /* NOTE: According to RM */ +wm 32 0x021b0400 0x11420000 /* MAARCR disable dyn jump */ +wm 32 0x021b0000 MDCTL_LPDDR2 + +/* + * Configure MMDC Channel 1 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b4018 0x00001602 +check 32 until_all_bits_clear 0x021b4018 0x00000002 + +wm 32 0x021b4004 0x00020036 +wm 32 0x021b4008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b400c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b4010 MDCFG1_LPDDR2 +wm 32 0x021b4014 MDCFG2_LPDDR2 + +wm 32 0x021b4018 0x0000174c +wm 32 0x021b401c 0x00008000 +wm 32 0x021b402c 0x0f9f26d2 /* MDOR */ +wm 32 0x021b4030 MDOR_LPDDR2 +wm 32 0x021b4038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b4040 MDASP_768MIB /* NOTE: According to RM */ +wm 32 0x021b4400 0x11420000 /* MAARCR disable dyn jump */ +wm 32 0x021b4000 MDCTL_LPDDR2 + +/* + * Configure LPDDR2 devices + */ + +wm 32 0x021b001c 0x00008010 /* Precharge all ch 0 */ +wm 32 0x021b401c 0x00008010 /* Precharge all ch 1 */ + +/* Channel 0 */ +wm 32 0x021b001c 0x003f8030 /* Reset */ +wm 32 0x021b001c 0xff0a8030 /* Calibrate */ +wm 32 0x021b001c 0x82018030 /* MR1: nWR=6, WC=0, BT=0, BL=BL4 */ +wm 32 0x021b001c 0x04028030 /* MR2: RL6/WL3 */ +wm 32 0x021b001c 0x02038030 /* MR3: DS = 40 Ohm */ + +/* Channel 1 */ +wm 32 0x021b401c 0x003f8030 +wm 32 0x021b401c 0xff0a8030 +wm 32 0x021b401c 0x82018030 +wm 32 0x021b401c 0x04028030 +wm 32 0x021b401c 0x02038030 + +/* MPDGCTRL disabled, reset fifos */ +wm 32 0x021b083c 0xa0000000 +wm 32 0x021b083c 0xa0000000 +check 32 until_all_bits_clear 0x021b083c 0x80000000 +wm 32 0x021b483c 0xa0000000 +wm 32 0x021b483c 0xa0000000 +check 32 until_all_bits_clear 0x021b483c 0x80000000 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0020 MDREF_64KHZ +wm 32 0x021b4020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000000 /* LPDDR2: Disable ODT! */ +wm 32 0x021b4818 0x00000000 + +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b4004 MDPDC_400MHZ + +/* MAPSR */ +wm 32 0x021b0404 0x00011006 /* Enable autorefresh */ +wm 32 0x021b4404 0x00011006 /* Enable autorefresh */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ +wm 32 0x021b401c 0x00000000 /* Disable configuration req */ + + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* configure 100K pull down on USB_ETH_CHG -> ADC_ICHG */ +wm 32 0x020e06cc 0x000130f9 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg new file mode 100644 index 0000000000..be2b9883a8 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg @@ -0,0 +1,282 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "lpddr2-defines.imxcfg" + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* Set DDR clk to 400MHz. */ +wm 32 0x020c4018 0x00060324 + +/* #include "padsetup-q.imxcfg" */ + +/* LPDDR2 i.MX6D/Q pad setup */ +wm 32 0x020e0798 0x00080000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00003030 +wm 32 0x020e05b0 0x00003030 +wm 32 0x020e0524 0x00003030 +wm 32 0x020e051c 0x00003030 +wm 32 0x020e0518 0x00003030 +wm 32 0x020e050c 0x00003030 +wm 32 0x020e05b8 0x00003030 +wm 32 0x020e05c0 0x00003030 + +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 +wm 32 0x021b401c 0x00008000 +/* check 32 until_any_bit_set 0x021b401c 0x00004000 */ + + +wm 32 0x021b085c 0x1b4700c7 +wm 32 0x021b485c 0x1b4700c7 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0890 0x00400000 +wm 32 0x021b4890 0x00400000 + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +wm 32 0x021b083c 0x20000000 +wm 32 0x021b0840 0x00000000 +wm 32 0x021b483c 0x20000000 +wm 32 0x021b4840 0x00000000 + + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* Set Write data delay 3 delay units for all bits */ +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b0834 0xf3333333 +wm 32 0x021b0838 0xf3333333 +wm 32 0x021b482c 0xf3333333 +wm 32 0x021b4830 0xf3333333 +wm 32 0x021b4834 0xf3333333 +wm 32 0x021b4838 0xf3333333 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* NOC: DDRCONF */ +/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */ +/* Values (Address mapping for 64bit): + * 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit) + * 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit) + * 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit) + * 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit) + * 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave + * ... + */ +wm 32 0x00bb0008 0x00000000 + +/* + * NOC DdrTiming: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * ActToAct 533MHz 0x1b (28) 0 0x0000001b + * LPDDR2 0x18 (24) 0 0x00000018 + * RdToMiss 533MHz 0x10 (16) 6 0x00000400 + * LPDDR2 0x11 (17) 6 0x00000440 + * WrToMiss * 0x1e (30) 12 0x0001e000 + * LPDDR2 0x19 (25) 12 0x00019000 + * BurstLen * 0x4 (8/2) 18 0x00100000 + * LPDDR2 0x2 (4/2) 18 0x00080000 + * RdToWr * 0x3 (3) 21 0x00600000 + * LPDDR2 0x5 (5) 21 0x00a00000 + * WrToRd * 0xa (10) 26 0x28000000 + * LPDDR2 0x6 (6) 26 0x18000000 + * BwRatio * 0x0 (0) 31 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */ +wm 32 0x00bb000c 0x18a99459 + +/* + * NOC Activate: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * Rrd * 0x6 (6) 0 0x00000006 + * LPDDR2 0x4 (4) 0 0x00000004 + * Faw * 0x1b (27) 4 0x000001b0 + * LPDDR2 0x14 (20) 4 0x00000140 + * FawBank * 0x0 (0) 10 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */ +wm 32 0x00bb0038 0x00000144 + +/* + * NOC ReadLatency: (FIXME) + */ +wm 32 0x00bb0014 0x00000040 + +/* + * Configure MMDC Channel 0 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b0018 0x00001602 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b000c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b0010 MDCFG1_LPDDR2 +wm 32 0x021b0014 MDCFG2_LPDDR2 + +wm 32 0x021b0018 0x0000174c +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b0030 MDOR_LPDDR2 +wm 32 0x021b0038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b0040 0x0000004f /* NOTE: According to RM */ +wm 32 0x021b0400 0x15420000 /* MAARCR disable dyn jump/reordering */ +wm 32 0x021b0000 MDCTL_LPDDR2 + +/* + * Configure MMDC Channel 1 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b4018 0x00001602 +check 32 until_all_bits_clear 0x021b4018 0x00000002 + +wm 32 0x021b4004 0x00020036 +wm 32 0x021b4008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b400c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b4010 MDCFG1_LPDDR2 +wm 32 0x021b4014 MDCFG2_LPDDR2 + +wm 32 0x021b4018 0x0000174c +wm 32 0x021b401c 0x00008000 +wm 32 0x021b402c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b4030 MDOR_LPDDR2 +wm 32 0x021b4038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b4040 MDASP_768MIB /* NOTE: According to RM */ +wm 32 0x021b4400 0x15420000 /* MAARCR disable dyn jump/reordering */ +wm 32 0x021b4000 MDCTL_LPDDR2 + +/* + * Configure LPDDR2 devices + */ + +wm 32 0x021b001c 0x00008010 /* Precharge all ch 0 */ +wm 32 0x021b401c 0x00008010 /* Precharge all ch 1 */ + +/* Channel 0 */ +wm 32 0x021b001c 0x003f8030 /* Reset */ +wm 32 0x021b001c 0xff0a8030 /* Calibrate */ +wm 32 0x021b001c 0x82018030 /* MR1: nWR=6, WC=0, BT=0, BL=BL4 */ +wm 32 0x021b001c 0x04028030 /* MR2: RL6/WL3 */ +wm 32 0x021b001c 0x02038030 /* MR3: DS = 40 Ohm */ + +/* Channel 1 */ +wm 32 0x021b401c 0x003f8030 +wm 32 0x021b401c 0xff0a8030 +wm 32 0x021b401c 0x82018030 +wm 32 0x021b401c 0x04028030 +wm 32 0x021b401c 0x02038030 + +/* MPDGCTRL disabled, reset fifos */ +wm 32 0x021b083c 0xa0000000 +wm 32 0x021b083c 0xa0000000 +check 32 until_all_bits_clear 0x021b083c 0x80000000 +wm 32 0x021b483c 0xa0000000 +wm 32 0x021b483c 0xa0000000 +check 32 until_all_bits_clear 0x021b483c 0x80000000 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0020 MDREF_64KHZ +wm 32 0x021b4020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000000 /* LPDDR2: Disable ODT! */ +wm 32 0x021b4818 0x00000000 + +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b4004 MDPDC_400MHZ + +/* MAPSR */ +wm 32 0x021b0404 0x00011006 /* Enable autorefresh */ +wm 32 0x021b4404 0x00011006 /* Enable autorefresh */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ +wm 32 0x021b401c 0x00000000 /* Disable configuration req */ + + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* configure 100K pull down on USB_ETH_CHG -> ADC_ICHG */ +wm 32 0x020e06cc 0x000130f9 diff --git a/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg new file mode 100644 index 0000000000..e3f0f0a19a --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg new file mode 100644 index 0000000000..a879229923 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_2GIB25 +wm 32 0x021b0000 MDCTL_4G + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config */ +wm 32 0x020e0768 0x00080000 /* 1V2 DDR IO */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x0001f0b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg new file mode 100644 index 0000000000..8e41a410df --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +/* wm 32 0x020e0244 0x00000005 */ +wm 32 0x020e05f8 0x000130b0 +/* wm 32 0x020e0614 0x000130b0 */ + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_8G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_4GIB00 +wm 32 0x021b0000 MDCTL_8G +// check 32 until_any_bit_set 0x021b0018 0x80000000 + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +/* DQS gating calibration measured on UT2 and UTC boards */ +wm 32 0x021b083c 0x43000300 +wm 32 0x021b483c 0x430a0310 + +wm 32 0x021b0840 0x030002b0 +wm 32 0x021b4840 0x02b00255 + +/* MPRDDLCTL, MPWRDLCTL */ +/* Measured on UT2 and UTC, good averages */ +wm 32 0x021b0848 0x453a3a3a +wm 32 0x021b4848 0x403b3947 +wm 32 0x021b0850 0x40444540 +wm 32 0x021b4850 0x46404840 + +/* MPWLDECTRL0,1 */ +/* Measured and averaged on UT2 and UTC boards */ +wm 32 0x021b080c 0x00200020 +wm 32 0x021b0810 0x0026001e +wm 32 0x021b480c 0x00100028 +wm 32 0x021b4810 0x0012001b + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg new file mode 100644 index 0000000000..54a86a0008 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +/* wm 32 0x020e0244 0x00000005 */ +wm 32 0x020e05f8 0x000130b0 +/* wm 32 0x020e0614 0x000130b0 */ + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00001742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_4G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_2GIB25 + +/* Dual-Plus specific configuration */ +/* MMDC: MAARCR: Disable reordering */ +wm 32 0x021b0400 0x14420000 +/* MMDC: MPPDCMPR2: ZQ Offset setting (TODO) */ +wm 32 0x021b0890 0x00400008 /* Freescale sabre-auto: 0x00400C58 */ + +/* NOC: DDRCONF */ +/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */ +/* Values (Address mapping for 64bit): + * 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit) + * 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit) + * 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit) + * 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit) + * 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave + * ... + */ +wm 32 0x00bb0008 0x00000000 + +/* + * NOC DdrTiming: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * ActToAct 533MHz 0x1b (28) 0 0x0000001b + * RdToMiss 533MHz 0x10 (16) 6 0x00000400 + * WrToMiss * 0x1e (30) 12 0x0001e000 + * BurstLen * 0x4 (8/2) 18 0x00100000 + * RdToWr * 0x3 (3) 21 0x00600000 + * WrToRd * 0xa (10) 26 0x28000000 + * BwRatio * 0x0 (0) 31 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */ +wm 32 0x00bb000c 0x2871e41c + +/* + * NOC Activate: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * Rrd * 0x6 (6) 0 0x00000006 + * Faw * 0x1b (27) 4 0x000001b0 + * FawBank * 0x0 (0) 10 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */ +wm 32 0x00bb0038 0x000001b6 + +/* + * NOC ReadLatency: (FIXME) + */ +wm 32 0x00bb0014 0x00000040 + +/* + * NOC IPU1/IPU2 aging: (FIXME) + */ +wm 32 0x00bb0028 0x00000020 +wm 32 0x00bb002c 0x00000020 + +wm 32 0x021b0000 MDCTL_4G +// check 32 until_any_bit_set 0x021b0018 0x80000000 + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ diff --git a/arch/arm/boards/protonic-imx6/lowlevel.c b/arch/arm/boards/protonic-imx6/lowlevel.c new file mode 100644 index 0000000000..38e65037e6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/lowlevel.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 Protonic Holland + * Copyright (C) 2020 Oleksij Rempel, Pengutronix + */ + +#include <asm/barebox-arm.h> +#include <common.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> + +extern char __dtb_z_imx6q_prti6q_start[]; +extern char __dtb_z_imx6q_prtwd2_start[]; +extern char __dtb_z_imx6q_vicut1_start[]; +extern char __dtb_z_imx6dl_alti6p_start[]; +extern char __dtb_z_imx6dl_lanmcu_start[]; +extern char __dtb_z_imx6dl_plybas_start[]; +extern char __dtb_z_imx6dl_plym2m_start[]; +extern char __dtb_z_imx6dl_prtmvt_start[]; +extern char __dtb_z_imx6dl_prtrvt_start[]; +extern char __dtb_z_imx6dl_prtvt7_start[]; +extern char __dtb_z_imx6dl_victgo_start[]; +extern char __dtb_z_imx6dl_vicut1_start[]; +extern char __dtb_z_imx6qp_prtwd3_start[]; +extern char __dtb_z_imx6qp_vicutp_start[]; +extern char __dtb_z_imx6ul_prti6g_start[]; +extern char __dtb_z_imx6ull_jozacp_start[]; + +ENTRY_FUNCTION(start_imx6q_prti6q, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_prti6q_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6q_prtwd2, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_prtwd2_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6q_vicut1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_vicut1_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_alti6p, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_alti6p_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_lanmcu, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_lanmcu_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_plybas, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_plybas_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_plym2m, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_plym2m_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtmvt, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtmvt_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtrvt, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtrvt_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtvt7, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtvt7_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_victgo, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_victgo_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_vicut1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_vicut1_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6qp_prtwd3, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6qp_prtwd3_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6qp_vicutp, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6qp_vicutp_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6ul_prti6g, r0, r1, r2) +{ + void *fdt; + + imx6ul_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6ul_prti6g_start + get_runtime_offset(); + + imx6ul_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6ull_jozacp, r0, r1, r2) +{ + void *fdt; + + imx6ul_cpu_lowlevel_init(); + + /* Disconnect USDHC2 from SD card */ + writel(0x5, 0x020e0178); + writel(0x5, 0x020e017c); + writel(0x5, 0x020e0180); + writel(0x5, 0x020e0184); + writel(0x5, 0x020e0188); + writel(0x5, 0x020e018c); + + fdt = __dtb_z_imx6ull_jozacp_start + get_runtime_offset(); + + imx6ul_barebox_entry(fdt); +} diff --git a/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg new file mode 100644 index 0000000000..b54b9542bd --- /dev/null +++ b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg @@ -0,0 +1,386 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Timing configuration: + * + * MDCFG0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRFC 2Gb 400MHz 0x3f (64) 24 0x3f000000 + * 4Gb 400MHz 0x77 (120) 24 0x77000000 + * 8Gb 400MHz 0x8b (140) 24 0x8b000000 + * 2Gb 533MHz 0x55 (86) 24 0x55000000 + * 4Gb 533MHz 0x9f (160) 24 0x9f000000 + * 8Gb 533MHz 0xba (187) 24 0xba000000 + * 4Gb LPDDR2 0x33 (52) 24 0x33000000 + * tXS 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * 4Gb LPDDR2 0x37 (56) 16 0x00370000 + * tXP * 400MHz 0x2 (3) 13 0x00004000 + * * 533MHz 0x3 (4) 13 0x00006000 + * * LPDDR2 0x2 (3) 13 0x00004000 + * tXPDLL * 400MHz 0x9 (10) 9 0x00001200 + * * 533MHz 0xc (13) 9 0x00001800 + * * LPDDR2 0x1 (-) 9 0x00000200 + * tFAW * 400MHz 0x13 (20) 4 0x00000130 + * * 533MHz 0x1a (27) 4 0x000001a0 + * * LPDDR2 0x13 (20) 4 0x00000130 + * tCL * 400MHz 0x3 (6) 0 0x00000003 + * * 533MHz-CL7 0x4 (7) 0 0x00000004 + * * 533MHz-CL8 0x5 (8) 0 0x00000005 + * * LPDDR2 0x3 (6) 0 0x00000003 + * ---------------------------------------------------------------- + */ +#define MDCFG0_2G_400MHZ 0x3f435333 +#define MDCFG0_4G_400MHZ 0x777b5333 +#define MDCFG0_8G_400MHZ 0x8b8f5333 +#define MDCFG0_2G_533MHZ_CL8 0x555b79a5 +#define MDCFG0_2G_533MHZ_CL7 0x555b79a4 +#define MDCFG0_4G_533MHZ_CL8 0x9fa579a5 +#define MDCFG0_4G_533MHZ_CL7 0x9fa579a4 +#define MDCFG0_8G_533MHZ_CL8 0xbac079a5 +#define MDCFG0_8G_533MHZ_CL7 0xbac079a4 +#define MDCFG0_4G_LPDDR2_CL6 0x33374133 +#define MDCFG0_8G_LPDDR2_CL6 0x53574133 + + +/* + * MDCFG1: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRCD * 400MHz 0x5 (6) 28 0xa0000000 + * * 533MHz 0x7 (8) 28 0xe0000000 + * * LPDDR2 0x5 (-) 28 0xa0000000 + * tRP * 400MHz 0x5 (6) 26 0x14000000 + * * 533MHz 0x7 (8) 26 0x1c000000 + * * LPDDR2 0x5 (-) 26 0x14000000 + * tRC * 400MHz 0x14 (21) 21 0x02800000 + * * 533MHz 0x1b (28) 21 0x03600000 + * * LPDDR2 0x15 (-) 21 0x02a00000 + * tRAS * 400MHz 0x0e (15) 16 0x000e0000 + * * 533MHz 0x13 (20) 16 0x00130000 + * * LPDDR2 0x10 (17) 16 0x00100000 + * tRPA * 0x1 (tRP+1) 15 0x00008000 + * RM rev 4: unused, read-only! 15 0x00000000 + * tWR * 400MHz 0x5 (6) 9 0x00000a00 + * * 533MHz 0x7 (8) 9 0x00000e00 + * * LPDDR2 0x5 (6) 9 0x00000a00 + * tMRD * 0x3 (4) 5 0x00000060 + * max(tMRR,tMRW) LPDDR2 0x4 (5) 5 0x00000080 + * tCWL * 400MHz 0x3 (5) 0 0x00000003 + * * 533MHz 0x4 (6) 0 0x00000004 + * tWL * LPDDR2 0x2 (3) 0 0x00000002 + * ---------------------------------------------------------------- + */ +#define MDCFG1_400MHZ 0xb68e8a63 +#define MDCFG1_533MHZ 0xff738e64 +#define MDCFG1_LPDDR2 0x00100a82 + +/* + * MDCFG2: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tDLLK * 0x1ff (512) 16 0x01ff0000 + * LPDDR2 0x0c7 (-) 16 0x00c70000 + * tRTP * 0x3 (4) 6 0x000000c0 + * LPDDR2 0x2 (3) 6 0x00000080 + * tWTR * 0x3 (4) 3 0x00000018 + * LPDDR2 0x2 (3) 3 0x00000010 + * tRRD * 400MHz 0x3 (4) 0 0x00000003 + * * 533MHz 0x5 (6) 0 0x00000005 + * LPDDR2 0x3 (4) 0 0x00000003 + * ---------------------------------------------------------------- + */ +#define MDCFG2_400MHZ 0x01ff00db +#define MDCFG2_533MHZ 0x01ff00dd +#define MDCFG2_LPDDR2 0x00000093 + +/* + * MDOR: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tXPR 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * * LPDDR2 0x9f (-) 16 0x009f0000 + * SDE_to_RST * 0x10 (14) 8 0x00001000 + * * LPDDR2 0xe (-) 8 0x00000e00 + * RST_to_CKE * 0x23 (33) 0 0x00000023 + * * LPDDR2 0x10 (14) 0 0x00000010 + * ---------------------------------------------------------------- + */ +#define MDOR_2G_400MHZ 0x00431023 +#define MDOR_4G_400MHZ 0x007b1023 +#define MDOR_8G_400MHZ 0x008f1023 +#define MDOR_2G_533MHZ 0x005b1023 +#define MDOR_4G_533MHZ 0x00a51023 +#define MDOR_8G_533MHZ 0x00c01023 +#define MDOR_LPDDR2 0x009f0e10 + +/* + * MDOTC ODT delays: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tAOFPD * 400MHz 0x3 (4) 27 0x18000000 + * * 533MHz 0x4 (5) 27 0x20000000 + * tAONPD * 400MHz 0x3 (4) 24 0x03000000 + * * 533MHz 0x4 (5) 24 0x04000000 + * tANPD * 400MHz 0x3 (4) 20 0x00300000 + * * 533MHz 0x4 (5) 20 0x00400000 + * tAXPD * 400MHz 0x3 (4) 16 0x00030000 + * * 533MHz 0x4 (5) 16 0x00040000 + * tODTLon * 400MHz 0x3 (3) 12 0x00003000 + * * 533MHz 0x4 (4) 12 0x00004000 + * tODTidle_off * 400MHz 0x3 (3) 4 0x00000030 + * * 533MHz 0x4 (4) 4 0x00000040 + * ---------------------------------------------------------------- + */ +#define MDOTC_400MHZ 0x1b333030 +#define MDOTC_533MHZ 0x24444040 +/* LPDDR2: not relevant, leave in reset state!! */ + +/* + * MDPDC: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * PRCT_1 * 0x0 28 0x00000000 + * PRCT_0 * 0x0 24 0x00000000 + * tCKE * 0x2 (3) 16 0x00020000 + * PWDT_1 * 0x5 (256) 12 0x00005000 + * PWDT_0 * 0x5 (256) 8 0x00000500 + * SLOW_PD * 0x0 (0) 7 0x00000000 + * BOTH_CS_PD * 0x1 (1) 6 0x00000040 + * tCKSRX * 400MHz 0x5 (5) 3 0x00000028 + * * 533MHz 0x6 (6) 3 0x00000030 + * tCKSRE * 400MHz 0x5 (5) 0 0x00000005 + * * 533MHz 0x6 (6) 0 0x00000006 + * ---------------------------------------------------------------- + */ +#define MDPDC_400MHZ 0x0002556d +#define MDPDC_533MHZ 0x00025576 +#define MDPDC_LPDDR2 0x00025576 /* FIXME? */ + +/* + * MDCTL: + * 2Gb: CS0 enable, 14bit ROW, 10bit COL, BL=8, 64bit data + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * SDE_0 * 0x1 (1) 31 0x80000000 + * SDE_1 * 0x0 (0) 30 0x00000000 + * SDE_1 LPDDR2 0x1 (1) 30 0x40000000 + * ROW 2Gb * 0x3 (14) 24 0x03000000 + * 4Gb * 0x4 (15) 24 0x04000000 + * 8Gb * 0x5 (16) 24 0x05000000 + * * LPDDR2 0x3 (14) 24 0x03000000 + * COL * 0x1 (10) 20 0x00100000 + * BL * 0x1 (8) 19 0x00080000 + * LPDDR2 0x0 (4) 19 0x00000000 + * DSIZ 64bit 0x2 (64) 16 0x00020000 + * DSIZ 32bit 0x1 (32) 16 0x00010000 + * DSIZ 16bit 0x0 (16) 16 0x00000000 + * ---------------------------------------------------------------- + */ +#define MDCTL_2G_16BIT 0x83180000 +#define MDCTL_2G_32BIT 0x83190000 +#define MDCTL_2G 0x831a0000 +#define MDCTL_4G_16BIT 0x84180000 +#define MDCTL_4G_32BIT 0x84190000 +#define MDCTL_4G 0x841a0000 +#define MDCTL_8G 0x851a0000 +#define MDCTL_LPDDR2 0x83110000 + + +/* + * MDASP Address space partitioning: + * + * At 0.25GiB, internal address space ends. Above that DDR3 should be + * located. The CS1/CS0 split-line determines where: + * + * For 1x2Gb chips (0.25GiB total on CS0): 0.5GiB + * For 2x4Gb chips (1GiB total on CS0): 1.25GiB + * For 4x2Gb chips (1GiB total on CS0): 1.25GiB + * For 4x4Gb chips (2GiB total on CS0): 2.25GiB + * For 4x8Gb chips (4GiB total on CS0): 4.00GiB (maximum possible, + * shadowed partially by internal address space). + * + * Register value Split + * --------------------------- + * 0x0000000f 0.5GiB + * 0x00000017 0.75GiB + * 0x00000027 1.25GiB + * 0x00000047 2.25GiB + * 0x0000007f 4.00GiB + */ +#define MDASP_512MIB 0x0000000f +#define MDASP_768MIB 0x00000017 +#define MDASP_1GIB25 0x00000027 +#define MDASP_2GIB25 0x00000047 +#define MDASP_4GIB00 0x0000007f + +/* + * Initialize DDR3 chips + * MDSCR: Value = 0xvvvv803n, with 0xvvvv = value, n = Reg. number (BA) + */ +/* + * DDR3 chip MR2, n = 2: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Rtt(wr) * 0x0 (disabled) 10, 9 0x0000 + * SR-Temp. * 0x1 (Extended) 7 0x0080 + * Auto-SR * 0x0 (Manual) 6 0x0000 + * CWL * 400MHz 0x0 (5tCK) 5, 4, 3 0x0000 + * * 533MHz 0x1 (6tCK) 5, 4, 3 0x0008 + * ---------------------------------------------------------------- + */ +#define DDR3_MR2_400MHZ_RTT_OFF 0x00808032 +#define DDR3_MR2_533MHZ_RTT_OFF 0x00888032 +#define DDR3_MR2_400MHZ_RTT_120 0x04808032 +#define DDR3_MR2_533MHZ_RTT_120 0x04888032 + +/* + * DDR3 chip MR1, n = 1: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Qoff * 0x0 (enabled) 12 0x0000 + * TDQS * 0x0 (disabled) 11 0x0000 + * Rtt * 0x0 (disabled) 9, 6, 2 0x0000 + * Write-levelling * 0x0 (disable) 7 0x0000 + * ODS * 0x0 (RZQ/6=40) 5, 1 0x0000 + * DLL * 0x0 (enable) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR1_RTT_OFF_ODS_40 0x00008031 +#define DDR3_MR1_RTT_120_ODS_40 0x00408031 +#define DDR3_MR1_RTT_60_ODS_40 0x00048031 +#define DDR3_MR1_RTT_OFF_ODS_34 0x00028031 +#define DDR3_MR1_RTT_120_ODS_34 0x00428031 +#define DDR3_MR1_RTT_60_ODS_34 0x00068031 + +/* + * DDR3 chip MR0, n = 0: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Precharge PD * 0x1 (fast exit) 12 0x1000 + * WR 400MHz 0x2 (6) 11,10,9 0x0400 + * 533MHz 0x4 (8) 11,10,9 0x0800 + * DLL reset * 0x1 (Yes) 8 0x0100 + * CL 400MHz 0x4 (6) 6,5,4,2 0x0020 + * 533MHz 0x6 (7) 6,5,4,2 0x0030 + * 533MHz 0x8 (8) 6,5,4,2 0x0040 + * RD burst type * 0x0 (seq.) 3 0x0000 + * BL * 0x0 (BL8) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR0_400MHZ 0x15208030 +#define DDR3_MR0_533MHZ_CL7 0x19308030 +#define DDR3_MR0_533MHZ_CL8 0x19408030 + + +/* + * MDREF: + * REF_SEL (bit 14,15): 0 (64kHz, needed for high-temp.) + * REFR (bit 11, 12, 13): 0x3 (4 refreshes) -> 0x00001800 + * 0x7 (8 refreshes) -> 0x00003800 + */ +#define MDREF_64KHZ 0x00001800 +#define MDREF_32KHZ 0x00007800 + +/* MPODTCTRL */ +#define MPODTCTRL_ODT_OFF 0x00000007 +#define MPODTCTRL_ODT_120 0x00011117 +#define MPODTCTRL_ODT_60 0x00022227 +#define MPODTCTRL_ODT_40 0x00033337 + +/* + * MPDGCTRL0: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * RST_RD_FIFO * 0 31 0x00000000 + * DG_CMP_CYC * 1 30 0x40000000 + * DG_DIS * 0 29 0x00000000 + * HW_DG_EN * 0 28 0x00000000 + * DG_HC_DEL1 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_EXT_UP * 0 23 0x00000000 + * DG_DL_ABS_OFFS1 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH0_400MHZ 0x42350231 +#define MPDGCTRL0_CH0_533MHZ 0x434b0350 +/* + * + * Channel 1: + * + * DG_HC_DEL1 (5) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS1 (5) 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 (4) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 (4) 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH1_400MHZ 0x42350231 +#define MPDGCTRL0_CH1_533MHZ 0x434b0350 + +/* + * MPDGCTRL1: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * DG_HC_DEL3 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x4c 16 0x004c0000 + * DG_HC_DEL2 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 400MHz 0x18 0 0x00000018 + * 533MHz 0x59 0 0x00000059 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH0_400MHZ 0x021a0218 +#define MPDGCTRL1_CH0_533MHZ 0x034c0359 +/* + * + * Channel 1: + * + * DG_HC_DEL3 (7) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 (7) 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x65 16 0x00650000 + * DG_HC_DEL2 (6) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 (6) 400MHz 0x18 0 0x00000018 + * 533MHz 0x48 0 0x00000048 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH1_400MHZ 0x021a0218 +#define MPDGCTRL1_CH1_533MHZ 0x03650348 diff --git a/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg new file mode 100644 index 0000000000..380ce8863c --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e04a8 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e04bc PAD_SDQS /* SDQS0_P */ +wm 32 0x020e04c0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e04c4 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e04c8 PAD_SDQS /* SDQS3_P */ +wm 32 0x020e04cc PAD_SDQS /* SDQS4_P */ +wm 32 0x020e04d0 PAD_SDQS /* SDQS5_P */ +wm 32 0x020e04d4 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e04d8 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e0470 PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e0474 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0478 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e047c PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0480 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0484 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e0488 PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e048c PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e0464 PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0490 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e04ac PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e04b0 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e0494 PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e04a4 0x00003000 /* SDCKE0 */ +wm 32 0x020e04a8 0x00003000 /* SDCKE1 */ +wm 32 0x020e04a0 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e04b4 0x00003030 /* ODT0 */ +wm 32 0x020e04b8 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0764 PAD_BxDS /* B0DS */ +wm 32 0x020e0770 PAD_BxDS /* B1DS */ +wm 32 0x020e0778 PAD_BxDS /* B2DS */ +wm 32 0x020e077c PAD_BxDS /* B3DS */ +wm 32 0x020e0780 PAD_BxDS /* B4DS */ +wm 32 0x020e0784 PAD_BxDS /* B5DS */ +wm 32 0x020e078c PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0754 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0760 0x00020000 /* DDRMODE data */ + +wm 32 0x020e076c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0774 0x000c0000 /* DDR_TYPE DDR3 */ + diff --git a/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg new file mode 100644 index 0000000000..c58a481e13 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e0420 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e05a8 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e05b0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e0524 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e051c PAD_SDQS /* SDQS3_P */ +wm 32 0x020e0518 PAD_SDQS /* SDQS4_P */ +wm 32 0x020e050c PAD_SDQS /* SDQS5_P */ +wm 32 0x020e05b8 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e05c0 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e05ac PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e05b4 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0528 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e0520 PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0514 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0510 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e05bc PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e05c4 PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e056c PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0578 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0588 PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0594 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e057c PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e0590 0x00003000 /* SDCKE0 */ +wm 32 0x020e0598 0x00003000 /* SDCKE1 */ +wm 32 0x020e058c 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e059c 0x00003030 /* ODT0 */ +wm 32 0x020e05a0 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0784 PAD_BxDS /* B0DS */ +wm 32 0x020e0788 PAD_BxDS /* B1DS */ +wm 32 0x020e0794 PAD_BxDS /* B2DS */ +wm 32 0x020e079c PAD_BxDS /* B3DS */ +wm 32 0x020e07a0 PAD_BxDS /* B4DS */ +wm 32 0x020e07a4 PAD_BxDS /* B5DS */ +wm 32 0x020e07a8 PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0758 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0774 0x00020000 /* DDRMODE data */ + +wm 32 0x020e078c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0798 0x000c0000 /* DDR_TYPE DDR3 */ diff --git a/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg new file mode 100644 index 0000000000..9cdc9ac9a3 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ + +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e0280 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e0284 PAD_SDQS /* SDQS1_P */ + +#define PAD_DQM_CTRL PAD_DSE_48 +#define PAD_SDCLK PAD_DSE_48 + +wm 32 0x020e0244 PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e0248 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e024c PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0250 PAD_DQM_CTRL /* CAS */ +wm 32 0x020e027c PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0288 PAD_DQM_CTRL /* RESET */ + +wm 32 0x020e0270 0x00000000 /* SDBA2: disable PU */ + +wm 32 0x020e0260 PAD_DSE_48 /* ODT0 */ +wm 32 0x020e0264 PAD_DSE_48 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0498 PAD_BxDS /* B0DS */ +wm 32 0x020e04a4 PAD_BxDS /* B1DS */ + +wm 32 0x020e0490 PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0494 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e04ac 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e04b0 0x00020000 /* DDRMODE data */ + +wm 32 0x020e04a0 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e04b4 0x000c0000 /* DDR_TYPE DDR3 */ diff --git a/arch/arm/boards/protonic-imx8m/Makefile b/arch/arm/boards/protonic-imx8m/Makefile new file mode 100644 index 0000000000..18da0f5a44 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel-prt8mm.o lpddr4-timing-prt8mm.o +bbenv-y += defaultenv-prt8m diff --git a/arch/arm/boards/protonic-imx8m/board.c b/arch/arm/boards/protonic-imx8m/board.c new file mode 100644 index 0000000000..d4bacbc6f0 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/board.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2020 David Jander, Protonic Holland + +#include <bootsource.h> +#include <common.h> +#include <envfs.h> +#include <environment.h> +#include <i2c/i2c.h> +#include <init.h> +#include <mach/imx/bbu.h> + +static int prt_prt8mm_init_power(void) +{ + struct i2c_adapter *adapter = NULL; + struct i2c_client client; + int ret; + char buf[2]; + + client.addr = 0x60; + adapter = i2c_get_adapter(1); + if (!adapter) { + printf("i2c bus not found\n"); + return -ENODEV; + } + client.adapter = adapter; + + buf[0] = 0xe3; + ret = i2c_write_reg(&client, 0x00, buf, 1); // VSEL0 = 0.95V, force PWM + if (ret < 0) { + printf("i2c write error\n"); + return -ENODEV; + } + buf[0] = 0xe0; + ret = i2c_write_reg(&client, 0x01, buf, 1); // VSEL1 = 0.92V, force PWM + if (ret < 0) { + printf("i2c write error\n"); + return -ENODEV; + } + return 0; +} + +static int prt_prt8mm_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + prt_prt8mm_init_power(); + + barebox_set_hostname("prt8mm"); + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", + sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", + emmc_bbu_flag); + + defaultenv_append_directory(defaultenv_prt8m); + + return 0; +} + +static const struct of_device_id prt_imx8mm_of_match[] = { + { .compatible = "prt,prt8mm", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, prt_imx8mm_of_match); + +static struct driver prt_prt8mm_board_driver = { + .name = "board-protonic-imx8mm", + .probe = prt_prt8mm_probe, + .of_compatible = DRV_OF_COMPAT(prt_imx8mm_of_match), +}; +device_platform_driver(prt_prt8mm_board_driver); diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default new file mode 100644 index 0000000000..ca8bef306d --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/boot/prt8mm-default @@ -0,0 +1,7 @@ +#!/bin/sh + +if [ "$bootsource_instance" = "2" ]; then + boot mmc2 +else + boot mmc3 +fi diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover new file mode 100644 index 0000000000..18f2446387 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +# PRT8M doesn't have a ETH port, but may have USB network attached +usb diff --git a/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default new file mode 100644 index 0000000000..ba8938923a --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/defaultenv-prt8m/nv/boot.default @@ -0,0 +1 @@ +prt8mm-default diff --git a/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg b/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg new file mode 100644 index 0000000000..8aff991618 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/flash-header-prt8mm.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mm + +loadaddr 0x007e1000 +max_load_size 0x3f000 +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c new file mode 100644 index 0000000000..711316ae4b --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/barebox-arm.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/imx8mm-regs.h> +#include <mach/imx/iomux-mx8mm.h> +#include <mach/imx/xload.h> +#include <soc/fsl/fsl_udc.h> +#include <soc/imx8m/ddr.h> + +extern char __dtb_z_imx8mm_prt8mm_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART4_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mm_setup_pad(IMX8MM_PAD_UART4_TXD_UART4_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +extern struct dram_timing_info prt8mm_dram_timing; + +static void start_atf(void) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mm_early_clock_init(); + + imx8mm_ddr_init(&prt8mm_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mm_load_and_start_image_via_tfa(); +} + +/* + * Power-on execution flow of start_prt_prt8mm() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void prt_prt8mm_start(void) +{ + setup_uart(); + + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mm_barebox_entry(__dtb_z_imx8mm_prt8mm_start); +} + +ENTRY_FUNCTION(start_prt_prt8mm, r0, r1, r2) +{ + imx8mm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + prt_prt8mm_start(); +} diff --git a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c new file mode 100644 index 0000000000..6fea2f0625 --- /dev/null +++ b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c @@ -0,0 +1,1269 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> + +#define DDR_ONE_RANK +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa1080020 }, + { DDRC_RFSHTMG(0), 0x005b0087 }, + { DDRC_INIT0(0), 0xc00305ba }, + { DDRC_INIT1(0), 0x00940000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_INIT6(0), 0x0066004d }, + { DDRC_INIT7(0), 0x0016004d }, + + { DDRC_DRAMTMG0(0), 0x191e1920 }, + { DDRC_DRAMTMG1(0), 0x00060630 }, + { DDRC_DRAMTMG3(0), 0x00B0B000 }, + { DDRC_DRAMTMG4(0), 0x0e04080e }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0c100002 }, + { DDRC_DRAMTMG14(0), 0x0000008d }, + { DDRC_DRAMTMG17(0), 0x0090004b }, + + //{ DDRC_DERATEEN(0), 0x00000203 }, + //{ DDRC_DERATEINT(0), 0x0003a980 }, + + { DDRC_ZQCTL0(0), 0x02ee0017 }, + { DDRC_ZQCTL1(0), 0x02605b8e }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070e1617 }, + { DDRC_DBICTL(0), 0x00000001 }, + + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x0000001f }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x0F070707 }, + { DDRC_ADDRMAP7(0), 0x00000f0f }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x04000030 }, + { DDRC_PERFLPR1(0), 0x900093e7 }, + { DDRC_PERFWR1(0), 0x02005574 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCFGQOS0_0(0), 0x02100e07 }, + { DDRC_PCFGQOS1_0(0), 0x00620096 }, + { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, + { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + + /* frequency P1&P2 */ + /* Frequency 1: 400MHz */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0c080609 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x0003040d }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x00000301 }, + //{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 }, + //{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000026 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00280014 }, + //{ DDRC_FREQ1_DERATEEN(0), 0x00000001 }, + { DDRC_FREQ1_DERATEINT(0), 0x00007a00 }, + //{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 }, + //{ DDRC_FREQ1_ZQCTL0(0), 0x00c80006 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858202 }, + //{ DDRC_FREQ1_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000502 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00180024 }, + { DDRC_FREQ1_INIT3(0), 0x00940009 }, + { DDRC_FREQ1_INIT4(0), 0x00310000 }, + { DDRC_FREQ1_INIT6(0), 0x0066004d }, + { DDRC_FREQ1_INIT7(0), 0x0016004d }, + // { DDRC_FREQ1_RANKCTL(0), 0x00000c99 }, + + /* Frequency 2: 100MHz */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0a020103 }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030405 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0203060b }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x02040202 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x02030202 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x00000301 }, + //{ DDRC_FREQ2_DRAMTMG12(0), 0x00020300 }, + //{ DDRC_FREQ2_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ2_DRAMTMG14(0), 0x0000000a }, + { DDRC_FREQ2_DRAMTMG17(0), 0x000a0005 }, + //{ DDRC_FREQ2_DERATEEN(0), 0x00000001 }, + { DDRC_FREQ2_DERATEINT(0), 0x00003e80 }, + //{ DDRC_FREQ2_RFSHCTL0(0), 0x0020d040 }, + //{ DDRC_FREQ2_ZQCTL0(0), 0x00320004 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + //{ DDRC_FREQ2_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000100 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00060009 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + //{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, + { DDRC_FREQ2_INIT6(0), 0x0066004d }, + { DDRC_FREQ2_INIT7(0), 0x0016004d }, + // { DDRC_FREQ2_RANKCTL(0), 0x00000c99 }, + + /* boot start point */ + { DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2 +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + + { 0x200b2, 0x1d4 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + + { 0x20025, 0x0 }, + { 0x2002d, LPDDR4_PHY_DMIPinPresent }, + { 0x12002d, LPDDR4_PHY_DMIPinPresent }, + { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, // 3000 + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, // LPDDR4_HDT_CTL_3200_1D + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0x8400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54011, 0x0 }, + { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d08 }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d08 }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, LPDDR4_CS }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84d }, + { 0x54036, 0x4d }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54038, 0xd400 }, + { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84d }, + { 0x5403c, 0x4d }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xf }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x630 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x630 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x630 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x630 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x630 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x630 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xa }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info prt8mm_dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), +}; diff --git a/arch/arm/boards/protonic-mecsbc/Makefile b/arch/arm/boards/protonic-mecsbc/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/protonic-mecsbc/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/protonic-mecsbc/board.c b/arch/arm/boards/protonic-mecsbc/board.c new file mode 100644 index 0000000000..56f7ca393a --- /dev/null +++ b/arch/arm/boards/protonic-mecsbc/board.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "MECSBC: " fmt + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/rockchip/bbu.h> +#include <environment.h> +#include <param.h> +#include <of_device.h> +#include <aiodev.h> +#include <globalvar.h> + +struct mecsbc_model { + const char *name; + const char *shortname; +}; + +struct mecsbc_priv { + int hw_id; + int hw_rev; +}; + +static struct mecsbc_priv mecsbc_data; + +static int saradc_get_value(const char *chan) +{ + int ret, voltage; + + ret = aiochannel_name_get_value(chan, &voltage); + if (ret) { + pr_warn_once("Cannot read ADC %s: %pe\n", chan, ERR_PTR(ret)); + return 0; + } + + return voltage; +} + +static int mecsbc_get_vin_mv(void) +{ + return saradc_get_value("aiodev0.in_value2_mV") * 22; +} + +static bool mecsbc_get_usb_boot(void) +{ + return saradc_get_value("aiodev0.in_value0_mV") < 74; +} + +static int mecsbc_adc_id_values[] = { + 1800, 1662, 1521, 1354, 1214, 1059, 900, 742, 335, 589, 278, 137, 0 +}; + +static int mecsbc_get_adc_id(const char *chan) +{ + int val; + unsigned int t; + + val = saradc_get_value(chan) + 74; + + for (t = 0; t < ARRAY_SIZE(mecsbc_adc_id_values); t++) { + if (val > mecsbc_adc_id_values[t]) + return t; + } + + return t; +} + +static void mecsbc_process_adc(struct device *dev) +{ + mecsbc_data.hw_id = mecsbc_get_adc_id("aiodev0.in_value1_mV"); + mecsbc_data.hw_rev = mecsbc_get_adc_id("aiodev0.in_value3_mV"); + + dev_add_param_uint32_ro(dev, "boardrev", &mecsbc_data.hw_rev, "%u"); + dev_add_param_uint32_ro(dev, "boardid", &mecsbc_data.hw_id, "%u"); + + /* Check if we need to enable the USB gadget instead of booting */ + if (mecsbc_get_usb_boot()) { + globalvar_add_simple("boot.default", "net"); + globalvar_add_simple("usbgadget.acm", "1"); + globalvar_add_simple("usbgadget.autostart", "1"); + globalvar_add_simple("system.partitions", "/dev/mmc0(mmc0)"); + pr_info("MECSBC: Enter USB recovery\n"); + } else { + globalvar_add_simple("boot.default", "bootchooser"); + } + + pr_info("Board id: %d, revision %d\n", mecsbc_data.hw_id, mecsbc_data.hw_rev); + pr_info("VIN = %d V\n", mecsbc_get_vin_mv() / 1000); +} + +static int mecsbc_sd_of_fixup(struct device_node *root, void *context) +{ + struct device *dev = context; + struct device_node *np; + + dev_info(dev, "Fixing up /regulator-sd\n"); + + np = of_find_node_by_path_from(root, "/regulator-sd"); + if (!np) { + dev_err(dev, "Cannot find /regulator-sd node\n"); + return 0; + } + + of_property_write_u32(np, "regulator-min-microvolt", 3300000); + + return 0; +} + +static int mecsbc_of_fixup_hwrev(struct device *dev) +{ + const char *compat; + char *buf; + + compat = of_device_get_match_compatible(dev); + + buf = xasprintf("%s-m%u-r%u", compat, mecsbc_data.hw_id, + mecsbc_data.hw_rev); + barebox_set_of_machine_compatible(buf); + + free(buf); + + if (mecsbc_data.hw_id == 0 && mecsbc_data.hw_rev == 0) + of_register_fixup(mecsbc_sd_of_fixup, dev); + + return 0; +} + +static int mecsbc_probe(struct device *dev) +{ + int ret = 0; + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + const struct mecsbc_model *model; + struct device_node *np; + + np = of_find_node_by_name_address(NULL, "saradc@fe720000"); + of_device_ensure_probed(np); + + model = device_get_match_data(dev); + + barebox_set_model(model->name); + barebox_set_hostname(model->shortname); + + if (bootsource == BOOTSOURCE_MMC && instance == 1) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc0"); + rk3568_bbu_mmc_register("sd", 0, "/dev/mmc1"); + + mecsbc_process_adc(dev); + mecsbc_of_fixup_hwrev(dev); + + return ret; +} + +static const struct mecsbc_model mecsbc = { + .name = "Protonic MECSBC board", + .shortname = "mecsbc", +}; + +static const struct of_device_id mecsbc_of_match[] = { + { + .compatible = "prt,mecsbc", + .data = &mecsbc, + }, + { /* sentinel */ }, +}; + +static struct driver mecsbc_board_driver = { + .name = "board-mecsbc", + .probe = mecsbc_probe, + .of_compatible = mecsbc_of_match, +}; +coredevice_platform_driver(mecsbc_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(mecsbc_of_match); diff --git a/arch/arm/boards/protonic-mecsbc/lowlevel.c b/arch/arm/boards/protonic-mecsbc/lowlevel.c new file mode 100644 index 0000000000..830d708b6e --- /dev/null +++ b/arch/arm/boards/protonic-mecsbc/lowlevel.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3568_mecsbc_start[]; + +ENTRY_FUNCTION(start_mecsbc, r0, r1, r2) +{ + /* + * MECSBC IO domain voltages are all +3.3V, except VCCIO4 and VCCIO6 + * Both GMAC interfaces need this to work properly. + * FIXME: This is done by the io-domain driver as well, but there + * currently is no mechanism to make sure the driver gets probed + * before its consumers. Remove this setup once this issue is + * resolved. + */ + writel(RK_SETBITS(0x50), 0xfdc20140); + + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3568_mecsbc_start); +} diff --git a/arch/arm/boards/protonic-stm32mp1/Makefile b/arch/arm/boards/protonic-stm32mp1/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/protonic-stm32mp1/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/protonic-stm32mp1/board.c b/arch/arm/boards/protonic-stm32mp1/board.c new file mode 100644 index 0000000000..68297debab --- /dev/null +++ b/arch/arm/boards/protonic-stm32mp1/board.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland +// SPDX-FileCopyrightText: 2021 Oleksij Rempel, Pengutronix + +#include <bootsource.h> +#include <common.h> +#include <init.h> +#include <mach/stm32mp/bbu.h> +#include <of_device.h> +#include <deep-probe.h> + +/* board specific flags */ +#define PRT_STM32_BOOTSRC_SD BIT(2) +#define PRT_STM32_BOOTSRC_EMMC BIT(1) +#define PRT_STM32_BOOTSRC_SPI_NOR BIT(0) + +struct prt_stm32_machine_data { + u32 flags; +}; + +struct prt_stm32_boot_dev { + char *name; + char *env; + char *dev; + int flags; + int boot_idx; + enum bootsource boot_src; +}; + +static const struct prt_stm32_boot_dev prt_stm32_boot_devs[] = { + { + .name = "emmc", + .env = "/chosen/environment-emmc", + .dev = "/dev/mmc1.ssbl", + .flags = PRT_STM32_BOOTSRC_EMMC, + .boot_src = BOOTSOURCE_MMC, + .boot_idx = 1, + }, { + .name = "qspi", + .env = "/chosen/environment-qspi", + .dev = "/dev/flash.ssbl", + .flags = PRT_STM32_BOOTSRC_SPI_NOR, + .boot_src = BOOTSOURCE_SPI_NOR, + .boot_idx = -1, + }, { + /* SD is optional boot source and should be last device in the + * list. */ + .name = "sd", + .env = "/chosen/environment-sd", + .dev = "/dev/mmc0.ssbl", + .flags = PRT_STM32_BOOTSRC_SD, + .boot_src = BOOTSOURCE_MMC, + .boot_idx = 0, + }, +}; + +static int prt_stm32_probe(struct device *dev) +{ + const struct prt_stm32_machine_data *dcfg; + char *env_path_back = NULL, *env_path = NULL; + int ret, i; + + dcfg = of_device_get_match_data(dev); + if (!dcfg) { + ret = -EINVAL; + goto exit_get_dcfg; + } + + for (i = 0; i < ARRAY_SIZE(prt_stm32_boot_devs); i++) { + const struct prt_stm32_boot_dev *bd = &prt_stm32_boot_devs[i]; + int bbu_flags = 0; + + /* skip not supported boot sources */ + if (!(bd->flags & dcfg->flags)) + continue; + + /* first device is build-in device */ + if (!env_path_back) + env_path_back = bd->env; + + if (bd->boot_src == bootsource_get() && (bd->boot_idx == -1 || + bd->boot_idx == bootsource_get_instance())) { + bbu_flags = BBU_HANDLER_FLAG_DEFAULT; + env_path = bd->env; + } + + ret = stm32mp_bbu_mmc_register_handler(bd->name, bd->dev, + bbu_flags); + if (ret < 0) + dev_warn(dev, "Failed to enable %s bbu (%pe)\n", + bd->name, ERR_PTR(ret)); + } + + if (!env_path) + env_path = env_path_back; + ret = of_device_enable_path(env_path); + if (ret < 0) + dev_warn(dev, "Failed to enable environment partition '%s' (%pe)\n", + env_path, ERR_PTR(ret)); + + return 0; + +exit_get_dcfg: + dev_err(dev, "Failed to get dcfg: %pe\n", ERR_PTR(ret)); + return ret; +} + +static const struct prt_stm32_machine_data prt_stm32_prtt1a = { + .flags = PRT_STM32_BOOTSRC_SD | PRT_STM32_BOOTSRC_SPI_NOR, +}; + +static const struct prt_stm32_machine_data prt_stm32_prtt1c = { + .flags = PRT_STM32_BOOTSRC_SD | PRT_STM32_BOOTSRC_EMMC, +}; + +static const struct of_device_id prt_stm32_of_match[] = { + { .compatible = "prt,prtt1a", .data = &prt_stm32_prtt1a }, + { .compatible = "prt,prtt1c", .data = &prt_stm32_prtt1c }, + { .compatible = "prt,prtt1s", .data = &prt_stm32_prtt1a }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(prt_stm32_of_match); + +static struct driver prt_stm32_board_driver = { + .name = "board-protonic-stm32", + .probe = prt_stm32_probe, + .of_compatible = prt_stm32_of_match, +}; +postcore_platform_driver(prt_stm32_board_driver); diff --git a/arch/arm/boards/protonic-stm32mp1/lowlevel.c b/arch/arm/boards/protonic-stm32mp1/lowlevel.c new file mode 100644 index 0000000000..2fd7f8ba8b --- /dev/null +++ b/arch/arm/boards/protonic-stm32mp1/lowlevel.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2021 David Jander, Protonic Holland + +#include <common.h> +#include <debug_ll.h> +#include <mach/stm32mp/entry.h> + +extern char __dtb_z_stm32mp151_prtt1a_start[]; +extern char __dtb_z_stm32mp151_prtt1c_start[]; +extern char __dtb_z_stm32mp151_prtt1s_start[]; + +static void setup_uart(void) +{ + /* first stage has set up the UART, so nothing to do here */ + putc_ll('>'); +} + +ENTRY_FUNCTION(start_prtt1a, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_z_stm32mp151_prtt1a_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_prtt1c, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_z_stm32mp151_prtt1c_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_prtt1s, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_z_stm32mp151_prtt1s_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} diff --git a/arch/arm/boards/qemu-virt/Makefile b/arch/arm/boards/qemu-virt/Makefile new file mode 100644 index 0000000000..ad283446ea --- /dev/null +++ b/arch/arm/boards/qemu-virt/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o diff --git a/arch/arm/boards/qemu-virt64/Makefile b/arch/arm/boards/qemu-virt64/Makefile deleted file mode 100644 index e354607548..0000000000 --- a/arch/arm/boards/qemu-virt64/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += init.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-qemu-virt64 diff --git a/arch/arm/boards/qemu-virt64/defaultenv-qemu-virt64/config b/arch/arm/boards/qemu-virt64/defaultenv-qemu-virt64/config deleted file mode 100644 index 781dbfefa6..0000000000 --- a/arch/arm/boards/qemu-virt64/defaultenv-qemu-virt64/config +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -autoboot_timeout=3 - -bootargs="console=ttyAMA0,115200" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;31m[barebox@\h]:\w\e[0m\n# " diff --git a/arch/arm/boards/qemu-virt64/init.c b/arch/arm/boards/qemu-virt64/init.c deleted file mode 100644 index 19cfcae1f0..0000000000 --- a/arch/arm/boards/qemu-virt64/init.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2016 Raphaël Poggi <poggi.raph@gmail.com> - * - * GPLv2 only - */ - -#include <common.h> -#include <init.h> -#include <asm/armlinux.h> -#include <asm/system_info.h> -#include <asm/pgtable64.h> -#include <mach/devices.h> -#include <environment.h> -#include <linux/sizes.h> -#include <io.h> -#include <envfs.h> -#include <globalvar.h> -#include <asm/mmu.h> - -static int virt_mem_init(void) -{ - virt_add_ddram(SZ_2G); - - return 0; -} -mem_initcall(virt_mem_init); - -static int virt_env_init(void) -{ - add_cfi_flash_device(0, 0x00000000, SZ_128M, 0); - - devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_qemu_virt64); - - return 0; -} -device_initcall(virt_env_init); - -static int virt_console_init(void) -{ - virt_register_uart(0); - - return 0; -} -console_initcall(virt_console_init); - -static int virt_core_init(void) -{ - char *hostname = "virt64"; - - if (cpu_is_cortex_a53()) - hostname = "virt64-a53"; - else if (cpu_is_cortex_a57()) - hostname = "virt64-a57"; - - barebox_set_model("ARM QEMU virt64"); - barebox_set_hostname(hostname); - - return 0; -} -postcore_initcall(virt_core_init); diff --git a/arch/arm/boards/qemu-virt64/lowlevel.c b/arch/arm/boards/qemu-virt64/lowlevel.c deleted file mode 100644 index 629e2e9f6e..0000000000 --- a/arch/arm/boards/qemu-virt64/lowlevel.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * GPLv2 only - */ - -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <asm/system_info.h> - -void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - arm_setup_stack(0x40000000 + SZ_2G - SZ_16K); - - barebox_arm_entry(0x40000000, SZ_2G, NULL); -} diff --git a/arch/arm/boards/qil-a926x/Makefile b/arch/arm/boards/qil-a926x/Makefile index 82e46b369f..bf5ed8b4f4 100644 --- a/arch/arm/boards/qil-a926x/Makefile +++ b/arch/arm/boards/qil-a926x/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/qil-a926x/init.c b/arch/arm/boards/qil-a926x/init.c index fa7575d270..988657b354 100644 --- a/arch/arm/boards/qil-a926x/init.c +++ b/arch/arm/boards/qil-a926x/init.c @@ -10,24 +10,24 @@ #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <linux/clk.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> #include <led.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> static void qil_a9260_set_board_type(void) { diff --git a/arch/arm/boards/qil-a926x/lowlevel.c b/arch/arm/boards/qil-a926x/lowlevel.c index 7f52f824df..314980e84c 100644 --- a/arch/arm/boards/qil-a926x/lowlevel.c +++ b/arch/arm/boards/qil-a926x/lowlevel.c @@ -7,14 +7,23 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> +AT91_ENTRY_FUNCTION(start_qil_a926x, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); + + barebox_arm_entry(AT91_CHIPSELECT_1, + at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), + NULL); +} -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_qil_a9g20, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/radxa-cm3/.gitignore b/arch/arm/boards/radxa-cm3/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/radxa-cm3/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/radxa-cm3/Makefile b/arch/arm/boards/radxa-cm3/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/radxa-cm3/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/radxa-cm3/board.c b/arch/arm/boards/radxa-cm3/board.c new file mode 100644 index 0000000000..19d37e31d9 --- /dev/null +++ b/arch/arm/boards/radxa-cm3/board.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/rockchip/bbu.h> + +struct cm3_model { + const char *name; + const char *shortname; +}; + +static int cm3_probe(struct device *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + const struct cm3_model *model; + + model = device_get_match_data(dev); + + barebox_set_model(model->name); + barebox_set_hostname(model->shortname); + + if (bootsource == BOOTSOURCE_MMC && instance == 1) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rockchip_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, + "/dev/mmc0"); + rockchip_bbu_mmc_register("sd", 0, "/dev/mmc1"); + + return 0; +} + +static const struct cm3_model cm3_io = { + .name = "Radxa CM3 on IO Board", + .shortname = "cm3-io", +}; + +static const struct of_device_id cm3_of_match[] = { + { + .compatible = "radxa,cm3-io", + .data = &cm3_io, + }, + { /* sentinel */ }, +}; + +static struct driver cm3_io_board_driver = { + .name = "board-cm3-io", + .probe = cm3_probe, + .of_compatible = cm3_of_match, +}; +coredevice_platform_driver(cm3_io_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(cm3_of_match); diff --git a/arch/arm/boards/radxa-cm3/lowlevel.c b/arch/arm/boards/radxa-cm3/lowlevel.c new file mode 100644 index 0000000000..e1b453f21f --- /dev/null +++ b/arch/arm/boards/radxa-cm3/lowlevel.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3566_cm3_io_start[]; + +ENTRY_FUNCTION(start_radxa_cm3_io, r0, r1, r2) +{ + /* + * Enable vccio4 1.8V and vccio6 1.8V + * Needed for GMAC to work. + * FIXME: This is done by the io-domain driver as well, but there + * currently is no mechanism to make sure the driver gets probed + * before its consumers. Remove this setup once this issue is + * resolved. + */ + writel(RK_SETBITS(0x50), 0xfdc20140); + + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3566_cm3_io_start); +} diff --git a/arch/arm/boards/radxa-rock/Makefile b/arch/arm/boards/radxa-rock/Makefile index 79c8aec199..79d3969dcd 100644 --- a/arch/arm/boards/radxa-rock/Makefile +++ b/arch/arm/boards/radxa-rock/Makefile @@ -1,2 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_MACH_RADXA_ROCK) += board.o lwl-y += lowlevel.o +bbenv-y += defaultenv-radxa-rock diff --git a/arch/arm/boards/radxa-rock/board.c b/arch/arm/boards/radxa-rock/board.c index d45e8a9c52..1c93d6e522 100644 --- a/arch/arm/boards/radxa-rock/board.c +++ b/arch/arm/boards/radxa-rock/board.c @@ -1,22 +1,13 @@ -/* - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Beniamino Galvani <b.galvani@gmail.com> #include <common.h> #include <init.h> #include <io.h> +#include <envfs.h> #include <i2c/i2c.h> #include <i2c/i2c-gpio.h> -#include <mach/rk3188-regs.h> +#include <mach/rockchip/rk3188-regs.h> #include <mfd/act8846.h> #include <asm/armlinux.h> @@ -61,6 +52,8 @@ static int devices_init(void) writel((RK_SOC_CON0_REMAP << 16) | RK_SOC_CON0_REMAP, RK_GRF_BASE + RK_GRF_SOC_CON0); + defaultenv_append_directory(defaultenv_radxa_rock); + return 0; } device_initcall(devices_init); diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1 b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1 index c24a88edc5..c24a88edc5 100644 --- a/arch/arm/boards/radxa-rock/env/boot/mshc1 +++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1 diff --git a/arch/arm/boards/radxa-rock/env/boot/mshc1-old b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1-old index 2e43a3aafe..2e43a3aafe 100644 --- a/arch/arm/boards/radxa-rock/env/boot/mshc1-old +++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/boot/mshc1-old diff --git a/arch/arm/boards/radxa-rock/env/init/bootsource b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/init/bootsource index 4e8299b8dd..4e8299b8dd 100644 --- a/arch/arm/boards/radxa-rock/env/init/bootsource +++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/init/bootsource diff --git a/arch/arm/boards/radxa-rock/env/nv/hostname b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/hostname index 16523aca12..16523aca12 100644 --- a/arch/arm/boards/radxa-rock/env/nv/hostname +++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/hostname diff --git a/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.console b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/linux.bootargs.console index 37a03fd430..37a03fd430 100644 --- a/arch/arm/boards/radxa-rock/env/nv/linux.bootargs.console +++ b/arch/arm/boards/radxa-rock/defaultenv-radxa-rock/nv/linux.bootargs.console diff --git a/arch/arm/boards/radxa-rock/lowlevel.c b/arch/arm/boards/radxa-rock/lowlevel.c index 611dc938cf..982090e08c 100644 --- a/arch/arm/boards/radxa-rock/lowlevel.c +++ b/arch/arm/boards/radxa-rock/lowlevel.c @@ -1,15 +1,5 @@ -/* - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Beniamino Galvani <b.galvani@gmail.com> #include <common.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/radxa-rock3/.gitignore b/arch/arm/boards/radxa-rock3/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/radxa-rock3/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/radxa-rock3/Makefile b/arch/arm/boards/radxa-rock3/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/radxa-rock3/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/radxa-rock3/board.c b/arch/arm/boards/radxa-rock3/board.c new file mode 100644 index 0000000000..df99eded2c --- /dev/null +++ b/arch/arm/boards/radxa-rock3/board.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/rockchip/bbu.h> + +struct rock3_model { + const char *name; + const char *shortname; +}; + +static int rock3_probe(struct device *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + const struct rock3_model *model; + + model = device_get_match_data(dev); + + barebox_set_model(model->name); + barebox_set_hostname(model->shortname); + + if (bootsource == BOOTSOURCE_MMC && instance == 1) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rockchip_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc0"); + rockchip_bbu_mmc_register("sd", 0, "/dev/mmc1"); + + return 0; +} + +static const struct rock3_model rock3a = { + .name = "Radxa ROCK3 Model A", + .shortname = "rock3a", +}; + +static const struct of_device_id rock3_of_match[] = { + { + .compatible = "radxa,rock3a", + .data = &rock3a, + }, + { /* sentinel */ }, +}; + +static struct driver rock3_board_driver = { + .name = "board-rock3", + .probe = rock3_probe, + .of_compatible = rock3_of_match, +}; +coredevice_platform_driver(rock3_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rock3_of_match); diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c new file mode 100644 index 0000000000..ec407404b9 --- /dev/null +++ b/arch/arm/boards/radxa-rock3/lowlevel.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3568_rock_3a_start[]; + +ENTRY_FUNCTION(start_rock3a, r0, r1, r2) +{ + /* + * Enable vccio4 1.8V and vccio6 1.8V + * Needed for GMAC to work. + * FIXME: This is done by the io-domain driver as well, but there + * currently is no mechanism to make sure the driver gets probed + * before its consumers. Remove this setup once this issue is + * resolved. + */ + writel(RK_SETBITS(0x50), 0xfdc20140); + + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3568_rock_3a_start); +} diff --git a/arch/arm/boards/radxa-rock5/.gitignore b/arch/arm/boards/radxa-rock5/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/radxa-rock5/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/radxa-rock5/Makefile b/arch/arm/boards/radxa-rock5/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/radxa-rock5/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/radxa-rock5/board.c b/arch/arm/boards/radxa-rock5/board.c new file mode 100644 index 0000000000..eab0c01040 --- /dev/null +++ b/arch/arm/boards/radxa-rock5/board.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/rockchip/bbu.h> + +struct rock5_model { + const char *name; + const char *shortname; +}; + +static int rock5_probe(struct device *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + const struct rock5_model *model; + + model = device_get_match_data(dev); + + if (bootsource == BOOTSOURCE_MMC && instance == 1) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rockchip_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc0"); + rockchip_bbu_mmc_register("sd", 0, "/dev/mmc1"); + + return 0; +} + +static const struct rock5_model rock5b = { + .name = "Radxa ROCK5 Model B", + .shortname = "rock5b", +}; + +static const struct of_device_id rock5_of_match[] = { + { + .compatible = "radxa,rock-5b", + .data = &rock5b, + }, + { /* sentinel */ }, +}; + +static struct driver rock5_board_driver = { + .name = "board-rock5", + .probe = rock5_probe, + .of_compatible = rock5_of_match, +}; +coredevice_platform_driver(rock5_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rock5_of_match); diff --git a/arch/arm/boards/radxa-rock5/lowlevel.c b/arch/arm/boards/radxa-rock5/lowlevel.c new file mode 100644 index 0000000000..6f0ac732cc --- /dev/null +++ b/arch/arm/boards/radxa-rock5/lowlevel.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> +#include <mach/rockchip/rockchip.h> + +extern char __dtb_rk3588_rock_5b_start[]; + +ENTRY_FUNCTION(start_rock5b, r0, r1, r2) +{ + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3588_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3588_barebox_entry(__dtb_rk3588_rock_5b_start); +} diff --git a/arch/arm/boards/raspberry-pi/Makefile b/arch/arm/boards/raspberry-pi/Makefile index a3e93eb73a..e4f91b4979 100644 --- a/arch/arm/boards/raspberry-pi/Makefile +++ b/arch/arm/boards/raspberry-pi/Makefile @@ -1,2 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_MACH_RPI_COMMON) += rpi-common.o lwl-y += lowlevel.o +obj-pbl-y += mbox-helpers.o +bbenv-y += defaultenv-rpi diff --git a/arch/arm/boards/raspberry-pi/defaultenv-rpi/boot/rpi b/arch/arm/boards/raspberry-pi/defaultenv-rpi/boot/rpi new file mode 100755 index 0000000000..bf81aeb87b --- /dev/null +++ b/arch/arm/boards/raspberry-pi/defaultenv-rpi/boot/rpi @@ -0,0 +1,5 @@ +#!/bin/sh + +global linux.bootargs.dyn.vc="${global.vc.bootargs}" +global.bootm.image="/boot/${global.vc.kernel}" +global.bootm.oftree=/vc.dtb diff --git a/arch/arm/boards/raspberry-pi/env/init/bootargs-base b/arch/arm/boards/raspberry-pi/env/init/bootargs-base deleted file mode 100644 index 416dc8a6f4..0000000000 --- a/arch/arm/boards/raspberry-pi/env/init/bootargs-base +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -global.linux.bootargs.base="console=ttyAMA0,115200" diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c index 70f1936522..b3727d930f 100644 --- a/arch/arm/boards/raspberry-pi/lowlevel.c +++ b/arch/arm/boards/raspberry-pi/lowlevel.c @@ -1,8 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <asm/barebox-arm.h> #include <asm/cache.h> #include <common.h> #include <linux/sizes.h> -#include <mach/platform.h> +#include <asm/unaligned.h> +#include <mach/bcm283x/platform.h> +#include <debug_ll.h> +#include <mach/bcm283x/debug_ll.h> +#include <mach/bcm283x/mbox.h> #include <of.h> #include "lowlevel.h" @@ -11,8 +17,15 @@ static void copy_vc_fdt(void *dest, void *src, unsigned long max_size) { struct fdt_header *oftree_src = src; struct fdt_header *oftree_dest = dest; + unsigned long size; + + if (!src) { + oftree_dest->magic = cpu_to_be32(VIDEOCORE_FDT_ERROR); + oftree_dest->totalsize = cpu_to_be32(0); + return; + } - unsigned long size = be32_to_cpu(oftree_src->totalsize); + size = be32_to_cpu(oftree_src->totalsize); if (size > max_size) { oftree_dest->magic = cpu_to_be32(VIDEOCORE_FDT_ERROR); /* Save an error code after the magic value for easier @@ -24,52 +37,151 @@ static void copy_vc_fdt(void *dest, void *src, unsigned long max_size) memmove(dest, src, size); } -/* Must be inline since stack isn't setup yet. */ static inline void start_raspberry_pi(unsigned long memsize, void *fdt, void *vc_fdt) { - void *saved_vc_fdt; - unsigned long membase = BCM2835_SDRAM_BASE; + unsigned long endmem; - /* A pointer to the FDT created by VideoCore was passed to us in r2. We - * reserve some memory just above the region used for Basebox and copy - * this FDT there. We fetch it from there later in rpi_devices_init().*/ + /* + * A pointer to the FDT created by VideoCore was passed to us in x0/r2. We + * reserve some memory at the end of SDRAM copy this FDT there. We fetch it + * from there later in rpi_devices_init(). + */ memsize -= VIDEOCORE_FDT_SZ; + endmem = BCM2835_SDRAM_BASE + memsize; - arm_cpu_lowlevel_init(); - - /* Copied from barebox_arm_entry(). We need stack here early - * for normal function calls to work. */ - arm_setup_stack(arm_mem_stack_top(membase, membase + memsize)); + /* leave SZ_1K for the initial stack */ + copy_vc_fdt((void *)endmem, vc_fdt, VIDEOCORE_FDT_SZ - SZ_1K); fdt += get_runtime_offset(); - saved_vc_fdt = (void *)(membase + memsize); - copy_vc_fdt(saved_vc_fdt, vc_fdt, VIDEOCORE_FDT_SZ); + barebox_arm_entry(BCM2835_SDRAM_BASE, memsize, fdt); +} + +#ifdef CONFIG_CPU_V8 +#define RPI_ENTRY_FUNCTION(name, memsize, fdt) \ + ENTRY_FUNCTION_WITHSTACK(name, BCM2835_SDRAM_BASE + (memsize), fdt, __x1, __x2) +#else +#define RPI_ENTRY_FUNCTION(name, memsize, fdt) \ + ENTRY_FUNCTION_WITHSTACK(name, BCM2835_SDRAM_BASE + (memsize), __r0, __r1, fdt) +#endif + +extern char __dtb_z_bcm2835_rpi_start[]; +extern char __dtb_z_bcm2836_rpi_2_start[]; +extern char __dtb_z_bcm2837_rpi_3_start[]; +extern char __dtb_z_bcm2837_rpi_cm3_start[]; +extern char __dtb_z_bcm2711_rpi_4_start[]; +extern char __dtb_z_bcm2711_rpi_400_start[]; +extern char __dtb_z_bcm2711_rpi_cm4_io_start[]; +extern char __dtb_z_bcm2711_rpi_cm4s_io_start[]; + +RPI_ENTRY_FUNCTION(start_raspberry_pi1, SZ_128M, fdt) +{ + arm_cpu_lowlevel_init(); - barebox_arm_entry(membase, memsize, fdt); + start_raspberry_pi(SZ_128M, __dtb_z_bcm2835_rpi_start, (void *)fdt); } -extern char __dtb_bcm2835_rpi_start[]; -ENTRY_FUNCTION(start_raspberry_pi1, r0, r1, r2) +RPI_ENTRY_FUNCTION(start_raspberry_pi2, SZ_512M, fdt) { - start_raspberry_pi(SZ_128M, __dtb_bcm2835_rpi_start, (void *)r2); + arm_cpu_lowlevel_init(); + + start_raspberry_pi(SZ_512M, __dtb_z_bcm2836_rpi_2_start, (void *)fdt); } -extern char __dtb_bcm2836_rpi_2_start[]; -ENTRY_FUNCTION(start_raspberry_pi2, r0, r1, r2) +RPI_ENTRY_FUNCTION(start_raspberry_pi3, SZ_512M, fdt) { - start_raspberry_pi(SZ_512M, __dtb_bcm2836_rpi_2_start, (void *)r2); + arm_cpu_lowlevel_init(); + + start_raspberry_pi(SZ_512M, __dtb_z_bcm2837_rpi_3_start, (void *)fdt); +} + +RPI_ENTRY_FUNCTION(start_raspberry_pi_cm3, SZ_512M, fdt) +{ + arm_cpu_lowlevel_init(); + + start_raspberry_pi(SZ_512M, __dtb_z_bcm2837_rpi_cm3_start, (void *)fdt); } -extern char __dtb_bcm2837_rpi_3_start[]; -ENTRY_FUNCTION(start_raspberry_pi3, r0, r1, r2) +#define DT_IF_ENABLED(dt, cfg) \ + (IS_ENABLED(cfg) ? (dt) : NULL) + +static void *rpi_get_board_fdt(int rev) { - start_raspberry_pi(SZ_512M, __dtb_bcm2837_rpi_3_start, (void *)r2); + if (!(rev & 0x800000)) + return DT_IF_ENABLED(__dtb_z_bcm2835_rpi_start, CONFIG_MACH_RPI); + + switch (((rev >> 4) & 0xff)) { + case BCM2835_BOARD_REV_A: + case BCM2835_BOARD_REV_B: + case BCM2835_BOARD_REV_A_PLUS: + case BCM2835_BOARD_REV_B_PLUS: + case BCM2835_BOARD_REV_CM1: + case BCM2835_BOARD_REV_ZERO: + case BCM2835_BOARD_REV_ZERO_W: + return DT_IF_ENABLED(__dtb_z_bcm2835_rpi_start, CONFIG_MACH_RPI); + + case BCM2836_BOARD_REV_2_B: + return DT_IF_ENABLED(__dtb_z_bcm2836_rpi_2_start, CONFIG_MACH_RPI2); + + case BCM2837_BOARD_REV_3_B: + case BCM2837B0_BOARD_REV_3B_PLUS: + case BCM2837B0_BOARD_REV_3A_PLUS: + case BCM2837B0_BOARD_REV_ZERO_2: + return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_3_start, CONFIG_MACH_RPI3); + + case BCM2837_BOARD_REV_CM3: + case BCM2837B0_BOARD_REV_CM3_PLUS: + return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_cm3_start, CONFIG_MACH_RPI_CM3); + + case BCM2711_BOARD_REV_4_B: + return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_4_start, CONFIG_MACH_RPI4); + case BCM2711_BOARD_REV_400: + return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_400_start, CONFIG_MACH_RPI4); + case BCM2711_BOARD_REV_CM4: + return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_cm4_io_start, CONFIG_MACH_RPI4); + case BCM2711_BOARD_REV_CM4_S: + return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_cm4s_io_start, CONFIG_MACH_RPI4); + } + + return NULL; } -extern char __dtb_bcm2837_rpi_cm3_start[]; -ENTRY_FUNCTION(start_raspberry_pi_cm3, r0, r1, r2) +RPI_ENTRY_FUNCTION(start_raspberry_pi_generic, SZ_128M, vc_fdt) { - start_raspberry_pi(SZ_512M, __dtb_bcm2837_rpi_cm3_start, (void *)r2); + void *fdt = NULL; + ssize_t memsize; + int rev; + + arm_cpu_lowlevel_init(); + + debug_ll_init(); + + putc_ll('>'); + + relocate_to_current_adr(); + setup_c(); + + memsize = rpi_get_arm_mem(); + if (memsize < 0) { + pr_warn("mbox: failed to query ARM memory size. 128M assumed.\n"); + memsize = SZ_128M; + } + + rev = rpi_get_board_rev(); + if (rev >= 0) { + pr_debug("Detected revision %08x\n", rev); + fdt = rpi_get_board_fdt(rev); + } + + if (!fdt) { + fdt = (void *)vc_fdt; + + pr_warn("Unknown Rpi board with rev %08x.\n", rev); + + if (get_unaligned_be32(fdt) != 0xd00dfeed) + panic("No suitable built-in or videocore-supplied DT\n"); + } + + start_raspberry_pi(memsize, fdt, (void *)vc_fdt); } diff --git a/arch/arm/boards/raspberry-pi/lowlevel.h b/arch/arm/boards/raspberry-pi/lowlevel.h index 9ef9135b2d..a29860d607 100644 --- a/arch/arm/boards/raspberry-pi/lowlevel.h +++ b/arch/arm/boards/raspberry-pi/lowlevel.h @@ -1,9 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ARCH_ARM_BOARDS_LOWLEVEL_H__ #define __ARCH_ARM_BOARDS_LOWLEVEL_H__ +#include <linux/types.h> #include <linux/sizes.h> #define VIDEOCORE_FDT_SZ SZ_1M #define VIDEOCORE_FDT_ERROR 0xdeadfeed +ssize_t rpi_get_arm_mem(void); +int rpi_get_usbethaddr(u8 mac[6]); +int rpi_get_board_rev(void); + #endif /* __ARCH_ARM_BOARDS_LOWLEVEL_H__ */ diff --git a/arch/arm/boards/raspberry-pi/mbox-helpers.c b/arch/arm/boards/raspberry-pi/mbox-helpers.c new file mode 100644 index 0000000000..3a76ac2b01 --- /dev/null +++ b/arch/arm/boards/raspberry-pi/mbox-helpers.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Carlo Caione <carlo@carlocaione.org> + +#include <mach/bcm283x/mbox.h> +#include "lowlevel.h" + +struct msg_get_arm_mem { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; + u32 end_tag; +}; + +struct msg_get_board_rev { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_board_rev get_board_rev; + u32 end_tag; +}; + +struct msg_get_mac_address { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_mac_address get_mac_address; + u32 end_tag; +}; + +ssize_t rpi_get_arm_mem(void) +{ + BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg); + int ret; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) + return ret; + + return msg->get_arm_mem.body.resp.mem_size; +} + +int rpi_get_usbethaddr(u8 mac[6]) +{ + BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg); + int ret; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + pr_info("bcm2835: Could not query MAC address\n"); + return ret; + } + + memcpy(mac, msg->get_mac_address.body.resp.mac, 6); + return 0; +} + +int rpi_get_board_rev(void) +{ + int ret; + + BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg); + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + pr_err("Could not query board revision\n"); + return ret; + } + + return msg->get_board_rev.body.resp.rev; +} diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index dd6bbd5bdd..628f657ea2 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -1,26 +1,17 @@ -/* - * Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2009 Carlo Caione <carlo@carlocaione.org> #include <common.h> +#include <deep-probe.h> #include <init.h> #include <fs.h> #include <of.h> +#include <of_device.h> #include <linux/stat.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <envfs.h> +#include <regulator.h> #include <malloc.h> #include <libfile.h> #include <gpio.h> @@ -28,93 +19,72 @@ #include <led.h> #include <asm/armlinux.h> #include <asm/barebox-arm.h> -#include <generated/mach-types.h> +#include <asm/mach-types.h> #include <linux/sizes.h> #include <globalvar.h> +#include <asm/system_info.h> +#include <reset_source.h> -#include <mach/core.h> -#include <mach/mbox.h> -#include <mach/platform.h> +#include <mach/bcm283x/core.h> +#include <mach/bcm283x/mbox.h> +#include <mach/bcm283x/platform.h> + +#include <soc/bcm283x/wdt.h> -#include "rpi.h" #include "lowlevel.h" -struct msg_get_arm_mem { - struct bcm2835_mbox_hdr hdr; - struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; - u32 end_tag; +//https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#BOOT_ORDER +static const char * const boot_mode_names[] = { + [0x0] = "unknown", + [0x1] = "sd", + [0x2] = "net", + [0x3] = "rpiboot", + [0x4] = "usbmsd", + [0x5] = "usbc", + [0x6] = "nvme", + [0x7] = "http", }; -struct msg_get_clock_rate { - struct bcm2835_mbox_hdr hdr; - struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; - u32 end_tag; +struct rpi_priv; +struct rpi_machine_data { + int (*init)(struct rpi_priv *priv); + u8 hw_id; +#define RPI_OLD_SCHEMA BIT(0) + u8 flags; }; -struct msg_get_board_rev { - struct bcm2835_mbox_hdr hdr; - struct bcm2835_mbox_tag_get_board_rev get_board_rev; - u32 end_tag; +struct rpi_priv { + struct device *dev; + const struct rpi_machine_data *dcfg; + unsigned int hw_id; + const char *name; }; -struct msg_get_mac_address { - struct bcm2835_mbox_hdr hdr; - struct bcm2835_mbox_tag_get_mac_address get_mac_address; - u32 end_tag; +struct rpi_property_fixup_data { + const struct device_node* vc_node; + const char *propname; }; -static int rpi_get_arm_mem(u32 *size) -{ - BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg); - int ret; - - BCM2835_MBOX_INIT_HDR(msg); - BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY); - - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); - if (ret) - return ret; - - *size = msg->get_arm_mem.body.resp.mem_size; - - return 0; -} - -static struct clk *rpi_register_firmware_clock(u32 clock_id, const char *name) +static void rpi_set_usbethaddr(void) { - BCM2835_MBOX_STACK_ALIGN(struct msg_get_clock_rate, msg); - int ret; - - BCM2835_MBOX_INIT_HDR(msg); - BCM2835_MBOX_INIT_TAG(&msg->get_clock_rate, GET_CLOCK_RATE); - msg->get_clock_rate.body.req.clock_id = clock_id; + u8 mac[ETH_ALEN]; - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); - if (ret) - return ERR_PTR(ret); + if (rpi_get_usbethaddr(mac)) + return; /* Ignore error; not critical */ - return clk_fixed(name, msg->get_clock_rate.body.resp.rate_hz); + eth_register_ethaddr(0, mac); } -void rpi_set_usbethaddr(void) +static void rpi_set_usbotg(const char *alias) { - BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg); - int ret; - - BCM2835_MBOX_INIT_HDR(msg); - BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS); - - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); - if (ret) { - printf("bcm2835: Could not query MAC address\n"); - /* Ignore error; not critical */ - return; - } + struct device_node *usb; - eth_register_ethaddr(0, msg->get_mac_address.body.resp.mac); + usb = of_find_node_by_alias(NULL, alias); + if (usb) + of_property_write_string(usb, "dr_mode", "otg"); } -struct gpio_led rpi_leds[] = { +static struct gpio_led rpi_leds[] = { { .gpio = -EINVAL, .led = { @@ -145,325 +115,658 @@ static void rpi_add_led(void) led_set_trigger(LED_TRIGGER_HEARTBEAT, &l->led); } -static void rpi_b_init(void) +static int rpi_eth_init(struct rpi_priv *priv) +{ + rpi_set_usbethaddr(); + return 0; +} + +static int rpi_b_init(struct rpi_priv *priv) { rpi_leds[0].gpio = 16; rpi_leds[0].active_low = 1; rpi_set_usbethaddr(); + + return 0; } -static void rpi_b_plus_init(void) +static int rpi_b_plus_init(struct rpi_priv *priv) { rpi_leds[0].gpio = 47; rpi_leds[1].gpio = 35; rpi_set_usbethaddr(); -} -/* See comments in mbox.h for data source */ -const struct rpi_model rpi_models_old_scheme[] = { - RPI_MODEL(0, "Unknown model", NULL), - RPI_MODEL(BCM2835_BOARD_REV_B_I2C0_2, "Model B (no P5)", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_I2C0_3, "Model B (no P5)", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_I2C1_4, "Model B", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_I2C1_5, "Model B", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_I2C1_6, "Model B", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_A_7, "Model A", NULL), - RPI_MODEL(BCM2835_BOARD_REV_A_8, "Model A", NULL), - RPI_MODEL(BCM2835_BOARD_REV_A_9, "Model A", NULL), - RPI_MODEL(BCM2835_BOARD_REV_B_REV2_d, "Model B rev2", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_REV2_e, "Model B rev2", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_REV2_f, "Model B rev2", rpi_b_init), - RPI_MODEL(BCM2835_BOARD_REV_B_PLUS_10, "Model B+", rpi_b_plus_init), - RPI_MODEL(BCM2835_BOARD_REV_CM_11, "Compute Module", NULL), - RPI_MODEL(BCM2835_BOARD_REV_A_PLUS_12, "Model A+", NULL), - RPI_MODEL(BCM2835_BOARD_REV_B_PLUS_13, "Model B+", rpi_b_plus_init), - RPI_MODEL(BCM2835_BOARD_REV_CM_14, "Compute Module", NULL), - RPI_MODEL(BCM2835_BOARD_REV_A_PLUS_15, "Model A+", NULL), -}; + return 0; +} -const struct rpi_model rpi_models_new_scheme[] = { - RPI_MODEL(BCM2835_BOARD_REV_A, "Model A", NULL ), - RPI_MODEL(BCM2835_BOARD_REV_B, "Model B", rpi_b_init ), - RPI_MODEL(BCM2835_BOARD_REV_A_PLUS, "Model A+", NULL ), - RPI_MODEL(BCM2835_BOARD_REV_B_PLUS, "Model B+", rpi_b_plus_init ), - RPI_MODEL(BCM2836_BOARD_REV_2_B, "Model 2B", rpi_b_plus_init), - RPI_MODEL(BCM283x_BOARD_REV_Alpha, "Alpha", NULL), - RPI_MODEL(BCM2835_BOARD_REV_CM1, "Compute Module", NULL ), - RPI_MODEL(0x7, "Unknown model", NULL), - RPI_MODEL(BCM2837_BOARD_REV_3_B, "Model 3B", rpi_b_init ), - RPI_MODEL(BCM2835_BOARD_REV_ZERO, "Zero", rpi_b_plus_init), - RPI_MODEL(BCM2837_BOARD_REV_CM3, "Compute Module 3", NULL ), - RPI_MODEL(0xb, "Unknown model", NULL), - RPI_MODEL(BCM2835_BOARD_REV_ZERO_W, "Zero W", rpi_b_plus_init), - RPI_MODEL(BCM2837B0_BOARD_REV_3B_PLUS, "Model 3 B+", rpi_b_plus_init ), - RPI_MODEL(BCM2837B0_BOARD_REV_3A_PLUS, "Nodel 3 A+", rpi_b_plus_init), - RPI_MODEL(0xf, "Unknown model", NULL), - RPI_MODEL(BCM2837B0_BOARD_REV_CM3_PLUS, "Compute Module 3+", NULL), -}; +static int rpi_0_init(struct rpi_priv *priv) +{ + rpi_leds[0].gpio = 47; + rpi_set_usbotg("usb0"); -static int rpi_board_rev = 0; -const struct rpi_model *model = NULL; + return 0; +} -static void rpi_get_board_rev(void) +static int rpi_0_w_init(struct rpi_priv *priv) { + struct device_node *np; int ret; - char *name; - const struct rpi_model *rpi_models; - size_t rpi_models_size; - BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg); - BCM2835_MBOX_INIT_HDR(msg); - BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV); + rpi_0_init(priv); - ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); - if (ret) { - printf("bcm2835: Could not query board revision\n"); - /* Ignore error; not critical */ - return; - } + np = of_find_node_by_path("/chosen"); + if (!np) + return -ENODEV; - /* Comments from u-boot: - * For details of old-vs-new scheme, see: - * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py - * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282 - * (a few posts down) - * - * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the - * lower byte to use as the board rev: - * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 - * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 - */ - rpi_board_rev = msg->get_board_rev.body.resp.rev; - if (rpi_board_rev & 0x800000) { - rpi_board_rev = (rpi_board_rev >> 4) & 0xff; - rpi_models = rpi_models_new_scheme; - rpi_models_size = ARRAY_SIZE(rpi_models_new_scheme); + if (!of_device_enable_and_register_by_alias("serial1")) + return -ENODEV; - } else { - rpi_board_rev &= 0xff; - rpi_models = rpi_models_old_scheme; - rpi_models_size = ARRAY_SIZE(rpi_models_old_scheme); - } + ret = of_property_write_string(np, "stdout-path", "serial1:115200n8"); + if (ret) + return ret; - if (rpi_board_rev >= rpi_models_size) { - printf("RPI: Board rev %u outside known range\n", - rpi_board_rev); - goto unknown_rev; - } + return of_device_disable_by_alias("serial0"); +} - if (!rpi_models[rpi_board_rev].name) { - printf("RPI: Board rev %u unknown\n", rpi_board_rev); - goto unknown_rev; - } +static int rpi_mem_init(void) +{ + ssize_t size; - if (!rpi_board_rev) - goto unknown_rev; + if (!of_machine_is_compatible("brcm,bcm2837") && + !of_machine_is_compatible("brcm,bcm2835") && + !of_machine_is_compatible("brcm,bcm2711") && + !of_machine_is_compatible("brcm,bcm2836")) + return 0; - model = &rpi_models[rpi_board_rev]; - name = basprintf("RaspberryPi %s", model->name); - barebox_set_model(name); - free(name); + size = rpi_get_arm_mem(); + if (size < 0) { + printf("could not query ARM memory size\n"); + size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M); + } - return; + bcm2835_add_device_sdram(size); -unknown_rev: - rpi_board_rev = 0; - barebox_set_model("RaspberryPi (unknown rev)"); + return 0; } +mem_initcall(rpi_mem_init); -static void rpi_model_init(void) +static int rpi_env_init(void) { - if (!model) - return; + struct stat s; + const char *diskdev; + int ret; - if (!model->init) - return; + device_detect_by_name("mci0"); + device_detect_by_name("mci1"); - model->init(); - rpi_add_led(); -} + diskdev = "/dev/disk0.0"; + ret = stat(diskdev, &s); + if (ret) { + device_detect_by_name("mmc0"); + diskdev = "/dev/mmc0.0"; + ret = stat(diskdev, &s); + } + if (ret) { + printf("no /dev/disk0.0 or /dev/mmc0.0. using default env\n"); + return 0; + } -static int rpi_mem_init(void) -{ - u32 size = 0; - int ret; + mkdir("/boot", 0666); + ret = mount(diskdev, "fat", "/boot", NULL); + if (ret) { + printf("failed to mount %s\n", diskdev); + return 0; + } - ret = rpi_get_arm_mem(&size); - if (ret) - printf("could not query ARM memory size\n"); + defaultenv_append_directory(defaultenv_rpi); - bcm2835_add_device_sdram(size); + default_environment_path_set("/boot/barebox.env"); - return ret; + return 0; } -mem_initcall(rpi_mem_init); -static int rpi_postcore_init(void) +/* Some string properties in fdt passed to us from vc may be + * malformed by not being null terminated, so just create and + * return a fixed copy. + */ +static char *of_read_vc_string(struct device_node *node, + const char *prop_name) { - rpi_get_board_rev(); - barebox_set_hostname("rpi"); - - return 0; + int len; + const char *str; + + str = of_get_property(node, prop_name, &len); + if (!str) { + pr_warn("no property '%s' found in vc fdt's '%pOF' node\n", + prop_name, node); + return NULL; + } + return xstrndup(str, len); } -postcore_initcall(rpi_postcore_init); -static int rpi_clock_init(void) +static enum reset_src_type rpi_decode_pm_rsts(struct device_node *chosen, + struct device_node *bootloader) { - struct clk *clk; + u32 pm_rsts; + int ret; + + ret = of_property_read_u32(chosen, "pm_rsts", &pm_rsts); + if (ret && bootloader) + ret = of_property_read_u32(bootloader, "rsts", &pm_rsts); + + if (ret) { + pr_warn("'pm_rsts' value not found in vc fdt\n"); + return RESET_UKWN; + } + /* + * https://github.com/raspberrypi/linux/issues/932#issuecomment-93989581 + */ - clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_EMMC, - "bcm2835_mci0"); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (pm_rsts & PM_RSTS_HADPOR_SET) + return RESET_POR; + if (pm_rsts & PM_RSTS_HADDR_SET) + return RESET_JTAG; + if (pm_rsts & PM_RSTS_HADWR_SET) + return RESET_WDG; + if (pm_rsts & PM_RSTS_HADSR_SET) + return RESET_RST; - clkdev_add_physbase(clk, 0x20300000, NULL); - clkdev_add_physbase(clk, 0x3f300000, NULL); + return RESET_UKWN; +} - clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE, - "bcm2835_sdhost"); - if (IS_ERR(clk)) - return PTR_ERR(clk); +static int rpi_vc_fdt_fixup(struct device_node *root, void *data) +{ + const struct device_node *vc_node = data; + struct device_node *node; + struct property *pp; - clkdev_add_physbase(clk, 0x20202000, NULL); - clkdev_add_physbase(clk, 0x3f202000, NULL); + node = of_create_node(root, vc_node->full_name); + if (!node) + return -ENOMEM; + + for_each_property_of_node(vc_node, pp) + of_copy_property(vc_node, pp->name, node); return 0; } -postconsole_initcall(rpi_clock_init); -static int rpi_console_clock_init(void) +static struct device_node *register_vc_fixup(struct device_node *root, + const char *path) { - struct clk *clk; + struct device_node *ret, *tmp; - clk = clk_fixed("apb_pclk", 0); - clk_register_clkdev(clk, "apb_pclk", NULL); + ret = of_find_node_by_path_from(root, path); + if (ret) { + tmp = of_dup(ret); + tmp->full_name = xstrdup(ret->full_name); + of_register_fixup(rpi_vc_fdt_fixup, tmp); + } else { + pr_info("no '%s' node found in vc fdt\n", path); + } - clk = clk_fixed("uart0-pl0110", 3 * 1000 * 1000); - clk_register_clkdev(clk, NULL, "uart0-pl0110"); - clkdev_add_physbase(clk, BCM2835_PL011_BASE, NULL); - clkdev_add_physbase(clk, BCM2836_PL011_BASE, NULL); + return ret; +} - clk = rpi_register_firmware_clock(BCM2835_MBOX_CLOCK_ID_CORE, - "uart1-8250"); - if (IS_ERR(clk)) - return PTR_ERR(clk); +static int rpi_vc_fdt_fixup_property(struct device_node *root, void *data) +{ + const struct rpi_property_fixup_data *fixup = data; + struct device_node *node; + struct property *prop; - clkdev_add_physbase(clk, BCM2836_MINIUART_BASE, NULL); + node = of_create_node(root, fixup->vc_node->full_name); + if (!node) + return -ENOMEM; - clk = clk_fixed("bcm2835-cs", 1 * 1000 * 1000); - clk_register_clkdev(clk, NULL, "bcm2835-cs"); + prop = of_find_property(fixup->vc_node, fixup->propname, NULL); + if (!prop) + return -ENOENT; + + return of_set_property(node, prop->name, + of_property_get_value(prop), prop->length, 1); +} + +static int register_vc_property_fixup(struct device_node *root, + const char *path, const char *propname) +{ + struct device_node *node, *tmp; + struct rpi_property_fixup_data* fixup_data; + + node = of_find_node_by_path_from(root, path); + if (node) { + tmp = of_dup(node); + tmp->full_name = xstrdup(node->full_name); + fixup_data = xzalloc(sizeof(*fixup_data)); + fixup_data->vc_node = tmp; + fixup_data->propname = xstrdup(propname); + + of_register_fixup(rpi_vc_fdt_fixup_property, fixup_data); + } else { + pr_info("no '%s' node found in vc fdt\n", path); + return -ENOENT; + } return 0; } -postcore_initcall(rpi_console_clock_init); -static int rpi_env_init(void) +static u32 rpi_boot_mode, rpi_boot_part; +/* Extract useful information from the VideoCore FDT we got. + * Some parameters are defined here: + * https://www.raspberrypi.com/documentation/computers/configuration.html#part4 + */ +static void rpi_vc_fdt_parse(struct device_node *root) { - struct stat s; - const char *diskdev = "/dev/disk0.0"; int ret; + struct device_node *chosen, *bootloader, *memory; + char *str; - device_detect_by_name("mci0"); - - ret = stat(diskdev, &s); - if (ret) { - printf("no %s. using default env\n", diskdev); - return 0; + str = of_read_vc_string(root, "serial-number"); + if (str) { + barebox_set_serial_number(str); + free(str); } - mkdir("/boot", 0666); - ret = mount(diskdev, "fat", "/boot", NULL); - if (ret) { - printf("failed to mount %s\n", diskdev); - return 0; + str = of_read_vc_string(root, "model"); + if (str) { + barebox_set_model(str); + free(str); } - default_environment_path_set("/boot/barebox.env"); + register_vc_fixup(root, "/system"); + register_vc_fixup(root, "/axi"); + register_vc_property_fixup(root, "/reserved-memory/nvram@0", "reg"); + register_vc_property_fixup(root, "/reserved-memory/nvram@0", "status"); + register_vc_fixup(root, "/hat"); + register_vc_property_fixup(root, "/emmc2bus", "dma-ranges"); + register_vc_fixup(root, "/chosen/bootloader"); + chosen = register_vc_fixup(root, "/chosen"); + if (!chosen) { + pr_err("no '/chosen' node found in vc fdt\n"); + return; + } - return 0; -} + bootloader = of_find_node_by_name(chosen, "bootloader"); -/* Extract /chosen/bootargs from the VideoCore FDT into vc.bootargs - * global variable. */ -static int rpi_vc_fdt_bootargs(void *fdt) -{ - int ret = 0; - struct device_node *root = NULL, *node; - const char *cmdline; - - root = of_unflatten_dtb(fdt); - if (IS_ERR(root)) { - ret = PTR_ERR(root); - root = NULL; - goto out; + str = of_read_vc_string(chosen, "bootargs"); + if (str) { + globalvar_add_simple("vc.bootargs", str); + free(str); } - node = of_find_node_by_path_from(root, "/chosen"); - if (!node) { - pr_err("no /chosen node\n"); - ret = -ENOENT; - goto out; + str = of_read_vc_string(chosen, "overlay_prefix"); + if (str) { + globalvar_add_simple("vc.overlay_prefix", str); + free(str); } - cmdline = of_get_property(node, "bootargs", NULL); - if (!cmdline) { - pr_err("no bootargs property in the /chosen node\n"); - ret = -ENOENT; - goto out; + str = of_read_vc_string(chosen, "os_prefix"); + if (str) { + globalvar_add_simple("vc.os_prefix", str); + free(str); } - globalvar_add_simple("vc.bootargs", cmdline); + ret = of_property_read_u32(chosen, "boot-mode", &rpi_boot_mode); + if (ret && bootloader) + ret = of_property_read_u32(bootloader, "boot-mode", &rpi_boot_mode); + if (ret) + pr_debug("'boot-mode' property not found in vc fdt\n"); + else + globalvar_add_simple_enum("vc.boot_mode", &rpi_boot_mode, + boot_mode_names, + ARRAY_SIZE(boot_mode_names)); + + ret = of_property_read_u32(chosen, "partition", &rpi_boot_part); + if (ret && bootloader) + ret = of_property_read_u32(bootloader, "partition", &rpi_boot_part); + if (ret) + pr_debug("'partition' property not found in vc fdt\n"); + else + globalvar_add_simple_int("vc.boot_partition", &rpi_boot_part, "%u"); -out: - if (root) - of_delete_node(root); + if (IS_ENABLED(CONFIG_RESET_SOURCE)) + reset_source_set(rpi_decode_pm_rsts(chosen, bootloader)); - return ret; + /* Parse all available nodes with "memory" device_type */ + memory = root; + while (1) { + memory = of_find_node_by_type(memory, "memory"); + if (!memory) + break; + + of_add_memory(memory, false); + } } -static void rpi_vc_fdt(void) +/** + * rpi_vc_fdt - unflatten VideoCore provided DT + * + * If configured via config.txt, the VideoCore firmware will pass barebox PBL + * a device-tree in a register. This is saved to a handover memory area by + * the Raspberry Pi PBL, which is parsed here. barebox-dt-2nd doesn't + * populate this area, instead it uses the VideoCore DT as its own DT. + * + * Return: an unflattened DT on success, an error pointer if parsing the DT + * fails and NULL if a Raspberry Pi PBL has run, but no VideoCore FDT was + * saved. + */ +static struct device_node *rpi_vc_fdt(void) { void *saved_vc_fdt; struct fdt_header *oftree; unsigned long magic, size; - int ret; /* VideoCore FDT was copied in PBL just above Barebox memory */ saved_vc_fdt = (void *)(arm_mem_endmem_get()); oftree = saved_vc_fdt; magic = be32_to_cpu(oftree->magic); - if (magic != FDT_MAGIC) { - pr_err("videocore fdt saved in pbl has invalid magic\n"); - if (magic == VIDEOCORE_FDT_ERROR) { + if (magic == VIDEOCORE_FDT_ERROR) { + if (oftree->totalsize) pr_err("there was an error copying fdt in pbl: %d\n", be32_to_cpu(oftree->totalsize)); - } - return; + return NULL; } + if (magic != FDT_MAGIC) + return ERR_PTR(-EINVAL); + size = be32_to_cpu(oftree->totalsize); - if (write_file("/vc.dtb", saved_vc_fdt, size)) { + if (write_file("/vc.dtb", saved_vc_fdt, size)) pr_err("failed to save videocore fdt to a file\n"); - return; + + return of_unflatten_dtb(saved_vc_fdt, INT_MAX); +} + +static void rpi_set_kernel_name(void) { + switch(cpu_architecture()) { + case CPU_ARCH_ARMv6: + globalvar_add_simple("vc.kernel", "kernel.img"); + break; + case CPU_ARCH_ARMv7: + globalvar_add_simple("vc.kernel", "kernel7.img"); + break; + case CPU_ARCH_ARMv8: + globalvar_add_simple("vc.kernel", "kernel8.img"); + break; } +} - ret = rpi_vc_fdt_bootargs(saved_vc_fdt); - if (ret) { - pr_err("failed to extract bootargs from videocore fdt: %d\n", - ret); - return; +static const struct rpi_machine_data *rpi_get_dcfg(struct rpi_priv *priv) +{ + const struct rpi_machine_data *dcfg; + + dcfg = of_device_get_match_data(priv->dev); + if (!dcfg) { + dev_err(priv->dev, "Unknown board. Not applying fixups\n"); + return NULL; + } + + /* Comments from u-boot: + * For details of old-vs-new scheme, see: + * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282 + * (a few posts down) + * + * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the + * lower byte to use as the board rev: + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 + * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 + */ + + for (; dcfg->hw_id != U8_MAX; dcfg++) { + if (priv->hw_id & 0x800000) { + if (dcfg->hw_id != ((priv->hw_id >> 4) & 0xff)) + continue; + } else { + if (!(dcfg->flags & RPI_OLD_SCHEMA)) + continue; + if (dcfg->hw_id != (priv->hw_id & 0xff)) + continue; + } + + return dcfg; } + + dev_err(priv->dev, "dcfg 0x%x for board_id doesn't match DT compatible\n", + priv->hw_id); + return ERR_PTR(-ENODEV); } -static int rpi_devices_init(void) +static int rpi_devices_probe(struct device *dev) { - rpi_model_init(); + const struct rpi_machine_data *dcfg; + struct regulator *reg; + struct rpi_priv *priv; + struct device_node *vc_root; + const char *name, *ptr; + char *hostname; + int ret; + + priv = xzalloc(sizeof(*priv)); + priv->dev = dev; + + ret = rpi_get_board_rev(); + if (ret < 0) + goto free_priv; + + priv->hw_id = ret; + + dcfg = rpi_get_dcfg(priv); + if (IS_ERR(dcfg)) + goto free_priv; + + /* construct short recognizable host name */ + name = of_device_get_match_compatible(priv->dev); + ptr = strchr(name, ','); + hostname = basprintf("rpi-%s", ptr ? ptr + 1 : name); + barebox_set_hostname(hostname); + free(hostname); + + rpi_add_led(); bcm2835_register_fb(); armlinux_set_architecture(MACH_TYPE_BCM2708); rpi_env_init(); - rpi_vc_fdt(); + + vc_root = rpi_vc_fdt(); + if (!vc_root) { + dev_dbg(dev, "No VideoCore FDT was provided\n"); + } else if (!IS_ERR(vc_root)) { + dev_dbg(dev, "VideoCore FDT was provided\n"); + rpi_vc_fdt_parse(vc_root); + of_delete_node(vc_root); + } else if (IS_ERR(vc_root)) { + /* This is intentionally at a higher logging level, because we can't + * be sure that the external DT is indeed a barebox DT (and not a + * kernel DT that happened to be in the partition). So for ease + * of debugging, we report this at info log level. + */ + dev_info(dev, "barebox FDT will be used for VideoCore FDT\n"); + rpi_vc_fdt_parse(priv->dev->device_node); + } + + rpi_set_kernel_name(); + + if (dcfg && dcfg->init) + dcfg->init(priv); + + reg = regulator_get_name("bcm2835_usb"); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + regulator_enable(reg); + return 0; + +free_priv: + kfree(priv); + return ret; } -late_initcall(rpi_devices_init); + +static const struct rpi_machine_data rpi_1_ids[] = { + { + .hw_id = BCM2835_BOARD_REV_A_7, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_A_8, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_A_9, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_A, + }, { + .hw_id = BCM2835_BOARD_REV_A_PLUS_12, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_A_PLUS_15, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_A_PLUS, + }, { + .hw_id = BCM2835_BOARD_REV_B_I2C1_4, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_B_I2C1_5, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_B_I2C1_6, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_B, + }, { + .hw_id = BCM2835_BOARD_REV_B_I2C0_2, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_B_I2C0_3, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_B_REV2_d, + .flags = RPI_OLD_SCHEMA, + .init = rpi_b_init, + }, { + .hw_id = BCM2835_BOARD_REV_B_REV2_e, + .flags = RPI_OLD_SCHEMA, + .init = rpi_b_init, + }, { + .hw_id = BCM2835_BOARD_REV_B_REV2_f, + .flags = RPI_OLD_SCHEMA, + .init = rpi_b_init, + }, { + .hw_id = BCM2835_BOARD_REV_B_PLUS_10, + .flags = RPI_OLD_SCHEMA, + .init = rpi_b_plus_init, + }, { + .hw_id = BCM2835_BOARD_REV_B_PLUS_13, + .flags = RPI_OLD_SCHEMA, + .init = rpi_b_plus_init, + }, { + .hw_id = BCM2835_BOARD_REV_B_PLUS, + .init = rpi_b_plus_init, + }, { + .hw_id = BCM2835_BOARD_REV_CM_11, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_CM_14, + .flags = RPI_OLD_SCHEMA, + }, { + .hw_id = BCM2835_BOARD_REV_CM1, + }, { + .hw_id = BCM2835_BOARD_REV_ZERO, + .init = rpi_0_init, + }, { + .hw_id = BCM2835_BOARD_REV_ZERO_W, + .init = rpi_0_w_init, + }, { + .hw_id = U8_MAX + }, +}; + +static const struct rpi_machine_data rpi_2_ids[] = { + { + .hw_id = BCM2836_BOARD_REV_2_B, + .init = rpi_b_plus_init, + }, { + .hw_id = U8_MAX + }, +}; + +static const struct rpi_machine_data rpi_3_ids[] = { + { + .hw_id = BCM2837B0_BOARD_REV_3A_PLUS, + .init = rpi_b_plus_init, + }, { + .hw_id = BCM2837_BOARD_REV_3_B, + .init = rpi_b_init, + }, { + .hw_id = BCM2837B0_BOARD_REV_3B_PLUS, + .init = rpi_b_plus_init, + }, { + .hw_id = BCM2837_BOARD_REV_CM3, + .init = rpi_eth_init, + }, { + .hw_id = BCM2837B0_BOARD_REV_CM3_PLUS, + }, { + .hw_id = BCM2837B0_BOARD_REV_ZERO_2, + }, { + .hw_id = U8_MAX + }, +}; + +static const struct rpi_machine_data rpi_4_ids[] = { + { + .hw_id = BCM2711_BOARD_REV_4_B, + .init = rpi_eth_init, + }, { + .hw_id = BCM2711_BOARD_REV_400, + .init = rpi_eth_init, + }, { + .hw_id = BCM2711_BOARD_REV_CM4, + .init = rpi_eth_init, + }, { + .hw_id = BCM2711_BOARD_REV_CM4_S, + .init = rpi_eth_init, + }, { + .hw_id = U8_MAX + }, +}; + +static const struct of_device_id rpi_of_match[] = { + /* BCM2835 based Boards */ + { .compatible = "raspberrypi,model-a", .data = rpi_1_ids }, + { .compatible = "raspberrypi,model-a-plus", .data = rpi_1_ids }, + { .compatible = "raspberrypi,model-b", .data = rpi_1_ids }, + /* Raspberry Pi Model B (no P5) */ + { .compatible = "raspberrypi,model-b-i2c0", .data = rpi_1_ids }, + { .compatible = "raspberrypi,model-b-rev2", .data = rpi_1_ids }, + { .compatible = "raspberrypi,model-b-plus", .data = rpi_1_ids }, + { .compatible = "raspberrypi,compute-module", .data = rpi_1_ids }, + { .compatible = "raspberrypi,model-zero", .data = rpi_1_ids }, + { .compatible = "raspberrypi,model-zero-w", .data = rpi_1_ids }, + + /* BCM2836 based Boards */ + { .compatible = "raspberrypi,2-model-b", .data = rpi_2_ids }, + + /* BCM2837 based Boards */ + { .compatible = "raspberrypi,3-model-a-plus", .data = rpi_3_ids }, + { .compatible = "raspberrypi,3-model-b", .data = rpi_3_ids }, + { .compatible = "raspberrypi,3-model-b-plus", .data = rpi_3_ids }, + { .compatible = "raspberrypi,model-zero-2-w", .data = rpi_3_ids }, + { .compatible = "raspberrypi,3-compute-module", .data = rpi_3_ids }, + { .compatible = "raspberrypi,3-compute-module-lite", .data = rpi_3_ids }, + + /* BCM2711 based Boards */ + { .compatible = "raspberrypi,4-model-b", .data = rpi_4_ids }, + { .compatible = "raspberrypi,4-compute-module", .data = rpi_4_ids }, + { .compatible = "raspberrypi,4-compute-module-s", .data = rpi_4_ids }, + { .compatible = "raspberrypi,400", .data = rpi_4_ids }, + + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(rpi_of_match); + +static struct driver rpi_board_driver = { + .name = "board-rpi", + .probe = rpi_devices_probe, + .of_compatible = DRV_OF_COMPAT(rpi_of_match), +}; +late_platform_driver(rpi_board_driver); diff --git a/arch/arm/boards/raspberry-pi/rpi.h b/arch/arm/boards/raspberry-pi/rpi.h deleted file mode 100644 index b2a0401bd0..0000000000 --- a/arch/arm/boards/raspberry-pi/rpi.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __ARCH_ARM_BOARDS_RPI_H__ -#define __ARCH_ARM_BOARDS_RPI_H__ - -#include <types.h> -#include <led.h> - -#include <mach/mbox.h> - -#define RPI_MODEL(_id, _name, _init) \ - [_id] = { \ - .name = _name,\ - .init = _init,\ - } - -struct rpi_model { - const char *name; - void (*init)(void); -}; - -extern struct gpio_led rpi_leds[]; - -void rpi_set_usbethaddr(void); - -#endif /* __ARCH_ARM_BOARDS_RPI_H__ */ diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile index 092c31d6b2..5678718188 100644 --- a/arch/arm/boards/reflex-achilles/Makefile +++ b/arch/arm/boards/reflex-achilles/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o diff --git a/arch/arm/boards/reflex-achilles/board.c b/arch/arm/boards/reflex-achilles/board.c index 2b8186e19f..96da18f22e 100644 --- a/arch/arm/boards/reflex-achilles/board.c +++ b/arch/arm/boards/reflex-achilles/board.c @@ -1,7 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <io.h> #include <bbu.h> +#include <mach/socfpga/arria10-system-manager.h> static int achilles_init(void) { @@ -12,7 +15,7 @@ static int achilles_init(void) if (!of_machine_is_compatible("reflex,achilles")) return 0; - pbl_index = readl(0xFFD06210); + pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD); pr_debug("Current barebox instance %d\n", pbl_index); diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index f910b67d5f..12ead6d6dd 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -8,34 +10,39 @@ #include <asm/unaligned.h> #include <debug_ll.h> #include <pbl.h> -#include <mach/arria10-sdram.h> -#include <mach/arria10-regs.h> -#include <mach/arria10-reset-manager.h> -#include <mach/arria10-clock-manager.h> -#include <mach/arria10-pinmux.h> -#include <mach/arria10-fpga.h> +#include <mach/socfpga/arria10-sdram.h> +#include <mach/socfpga/arria10-regs.h> +#include <mach/socfpga/arria10-reset-manager.h> +#include <mach/socfpga/arria10-clock-manager.h> +#include <mach/socfpga/arria10-pinmux.h> +#include <mach/socfpga/arria10-fpga.h> +#include <mach/socfpga/init.h> #include "pll-config-arria10.c" #include "pinmux-config-arria10.c" -#include <mach/generic.h> +#include <mach/socfpga/generic.h> #define BAREBOX_PART 0 #define BITSTREAM_PART 1 #define BAREBOX1_OFFSET SZ_1M -#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K -#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K -#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_512K) +#define BAREBOX3_OFFSET (BAREBOX2_OFFSET + SZ_512K) +#define BAREBOX4_OFFSET (BAREBOX3_OFFSET + SZ_512K) +// Offset from the start of the second partition on the eMMC. #define BITSTREAM1_OFFSET 0x0 -#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) + +extern char __dtb_z_socfpga_arria10_achilles_start[]; -extern char __dtb_socfpga_arria10_achilles_start[]; +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) -static noinline void achilles_start(void) +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2) { int pbl_index = 0; int barebox = 0; int bitstream = 0; - arm_early_mmu_cache_invalidate(); + arm_cpu_lowlevel_init(); + arria10_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -74,31 +81,21 @@ static noinline void achilles_start(void) arria10_start_image(barebox); } -ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2) -{ - arm_cpu_lowlevel_init(); - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - achilles_start(); -} - ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2) { void *fdt; - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } -ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) +ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r1, r2) { void *fdt; arm_cpu_lowlevel_init(); - - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); - - arm_early_mmu_cache_invalidate(); + arria10_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); @@ -112,7 +109,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arria10_ddr_calibration_sequence(); - fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset(); + fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset(); barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt); } diff --git a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c index b6a72304b6..aa65770fdd 100644 --- a/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c +++ b/arch/arm/boards/reflex-achilles/pinmux-config-arria10.c @@ -1,4 +1,6 @@ -#include <mach/arria10-pinmux.h> +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/socfpga/arria10-pinmux.h> static uint32_t pinmux[] = { [arria10_pinmux_shared_io_q4_12] = 8, diff --git a/arch/arm/boards/reflex-achilles/pll-config-arria10.c b/arch/arm/boards/reflex-achilles/pll-config-arria10.c index 9da41ecdf2..35d475bcfb 100644 --- a/arch/arm/boards/reflex-achilles/pll-config-arria10.c +++ b/arch/arm/boards/reflex-achilles/pll-config-arria10.c @@ -1,4 +1,6 @@ -#include <mach/arria10-clock-manager.h> +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/socfpga/arria10-clock-manager.h> static struct arria10_mainpll_cfg mainpll_cfg = { .cntr15clk_cnt = 900, diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/.gitignore b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/stm32mp157c-dk2/Makefile b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/Makefile index 092c31d6b2..01c7a259e9 100644 --- a/arch/arm/boards/stm32mp157c-dk2/Makefile +++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/Makefile @@ -1,2 +1,2 @@ -lwl-y += lowlevel.o obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c new file mode 100644 index 0000000000..7178c02d8f --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "rk3568-r2pro: " fmt + +#include <common.h> +#include <init.h> +#include <mach/rockchip/bbu.h> +#include <aiodev.h> +#include <bootsource.h> +#include <environment.h> +#include <globalvar.h> +#include <magicvar.h> +#include <deep-probe.h> + +static bool machine_is_bpi_r2pro = false; + +static int rk3568_bpi_r2pro_probe(struct device *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + + barebox_set_model("BPI R2PRO"); + barebox_set_hostname("bpi-r2pro"); + machine_is_bpi_r2pro = true; + + if (bootsource == BOOTSOURCE_MMC && instance == 0) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rockchip_bbu_mmc_register("sd", 0, "/dev/mmc0"); + rockchip_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc1"); + + return 0; +} + +static const struct of_device_id rk3568_bpi_r2pro_of_match[] = { + { .compatible = "rockchip,rk3568-bpi-r2pro" }, + { /* Sentinel */}, +}; + +static struct driver rk3568_bpi_r2pro_board_driver = { + .name = "board-rk3568-bpi-r2pro", + .probe = rk3568_bpi_r2pro_probe, + .of_compatible = rk3568_bpi_r2pro_of_match, +}; +coredevice_platform_driver(rk3568_bpi_r2pro_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rk3568_bpi_r2pro_of_match); + +static int rk3568_bpi_r2pro_detect_hwid(void) +{ + int ret; + int hwid_voltage; + struct aiochannel *hwid_chan; + char *hwid; + + if (!IS_ENABLED(CONFIG_AIODEV)) + return 0; + + if (!machine_is_bpi_r2pro) + return 0; + + hwid_chan = aiochannel_by_name("aiodev0.in_value1_mV"); + if (IS_ERR(hwid_chan)) { + ret = PTR_ERR(hwid_chan); + goto err_hwid; + } + + ret = aiochannel_get_value(hwid_chan, &hwid_voltage); + if (ret) + goto err_hwid; + + pr_info("hwid_voltage: %d\n", hwid_voltage); + + if (hwid_voltage == 1800) + hwid = "V00"; + else + hwid = "unknown"; + + pr_info("Detected RK3568 BananaPi R2 Pro %s\n", hwid); + + globalvar_add_simple("board.hwid", hwid); + + return 0; + +err_hwid: + pr_err("couldn't retrieve hardware ID\n"); + return ret; +} +late_initcall(rk3568_bpi_r2pro_detect_hwid); + +BAREBOX_MAGICVAR(global.board.hwid, "The board hardware ID"); diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c new file mode 100644 index 0000000000..12c2445287 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> +#include <mach/rockchip/rockchip.h> + +extern char __dtb_rk3568_bpi_r2_pro_start[]; + +ENTRY_FUNCTION(start_rk3568_bpi_r2pro, r0, r1, r2) +{ + putc_ll('>'); + + /* + * set iodomain vccio6 to 1.8V needed for GMAC1 to work. + * vccio4 (gmac0/switch) needs to stay at 3v3 (default) + * FIXME: This is done by the io-domain driver as well, but there + * currently is no mechanism to make sure the driver gets probed + * before its consumers. Remove this setup once this issue is + * resolved. + */ + //set bit 6 in PMU_GRF_IO_VSEL0 for vccio6 1v8 + writel(RK_SETBITS(BIT(6)), PMU_GRF_IO_VSEL0); + //clear bit 6 for 3v3 as it was set to 1v8 + writel(RK_CLRBITS(BIT(6)), PMU_GRF_IO_VSEL1); + + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3568_bpi_r2_pro_start); +} diff --git a/arch/arm/boards/rockchip-rk3568-evb/.gitignore b/arch/arm/boards/rockchip-rk3568-evb/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/rockchip-rk3568-evb/Makefile b/arch/arm/boards/rockchip-rk3568-evb/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/rockchip-rk3568-evb/board.c b/arch/arm/boards/rockchip-rk3568-evb/board.c new file mode 100644 index 0000000000..9659bd69c5 --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/board.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "rk3568-evb: " fmt + +#include <common.h> +#include <init.h> +#include <mach/rockchip/bbu.h> +#include <aiodev.h> +#include <bootsource.h> +#include <environment.h> +#include <globalvar.h> +#include <magicvar.h> +#include <deep-probe.h> + +static bool machine_is_rk3568_evb = false; + +static int rk3568_evb_probe(struct device *dev) +{ + enum bootsource bootsource = bootsource_get(); + int instance = bootsource_get_instance(); + + barebox_set_model("Rockchip RK3568 EVB"); + barebox_set_hostname("rk3568-evb"); + machine_is_rk3568_evb = true; + + if (bootsource == BOOTSOURCE_MMC && instance == 0) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + rockchip_bbu_mmc_register("sd", 0, "/dev/mmc0"); + rockchip_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc1"); + + return 0; +} + +static const struct of_device_id rk3568_evb_of_match[] = { + { .compatible = "rockchip,rk3568-evb1-v10" }, + { /* Sentinel */}, +}; + +static struct driver rk3568_evb_board_driver = { + .name = "board-rk3568-evb", + .probe = rk3568_evb_probe, + .of_compatible = rk3568_evb_of_match, +}; +coredevice_platform_driver(rk3568_evb_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(rk3568_evb_of_match); + +static int rk3568_evb_detect_hwid(void) +{ + int ret; + int evb_hwid_voltage; + struct aiochannel *evb_hwid_chan; + char *evb_hwid; + + if (!IS_ENABLED(CONFIG_AIODEV)) + return 0; + + if (!machine_is_rk3568_evb) + return 0; + + evb_hwid_chan = aiochannel_by_name("aiodev0.in_value1_mV"); + if (IS_ERR(evb_hwid_chan)) { + ret = PTR_ERR(evb_hwid_chan); + goto err_hwid; + } + + ret = aiochannel_get_value(evb_hwid_chan, &evb_hwid_voltage); + if (ret) + goto err_hwid; + + if (evb_hwid_voltage > 1650) { + evb_hwid = "1"; + } else if (evb_hwid_voltage > 1350) { + evb_hwid = "2"; + } else if (evb_hwid_voltage > 1050) { + evb_hwid = "3"; + } else if (evb_hwid_voltage > 750) { + evb_hwid = "4"; + } else if (evb_hwid_voltage > 450) { + evb_hwid = "5"; + } else if (evb_hwid_voltage > 150) { + evb_hwid = "6"; + } else { + evb_hwid = "7"; + } + pr_info("Detected RK3568 EVB%s\n", evb_hwid); + + globalvar_add_simple("board.hwid", evb_hwid); + + return 0; + +err_hwid: + pr_err("couldn't retrieve hardware ID\n"); + return ret; +} +late_initcall(rk3568_evb_detect_hwid); + +BAREBOX_MAGICVAR(global.board.hwid, "The board hardware ID"); diff --git a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c new file mode 100644 index 0000000000..d5ae70049e --- /dev/null +++ b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> + +extern char __dtb_rk3568_evb1_v10_start[]; + +ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2) +{ + /* + * Enable vccio4 1.8V and vccio6 1.8V + * Needed for GMAC to work. + * FIXME: This is done by the io-domain driver as well, but there + * currently is no mechanism to make sure the driver gets probed + * before its consumers. Remove this setup once this issue is + * resolved. + */ + writel(RK_SETBITS(0x50), 0xfdc20140); + + putc_ll('>'); + + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3568_evb1_v10_start); +} diff --git a/arch/arm/boards/sama5d27-giantboard/Makefile b/arch/arm/boards/sama5d27-giantboard/Makefile new file mode 100644 index 0000000000..e2c6a3adf6 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-giantboard diff --git a/arch/arm/boards/sama5d27-giantboard/board.c b/arch/arm/boards/sama5d27-giantboard/board.c new file mode 100644 index 0000000000..006c6ffad5 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/board.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <init.h> +#include <envfs.h> +#include <bbu.h> +#include <of.h> + +static int giantboard_device_init(void) +{ + if (!of_machine_is_compatible("groboards,sama5d27-giantboard")) + return 0; + + bbu_register_std_file_update("microSD", BBU_HANDLER_FLAG_DEFAULT, + "/mnt/mmc1.0/barebox.bin", + filetype_arm_barebox); + + defaultenv_append_directory(defaultenv_giantboard); + + return 0; +} +device_initcall(giantboard_device_init); diff --git a/arch/arm/boards/sama5d27-giantboard/defaultenv-giantboard/nv/boot.default b/arch/arm/boards/sama5d27-giantboard/defaultenv-giantboard/nv/boot.default new file mode 100644 index 0000000000..646f435652 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/defaultenv-giantboard/nv/boot.default @@ -0,0 +1 @@ +mmc1 diff --git a/arch/arm/boards/sama5d27-giantboard/lowlevel.c b/arch/arm/boards/sama5d27-giantboard/lowlevel.c new file mode 100644 index 0000000000..49540bede0 --- /dev/null +++ b/arch/arm/boards/sama5d27-giantboard/lowlevel.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Ahmad Fatoum, Pengutronix + */ + +#include <common.h> +#include <init.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/sama5d2_ll.h> +#include <mach/at91/xload.h> +#include <mach/at91/sama5d2-sip-ddramc.h> +#include <mach/at91/iomux.h> +#include <debug_ll.h> + +/* PCK = 492MHz, MCK = 164MHz */ +#define MASTER_CLOCK 164000000 + +SAMA5D2_ENTRY_FUNCTION(start_sama5d27_giantboard_xload_mmc, r4) +{ + void __iomem *dbgu_base; + + sama5d2_lowlevel_init(); + + dbgu_base = sama5d2_resetup_uart_console(MASTER_CLOCK); + putc_ll('>'); + + relocate_to_current_adr(); + setup_c(); + + pbl_set_putc(at91_dbgu_putc, dbgu_base); + + sama5d2_udelay_init(MASTER_CLOCK); + sama5d2_d1g_ddrconf(); + sama5d2_sdhci_start_image(r4); +} + +extern char __dtb_z_at91_sama5d27_giantboard_start[]; + +SAMA5D2_ENTRY_FUNCTION(start_sama5d27_giantboard, r4) +{ + void *fdt; + + putc_ll('>'); + + fdt = __dtb_z_at91_sama5d27_giantboard_start + get_runtime_offset(); + + sama5d2_barebox_entry(r4, fdt); +} diff --git a/arch/arm/boards/sama5d27-som1/Makefile b/arch/arm/boards/sama5d27-som1/Makefile index b08c4a93ca..96cd8f520f 100644 --- a/arch/arm/boards/sama5d27-som1/Makefile +++ b/arch/arm/boards/sama5d27-som1/Makefile @@ -1 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o +obj-y += board.o +bbenv-$(CONFIG_DEFAULT_ENVIRONMENT) += defaultenv-sama5d27-som1 diff --git a/arch/arm/boards/sama5d27-som1/board.c b/arch/arm/boards/sama5d27-som1/board.c new file mode 100644 index 0000000000..6fa903bca4 --- /dev/null +++ b/arch/arm/boards/sama5d27-som1/board.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <bbu.h> +#include <envfs.h> +#include <bootsource.h> +#include <of.h> + +static int ek_device_init(void) +{ + int flags_sd = 0, flags_usd = 0; + if (!of_machine_is_compatible("atmel,sama5d27-som1-ek")) + return 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 0) { + flags_sd = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-sd"); + } else { + flags_usd = BBU_HANDLER_FLAG_DEFAULT; + of_device_enable_path("/chosen/environment-microsd"); + } + } else { + of_device_enable_path("/chosen/environment-qspi"); + } + + bbu_register_std_file_update("SD", flags_sd, "/mnt/mmc0.0/barebox.bin", + filetype_arm_barebox); + bbu_register_std_file_update("microSD", flags_usd, "/mnt/mmc1.0/barebox.bin", + filetype_arm_barebox); + + defaultenv_append_directory(defaultenv_sama5d27_som1); + + return 0; +} +device_initcall(ek_device_init); diff --git a/arch/arm/boards/sama5d27-som1/defaultenv-sama5d27-som1/nv/dev.wdog0.autoping b/arch/arm/boards/sama5d27-som1/defaultenv-sama5d27-som1/nv/dev.wdog0.autoping new file mode 100644 index 0000000000..d00491fd7e --- /dev/null +++ b/arch/arm/boards/sama5d27-som1/defaultenv-sama5d27-som1/nv/dev.wdog0.autoping @@ -0,0 +1 @@ +1 diff --git a/arch/arm/boards/sama5d27-som1/lowlevel.c b/arch/arm/boards/sama5d27-som1/lowlevel.c index 7df5a4772d..67300587fe 100644 --- a/arch/arm/boards/sama5d27-som1/lowlevel.c +++ b/arch/arm/boards/sama5d27-som1/lowlevel.c @@ -5,15 +5,12 @@ #include <common.h> #include <init.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/at91_pmc_ll.h> - -#include <mach/hardware.h> -#include <mach/iomux.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/sama5d2_ll.h> +#include <mach/at91/iomux.h> +#include <mach/at91/xload.h> #include <debug_ll.h> -#include <mach/at91_dbgu.h> +#include <mach/at91/sama5d2-sip-ddramc.h> #define RGB_LED_GREEN (1 << 0) #define RGB_LED_RED (1 << 1) @@ -22,13 +19,10 @@ /* PCK = 492MHz, MCK = 164MHz */ #define MASTER_CLOCK 164000000 -#define sama5d2_pmc_enable_periph_clock(clk) \ - at91_pmc_sam9x5_enable_periph_clock(IOMEM(SAMA5D2_BASE_PMC), clk) - static void ek_turn_led(unsigned color) { struct { - unsigned long pio; + void __iomem *pio; unsigned bit; unsigned color; } *led, leds[] = { @@ -39,43 +33,41 @@ static void ek_turn_led(unsigned color) }; for (led = leds; led->pio; led++) { - at91_mux_gpio4_enable(IOMEM(led->pio), BIT(led->bit)); - at91_mux_gpio4_input(IOMEM(led->pio), BIT(led->bit), false); - at91_mux_gpio4_set(IOMEM(led->pio), BIT(led->bit), led->color); + at91_mux_gpio4_enable(led->pio, BIT(led->bit)); + at91_mux_gpio4_input(led->pio, BIT(led->bit), false); + at91_mux_gpio4_set(led->pio, BIT(led->bit), led->color); } } -static void ek_dbgu_init(void) +SAMA5D2_ENTRY_FUNCTION(start_sama5d27_som1_ek_xload_mmc, r4) { - unsigned mck = MASTER_CLOCK / 2; + void __iomem *dbgu_base; + sama5d2_lowlevel_init(); - sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOD); - - at91_mux_pio4_set_A_periph(IOMEM(SAMA5D2_BASE_PIOD), - pin_to_mask(AT91_PIN_PD3)); /* DBGU TXD */ + dbgu_base = sama5d2_resetup_uart_console(MASTER_CLOCK); + putc_ll('>'); - sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_UART1); + relocate_to_current_adr(); + setup_c(); - at91_dbgu_setup_ll(IOMEM(SAMA5D2_BASE_UART1), mck, 115200); + pbl_set_putc(at91_dbgu_putc, dbgu_base); - putc_ll('>'); + ek_turn_led(RGB_LED_RED | RGB_LED_GREEN); /* Yellow */ + sama5d2_udelay_init(MASTER_CLOCK); + sama5d2_d1g_ddrconf(); + sama5d2_sdhci_start_image(r4); } extern char __dtb_z_at91_sama5d27_som1_ek_start[]; -ENTRY_FUNCTION(start_sama5d27_som1_ek, r0, r1, r2) +SAMA5D2_ENTRY_FUNCTION(start_sama5d27_som1_ek, r4) { void *fdt; - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D2_SRAM_BASE + SAMA5D2_SRAM_SIZE - 16); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - ek_dbgu_init(); + putc_ll('>'); fdt = __dtb_z_at91_sama5d27_som1_ek_start + get_runtime_offset(); ek_turn_led(RGB_LED_GREEN); - barebox_arm_entry(SAMA5_DDRCS, SZ_128M, fdt); + sama5d2_barebox_entry(r4, fdt); } diff --git a/arch/arm/boards/sama5d3_xplained/Makefile b/arch/arm/boards/sama5d3_xplained/Makefile index fc6d83be8c..b7d6b2e7fa 100644 --- a/arch/arm/boards/sama5d3_xplained/Makefile +++ b/arch/arm/boards/sama5d3_xplained/Makefile @@ -1,3 +1,5 @@ -obj-y += init.o +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o lwl-y += lowlevel.o bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-sama5d3_xplained diff --git a/arch/arm/boards/sama5d3_xplained/board.c b/arch/arm/boards/sama5d3_xplained/board.c new file mode 100644 index 0000000000..4d908e6b9f --- /dev/null +++ b/arch/arm/boards/sama5d3_xplained/board.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include <common.h> +#include <init.h> +#include <envfs.h> +#include <mach/at91/at91sam9_smc.h> +#include <mach/at91/hardware.h> +#include <linux/clk.h> + +static struct sam9_smc_config sama5d3_xplained_nand_smc_config = { + .ncs_read_setup = 1, + .nrd_setup = 2, + .ncs_write_setup = 1, + .nwe_setup = 2, + + .ncs_read_pulse = 5, + .nrd_pulse = 3, + .ncs_write_pulse = 5, + .nwe_pulse = 3, + + .read_cycle = 8, + .write_cycle = 8, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, + .tdf_cycles = 3, + + .tclr = 3, + .tadl = 10, + .tar = 3, + .ocms = 0, + .trr = 4, + .twb = 5, + .rbnsel = 3, + .nfsel = 1 +}; + +static int sama5d3_xplained_probe(struct device *dev) +{ + struct clk *clk; + + barebox_set_hostname("sama5d3_xplained"); + + if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) + defaultenv_append_directory(defaultenv_sama5d3_xplained); + + add_generic_device("at91sam9-smc", DEVICE_ID_SINGLE, NULL, + SAMA5D3_BASE_HSMC + 0x600, 0xa0, + IORESOURCE_MEM, NULL); + + clk = clk_lookup("hsmc_clk"); + if (IS_ERR(clk)) + dev_warn(dev, "couldn't get hsmc_clk: %pe\n", clk); + + clk_enable(clk); + + /* configure chip-select 3 (NAND) */ + sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config); + + return 0; +} + +static const struct of_device_id sama5d3_xplained_of_match[] = { + { .compatible = "atmel,sama5d3-xplained" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, sama5d3_xplained_of_match); + +static struct driver sama5d3_xplained_board_driver = { + .name = "board-sama5d3_xplained", + .probe = sama5d3_xplained_probe, + .of_compatible = sama5d3_xplained_of_match, +}; +coredevice_platform_driver(sama5d3_xplained_board_driver); diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c deleted file mode 100644 index 2433e25f16..0000000000 --- a/arch/arm/boards/sama5d3_xplained/init.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (C) 2014 Bo Shen <voice.shen@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <fs.h> -#include <fcntl.h> -#include <io.h> -#include <envfs.h> -#include <mach/hardware.h> -#include <nand.h> -#include <linux/sizes.h> -#include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> -#include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9x5_matrix.h> -#include <readkey.h> -#include <poller.h> -#include <linux/clk.h> -#include <linux/phy.h> -#include <linux/micrel_phy.h> - -#if defined(CONFIG_NAND_ATMEL) -static struct atmel_nand_data nand_pdata = { - .ale = 21, - .cle = 22, - .det_pin = -EINVAL, - .rdy_pin = -EINVAL, - .enable_pin = -EINVAL, - .ecc_mode = NAND_ECC_HW, - .has_pmecc = 1, - .pmecc_sector_size = 512, - .pmecc_corr_cap = 4, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#endif - .on_flash_bbt = 1, -}; - -static struct sam9_smc_config sama5d3_xplained_nand_smc_config = { - .ncs_read_setup = 1, - .nrd_setup = 2, - .ncs_write_setup = 1, - .nwe_setup = 2, - - .ncs_read_pulse = 5, - .nrd_pulse = 3, - .ncs_write_pulse = 5, - .nwe_pulse = 3, - - .read_cycle = 8, - .write_cycle = 8, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 3, - - .tclr = 3, - .tadl = 10, - .tar = 3, - .ocms = 0, - .trr = 4, - .twb = 5, - .rbnsel = 3, - .nfsel = 1 -}; - -static void ek_add_device_nand(void) -{ - struct clk *clk = clk_get(NULL, "smc_clk"); - - clk_enable(clk); - - /* setup bus-width (8 or 16) */ - if (nand_pdata.bus_width_16) - sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16; - else - sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8; - - /* configure chip-select 3 (NAND) */ - sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config); - - at91_add_device_nand(&nand_pdata); -} -#else -static void ek_add_device_nand(void) {} -#endif - -#if defined(CONFIG_DRIVER_NET_MACB) -static struct macb_platform_data gmac_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RGMII, - .phy_addr = 7, -}; - -static struct macb_platform_data macb_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RMII, - .phy_addr = 0, -}; - -static void ek_add_device_eth(void) -{ - at91_add_device_eth(0, &gmac_pdata); - at91_add_device_eth(1, &macb_pdata); -} -#else -static void ek_add_device_eth(void) {} -#endif - -#if defined(CONFIG_MCI_ATMEL) -/* - * MCI (SD/MMC) - */ -static struct atmel_mci_platform_data mci0_data = { - .bus_width = 8, - .detect_pin = AT91_PIN_PE0, - .wp_pin = -EINVAL, -}; - -static void ek_add_device_mci(void) -{ - /* MMC0 */ - at91_add_device_mci(0, &mci0_data); -} -#else -static void ek_add_device_mci(void) {} -#endif - -#ifdef CONFIG_LED_GPIO -struct gpio_led leds[] = { - { - .gpio = AT91_PIN_PE23, - .active_low = 1, - .led = { - .name = "d2", - }, - }, { - .gpio = AT91_PIN_PE24, - .active_low = 1, - .led = { - .name = "d3", - }, - }, -}; - -static void ek_add_led(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(leds); i++) { - at91_set_gpio_output(leds[i].gpio, leds[i].active_low); - led_gpio_register(&leds[i]); - } - led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); -} -#else -static void ek_add_led(void) {} -#endif - -static int sama5d3_xplained_mem_init(void) -{ - at91_add_device_sdram(0); - - return 0; -} -mem_initcall(sama5d3_xplained_mem_init); - -static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = { - { - .offset = 0x00000, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "at91bootstrap_raw", - .bbname = "at91bootstrap", - }, { - .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */ - .size = SZ_256K + SZ_128K, - .flags = DEVFS_PARTITION_FIXED, - .name = "self_raw", - .bbname = "self0", - }, - /* hole of 128 KiB */ - { - .offset = SZ_512K + SZ_256K, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw", - .bbname = "env0", - }, { - .offset = DEVFS_PARTITION_APPEND, /* 1 MiB */ - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw1", - .bbname = "env1", - }, { - /* sentinel */ - } -}; - -static int sama5d3_xplained_devices_init(void) -{ - ek_add_device_nand(); - ek_add_led(); - ek_add_device_eth(); - ek_add_device_mci(); - - devfs_create_partitions("nand0", sama5d3_xplained_nand0_partitions); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_sama5d3_xplained); - - return 0; -} -device_initcall(sama5d3_xplained_devices_init); - -static int sama5d3_xplained_console_init(void) -{ - barebox_set_model("Atmel sama5d3_xplained"); - barebox_set_hostname("sama5d3_xplained"); - - at91_register_uart(0, 0); - - return 0; -} -console_initcall(sama5d3_xplained_console_init); - -static int sama5d3_xplained_main_clock(void) -{ - at91_set_main_clock(12000000); - - return 0; -} -pure_initcall(sama5d3_xplained_main_clock); diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index 8653c48c69..d66b10fa8f 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -1,23 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause /* - * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 + * Copyright (C) 2014, Atmel Corporation + * Copyright (C) 2018 Ahmad Fatoum, Pengutronix */ #include <common.h> #include <init.h> #include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/iomux.h> +#include <mach/at91/sama5d3.h> +#include <mach/at91/sama5d3-xplained-ddramc.h> +#include <mach/at91/xload.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> +/* PCK = 528MHz, MCK = 132MHz */ +#define MASTER_CLOCK 132000000 -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +static void dbgu_init(void) { - arm_cpu_lowlevel_init(); + void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB); - barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); + at91_mux_pio3_pin(pio, pin_to_mask(AT91_PIN_PB31), AT91_MUX_PERIPH_A, 0); + + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU); + at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), MASTER_CLOCK, 115200); + + putc_ll('>'); + pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1)); +} + +SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained_xload_mmc, r4) +{ + sama5d3_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + dbgu_init(); + + sama5d3_udelay_init(MASTER_CLOCK); + sama5d3_xplained_ddrconf(); + + sama5d3_atmci_start_image(0, MASTER_CLOCK, 0); +} + +extern char __dtb_z_at91_sama5d3_xplained_start[]; + +SAMA5D3_ENTRY_FUNCTION(start_sama5d3_xplained, r4) +{ + void *fdt; + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + dbgu_init(); + + fdt = __dtb_z_at91_sama5d3_xplained_start + get_runtime_offset(); + + barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt); } diff --git a/arch/arm/boards/sama5d3xek/Makefile b/arch/arm/boards/sama5d3xek/Makefile index 6ed914fc0a..9691f07917 100644 --- a/arch/arm/boards/sama5d3xek/Makefile +++ b/arch/arm/boards/sama5d3xek/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o obj-$(CONFIG_W1) += hw_version.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c index e5077854e3..c64d4566c6 100644 --- a/arch/arm/boards/sama5d3xek/hw_version.c +++ b/arch/arm/boards/sama5d3xek/hw_version.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <fs.h> @@ -164,7 +151,7 @@ static void at91sama5d3xek_devices_detect_one(const char *name) struct one_wire_info info; struct board_info* binfo; struct vendor_info* vinfo; - struct device_d *dev = NULL; + struct device *dev = NULL; char str[16]; char *bname, *vname; u8 vendor_id = 0; diff --git a/arch/arm/boards/sama5d3xek/hw_version.h b/arch/arm/boards/sama5d3xek/hw_version.h index ed9ea88d42..d90c751629 100644 --- a/arch/arm/boards/sama5d3xek/hw_version.h +++ b/arch/arm/boards/sama5d3xek/hw_version.h @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #ifndef __HW_REVISION_H__ #define __HW_REVISION_H__ diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c index c768e98d26..b75856198e 100644 --- a/arch/arm/boards/sama5d3xek/init.c +++ b/arch/arm/boards/sama5d3xek/init.c @@ -1,41 +1,28 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9x5_matrix.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9x5_matrix.h> #include <input/qt1070.h> #include <readkey.h> #include <poller.h> @@ -408,7 +395,7 @@ static void ek_add_device_hdmi(void) hdmi_reset_start = get_time_ns(); hdmi_poller.func = hdmi_off_poller; - poller_register(&hdmi_poller); + poller_register(&hdmi_poller, "hdmi-reset"); } #else static void ek_add_device_hdmi(void) diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c index 8653c48c69..fe5f172127 100644 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ b/arch/arm/boards/sama5d3xek/lowlevel.c @@ -10,8 +10,8 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { diff --git a/arch/arm/boards/sama5d4_wifx/Makefile b/arch/arm/boards/sama5d4_wifx/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/sama5d4_wifx/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/sama5d4_wifx/board.c b/arch/arm/boards/sama5d4_wifx/board.c new file mode 100644 index 0000000000..028bedcfb0 --- /dev/null +++ b/arch/arm/boards/sama5d4_wifx/board.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <deep-probe.h> +#include <bootsource.h> +#include <driver.h> +#include <init.h> +#include <bbu.h> +#include <of.h> + +static int wifx_l1_probe(struct device *dev) +{ + int flags_sd = 0; + + if (bootsource_get() == BOOTSOURCE_NAND) { + of_device_enable_path("/chosen/environment-nand"); + } else { + of_device_enable_path("/chosen/environment-microsd"); + flags_sd = BBU_HANDLER_FLAG_DEFAULT; + } + + bbu_register_std_file_update("sd", flags_sd, "/mnt/mmc1.0/barebox.bin", + filetype_arm_barebox); + + return 0; +} + +static const struct of_device_id wifx_l1_of_match[] = { + { .compatible = "wifx,l1" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(wifx_l1_of_match); + +static struct driver wifx_l1_board_driver = { + .name = "board-lxa-mc1", + .probe = wifx_l1_probe, + .of_compatible = wifx_l1_of_match, +}; +device_platform_driver(wifx_l1_board_driver); diff --git a/arch/arm/boards/sama5d4_wifx/lowlevel.c b/arch/arm/boards/sama5d4_wifx/lowlevel.c new file mode 100644 index 0000000000..c47b14c55b --- /dev/null +++ b/arch/arm/boards/sama5d4_wifx/lowlevel.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix + +#include <debug_ll.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/ddramc.h> + +SAMA5D4_ENTRY_FUNCTION(start_sama5d4_wifx_l1, r4) +{ + extern char __dtb_z_at91_sama5d4_wifx_l1_start[]; + void *fdt; + + putc_ll('>'); + + fdt = __dtb_z_at91_sama5d4_wifx_l1_start + get_runtime_offset(); + + sama5d4_barebox_entry(r4, fdt); +} diff --git a/arch/arm/boards/sama5d4_xplained/Makefile b/arch/arm/boards/sama5d4_xplained/Makefile index 8873dfc22c..eece4cc381 100644 --- a/arch/arm/boards/sama5d4_xplained/Makefile +++ b/arch/arm/boards/sama5d4_xplained/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += sama5d4_xplained.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c index 9a6a767e5f..183bd9c5a9 100644 --- a/arch/arm/boards/sama5d4_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c @@ -10,8 +10,8 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { diff --git a/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c b/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c index f5b885ce0d..c88f0d090a 100644 --- a/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c +++ b/arch/arm/boards/sama5d4_xplained/sama5d4_xplained.c @@ -12,21 +12,21 @@ #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <partition.h> #include <fs.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9x5_matrix.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9x5_matrix.h> #include <input/qt1070.h> #include <readkey.h> #include <spi/spi.h> diff --git a/arch/arm/boards/sama5d4ek/Makefile b/arch/arm/boards/sama5d4ek/Makefile index 152750bbe0..82ffe9771c 100644 --- a/arch/arm/boards/sama5d4ek/Makefile +++ b/arch/arm/boards/sama5d4ek/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += sama5d4ek.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c index 9a6a767e5f..183bd9c5a9 100644 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ b/arch/arm/boards/sama5d4ek/lowlevel.c @@ -10,8 +10,8 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/hardware.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/hardware.h> void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { diff --git a/arch/arm/boards/sama5d4ek/sama5d4ek.c b/arch/arm/boards/sama5d4ek/sama5d4ek.c index 790a063266..0dda34614a 100644 --- a/arch/arm/boards/sama5d4ek/sama5d4ek.c +++ b/arch/arm/boards/sama5d4ek/sama5d4ek.c @@ -12,21 +12,21 @@ #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <partition.h> #include <fs.h> #include <fcntl.h> #include <io.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9x5_matrix.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9x5_matrix.h> #include <input/qt1070.h> #include <readkey.h> #include <spi/spi.h> diff --git a/arch/arm/boards/scb9328/Makefile b/arch/arm/boards/scb9328/Makefile index 8e1c7ef7a5..5c13dddc06 100644 --- a/arch/arm/boards/scb9328/Makefile +++ b/arch/arm/boards/scb9328/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only lwl-y += lowlevel_init.o lowlevel.o obj-y += scb9328.o diff --git a/arch/arm/boards/scb9328/lowlevel.c b/arch/arm/boards/scb9328/lowlevel.c index a2057f0c6b..d8b0d1cf18 100644 --- a/arch/arm/boards/scb9328/lowlevel.c +++ b/arch/arm/boards/scb9328/lowlevel.c @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 #include <common.h> -#include <mach/imx1-regs.h> -#include <mach/iomux-v1.h> -#include <mach/iomux-mx1.h> +#include <mach/imx/imx1-regs.h> +#include <mach/imx/iomux-v1.h> +#include <mach/imx/iomux-mx1.h> #include <asm/barebox-arm.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> extern char __dtb_imx1_scb9328_start[]; diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index e20e3b92da..6c23d2cfea 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -1,18 +1,7 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2004 Sascha Hauer, Synertronixx GmbH -#include <mach/imx1-regs.h> +#include <mach/imx/imx1-regs.h> #include <asm/barebox-arm-head.h> #define CFG_MPCTL0_VAL 0x00321431 diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index d1f741a70e..c2475476fd 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -1,36 +1,24 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2004 Sascha Hauer, Synertronixx GmbH #include <common.h> #include <net.h> #include <init.h> #include <environment.h> -#include <generated/mach-types.h> -#include <mach/imx1-regs.h> +#include <asm/mach-types.h> +#include <mach/imx/imx1-regs.h> #include <asm/armlinux.h> -#include <mach/weim.h> +#include <mach/imx/weim.h> #include <io.h> -#include <partition.h> #include <fs.h> #include <envfs.h> -#include <mach/iomux-mx1.h> -#include <mach/devices-imx1.h> +#include <mach/imx/iomux-mx1.h> static int scb9328_devices_init(void) { + if (!of_machine_is_compatible("stx,scb9328")) + return 0; + /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR); diff --git a/arch/arm/boards/seeed-odyssey/Makefile b/arch/arm/boards/seeed-odyssey/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/seeed-odyssey/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/seeed-odyssey/board.c b/arch/arm/boards/seeed-odyssey/board.c new file mode 100644 index 0000000000..5befd32664 --- /dev/null +++ b/arch/arm/boards/seeed-odyssey/board.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <mach/stm32mp/bbu.h> +#include <bootsource.h> +#include <of.h> + +static int odyssey_som_probe(struct device *dev) +{ + int flags; + int instance = bootsource_get_instance(); + + flags = instance == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); + + flags = instance == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("emmc", "/dev/mmc1.ssbl", flags); + + + if (instance == 0) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + return 0; +} + +static const struct of_device_id odyssey_som_of_match[] = { + { .compatible = "seeed,stm32mp157c-odyssey-som" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, odyssey_som_of_match); + +static struct driver odyssey_som_driver = { + .name = "odyssey-som", + .probe = odyssey_som_probe, + .of_compatible = odyssey_som_of_match, +}; +device_platform_driver(odyssey_som_driver); diff --git a/arch/arm/boards/seeed-odyssey/lowlevel.c b/arch/arm/boards/seeed-odyssey/lowlevel.c new file mode 100644 index 0000000000..a0e6173d49 --- /dev/null +++ b/arch/arm/boards/seeed-odyssey/lowlevel.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/stm32mp/entry.h> +#include <debug_ll.h> + +extern char __dtb_z_stm32mp157c_odyssey_start[]; + +ENTRY_FUNCTION(start_stm32mp157c_seeed_odyssey, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + putc_ll('>'); + + fdt = __dtb_z_stm32mp157c_odyssey_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} diff --git a/arch/arm/boards/skov-arm9cpu/Makefile b/arch/arm/boards/skov-arm9cpu/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/skov-arm9cpu/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/skov-arm9cpu/board.c b/arch/arm/boards/skov-arm9cpu/board.c new file mode 100644 index 0000000000..20507922cb --- /dev/null +++ b/arch/arm/boards/skov-arm9cpu/board.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +// SPDX-FileCopyrightText: 2017 Sam Ravnborg <sam@ravnborg.org> + +#include <common.h> +#include <globalvar.h> +#include <magicvar.h> +#include <envfs.h> +#include <init.h> +#include <gpio.h> +#include <bootsource.h> + +#include <linux/sizes.h> + +#include <mach/at91/at91sam9263_matrix.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9_smc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/iomux.h> + +static struct sam9_smc_config skov_nor_smc_config = { + /* Setup time is 2 cycles after the CS signal */ + .nwe_setup = 2, + .ncs_write_setup = 0, + .nrd_setup = 2, + .ncs_read_setup = 0, + + /* Set pulse long enough - pulse should be a bit shorter than the cycle */ + .nwe_pulse = 10, + .ncs_write_pulse = 12, + .nrd_pulse = 10, + .ncs_read_pulse = 12, + + /* Set cycle long enougth at least 12 Cycles->120ns plus a little extra */ + .write_cycle = 0x13, + .read_cycle = 0x13, + + /* Set mode: 16Bit bus width, enable read and write + * Note: pagemode + 32 byte pages do not work with the 29GL512P flash + */ + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_BAT_WRITE | + AT91_SMC_DBW_16 | + AT91_SMC_TDFMODE, + .tdf_cycles = 1, +}; + +BAREBOX_MAGICVAR(board.mem, "The detected memory size in MiB"); + +static int mem; + +/* + * Initialize of SMC must come after we + * probe the at91sam9_smc_driver. + * But is required before we start the other drives. + * Use device_initcall() to maintain this order. + */ +static int skov_arm9_probe(struct device *dev) +{ + barebox_set_hostname("skov-arm9cpu"); + + add_generic_device("at91sam9-smc", 0, NULL, AT91SAM9263_BASE_SMC0, 0x200, + IORESOURCE_MEM, NULL); + add_generic_device("at91sam9-smc", 1, NULL, AT91SAM9263_BASE_SMC1, 0x200, + IORESOURCE_MEM, NULL); + + /* configure chip-select 0 (NOR) */ + sam9_smc_configure(0, 0, &skov_nor_smc_config); + + mem = at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0)); + mem = mem / SZ_1M; + globalvar_add_simple_int("board.mem", &mem, "%u"); + + /* + * NOR first stage bootloader is at91bootstrap, so if we find traces + * of barebox in on-chip SRAM, it must mean we have booted from SD + */ + if (is_barebox_arm_head((void *)AT91SAM9263_SRAM0_BASE)) + bootsource_set_raw(BOOTSOURCE_MMC, BOOTSOURCE_INSTANCE_UNKNOWN); + + return 0; +} + +static __maybe_unused struct of_device_id skov_arm9_ids[] = { + { + .compatible = "skov,arm9-cpu", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, skov_arm9_ids); + +static struct driver skov_arm9_driver = { + .name = "skov-arm9", + .probe = skov_arm9_probe, + .of_compatible = DRV_OF_COMPAT(skov_arm9_ids), +}; +coredevice_platform_driver(skov_arm9_driver); diff --git a/arch/arm/boards/skov-arm9cpu/lowlevel.c b/arch/arm/boards/skov-arm9cpu/lowlevel.c new file mode 100644 index 0000000000..baf0b7bfc9 --- /dev/null +++ b/arch/arm/boards/skov-arm9cpu/lowlevel.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: 2022 Sam Ravnborg <sam@ravnborg.org> + +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9263_matrix.h> +#include <mach/at91/sam92_ll.h> +#include <mach/at91/xload.h> +#include <mach/at91/barebox-arm.h> +#include <linux/build_bug.h> + +/* MCK = 20 MHz */ +#define MAIN_CLOCK 200000000 +#define MASTER_CLOCK (MAIN_CLOCK / 2) /* PMC_MCKR divides by 2 */ + +#define PLLA_SETTINGS (AT91_PMC_PLLA_WR_ERRATA | AT91_PMC_MUL_(49) | AT91_PMC_OUT_2 | \ + AT91_PMC_PLLCOUNT_(48) | AT91_PMC_DIV_(4)) +static_assert(PLLA_SETTINGS == 0x2031B004); + +#define PLLB_SETTINGS (AT91_PMC_USBDIV_2 | AT91_PMC_MUL_(5) | AT91_PMC_OUT_0 | \ + AT91_PMC_PLLCOUNT_(48) | AT91_PMC_DIV_BYPASS) +static_assert(PLLB_SETTINGS == 0x10053001); + +/* + * Check if target is 64 or 128 MB and adjust AT91_SDRAMC_CR + * accordingly. + * Size Start Size(hex) + * 64 MB => 0x20000000 0x4000000 + * 128 MB => 0x20000000 0x8000000 + * + * If 64 MiB RAM with NC_10 set, then we see holes in the memory, which + * is how we detect if memory is 64 or 128 MiB + */ +static int check_if_128mb(void) +{ + unsigned int *test_adr = (unsigned int *)AT91_CHIPSELECT_1; + unsigned int test_val = 0xdeadbee0; + unsigned int *p; + int i; + + /* Fill up memory with a known pattern */ + p = test_adr; + for (i = 0; i < 0xb00; i++) + *p++ = test_val + i; + + /* + * Check that we can read back the values just written + * If one or more fails, we have only 64 MB + */ + p = test_adr; + for (i = 0; i < 0xb00; i++) + if (*p++ != (test_val + i)) + return false; + + return true; +} + +static void sam9263_sdramc_init(void) +{ + void __iomem *piod = IOMEM(AT91SAM9263_BASE_PIOD); + static struct at91sam9_sdramc_config config = { + .sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0), + .mr = 0, + .tr = (MASTER_CLOCK * 7) / 1000000, // TODO 140 versus 0x13c (316)? + .cr = AT91_SDRAMC_NC_10 | AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_2 + | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 + | AT91_SDRAMC_TWR_2 | AT91_SDRAMC_TRC_7 + | AT91_SDRAMC_TRP_2 | AT91_SDRAMC_TRCD_2 + | AT91_SDRAMC_TRAS_5 | AT91_SDRAMC_TXSR_8, + .lpr = 0, + .mdr = AT91_SDRAMC_MD_SDRAM, + }; + + /* Define PD[31:16] as DATA[31:16] */ + at91_mux_gpio_disable(piod, GENMASK(31, 16)); + /* No pull-up for D[31:16] */ + at91_mux_set_pullup(piod, GENMASK(31, 16), false); + /* PD16 to PD31 are pheripheral A */ + at91_mux_set_A_periph(piod, GENMASK(31, 16)); + + /* EBI0_CSA, CS1 SDRAM, 3.3V memories */ + setbits_le32(IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA), + AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V | AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC); + + at91sam9_sdramc_initialize(&config, AT91SAM9263_BASE_EBI0_CS1); + + if (!check_if_128mb()) { + /* Change number of columns to 9 for 64MB ram. */ + /* Other parameters does not need to be changed due to chip size. */ + + pr_debug("64M variant detected\n"); + + /* Clear NC bits */ + config.cr &= ~AT91_SDRAMC_NC; + config.cr |= AT91_SDRAMC_NC_9; + at91sam9_sdramc_initialize(&config, AT91SAM9263_BASE_EBI0_CS1); + } +} + +static noinline void continue_skov_arm9cpu_xload_mmc(void) +{ + sam9263_lowlevel_init(PLLA_SETTINGS, PLLB_SETTINGS); + sam92_dbgu_setup_ll(MASTER_CLOCK); + + sam92_udelay_init(MASTER_CLOCK); + sam9263_sdramc_init(); + sam9263_atmci_start_image(1, MASTER_CLOCK, 0); +} + +SAM9_ENTRY_FUNCTION(start_skov_arm9cpu_xload_mmc) +{ + /* Configure system so we are less constrained */ + arm_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + + continue_skov_arm9cpu_xload_mmc(); +} + +extern char __dtb_at91_skov_arm9cpu_start[]; + +AT91_ENTRY_FUNCTION(start_skov_arm9cpu, r0, r1, r2) +{ + void *fdt; + + /* + * We may be running after at91bootstrap, so redo the initialization to + * be sure, everything is as we expect it. + */ + arm_cpu_lowlevel_init(); + + fdt = __dtb_at91_skov_arm9cpu_start + get_runtime_offset(); + barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9263_get_sdram_size(0), fdt); +} diff --git a/arch/arm/boards/skov-imx6/Makefile b/arch/arm/boards/skov-imx6/Makefile new file mode 100644 index 0000000000..b6b8b44b84 --- /dev/null +++ b/arch/arm/boards/skov-imx6/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o +obj-pbl-y += version.o +bbenv-y += defaultenv-skov-imx6 diff --git a/arch/arm/boards/skov-imx6/board.c b/arch/arm/boards/skov-imx6/board.c new file mode 100644 index 0000000000..8ebb4a6e58 --- /dev/null +++ b/arch/arm/boards/skov-imx6/board.c @@ -0,0 +1,708 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "skov-imx6: " fmt + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <envfs.h> +#include <environment.h> +#include <globalvar.h> +#include <gpio.h> +#include <init.h> +#include <linux/micrel_phy.h> +#include <mach/imx/bbu.h> +#include <net.h> +#include <of_gpio.h> + +#include "version.h" + +struct skov_imx6_priv { + struct device *dev; +}; + +static struct skov_imx6_priv *skov_priv; + +static int eth_of_fixup_node(struct device_node *root, const char *node_path, + const u8 *ethaddr) +{ + struct device_node *node; + int ret; + + if (!is_valid_ether_addr(ethaddr)) { + dev_err(skov_priv->dev, "The mac-address %pM is invalid.\n", ethaddr); + return -EINVAL; + } + + node = of_find_node_by_path_from(root, node_path); + if (!node) { + dev_err(skov_priv->dev, "Did not find node %s to fix up with stored mac-address.\n", + node_path); + return -ENOENT; + } + + ret = of_set_property(node, "mac-address", ethaddr, ETH_ALEN, 1); + if (ret) + dev_err(skov_priv->dev, "Setting mac-address property of %pOF failed with: %s.\n", + node, strerror(-ret)); + + return ret; +} + +static int eth_of_fixup_node_from_eth_device(struct device_node *root, + const char *node_path, + const char *ethname) +{ + struct eth_device *edev; + + edev = eth_get_byname(ethname); + if (!edev) { + dev_err(skov_priv->dev, "Did not find eth device \"%s\" to copy mac-address from.\n", ethname); + return -ENOENT; + } + + return eth_of_fixup_node(root, node_path, edev->ethaddr); +} + +static int get_mac_address_from_env_variable(const char *env, u8 ethaddr[ETH_ALEN]) +{ + const char *ethaddr_str; + int ret; + + ethaddr_str = getenv(env); + if (!ethaddr_str) { + dev_err(skov_priv->dev, "State variable %s storing the mac-address not found.\n", env); + return -ENOENT; + } + + ret = string_to_ethaddr(ethaddr_str, ethaddr); + if (ret < 0) { + dev_err(skov_priv->dev, "Could not convert \"%s\" in state variable %s into mac-address.\n", + ethaddr_str, env); + return -EINVAL; + } + + return 0; +} + +static int get_default_mac_address_from_state_node(const char *state_node_path, + u8 ethaddr[ETH_ALEN]) +{ + struct device_node *node; + int ret; + + node = of_find_node_by_path(state_node_path); + if (!node) { + dev_err(skov_priv->dev, "Node %s defining the state variable not found.\n", state_node_path); + return -ENOENT; + } + + ret = of_property_read_u8_array(node, "default", ethaddr, ETH_ALEN); + if (ret) { + dev_err(skov_priv->dev, "Node %s has no property \"default\" of proper type.\n", state_node_path); + return -ENOENT; + } + + return 0; +} + +static int eth2_of_fixup_node_individually(struct device_node *root, + const char *node_path, + const char *ethname, + const char *env, + const char *state_node_path) +{ + u8 env_ethaddr[ETH_ALEN], default_ethaddr[ETH_ALEN]; + int ret; + + ret = get_mac_address_from_env_variable(env, env_ethaddr); + if (ret) + goto copy_mac_from_eth0; + + ret = get_default_mac_address_from_state_node(state_node_path, default_ethaddr); + if (ret) + goto copy_mac_from_eth0; + + /* + * As the default is bogus copy the MAC address from eth0 if + * the state variable has not been set to a different variant + */ + if (memcmp(env_ethaddr, default_ethaddr, ETH_ALEN) == 0) + goto copy_mac_from_eth0; + + return eth_of_fixup_node(root, node_path, env_ethaddr); + +copy_mac_from_eth0: + return eth_of_fixup_node_from_eth_device(root, node_path, ethname); +} + +#define MAX_V_GPIO 8 + +struct board_description { + const char *variant; + const char *revision; + const char *soc; + const char *dts_compatible; + const char *display; + unsigned flags; +}; + +#define SKOV_NEED_ENABLE_RMII BIT(0) +#define SKOV_DISPLAY_PARALLEL BIT(1) +#define SKOV_ENABLE_MMC_POWER BIT(2) +#define SKOV_DISPLAY_LVDS BIT(3) + +static const struct board_description imx6_variants[] = { + [0] = { + .variant = "high performance", + .revision = "A", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6-imxq-revA", + .flags = SKOV_NEED_ENABLE_RMII | SKOV_DISPLAY_PARALLEL, + }, + [1] = { + .variant = "low cost", + .revision = "A", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6-imxdl-revA", + .flags = SKOV_NEED_ENABLE_RMII | SKOV_DISPLAY_PARALLEL, + }, + [2] = { + .variant = "high performance", + .revision = "A", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6-imxq-revA", + .flags = SKOV_NEED_ENABLE_RMII | SKOV_DISPLAY_PARALLEL, + }, + [4] = { + .variant = "low cost", + .revision = "A", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6-imxdl-revA", + .flags = SKOV_NEED_ENABLE_RMII | SKOV_DISPLAY_PARALLEL, + }, + [8] = { + .variant = "high performance", + .revision = "A", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6-imxq-revA", + .flags = SKOV_NEED_ENABLE_RMII | SKOV_DISPLAY_PARALLEL, + }, + [9] = { + .variant = "minimum cost", + .revision = "B", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6-imxdl-revB", + .flags = SKOV_DISPLAY_PARALLEL, + }, + [10] = { + .variant = "low cost", + .revision = "B", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6-imxdl-revB", + .flags = SKOV_DISPLAY_PARALLEL, + }, + [11] = { + .variant = "high performance", + .revision = "B", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6-imxq-revB", + .flags = SKOV_DISPLAY_PARALLEL, + }, + [12] = { + /* FIXME this one is a revision 'C' according to the schematics */ + .variant = "max performance", + .revision = "B", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6q-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_DISPLAY_PARALLEL, + }, + [13] = { + .variant = "low cost", + .revision = "C", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6dl-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [14] = { + .variant = "high performance", + .revision = "C", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6q-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [15] = { + .variant = "middle performance", + .revision = "C", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6dl-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [16] = { + .variant = "Solo_R512M_F4G", + .revision = "C", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6dl-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [17] = { + .variant = "Quad_R2G_F8G", + .revision = "C", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6q-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [18] = { + .variant = "QuadPlus_R4G_F16G", + .revision = "C", + .soc = "i.MX6Q+", + .dts_compatible = "skov,imx6q-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [19] = { + .variant = "Solo_R512M_F2G", + .revision = "C", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6dl-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [20] = { + .variant = "Quad_R1G_F4G", + .revision = "C", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6q-skov-revc-lt2", + .display = "l2rt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [21] = { + .variant = "Solo_R512M_F2G", + .revision = "C", + .soc = "i.MX6S", + .dts_compatible = "skov,imx6dl-skov-revc-lt6", + .display = "l6whrt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [22] = { + .variant = "Quad_R1G_F4G", + .revision = "C", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6q-skov-revc-lt6", + .display = "l6whrt", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_PARALLEL, + }, + [24] = { + .variant = "Quad_R1G_F4G", + .revision = "E", + .soc = "i.MX6Q", + .dts_compatible = "skov,imx6q-skov-reve-mi1010ait-1cp1", + .display = "mi1010ait-1cp1", + .flags = SKOV_ENABLE_MMC_POWER | SKOV_DISPLAY_LVDS, + }, +}; + +static int skov_board_no = -1; +static bool skov_have_switch = true; +static const char *no_switch_suffix = "-noswitch"; + +static void fixup_noswitch_machine_compatible(struct device_node *root) +{ + const char *compat = imx6_variants[skov_board_no].dts_compatible; + const char *generic = "skov,imx6"; + char *buf; + + /* add generic compatible, so systemd&co can make right decisions */ + buf = xasprintf("%s%s", generic, no_switch_suffix); + of_prepend_machine_compatible(root, buf); + + /* add specific compatible as fallback, in case this board has new + * challenges. + */ + buf = xasprintf("%s%s", compat, no_switch_suffix); + of_prepend_machine_compatible(root, buf); + + free(buf); +} + +static void skov_imx6_no_switch(struct device_node *root) +{ + const char *fec_alias = "ethernet0"; + struct device_node *node; + int ret; + + fixup_noswitch_machine_compatible(root); + + node = of_find_node_by_alias(root, fec_alias); + if (node) { + ret = of_device_disable(node); + if (ret) + dev_warn(skov_priv->dev, "Can't disable %s\n", fec_alias); + } else { + dev_warn(skov_priv->dev, "Can't find node by alias: %s\n", fec_alias); + } + + node = of_find_node_by_alias(root, "mdio-gpio0"); + if (node) { + ret = of_device_disable(node); + if (ret) + dev_warn(skov_priv->dev, "Can't disable mdio-gpio0 node\n"); + } else { + dev_warn(skov_priv->dev, "Can't find mdio-gpio0 node\n"); + } +} + +static int skov_imx6_switch_port(struct device_node *root, const char *path) +{ + size_t size; + char *buf; + int ret; + + /* size is, string + '\0' + port number */ + size = strlen(path) + 2; + buf = xzalloc(size); + if (!buf) + return -ENOMEM; + + ret = snprintf(buf, size, "%s0", path); + if (ret < 0) + return ret; + + ret = eth_of_fixup_node_from_eth_device(root, buf, "eth0"); + if (ret) + return ret; + + ret = snprintf(buf, size, "%s1", path); + if (ret < 0) + return ret; + + ret = eth2_of_fixup_node_individually(root, buf, "eth0", + "state.ethaddr.eth2", + "/state/ethaddr/eth2"); + return ret; +} + +static void skov_imx6_switch(struct device_node *root) +{ + const char *old = "/mdio-gpio/ksz8873@3/ports/ports@"; + const char *new = "/mdio/switch@0/ports/ports@"; + int ret; + + /* Old DTS variants (pre kernel mainline) use different path. Try first + * the new variant, then fall back to the old one. + */ + ret = skov_imx6_switch_port(root, new); + if (ret) { + ret = skov_imx6_switch_port(root, old); + if (ret) + dev_err(skov_priv->dev, "Filed to set mac address\n"); + } +} + +static int skov_imx6_fixup(struct device_node *root, void *unused) +{ + struct device_node *chosen = of_create_node(root, "/chosen"); + struct device_node *node; + uint32_t brightness; + const char *val; + int ret; + + if (skov_have_switch) + skov_imx6_switch(root); + else + skov_imx6_no_switch(root); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + /* use default variant of state variable defined in devicetree */ + brightness = 8; + break; + default: + val = getenv("state.display.brightness"); + if (!val) { + dev_err(skov_priv->dev, "could not get default display brightness\n"); + return 0; + } + + brightness = simple_strtoul(val, NULL, 0); + break; + } + + for_each_compatible_node_from(node, root, NULL, "pwm-backlight") { + ret = of_property_write_u32(node, "default-brightness-level", brightness); + if (ret) + dev_err(skov_priv->dev, "error %d while setting default-brightness-level property on node %s to %d\n", + ret, node->name, brightness); + } + + of_property_write_u32(chosen, "skov,imx6-board-version", skov_board_no); + of_property_write_string(chosen, "skov,imx6-board-variant", + imx6_variants[skov_board_no].variant); + + return 0; +} + +static void skov_init_parallel_lcd(void) +{ + struct device_node *lcd; + + lcd = of_find_compatible_node(NULL, NULL, "fsl,imx-parallel-display"); + if (!lcd) { + dev_err(skov_priv->dev, "Cannot find \"fsl,imx-parallel-display\" node\n"); + return; + } + + of_device_enable_and_register(lcd); +} + +static void skov_init_ldb(void) +{ + struct device_node *ldb, *chan; + + ldb = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ldb"); + if (!ldb) { + dev_err(skov_priv->dev, "Cannot find \"fsl,imx6q-ldb\" node\n"); + return; + } + + /* First enable channel 0, prior to enabling parent */ + chan = of_find_node_by_name_address(ldb, "lvds-channel@0"); + if (chan) + of_device_enable(chan); + else + dev_err(skov_priv->dev, "Cannot find \"lvds-channel@0\" node\n"); + + /* Now probe will see the expected device tree */ + of_device_enable_and_register(ldb); +} + +/* + * Some variants need tweaks to make them work + * + * Revision A has no backlight control, since revision B it is present (GPIO6/23) + * Revision A needs GPIO1/24 to be low to make network working + * Revision C can control the SD main power supply + */ +static void skov_init_board(const struct board_description *variant) +{ + struct device_node *gpio_np = NULL; + char *environment_path, *envdev; + int ret; + + gpio_np = of_find_node_by_name_address(NULL, "gpio@20b4000"); + if (gpio_np) { + ret = of_device_ensure_probed(gpio_np); + if (ret) + dev_warn(skov_priv->dev, "Can't probe GPIO node\n"); + } else { + dev_warn(skov_priv->dev, "Can't get GPIO node\n"); + } + + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + of_register_fixup(skov_imx6_fixup, NULL); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + environment_path = "/chosen/environment-sd"; + envdev = "MMC"; + break; + default: + environment_path = "/chosen/environment-spinor"; + envdev = "SPI NOR flash"; + break; + } + + dev_notice(skov_priv->dev, "Using environment in %s\n", envdev); + + ret = of_device_enable_path(environment_path); + if (ret < 0) + dev_warn(skov_priv->dev, "Failed to enable environment partition '%s' (%d)\n", + environment_path, ret); + + if (variant->flags & SKOV_NEED_ENABLE_RMII) { + /* + * MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 is a gpio which must be + * low to enable the RMII from the switch point of view + */ + gpio_request(24, "must_be_low"); + gpio_direction_output(24, 0); + gpio_free(24); + } + + /* SD card handling */ + gpio_request(205, "mmc io supply"); + gpio_direction_output(205, 0); /* select 3.3 V IO voltage */ + gpio_free(205); + + if (variant->flags & SKOV_ENABLE_MMC_POWER) { + /* + * keep in sync with devicetree's 'regulator-boot-on' setting for + * this regulator + */ + gpio_request(200, "mmc power supply"); + gpio_direction_output(200, 0); /* switch on */ + mdelay(1); + gpio_direction_output(200, 1); /* switch on */ + gpio_free(200); + } + + if (variant->flags & SKOV_DISPLAY_PARALLEL) + skov_init_parallel_lcd(); + + if (variant->flags & SKOV_DISPLAY_LVDS) + skov_init_ldb(); +} + +static int skov_set_switch_lan2_mac(struct skov_imx6_priv *priv) +{ + const char *state = "/state/ethaddr/eth2"; + struct device_node *lan2_np; + u8 ethaddr[ETH_ALEN]; + int ret; + + ret = get_mac_address_from_env_variable("state.ethaddr.eth2", ethaddr); + if (ret || !is_valid_ether_addr(ethaddr)) { + ret = get_default_mac_address_from_state_node(state, ethaddr); + if (ret || !is_valid_ether_addr(ethaddr)) { + dev_err(priv->dev, "can't get MAC for LAN2\n"); + return -ENODEV; + } + } + + lan2_np = of_find_node_by_path("/mdio/switch@0/ports/ports@1"); + if (!lan2_np) { + dev_err(priv->dev, "LAN2 node not found\n"); + return -ENODEV; + } + + of_eth_register_ethaddr(lan2_np, ethaddr); + + return 0; +} + +static int skov_switch_test(void) +{ + struct device *sw_dev; + struct device *eth0; + int ret; + + if (skov_board_no < 0) + return 0; + + /* Driver should be able to detect if device do actually + * exist. So, we need only to detect if driver is actually + * probed. + */ + sw_dev = of_find_device_by_node_path("/mdio/switch@0"); + if (!sw_dev) { + dev_err(skov_priv->dev, "switch@0 device was not created!\n"); + goto no_switch; + } + + if (dev_is_probed(sw_dev)) { + skov_set_switch_lan2_mac(skov_priv); + /* even if we fail, continue to boot as good as possible */ + return 0; + } + +no_switch: + skov_have_switch = false; + + dev_notice(skov_priv->dev, "No-switch variant is detected\n"); + + eth0 = get_device_by_name("eth0"); + if (eth0) { + ret = dev_set_param(eth0, "mode", "disabled"); + if (ret) + dev_warn(skov_priv->dev, "Can't set eth0 mode\n"); + } else { + dev_warn(skov_priv->dev, "Can't disable eth0\n"); + } + + return 0; +} +late_initcall(skov_switch_test); + +static int skov_imx6_probe(struct device *dev) +{ + struct skov_imx6_priv *priv; + unsigned v = 0; + const struct board_description *variant; + + v = skov_imx6_get_version(); + + if (v >= ARRAY_SIZE(imx6_variants)) { + dev_err(dev, "Invalid variant %u\n", v); + return -EINVAL; + } + + variant = &imx6_variants[v]; + + if (!variant->variant) { + dev_err(dev, "Invalid variant %u\n", v); + return -EINVAL; + } + + skov_board_no = v; + + priv = xzalloc(sizeof(*priv)); + priv->dev = dev; + skov_priv = priv; + + globalvar_add_simple_int("board.no", &skov_board_no, "%u"); + globalvar_add_simple("board.variant", variant->variant); + globalvar_add_simple("board.revision",variant->revision); + globalvar_add_simple("board.soc", variant->soc); + globalvar_add_simple("board.dts", variant->dts_compatible); + globalvar_add_simple("board.display", variant->display ?: NULL); + + of_prepend_machine_compatible(NULL, variant->dts_compatible); + + skov_init_board(variant); + + defaultenv_append_directory(defaultenv_skov_imx6); + + return 0; +} + +static __maybe_unused struct of_device_id skov_version_ids[] = { + { + .compatible = "skov,imx6", + }, { + /* sentinel */ + } +}; +BAREBOX_DEEP_PROBE_ENABLE(skov_version_ids); + +static struct driver skov_version_driver = { + .name = "skov-imx6", + .probe = skov_imx6_probe, + .of_compatible = DRV_OF_COMPAT(skov_version_ids), +}; +coredevice_platform_driver(skov_version_driver); + +static void skov_imx6_devices_shutdown(void) +{ + const char *external; + + if (skov_board_no < 0) + return; + + external = getenv("state.display.external"); + if (!external) { + dev_err(skov_priv->dev, "could not get state variable display.external\n"); + return; + } + + if (!strcmp(external, "0")) + setenv("backlight0.brightness", "0"); +} +predevshutdown_exitcall(skov_imx6_devices_shutdown); diff --git a/arch/arm/boards/skov-imx6/defaultenv-skov-imx6/network/eth1-discover b/arch/arm/boards/skov-imx6/defaultenv-skov-imx6/network/eth1-discover new file mode 100644 index 0000000000..e11a3f9006 --- /dev/null +++ b/arch/arm/boards/skov-imx6/defaultenv-skov-imx6/network/eth1-discover @@ -0,0 +1,8 @@ +#!/bin/sh + +# Some boards doesn't have a ETH port, but may have USB network attached +if [ "$eth0.mode" != "disabled" ]; then + exit 0; +fi + +usb diff --git a/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg b/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg new file mode 100644 index 0000000000..da4cd4bebf --- /dev/null +++ b/arch/arm/boards/skov-imx6/flash-header-mx6-skov-imx6.imxcfg @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx6 +loadaddr 0x00907000 +max_load_size 0x11000 +ivtofs 0x400 diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c new file mode 100644 index 0000000000..16809dd4a6 --- /dev/null +++ b/arch/arm/boards/skov-imx6/lowlevel.c @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "skov-imx6: " fmt + +#include <common.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <io.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> +#include <serial/imx-uart.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/imx-gpio.h> +#include "version.h" + +static void __udelay(int us) +{ + volatile int i; + + for (i = 0; i < us * 4; i++); +} + +/* ------------------------------------------------------------------------ */ + +/* + * Micron MT41K128M16JT-125 IT:K -> 2 GBit = 16 Meg x 16 x 8 banks + * + * Speed Grade Data Rate (MT/s) tRCD-tRP-CL tRCD(ns) tRP(ns) CL(ns) + * -125 ¹² 1600 11-11-11 13.75 13.75 13.75 + * (=800 MHz) + * + * ¹ Backward compatible to 1066 (=533 MHz), CL = 7 + * ² Backward compatible to 1333 (=667 MHz), CL = 9 + * + * Memory configuration used by variant + * - "High Performance", 64 bit data bus, 1066 MHz, 1 GiB memory + */ +static const struct mx6_ddr3_cfg skov_imx6_cfg_4x128Mb_1066MHz = { + .mem_speed = 1066, + .density = 2, /* GiBit */ + .width = 16, /* 16 bit data per device */ + .banks = 8, + .rowaddr = 14, /* 16 k */ + .coladdr = 10, /* 1 k */ + .pagesz = 2, /* [kiB] */ + .trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */ + .trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */ + .trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */ + .SRT = 0, +}; + +static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x128Mb_1066MHz = { + .dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */ + .cs_density = 8, /* four 2 GBit devices connected */ + .ncs = 1, /* one CS line for all devices */ + .cs1_mirror = 1, + .bi_on = 1, + .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ + .rtt_wr = 0, /* is LW_EN is 0 in their code */ + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .pd_fast_exit = 1, +}; + +/* calibration info for the "max performance" and "high performance" */ +static const struct mx6_mmdc_calibration skov_imx6_calib_4x128Mb_1066MHz = { + .p0_mpwldectrl0 = 0x00230023, + .p0_mpwldectrl1 = 0x0029001E, + .p0_mpdgctrl0 = 0x43400350, + .p0_mpdgctrl1 = 0x03380330, + .p0_mprddlctl = 0x3E323638, + .p0_mpwrdlctl = 0x383A3E3A, + + .p1_mpwldectrl0 = 0x001F002A, + .p1_mpwldectrl1 = 0x001A0028, + .p1_mpdgctrl0 = 0x43300340, + .p1_mpdgctrl1 = 0x03340300, + .p1_mprddlctl = 0x383A3242, + .p1_mpwrdlctl = 0x4232463A, +}; + +/* ------------------------------------------------------------------------ */ + +static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_reset = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, +}; + +static struct mx6dq_iomux_grp_regs grp_iomux_q = { + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ctlds = 0x00000030, + .grp_ddr_type = 0x000C0000, +}; + +static void spl_imx6q_dram_init(const struct mx6_ddr_sysinfo *si, + const struct mx6_mmdc_calibration *cb, + const struct mx6_ddr3_cfg *cfg) +{ + mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); + mx6_dram_cfg(si, cb, cfg); + __udelay(100); +} + +/* ------------------------------------------------------------------------ */ +/* + * Device Information: Varies per DDR3 part number and speed grade + * Note: this SDRAM type is used on the "Low Cost" variant + * + * Micron MT41K128M16JT-125 IT:K -> 2 GBit = 16 Meg x 16 x 8 banks + * + * Speed Grade Data Rate (MT/s) tRCD-tRP-CL tRCD(ns) tRP(ns) CL(ns) + * -125 ¹² 1600 11-11-11 13.75 13.75 13.75 + * (=800 MHz) + * + * ¹ Backward compatible to 1066 (=533 MHz), CL = 7 + * ² Backward compatible to 1333 (=667 MHz), CL = 9 + * + * Memory configuration used by variant + * - "Low Cost", 32 bit data bus, 800 MHz, 512 MiB memory + */ +static const struct mx6_ddr3_cfg skov_imx6_cfg_2x128Mb_800MHz = { + .mem_speed = 800, + .density = 2, /* GiBit */ + .width = 16, /* 16 bit data per device */ + .banks = 8, + .rowaddr = 14, /* 16 k */ + .coladdr = 10, /* 1 k */ + .pagesz = 2, /* [kiB] */ + .trcd = 1375, /* 13.75 ns = 11 clocks @ 1.6 GHz */ + .trcmin = 4875, /* 48.75 ns = 39 clocks @ 1.6 GHz */ + .trasmin = 3500, /* 35 ns = 28 clocks @ 1.6 GHz */ + .SRT = 0, +}; + +static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_2x128Mb_800MHz = { + .dsize = 1, /* 32 bit wide = 2 devices, 16 bit each */ + .cs_density = 4, /* two 2 GBit devices connected */ + .ncs = 1, /* one CS line for all devices */ + .cs1_mirror = 1, + .bi_on = 1, + .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ + .rtt_wr = 0, /* is LW_EN is 0 in their code */ + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .pd_fast_exit = 1, +}; + +static const struct mx6_mmdc_calibration skov_imx6_calib_2x128Mb_800MHz = { + .p0_mpwldectrl0 = 0x004A004B, + .p0_mpwldectrl1 = 0x00420046, + .p0_mpdgctrl0 = 0x42400240, + .p0_mpdgctrl1 = 0x02300230, + .p0_mprddlctl = 0x464A4A4A, + .p0_mpwrdlctl = 0x32342A32, +}; + +/* ------------------------------------------------------------------------ */ + +static const struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x0000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_reset = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, +}; + +static const struct mx6sdl_iomux_grp_regs grp_iomux_s = { /* TODO */ + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ctlds = 0x00000030, + .grp_ddr_type = 0x000C0000, +}; + +static void spl_imx6sdl_dram_init(const struct mx6_ddr_sysinfo *si, + const struct mx6_mmdc_calibration *cb, + const struct mx6_ddr3_cfg *cfg) +{ + mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); + mx6_dram_cfg(si, cb, cfg); + __udelay(100); +} + +/* ------------------------------------------------------------------------ */ + +#define BKLGT_PWR_PAD_CTRL MX6_PAD_CTL_SPEED_LOW | MX6_PAD_CTL_DSE_80ohm | MX6_PAD_CTL_SRE_SLOW + +static inline void init_backlight_gpios(int cpu_type, unsigned board_variant) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *gpio6base = IOMEM(MX6_GPIO6_BASE_ADDR); + void __iomem *gpio1base = IOMEM(MX6_GPIO1_BASE_ADDR); + + /* + * since revision B a backlight switch is present which can help to + * prevent any kind of flicker when switching on the board. Use it. + * GPIO6/23 controls the backlight. High switches off the backlight. + */ + switch (board_variant) { + case 0 ... 8: + break; + default: + imx6_gpio_direction_output(gpio6base, 23, 1); + + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(IOMUX_CONFIG_SION | 0x05, iomuxbase + 0x2D0); + writel(BKLGT_PWR_PAD_CTRL, iomuxbase + 0x6B8); + break; + case IMX6_CPUTYPE_IMX6D: + case IMX6_CPUTYPE_IMX6Q: + writel(IOMUX_CONFIG_SION | 0x05, iomuxbase + 0x068); + writel(BKLGT_PWR_PAD_CTRL, iomuxbase + 0x37C); + break; + } + } + + /* + * switch brightness to the lowest available value. This is what we + * can do for revision A boards + * GPIO1/1 controls (via PWM) the brightness. A static low means + * a very dark backlight + */ + imx6_gpio_direction_output(gpio1base, 1, 0); + + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(IOMUX_CONFIG_SION | 0x05, iomuxbase + 0x210); + writel(BKLGT_PWR_PAD_CTRL, iomuxbase + 0x5E0); + break; + case IMX6_CPUTYPE_IMX6D: + case IMX6_CPUTYPE_IMX6Q: + writel(IOMUX_CONFIG_SION | 0x05, iomuxbase + 0x224); + writel(BKLGT_PWR_PAD_CTRL, iomuxbase + 0x5F4); + break; + } +} + +#define LED_PAD_CTRL MX6_PAD_CTL_SPEED_LOW | MX6_PAD_CTL_DSE_240ohm | MX6_PAD_CTL_SRE_SLOW + +static inline void setup_leds(int cpu_type) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *gpiobase = IOMEM(MX6_GPIO1_BASE_ADDR); + + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(0x05, iomuxbase + 0x20C); /* LED1 (GPIO0) */ + writel(LED_PAD_CTRL, iomuxbase + 0x5DC); + writel(0x05, iomuxbase + 0x224); /* LED2 (GPIO2) */ + writel(LED_PAD_CTRL, iomuxbase + 0x5F4); + writel(0x05, iomuxbase + 0x22C); /* LED3 (GPIO4) */ + writel(LED_PAD_CTRL, iomuxbase + 0x5FC); + break; + case IMX6_CPUTYPE_IMX6D: + case IMX6_CPUTYPE_IMX6Q: + writel(0x05, iomuxbase + 0x220); /* LED1 (GPIO0) */ + writel(LED_PAD_CTRL, iomuxbase + 0x5f0); + writel(0x05, iomuxbase + 0x234); /* LED2 (GPIO2) */ + writel(LED_PAD_CTRL, iomuxbase + 0x604); + writel(0x05, iomuxbase + 0x238); /* LED3 (GPIO4) */ + writel(LED_PAD_CTRL, iomuxbase + 0x608); + break; + } + + /* Turn off all LEDS */ + imx6_gpio_direction_output(gpiobase, 1, 0); + imx6_gpio_direction_output(gpiobase, 4, 0); + imx6_gpio_direction_output(gpiobase, 16, 0); +} + +static inline void setup_uart(int cpu_type) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + + /* UART TxD output is pin EIM/D26, e.g. UART is in DTE mode */ + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(0x0, iomuxbase + 0x904); /* IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT */ + writel(0x4, iomuxbase + 0x16c); /* IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 */ + break; + case IMX6_CPUTYPE_IMX6D: + case IMX6_CPUTYPE_IMX6Q: + writel(0x0, iomuxbase + 0x928); /* IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT */ + writel(0x4, iomuxbase + 0x0bc); /* IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 */ + break; + } + + imx6_ungate_all_peripherals(); + imx6_uart_setup(IOMEM(MX6_UART2_BASE_ADDR)); + pbl_set_putc(imx_uart_putc, IOMEM(MX6_UART2_BASE_ADDR)); + + pr_debug("\n"); +} + +/* + * Hardware marked board revisions and deployments + * + * count board ram flash CPU + * rev. + * 00000000 A 1024 MiB 1024 MiB i.MX6Q + * 00000001 A 512 MiB 256 MiB i.MX6S + * 00000010 A 1024 MiB 512 MiB i.MX6Q + * 00000011 ---- not defined ---- + * 00000100 A 512 MiB 256 MiB i.MX6S + * 00000101 ---- not defined ---- + * 00000110 ---- not defined ---- + * 00000111 ---- not defined ---- + * 00001000 A 1024 MiB 512 MiB i.MX6Q + * 00001001 B 256 MiB 16 MiB i.MX6S + * 00001010 B 256 MiB 256 MiB i.MX6S + * 00001011 B 1024 MiB 256 MiB i.MX6Q + * 00001100 B 2048 MiB 8 GiB i.MX6Q + * 00001101 C 256 MiB 256 MiB i.MX6S + * 00001110 C 1024 MiB 256 MiB i.MX6Q + * 00001111 C 512 MiB 256 MiB i.MX6S + * 00010000 C 512 MiB 4 GiB i.MX6S + * 00010001 C 2048 MiB 8 GiB i.MX6Q + * 00010010 C 4096 MiB 16 GiB i.MX6Q+ + * 00010011 C 512 MiB 2 GiB i.MX6S + * 00010100 C 1024 MiB 4 GiB i.MX6Q + * 00010101 D 512 MiB 2 GIB i.MX6S + * 00010110 D 1024 MiB 4 GIB i.MX6Q + * 00010111 ---- not defined ---- + * 00011000 E 1024 MiB 4 GIB i.MX6Q + * + * This routine does not return if starting the image from SD card or NOR + * was successful. It restarts skov_imx6_start() instead + */ +static void skov_imx6_init(int cpu_type, unsigned board_variant) +{ + enum bootsource bootsrc; + int instance; + + switch (board_variant) { + case 19: /* i.MX6S "Solo_R512M_F2G" */ + if (cpu_type != IMX6_CPUTYPE_IMX6S) { + pr_err("Invalid SoC! i.MX6S expected\n"); + return; + } + pr_debug("Initializing board variant 19\n"); + spl_imx6sdl_dram_init(&skov_imx6_sysinfo_2x128Mb_800MHz, + &skov_imx6_calib_2x128Mb_800MHz, + &skov_imx6_cfg_2x128Mb_800MHz); + break; + case 20: /* i.MX6Q, "Quad_R1G_F2G" */ + if (cpu_type != IMX6_CPUTYPE_IMX6Q) { + pr_err("Invalid SoC! i.MX6Q expected\n"); + return; + } + pr_debug("Initializing board variant 20\n"); + spl_imx6q_dram_init(&skov_imx6_sysinfo_4x128Mb_1066MHz, + &skov_imx6_calib_4x128Mb_1066MHz, + &skov_imx6_cfg_4x128Mb_1066MHz); + break; + case 21: /* i.MX6S "Solo_R512M_F2G" */ + if (cpu_type != IMX6_CPUTYPE_IMX6S) { + pr_err("Invalid SoC! i.MX6S expected\n"); + return; + } + pr_debug("Initializing board variant 21\n"); + spl_imx6sdl_dram_init(&skov_imx6_sysinfo_2x128Mb_800MHz, + &skov_imx6_calib_2x128Mb_800MHz, + &skov_imx6_cfg_2x128Mb_800MHz); + break; + case 22: /* i.MX6Q, "Quad_R1G_F4G" */ + if (cpu_type != IMX6_CPUTYPE_IMX6Q) { + pr_err("Invalid SoC! i.MX6Q expected\n"); + return; + } + pr_debug("Initializing board variant 22\n"); + spl_imx6q_dram_init(&skov_imx6_sysinfo_4x128Mb_1066MHz, + &skov_imx6_calib_4x128Mb_1066MHz, + &skov_imx6_cfg_4x128Mb_1066MHz); + break; + case 24: /* i.MX6Q, "Quad_R1G_F4G" */ + if (cpu_type != IMX6_CPUTYPE_IMX6Q) { + pr_err("Invalid SoC! i.MX6Q expected\n"); + return; + } + pr_debug("Initializing board variant 24\n"); + spl_imx6q_dram_init(&skov_imx6_sysinfo_4x128Mb_1066MHz, + &skov_imx6_calib_4x128Mb_1066MHz, + &skov_imx6_cfg_4x128Mb_1066MHz); + break; + default: + pr_err("Unsupported board variant: 0x%x\n", board_variant); + /* don't continue */ + while(1); + break; + } + + imx6_get_boot_source(&bootsrc, &instance); + if (bootsrc == BOOTSOURCE_SPI_NOR) { + pr_info("Loading bootloader image from SPI flash..."); + imx6_spi_start_image(0); + } else { + pr_info("Loading bootloader image from SD card..."); + imx6_esdhc_start_image(instance); + } +} + +extern char __dtb_z_imx6q_skov_imx6_start[]; +extern char __dtb_z_imx6dl_skov_imx6_start[]; +extern char __dtb_z_imx6s_skov_imx6_start[]; + +/* called twice: once for SDRAM setup only, second for devicetree setup */ +static noinline void skov_imx6_start(void) +{ + int cpu_type = __imx6_cpu_type(); + unsigned board_variant = skov_imx6_get_version(); + + setup_uart(cpu_type); + + if (get_pc() <= MX6_MMDC_PORT01_BASE_ADDR) { + /* first call: do the lowlevel things first */ + init_backlight_gpios(cpu_type, board_variant); + setup_leds(cpu_type); + pr_info("Starting to init IMX6 system...\n"); + skov_imx6_init(cpu_type, board_variant); + pr_err("Unable to start bootloader\n"); + while (1); + } + + /* boot this platform (second call) */ + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + pr_debug("Startup i.MX6S based system...\n"); + imx6q_barebox_entry(__dtb_z_imx6s_skov_imx6_start); + break; + case IMX6_CPUTYPE_IMX6DL: + pr_debug("Startup i.MX6DL based system...\n"); + imx6q_barebox_entry(__dtb_z_imx6dl_skov_imx6_start); + break; + case IMX6_CPUTYPE_IMX6D: + case IMX6_CPUTYPE_IMX6Q: + pr_debug("Startup i.MX6Q based system...\n"); + imx6q_barebox_entry(__dtb_z_imx6q_skov_imx6_start); + break; + } +} + +ENTRY_FUNCTION(start_imx6_skov_imx6, r0, r1, r2) +{ + imx6_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + skov_imx6_start(); +} diff --git a/arch/arm/boards/skov-imx6/version.c b/arch/arm/boards/skov-imx6/version.c new file mode 100644 index 0000000000..503a60366f --- /dev/null +++ b/arch/arm/boards/skov-imx6/version.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "skov-imx6: " fmt + +#include <common.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/imx-gpio.h> +#include <mach/imx/imx6.h> + +#include "version.h" + +#define V_PAD_CTRL MX6_PAD_CTL_PUS_100K_UP | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \ + MX6_PAD_CTL_SPEED_LOW + +unsigned skov_imx6_get_version(void) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *gpiobase = IOMEM(MX6_GPIO2_BASE_ADDR); + unsigned reg; + unsigned var = 0; + int cpu_type = __imx6_cpu_type(); + + /* mux pins as GPIOs */ + switch (cpu_type) { + case IMX6_CPUTYPE_IMX6S: + case IMX6_CPUTYPE_IMX6DL: + writel(0x05, iomuxbase + 0x348); /* VERSION_0, GPIO2/10 */ + writel(V_PAD_CTRL, iomuxbase + 0x730); + writel(0x05, iomuxbase + 0x35c); /* VERSION_1, GPIO2/15 */ + writel(V_PAD_CTRL, iomuxbase + 0x744); + writel(0x05, iomuxbase + 0x340); /* VERSION_2, GPIO2/8 */ + writel(V_PAD_CTRL, iomuxbase + 0x728); + writel(0x05, iomuxbase + 0x344); /* VERSION_3, GPIO2/9 */ + writel(V_PAD_CTRL, iomuxbase + 0x72C); + writel(0x05, iomuxbase + 0x350); /* VERSION_4, GPIO2/12 */ + writel(V_PAD_CTRL, iomuxbase + 0x738); + writel(0x05, iomuxbase + 0x358); /* VERSION_5, GPIO2/14 */ + writel(V_PAD_CTRL, iomuxbase + 0x740); + writel(0x05, iomuxbase + 0x34c); /* VERSION_6, GPIO2/11 */ + writel(V_PAD_CTRL, iomuxbase + 0x734); + writel(0x05, iomuxbase + 0x354); /* VERSION_7, GPIO2/13 */ + writel(V_PAD_CTRL, iomuxbase + 0x73C); + break; + case IMX6_CPUTYPE_IMX6D: + case IMX6_CPUTYPE_IMX6Q: + writel(0x05, iomuxbase + 0x324); /* VERSION_0, GPIO2/10 */ + writel(V_PAD_CTRL, iomuxbase + 0x70c); + writel(0x05, iomuxbase + 0x338); /* VERSION_1, GPIO2/15 */ + writel(V_PAD_CTRL, iomuxbase + 0x720); + writel(0x05, iomuxbase + 0x31c); /* VERSION_2, GPIO2/8 */ + writel(V_PAD_CTRL, iomuxbase + 0x704); + writel(0x05, iomuxbase + 0x320); /* VERSION_3, GPIO2/9 */ + writel(V_PAD_CTRL, iomuxbase + 0x708); + writel(0x05, iomuxbase + 0x32c); /* VERSION_4, GPIO2/12 */ + writel(V_PAD_CTRL, iomuxbase + 0x714); + writel(0x05, iomuxbase + 0x334); /* VERSION_5, GPIO2/14 */ + writel(V_PAD_CTRL, iomuxbase + 0x71c); + writel(0x05, iomuxbase + 0x328); /* VERSION_6, GPIO2/11 */ + writel(V_PAD_CTRL, iomuxbase + 0x710); + writel(0x05, iomuxbase + 0x330); /* VERSION_7, GPIO2/13 */ + writel(V_PAD_CTRL, iomuxbase + 0x718); + break; + default: + pr_err("Invalid SoC! i.MX6S/DL or i.MX6Q expected (found %d)\n", cpu_type); + return -1; + } + + imx6_gpio_direction_input(gpiobase, 13); + imx6_gpio_direction_input(gpiobase, 11); + imx6_gpio_direction_input(gpiobase, 14); + imx6_gpio_direction_input(gpiobase, 12); + imx6_gpio_direction_input(gpiobase, 9); + imx6_gpio_direction_input(gpiobase, 8); + imx6_gpio_direction_input(gpiobase, 15); + imx6_gpio_direction_input(gpiobase, 10); + + reg = readl(gpiobase + 0x00); + var |= imx6_gpio_val(gpiobase, 13) << 7; + var |= imx6_gpio_val(gpiobase, 11) << 6; + var |= imx6_gpio_val(gpiobase, 14) << 5; + var |= imx6_gpio_val(gpiobase, 12) << 4; + var |= imx6_gpio_val(gpiobase, 9) << 3; + var |= imx6_gpio_val(gpiobase, 8) << 2; + var |= imx6_gpio_val(gpiobase, 15) << 1; + var |= imx6_gpio_val(gpiobase, 10) << 0; + + return (~var) & 0xff; +} diff --git a/arch/arm/boards/skov-imx6/version.h b/arch/arm/boards/skov-imx6/version.h new file mode 100644 index 0000000000..a5d205fe2e --- /dev/null +++ b/arch/arm/boards/skov-imx6/version.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SKOV_VERSION_H +#define __SKOV_VERSION_H + +unsigned skov_imx6_get_version(void); + +#endif /* __SKOV_VERSION_H */ diff --git a/arch/arm/boards/skov-imx8mp/Makefile b/arch/arm/boards/skov-imx8mp/Makefile new file mode 100644 index 0000000000..35d8640087 --- /dev/null +++ b/arch/arm/boards/skov-imx8mp/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/skov-imx8mp/board.c b/arch/arm/boards/skov-imx8mp/board.c new file mode 100644 index 0000000000..3cb7a8752a --- /dev/null +++ b/arch/arm/boards/skov-imx8mp/board.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "linux/kernel.h" +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <envfs.h> +#include <environment.h> +#include <globalvar.h> +#include <gpio.h> +#include <init.h> +#include <io.h> +#include <mach/imx/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/iomux-mx8mp.h> + +struct skov_imx8mp_priv { + struct device *dev; + int variant_id; +}; + +static struct skov_imx8mp_priv *skov_imx8mp_priv; + +#define GPIO_HW_VARIANT {\ + {IMX_GPIO_NR(1, 8), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var0"}, \ + {IMX_GPIO_NR(1, 9), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var1"}, \ + {IMX_GPIO_NR(1, 10), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var2"}, \ + {IMX_GPIO_NR(1, 11), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var3"}, \ + {IMX_GPIO_NR(1, 12), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var4"}, \ + {IMX_GPIO_NR(1, 13), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var5"}, \ + {IMX_GPIO_NR(1, 14), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var6"}, \ + {IMX_GPIO_NR(1, 15), GPIOF_DIR_IN | GPIOF_ACTIVE_HIGH, "var7"}, \ +} + +struct skov_imx8mp_storage { + const char *name; + const char *env_path; + const char *dev_path; + enum bootsource bootsource; + int bootsource_ext_id; + bool mmc_boot_part; +}; + +enum skov_imx8mp_boot_source { + SKOV_BOOT_SOURCE_EMMC, + SKOV_BOOT_SOURCE_SD, + SKOV_BOOT_SOURCE_UNKNOWN, +}; + +static const struct skov_imx8mp_storage skov_imx8mp_storages[] = { + [SKOV_BOOT_SOURCE_EMMC] = { + /* default boot source */ + .name = "eMMC", + .env_path = "/chosen/environment-emmc", + .dev_path = "/dev/mmc2", + .bootsource = BOOTSOURCE_MMC, + .bootsource_ext_id = 2, + .mmc_boot_part = true, + }, + [SKOV_BOOT_SOURCE_SD] = { + .name = "SD", + .env_path = "/chosen/environment-sd", + .dev_path = "/dev/mmc1.barebox", + .bootsource = BOOTSOURCE_MMC, + .bootsource_ext_id = 1, + }, +}; + +struct board_description { + const char *dts_compatible; + const char *dts_compatible_hdmi; + unsigned flags; +}; + +#define SKOV_IMX8MP_HAS_HDMI BIT(0) + +static const struct board_description imx8mp_variants[] = { + [0] = { + .dts_compatible = "skov,imx8mp-skov-revb-lt6", + }, + [1] = { + .dts_compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", + .dts_compatible_hdmi = "skov,imx8mp-skov-revb-hdmi", + .flags = SKOV_IMX8MP_HAS_HDMI, + }, + [2] = { + .dts_compatible = "skov,imx8mp-skov-revc-bd500", + }, +}; + +static const struct board_description imx8mp_basic_variant = { + .dts_compatible = "skov,imx8mp-skov-basic", +}; + +static int skov_imx8mp_fixup(struct device_node *root, void *data) +{ + struct device_node *chosen = of_create_node(root, "/chosen"); + const char *of_board = "skov,imx8mp-board-version"; + struct skov_imx8mp_priv *priv = data; + struct device *dev = priv->dev; + int ret; + + ret = of_property_write_u32(chosen, of_board, priv->variant_id); + if (ret) + dev_err(dev, "Failed to fixup %s: %pe\n", of_board, + ERR_PTR(ret)); + + return 0; +} + +static int skov_imx8mp_get_variant_id(uint *id) +{ + struct gpio gpios_rev[] = GPIO_HW_VARIANT; + struct device_node *gpio_np; + u32 hw_rev; + int ret; + + gpio_np = of_find_node_by_name_address(NULL, "gpio@30200000"); + if (!gpio_np) + return -ENODEV; + + ret = of_device_ensure_probed(gpio_np); + if (ret) + return ret; + + ret = gpio_array_to_id(gpios_rev, ARRAY_SIZE(gpios_rev), &hw_rev); + if (ret) + goto exit_get_id; + + *id = hw_rev; + + return 0; +exit_get_id: + pr_err("Failed to read gpio ID: %pe\n", ERR_PTR(ret)); + return ret; +} + +static int skov_imx8mp_get_hdmi(struct device *dev) +{ + const char *env = "state.display.external"; + struct device_node *state_np; + unsigned int val = 0; + int ret; + + state_np = of_find_node_by_name_address(NULL, "state"); + if (!state_np) { + dev_err(dev, "Failed to find state node\n"); + return -ENODEV; + } + + ret = of_device_ensure_probed(state_np); + if (ret) { + dev_err(dev, "Failed to probe state node: %pe\n", ERR_PTR(ret)); + return ret; + } + + ret = getenv_uint(env, &val); + if (ret) { + dev_err(dev, "Failed to read %s: %pe\n", env, ERR_PTR(ret)); + return ret; + } + + return val; +} + +static int skov_imx8mp_init_variant(struct skov_imx8mp_priv *priv) +{ + const struct board_description *variant; + struct device *dev = priv->dev; + const char *compatible; + unsigned int v = 0; + int ret; + + ret = skov_imx8mp_get_variant_id(&v); + if (ret) + return ret; + + priv->variant_id = v; + + if (v >= ARRAY_SIZE(imx8mp_variants)) { + dev_warn(dev, "Unsupported variant %u. Fall back to basic variant\n", v); + variant = &imx8mp_basic_variant; + } else { + variant = &imx8mp_variants[v]; + } + + if (variant->flags & SKOV_IMX8MP_HAS_HDMI) { + ret = skov_imx8mp_get_hdmi(dev); + if (ret < 0) + return ret; + + if (ret) + compatible = variant->dts_compatible_hdmi; + else + compatible = variant->dts_compatible; + } else { + compatible = variant->dts_compatible; + } + + of_prepend_machine_compatible(NULL, compatible); + + return 0; +} + +static void skov_imx8mp_enable_env(struct device *dev, + const struct skov_imx8mp_storage *st, + bool *enabled) +{ + int ret; + + if (bootsource_get() != st->bootsource || + bootsource_get_instance() != st->bootsource_ext_id) + return; + + ret = of_device_enable_path(st->env_path); + if (ret) { + dev_err(dev, "Failed to enable environment path: %s, %pe\n", + st->env_path, ERR_PTR(ret)); + return; + } + + *enabled = true; +} + +static void skov_imx8mp_add_bbu(struct device *dev, + const struct skov_imx8mp_storage *st, + bool default_env) +{ + unsigned long flags = 0; + int ret; + + if (default_env) + flags |= BBU_HANDLER_FLAG_DEFAULT; + + if (st->mmc_boot_part) { + ret = imx8m_bbu_internal_mmcboot_register_handler(st->name, + st->dev_path, + flags); + } else { + ret = imx8m_bbu_internal_mmc_register_handler(st->name, + st->dev_path, + flags); + } + if (ret) + dev_err(dev, "Failed to register %s BBU handler: %pe\n", + st->name, ERR_PTR(ret)); +} + +static void skov_imx8mp_init_storage(struct device *dev) +{ + int default_boot_src = SKOV_BOOT_SOURCE_EMMC; + int i; + + for (i = 0; i < ARRAY_SIZE(skov_imx8mp_storages); i++) { + bool enabled_env = false; + + skov_imx8mp_enable_env(dev, &skov_imx8mp_storages[i], + &enabled_env); + if (enabled_env) + default_boot_src = i; + } + + for (i = 0; i < ARRAY_SIZE(skov_imx8mp_storages); i++) + skov_imx8mp_add_bbu(dev, &skov_imx8mp_storages[i], + i == default_boot_src); +} + +static int skov_imx8mp_probe(struct device *dev) +{ + struct skov_imx8mp_priv *priv; + int ret; + + priv = xzalloc(sizeof(*priv)); + priv->dev = dev; + skov_imx8mp_priv = priv; + + skov_imx8mp_init_storage(dev); + + skov_imx8mp_init_variant(priv); + + ret = of_register_fixup(skov_imx8mp_fixup, priv); + if (ret) + dev_err(dev, "Failed to register fixup: %pe\n", ERR_PTR(ret)); + + return 0; +} + +static const struct of_device_id skov_imx8mp_of_match[] = { + /* generic, barebox specific compatible for all board variants */ + { .compatible = "skov,imx8mp" }, + { /* Sentinel */ } +}; +BAREBOX_DEEP_PROBE_ENABLE(skov_imx8mp_of_match); + +static struct driver skov_imx8mp_board_driver = { + .name = "skov-imx8m", + .probe = skov_imx8mp_probe, + .of_compatible = skov_imx8mp_of_match, +}; +coredevice_platform_driver(skov_imx8mp_board_driver); diff --git a/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg b/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg new file mode 100644 index 0000000000..6ea2e6c68e --- /dev/null +++ b/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/skov-imx8mp/lowlevel.c b/arch/arm/boards/skov-imx8mp/lowlevel.c new file mode 100644 index 0000000000..c35ffe526d --- /dev/null +++ b/arch/arm/boards/skov-imx8mp/lowlevel.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/xload.h> +#include <mfd/pca9450.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <soc/imx8m/ddr.h> + +extern char __dtb_z_imx8mp_skov_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* + * Increase VDD_ARM to 0.95V to avoid issues in case software after + * Barebox switches to the OD ARM frequency without reprogramming the + * PMIC first. + */ + { PCA9450_BUCK2OUT_DVS0, 0x1C }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +extern struct dram_timing_info imx8mp_skov_dram_timing; + +static void start_atf(struct dram_timing_info *dram_timing) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mp_early_clock_init(); + + power_init_board(); + + imx8mp_ddr_init(dram_timing, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); +} + +/* + * Power-on execution flow of imx8mp_skov_start() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void +imx8mp_skov_start(struct dram_timing_info *dram_timing, void *dtb) +{ + setup_uart(); + + start_atf(dram_timing); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(dtb); +} + +ENTRY_FUNCTION(start_skov_imx8mp, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + imx8mp_skov_start(&imx8mp_skov_dram_timing, + __dtb_z_imx8mp_skov_start); +} diff --git a/arch/arm/boards/skov-imx8mp/lpddr4-timing.c b/arch/arm/boards/skov-imx8mp/lpddr4-timing.c new file mode 100644 index 0000000000..a93506b0bd --- /dev/null +++ b/arch/arm/boards/skov-imx8mp/lpddr4-timing.c @@ -0,0 +1,1125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x402 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x302 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x302 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0x599 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* Samsung K4F6E3S4HB-MGCL ddr timing config params */ +struct dram_timing_info imx8mp_skov_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + diff --git a/arch/arm/boards/solidrun-cubox/Makefile b/arch/arm/boards/solidrun-cubox/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/solidrun-cubox/Makefile +++ b/arch/arm/boards/solidrun-cubox/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-cubox/board.c b/arch/arm/boards/solidrun-cubox/board.c index aac93afb0c..3c12c28594 100644 --- a/arch/arm/boards/solidrun-cubox/board.c +++ b/arch/arm/boards/solidrun-cubox/board.c @@ -1,22 +1,9 @@ -/* - * Copyright (C) 2013 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <init.h> -#include <mach/bbu.h> +#include <mach/mvebu/bbu.h> static int cubox_devices_init(void) { diff --git a/arch/arm/boards/solidrun-cubox/config.h b/arch/arm/boards/solidrun-cubox/config.h deleted file mode 100644 index ca15136817..0000000000 --- a/arch/arm/boards/solidrun-cubox/config.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/solidrun-cubox/lowlevel.c b/arch/arm/boards/solidrun-cubox/lowlevel.c index ec63986b38..8f1515e3b2 100644 --- a/arch/arm/boards/solidrun-cubox/lowlevel.c +++ b/arch/arm/boards/solidrun-cubox/lowlevel.c @@ -1,29 +1,16 @@ -/* - * Copyright (C) 2013 - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +// SPDX-FileCopyrightText: 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_dove_cubox_bb_start[]; -ENTRY_FUNCTION(start_solidrun_cubox, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_solidrun_cubox, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg index 6902fe113f..eb34d8b54c 100644 --- a/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg index ac336e532b..6fd7ac903b 100644 --- a/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg index c8e5a0ced1..4f4bebc4b2 100644 --- a/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg +++ b/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg index affb011dd9..5db0c91816 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg index 91322f4603..20e5b2782b 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg index 384e6fde42..6144864c1a 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0045004D diff --git a/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg index 021b40b9ef..5f00cd900d 100644 --- a/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg +++ b/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg @@ -1,21 +1,7 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Boundary Devices +// SPDX-FileCopyrightText: 2013 SolidRun ltd. +// SPDX-FileCopyrightText: 2013 Jon Nettleton <jon.nettleton@gmail.com> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/Makefile b/arch/arm/boards/solidrun-microsom/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/solidrun-microsom/Makefile +++ b/arch/arm/boards/solidrun-microsom/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-microsom/board.c b/arch/arm/boards/solidrun-microsom/board.c index 155199ff78..c55dcdd74f 100644 --- a/arch/arm/boards/solidrun-microsom/board.c +++ b/arch/arm/boards/solidrun-microsom/board.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <asm/armlinux.h> #include <asm/io.h> @@ -20,10 +9,10 @@ #include <envfs.h> #include <gpio.h> #include <init.h> -#include <mach/bbu.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <linux/clk.h> #include <linux/sizes.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg index eb7bc8486d..b049cfc746 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> #include "800mhz-32b.imxcfg" #include "800mhz-2x128mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg index 8930012885..b6634446f3 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> #include "800mhz-64b.imxcfg" #include "800mhz-4x128mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg index 4eb937a717..e1447b9d5a 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> #include "1066mhz-64b.imxcfg" #include "1066mhz-4x128mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg index 438bd8ea4d..ec9c3e385e 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> #include "1066mhz-64b.imxcfg" #include "1066mhz-4x256mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/lowlevel.c b/arch/arm/boards/solidrun-microsom/lowlevel.c index ea204e15f3..801678e777 100644 --- a/arch/arm/boards/solidrun-microsom/lowlevel.c +++ b/arch/arm/boards/solidrun-microsom/lowlevel.c @@ -1,7 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <asm/barebox-arm.h> #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> extern char __dtb_imx6dl_hummingboard_start[]; extern char __dtb_imx6q_hummingboard_start[]; diff --git a/arch/arm/boards/stm32mp13xx-dk/Makefile b/arch/arm/boards/stm32mp13xx-dk/Makefile new file mode 100644 index 0000000000..a031ae91bd --- /dev/null +++ b/arch/arm/boards/stm32mp13xx-dk/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o diff --git a/arch/arm/boards/stm32mp13xx-dk/board.c b/arch/arm/boards/stm32mp13xx-dk/board.c new file mode 100644 index 0000000000..a13d934a27 --- /dev/null +++ b/arch/arm/boards/stm32mp13xx-dk/board.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <driver.h> +#include <init.h> +#include <mach/stm32mp/bbu.h> +#include <deep-probe.h> +#include <asm/mach-types.h> + +static int stm32mp13xx_dk_probe(struct device *dev) +{ + if (machine_is_pcaaxs1()) + return 1; + stm32mp_bbu_mmc_fip_register("sd", "/dev/mmc0", BBU_HANDLER_FLAG_DEFAULT); + return 0; +} + +static const struct of_device_id stm32mp13xx_dk_of_match[] = { + { .compatible = "st,stm32mp135f-dk" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(stm32mp13xx_dk_of_match); + +static struct driver stm32mp13xx_dk_board_driver = { + .name = "board-stm32mp13xx_dk", + .probe = stm32mp13xx_dk_probe, + .of_compatible = stm32mp13xx_dk_of_match, +} ; +device_platform_driver(stm32mp13xx_dk_board_driver); diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c deleted file mode 100644 index f15ae0b4af..0000000000 --- a/arch/arm/boards/stm32mp157c-dk2/board.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <common.h> -#include <linux/sizes.h> -#include <init.h> -#include <asm/memory.h> -#include <mach/stm32.h> -#include <mach/bbu.h> - -static int dk2_mem_init(void) -{ - if (!of_machine_is_compatible("st,stm32mp157c-dk2")) - return 0; - - arm_add_mem_device("ram0", STM32_DDR_BASE, SZ_512M); - - return 0; -} -mem_initcall(dk2_mem_init); - -static int dk2_postcore_init(void) -{ - if (!of_machine_is_compatible("st,stm32mp157c-dk2")) - return 0; - - stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", - BBU_HANDLER_FLAG_DEFAULT); - - return 0; -} -postcore_initcall(dk2_postcore_init); diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c deleted file mode 100644 index 566ace79c9..0000000000 --- a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include <common.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/stm32.h> -#include <debug_ll.h> - -extern char __dtb_z_stm32mp157c_dk2_start[]; - -ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2) -{ - void *fdt; - - arm_cpu_lowlevel_init(); - - fdt = __dtb_z_stm32mp157c_dk2_start + get_runtime_offset(); - - barebox_arm_entry(STM32_DDR_BASE, SZ_512M, fdt); -} diff --git a/arch/arm/boards/stm32mp15x-ev1/Makefile b/arch/arm/boards/stm32mp15x-ev1/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/stm32mp15x-ev1/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/stm32mp15x-ev1/board.c b/arch/arm/boards/stm32mp15x-ev1/board.c new file mode 100644 index 0000000000..fd58e2817b --- /dev/null +++ b/arch/arm/boards/stm32mp15x-ev1/board.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <mach/stm32mp/bbu.h> + +static int ed1_probe(struct device *dev) +{ + int flags; + + flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", flags); + + flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; + stm32mp_bbu_mmc_register_handler("emmc", "/dev/mmc1.ssbl", flags); + + if (bootsource_get_instance() == 0) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + barebox_set_model("STM32MP157C-ED1"); + + return 0; +} + +/* ED1 is the SoM on top of the EV1 */ +static const struct of_device_id ed1_of_match[] = { + { .compatible = "st,stm32mp157c-ed1" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(ed1_of_match); + +static struct driver ed1_board_driver = { + .name = "board-stm32mp15x-ed1", + .probe = ed1_probe, + .of_compatible = ed1_of_match, +}; +postcore_platform_driver(ed1_board_driver); diff --git a/arch/arm/boards/stm32mp15x-ev1/lowlevel.c b/arch/arm/boards/stm32mp15x-ev1/lowlevel.c new file mode 100644 index 0000000000..13f16f8dcb --- /dev/null +++ b/arch/arm/boards/stm32mp15x-ev1/lowlevel.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/stm32mp/entry.h> +#include <debug_ll.h> + +extern char __dtb_z_stm32mp157c_ev1_start[]; + +static void setup_uart(void) +{ + /* first stage has set up the UART, so nothing to do here */ + putc_ll('>'); +} + +ENTRY_FUNCTION(start_stm32mp15x_ev1, r0, r1, r2) +{ + void *fdt; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_z_stm32mp157c_ev1_start + get_runtime_offset(); + + stm32mp1_barebox_entry(fdt); +} diff --git a/arch/arm/boards/stm32mp15xx-dkx/Makefile b/arch/arm/boards/stm32mp15xx-dkx/Makefile new file mode 100644 index 0000000000..5678718188 --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/stm32mp15xx-dkx/board.c b/arch/arm/boards/stm32mp15xx-dkx/board.c new file mode 100644 index 0000000000..1783c5ca17 --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/board.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <init.h> +#include <mach/stm32mp/bbu.h> +#include <deep-probe.h> + +static int dkx_probe(struct device *dev) +{ + const void *model; + + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl", + BBU_HANDLER_FLAG_DEFAULT); + + if (dev_get_drvdata(dev, &model) == 0) + barebox_set_model(model); + + barebox_set_hostname("stm32mp15xx-dkx"); + + return 0; +} + +static const struct of_device_id dkx_of_match[] = { + { .compatible = "st,stm32mp157a-dk1", .data = "STM32MP157A-DK1" }, + { .compatible = "st,stm32mp157c-dk2", .data = "STM32MP157C-DK2" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(dkx_of_match); + +static struct driver dkx_board_driver = { + .name = "board-stm32mp15xx-dkx", + .probe = dkx_probe, + .of_compatible = dkx_of_match, +}; +postcore_platform_driver(dkx_board_driver); diff --git a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c new file mode 100644 index 0000000000..402658d592 --- /dev/null +++ b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <mach/stm32mp/entry.h> +#include <debug_ll.h> +#include <mach/stm32mp/revision.h> + +extern char __dtb_z_stm32mp157c_dk2_start[]; +extern char __dtb_z_stm32mp157a_dk1_start[]; + +static void setup_uart(void) +{ + /* first stage has set up the UART, so nothing to do here */ + putc_ll('>'); +} + +ENTRY_FUNCTION(start_stm32mp15xx_dkx, r0, r1, r2) +{ + void *fdt; + u32 cputype; + int err; + + stm32mp_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + err = __stm32mp15_get_cpu_type(&cputype); + if (!err && cputype == CPU_STM32MP157Axx) + fdt = __dtb_z_stm32mp157a_dk1_start; + else + fdt = __dtb_z_stm32mp157c_dk2_start; + + stm32mp1_barebox_entry(fdt + get_runtime_offset()); +} diff --git a/arch/arm/boards/technexion-pico-hobbit/Makefile b/arch/arm/boards/technexion-pico-hobbit/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/technexion-pico-hobbit/Makefile +++ b/arch/arm/boards/technexion-pico-hobbit/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/technexion-pico-hobbit/board.c b/arch/arm/boards/technexion-pico-hobbit/board.c index f52f827f46..202b76bc8e 100644 --- a/arch/arm/boards/technexion-pico-hobbit/board.c +++ b/arch/arm/boards/technexion-pico-hobbit/board.c @@ -1,21 +1,5 @@ -/* - * Copyright (C) 2017 Michael Grzeschik, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2017 Michael Grzeschik, Pengutronix #include <asm/armlinux.h> #include <asm/io.h> @@ -25,10 +9,10 @@ #include <envfs.h> #include <gpio.h> #include <init.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> -#include <mach/imx6.h> -#include <mach/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6.h> +#include <mach/imx/bbu.h> #include <linux/sizes.h> #include <linux/phy.h> #include <mfd/imx6q-iomuxc-gpr.h> diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg index 12cda04e60..00ac4ef8ec 100644 --- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg index 0a1915b982..9152039507 100644 --- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c index f59c424dec..7cc7c12d84 100644 --- a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c +++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c @@ -1,12 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-regs.h> +#include <mach/imx/imx6-regs.h> #include <io.h> #include <debug_ll.h> -#include <mach/esdctl.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/esdctl.h> #include <asm/cache.h> #include <asm/sections.h> #include <image-metadata.h> diff --git a/arch/arm/boards/technexion-wandboard/Makefile b/arch/arm/boards/technexion-wandboard/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/technexion-wandboard/Makefile +++ b/arch/arm/boards/technexion-wandboard/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/technexion-wandboard/board.c b/arch/arm/boards/technexion-wandboard/board.c index 2e1f6254c2..a594adb411 100644 --- a/arch/arm/boards/technexion-wandboard/board.c +++ b/arch/arm/boards/technexion-wandboard/board.c @@ -1,13 +1,4 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <asm/armlinux.h> #include <asm/io.h> @@ -17,10 +8,10 @@ #include <envfs.h> #include <gpio.h> #include <init.h> -#include <mach/bbu.h> -#include <mach/generic.h> -#include <mach/imx6-regs.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/imx6.h> #include <mfd/imx6q-iomuxc-gpr.h> #include <linux/sizes.h> #include <linux/phy.h> diff --git a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg index 68cb08e200..61425976ec 100644 --- a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg +++ b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg @@ -1,4 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + loadaddr 0x00907000 soc imx6 max_load_size 0x11000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c index af04eadc9f..d29e2c9b24 100644 --- a/arch/arm/boards/technexion-wandboard/lowlevel.c +++ b/arch/arm/boards/technexion-wandboard/lowlevel.c @@ -1,25 +1,17 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-mmdc.h> -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6.h> -#include <mach/xload.h> -#include <mach/esdctl.h> +#include <mach/imx/imx6-mmdc.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> #include <serial/imx-uart.h> static void __udelay(int us) diff --git a/arch/arm/boards/telit-evk-pro3/Makefile b/arch/arm/boards/telit-evk-pro3/Makefile index e11fd5b692..d59545033d 100644 --- a/arch/arm/boards/telit-evk-pro3/Makefile +++ b/arch/arm/boards/telit-evk-pro3/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c index f6ee715bb1..43f9cbdf3a 100644 --- a/arch/arm/boards/telit-evk-pro3/init.c +++ b/arch/arm/boards/telit-evk-pro3/init.c @@ -1,17 +1,6 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2013 Fabio Porcedda <fabio.porcedda@gmail.com>, Telit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2007 Sascha Hauer, Pengutronix +// SPDX-FileCopyrightText: 2013 Fabio Porcedda <fabio.porcedda@gmail.com>, Telit #include <asm/armlinux.h> #include <common.h> @@ -19,10 +8,11 @@ #include <init.h> #include <linux/clk.h> #include <linux/mtd/nand.h> -#include <mach/at91_rstc.h> -#include <mach/at91sam9_smc.h> -#include <mach/board.h> -#include <mach/iomux.h> +#include <linux/mtd/rawnand.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9_smc.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> #include <nand.h> #define BOOTSTRAP_SIZE 0xC0000 diff --git a/arch/arm/boards/telit-evk-pro3/lowlevel.c b/arch/arm/boards/telit-evk-pro3/lowlevel.c index 7f52f824df..550a0740c5 100644 --- a/arch/arm/boards/telit-evk-pro3/lowlevel.c +++ b/arch/arm/boards/telit-evk-pro3/lowlevel.c @@ -7,14 +7,12 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_telit_evk_pro3, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/terasic-de0-nano-soc/Makefile b/arch/arm/boards/terasic-de0-nano-soc/Makefile index 8c927fe291..ea898309d7 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/Makefile +++ b/arch/arm/boards/terasic-de0-nano-soc/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += lowlevel.o board.o pbl-y += lowlevel.o diff --git a/arch/arm/boards/terasic-de0-nano-soc/board.c b/arch/arm/boards/terasic-de0-nano-soc/board.c index 8e69319d17..b4502f552a 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/board.c +++ b/arch/arm/boards/terasic-de0-nano-soc/board.c @@ -1,14 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <types.h> #include <driver.h> #include <init.h> #include <asm/armlinux.h> +#include <linux/mdio.h> #include <linux/micrel_phy.h> #include <linux/phy.h> #include <linux/sizes.h> #include <fcntl.h> #include <fs.h> -#include <mach/cyclone5-regs.h> +#include <mach/socfpga/cyclone5-regs.h> static int phy_fixup(struct phy_device *dev) { @@ -16,15 +19,15 @@ static int phy_fixup(struct phy_device *dev) * min rx data delay, max rx/tx clock delay, * min rx/tx control delay */ - phy_write_mmd_indirect(dev, 4, 2, 0); - phy_write_mmd_indirect(dev, 5, 2, 0); - phy_write_mmd_indirect(dev, 8, 2, 0x003ff); + phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff); return 0; } static int socfpga_init(void) { - if (!of_machine_is_compatible("terasic,de0-nano-soc")) + if (!of_machine_is_compatible("terasic,de0-atlas")) return 0; if (IS_ENABLED(CONFIG_PHYLIB)) diff --git a/arch/arm/boards/terasic-de0-nano-soc/config.h b/arch/arm/boards/terasic-de0-nano-soc/config.h deleted file mode 100644 index da84fa5f6b..0000000000 --- a/arch/arm/boards/terasic-de0-nano-soc/config.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing */ diff --git a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c index 80cb270313..27af250232 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-de0-nano-soc/iocsr_config_cyclone5.c @@ -27,9 +27,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/cyclone5-scan-manager.h> +#include <mach/socfpga/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, 0x0A804001, diff --git a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c index 46f6477a0f..71121b6d4c 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c +++ b/arch/arm/boards/terasic-de0-nano-soc/lowlevel.c @@ -1,4 +1,4 @@ -#define SECT(name) __attribute__((section("terasic_de0_nano_soc_" #name))) name +// SPDX-License-Identifier: GPL-2.0-only #include "sdram_config.h" #include "pinmux_config.c" @@ -9,7 +9,7 @@ #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" -#include <mach/lowlevel.h> +#include <mach/socfpga/lowlevel.h> SOCFPGA_C5_ENTRY(start_socfpga_de0_nano_soc, socfpga_cyclone5_de0_nano_soc, SZ_1G); SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_de0_nano_soc_xload, SZ_1G); diff --git a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c index c061901814..9c5c7f18ba 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c +++ b/arch/arm/boards/terasic-de0-nano-soc/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c index 1efe4f99c2..52be44f897 100644 --- a/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-de0-nano-soc/sequencer_auto_ac_init.c @@ -27,7 +27,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/terasic-de10-nano/Makefile b/arch/arm/boards/terasic-de10-nano/Makefile new file mode 100644 index 0000000000..ea898309d7 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += lowlevel.o board.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/terasic-de10-nano/board.c b/arch/arm/boards/terasic-de10-nano/board.c new file mode 100644 index 0000000000..e553e26da8 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/board.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <types.h> +#include <driver.h> +#include <init.h> +#include <asm/armlinux.h> +#include <linux/mdio.h> +#include <linux/micrel_phy.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <fcntl.h> +#include <fs.h> +#include <mach/socfpga/cyclone5-regs.h> + +static int phy_fixup(struct phy_device *dev) +{ + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff); + return 0; +} + +static int socfpga_init(void) +{ + if (!of_machine_is_compatible("terasic,de10-nano")) + return 0; + + if (IS_ENABLED(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, phy_fixup); + + return 0; +} +console_initcall(socfpga_init); diff --git a/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c new file mode 100644 index 0000000000..2f30d836d6 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/iocsr_config_cyclone5.c @@ -0,0 +1,678 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <mach/socfpga/cyclone5-scan-manager.h> + +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] + = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00020000, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] + = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00020000, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] + = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x200300C0, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x00010000, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] + = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x180D0000, + 0x71C06806, + 0x01450340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x01450340, + 0xD00A281A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0xCAAAA3DD, + 0xF6D5551E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xD559647A, + 0x1ECAAAA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0x8B2CA3DD, + 0xF6D9651E, + 0x034AB2C8, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8AAAA3D5, + 0xF6D9651E, + 0x034AB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8B2CA3D5, + 0xF6D9651E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0x48F6D965, + 0x000352D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; diff --git a/arch/arm/boards/terasic-de10-nano/lowlevel.c b/arch/arm/boards/terasic-de10-nano/lowlevel.c new file mode 100644 index 0000000000..74c8aec99d --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/lowlevel.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "sdram_config.h" +#include "pinmux_config.c" +#include "pll_config.h" +#include "sequencer_defines.h" +#include "sequencer_auto.h" +#include "sequencer_auto_inst_init.c" +#include "sequencer_auto_ac_init.c" +#include "iocsr_config_cyclone5.c" + +#include <mach/socfpga/lowlevel.h> + +SOCFPGA_C5_ENTRY(start_socfpga_de10_nano, socfpga_cyclone5_de10_nano, SZ_1G); +SOCFPGA_C5_XLOAD_ENTRY(start_socfpga_de10_nano_xload, SZ_1G); diff --git a/arch/arm/boards/terasic-de10-nano/pinmux_config.c b/arch/arm/boards/terasic-de10-nano/pinmux_config.c new file mode 100644 index 0000000000..7dbe1c1d1f --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/pinmux_config.c @@ -0,0 +1,241 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <common.h> + +/* pin MUX configuration data */ +static unsigned long sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/arch/arm/boards/terasic-de10-nano/pll_config.h b/arch/arm/boards/terasic-de10-nano/pll_config.h new file mode 100644 index 0000000000..d78eaae98a --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/pll_config.h @@ -0,0 +1,107 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (3125000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (12500000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (3) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/terasic-de10-nano/sdram_config.h b/arch/arm/boards/terasic-de10-nano/sdram_config.h new file mode 100644 index 0000000000..8f084021d5 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sdram_config.h @@ -0,0 +1,112 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (7) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (3120) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (6) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (14) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (20) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0) +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x10441) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x78) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200) + +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088) +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210) +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543) +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0xF) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0xF) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x1) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x1FF) + +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR (2) +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC (2) +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2) + +#endif /*#ifndef__SDRAM_CONFIG_H */ diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto.h b/arch/arm/boards/terasic-de10-nano/sequencer_auto.h new file mode 100644 index 0000000000..34dc3108aa --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto.h @@ -0,0 +1,225 @@ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_ac_mrs1 0x04 +#define __RW_MGR_ac_mrs3 0x06 +#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C +#define __RW_MGR_ac_act_1 0x11 +#define __RW_MGR_ac_write_postdata 0x1A +#define __RW_MGR_ac_act_0 0x10 +#define __RW_MGR_ac_des 0x0D +#define __RW_MGR_ac_init_reset_1_cke_0 0x01 +#define __RW_MGR_ac_write_data 0x19 +#define __RW_MGR_ac_init_reset_0_cke_0 0x00 +#define __RW_MGR_ac_read_bank_0_1_norden 0x22 +#define __RW_MGR_ac_pre_all 0x12 +#define __RW_MGR_ac_mrs0_user 0x02 +#define __RW_MGR_ac_mrs0_dll_reset 0x03 +#define __RW_MGR_ac_read_bank_0_0 0x1D +#define __RW_MGR_ac_write_bank_0_col_1 0x16 +#define __RW_MGR_ac_read_bank_0_1 0x1F +#define __RW_MGR_ac_write_bank_1_col_0 0x15 +#define __RW_MGR_ac_write_bank_1_col_1 0x17 +#define __RW_MGR_ac_write_bank_0_col_0 0x14 +#define __RW_MGR_ac_read_bank_1_0 0x1E +#define __RW_MGR_ac_mrs1_mirr 0x0A +#define __RW_MGR_ac_read_bank_1_1 0x20 +#define __RW_MGR_ac_des_odt_1 0x0E +#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09 +#define __RW_MGR_ac_zqcl 0x07 +#define __RW_MGR_ac_write_predata 0x18 +#define __RW_MGR_ac_mrs0_user_mirr 0x08 +#define __RW_MGR_ac_ref 0x13 +#define __RW_MGR_ac_nop 0x0F +#define __RW_MGR_ac_rdimm 0x23 +#define __RW_MGR_ac_mrs2_mirr 0x0B +#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B +#define __RW_MGR_ac_read_en 0x21 +#define __RW_MGR_ac_mrs3_mirr 0x0C +#define __RW_MGR_ac_mrs2 0x05 +#define __RW_MGR_CONTENT_ac_mrs1 0x10090044 +#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000 +#define __RW_MGR_CONTENT_ac_act_1 0x106B0000 +#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000 +#define __RW_MGR_CONTENT_ac_act_0 0x10680000 +#define __RW_MGR_CONTENT_ac_des 0x30780000 +#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000 +#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000 +#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000 +#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008 +#define __RW_MGR_CONTENT_ac_pre_all 0x10280400 +#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080431 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080530 +#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008 +#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000 +#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000 +#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000 +#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024 +#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008 +#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804C8 +#define __RW_MGR_CONTENT_ac_zqcl 0x10380400 +#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000 +#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080449 +#define __RW_MGR_CONTENT_ac_ref 0x10480000 +#define __RW_MGR_CONTENT_ac_nop 0x30780000 +#define __RW_MGR_CONTENT_ac_rdimm 0x10780000 +#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090008 +#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000 +#define __RW_MGR_CONTENT_ac_read_en 0x33780000 +#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000 +#define __RW_MGR_CONTENT_ac_mrs2 0x100A0010 + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_READ_B2B_WAIT2 0x6B +#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define __RW_MGR_REFRESH_ALL 0x14 +#define __RW_MGR_ZQCL 0x06 +#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define __RW_MGR_ACTIVATE_0_AND_1 0x0D +#define __RW_MGR_MRS2_MIRR 0x0A +#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define __RW_MGR_ACTIVATE_1 0x0F +#define __RW_MGR_MRS2 0x04 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define __RW_MGR_MRS1 0x03 +#define __RW_MGR_IDLE_LOOP1 0x7B +#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define __RW_MGR_MRS3 0x05 +#define __RW_MGR_IDLE_LOOP2 0x7A +#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define __RW_MGR_RDIMM_CMD 0x79 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define __RW_MGR_GUARANTEED_READ_CONT 0x54 +#define __RW_MGR_REFRESH_DELAY 0x15 +#define __RW_MGR_MRS3_MIRR 0x0B +#define __RW_MGR_IDLE 0x00 +#define __RW_MGR_READ_B2B 0x59 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define __RW_MGR_GUARANTEED_WRITE 0x18 +#define __RW_MGR_PRECHARGE_ALL 0x12 +#define __RW_MGR_SGLE_READ 0x7D +#define __RW_MGR_MRS0_USER_MIRR 0x0C +#define __RW_MGR_RETURN 0x01 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define __RW_MGR_MRS0_USER 0x07 +#define __RW_MGR_GUARANTEED_READ 0x4C +#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define __RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define __RW_MGR_MRS0_DLL_RESET 0x02 +#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define __RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define __RW_MGR_MRS1_MIRR 0x09 +#define __RW_MGR_READ_B2B_WAIT1 0x61 +#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980 +#define __RW_MGR_CONTENT_ZQCL 0x008380 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 +#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580 +#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 +#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880 +#define __RW_MGR_CONTENT_MRS2 0x008280 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS1 0x008200 +#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 +#define __RW_MGR_CONTENT_MRS3 0x008300 +#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 +#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 +#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 +#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680 +#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600 +#define __RW_MGR_CONTENT_IDLE 0x080000 +#define __RW_MGR_CONTENT_READ_B2B 0x040E88 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 +#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 +#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 +#define __RW_MGR_CONTENT_SGLE_READ 0x040F08 +#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 +#define __RW_MGR_CONTENT_RETURN 0x080680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_MRS0_USER 0x008100 +#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 +#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 +#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 +#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 +#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 +#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 +#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500 +#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c new file mode 100644 index 0000000000..05f1609674 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto_ac_init.c @@ -0,0 +1,67 @@ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t ac_rom_init_size = 36; +static const uint32_t ac_rom_init[36] = { + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090044, + 0x100a0010, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0024, + 0x10090008, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c new file mode 100644 index 0000000000..2ca79c65a5 --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_auto_inst_init.c @@ -0,0 +1,158 @@ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +static const uint32_t inst_rom_init_size = 127; +static const uint32_t inst_rom_init[127] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; diff --git a/arch/arm/boards/terasic-de10-nano/sequencer_defines.h b/arch/arm/boards/terasic-de10-nano/sequencer_defines.h new file mode 100644 index 0000000000..98d0475cbd --- /dev/null +++ b/arch/arm/boards/terasic-de10-nano/sequencer_defines.h @@ -0,0 +1,165 @@ +/* +Copyright (C) 2016 Intel Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _SEQUENCER_DEFINES_H_ +#define _SEQUENCER_DEFINES_H_ + +#define AC_ROM_MR1_MIRR 0000000100100 +#define AC_ROM_MR1_OCD_ENABLE +#define AC_ROM_MR2_MIRR 0000000001000 +#define AC_ROM_MR3_MIRR 0000000000000 +#define AC_ROM_MR0_CALIB +#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 +#define AC_ROM_MR0_DLL_RESET 0010100110000 +#define AC_ROM_MR0_MIRR 0010001001001 +#define AC_ROM_MR0 0010000110001 +#define AC_ROM_MR1 0000001000100 +#define AC_ROM_MR2 0000000010000 +#define AC_ROM_MR3 0000000000000 +#define AC_ROM_USER_ADD_0 0_0000_0000_0000 +#define AC_ROM_USER_ADD_1 0_0000_0000_1000 +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define AP_MODE 0 +#define ARRIAVGZ 0 +#define ARRIAV 0 +#define AVL_CLK_FREQ 67 +#define BFM_MODE 0 +#define BURST2 0 +#define CALIBRATE_BIT_SLIPS 0 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define CYCLONEV 1 +#define DDR2 0 +#define DDR3 1 +#define DDRX 1 +#define DM_PINS_ENABLED 1 +#define ENABLE_ASSERT 0 +#define ENABLE_BRINGUP_DEBUGGING 0 +#define ENABLE_DELAY_CHAIN_WRITE 0 +#define ENABLE_DQS_IN_CENTERING 1 +#define ENABLE_DQS_OUT_CENTERING 0 +#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 +#define ENABLE_INST_ROM_WRITE 1 +#define ENABLE_MARGIN_REPORT_GEN 0 +#define ENABLE_NON_DESTRUCTIVE_CALIB 0 +#define ENABLE_NON_DES_CAL_TEST 0 +#define ENABLE_NON_DES_CAL 0 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define ENABLE_TCL_DEBUG 0 +#define FAKE_CAL_FAIL 0 +#define FIX_READ_LATENCY 8 +#define FULL_RATE 1 +#define GUARANTEED_READ_BRINGUP_TEST 0 +#define HALF_RATE 0 +#define HARD_PHY 1 +#define HARD_VFIFO 1 +#define HCX_COMPAT_MODE 0 +#define HHP_HPS_SIMULATION 0 +#define HHP_HPS_VERIFICATION 0 +#define HHP_HPS 1 +#define HPS_HW 1 +#define HR_DDIO_OUT_HAS_THREE_REGS 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DM_OUT_RESERVE 0 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_DQ_OUT_RESERVE 0 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define LPDDR1 0 +#define LPDDR2 0 +#define LRDIMM 0 +#define MARGIN_VARIATION_TEST 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define MEM_ADDR_WIDTH 13 +#define MRS_MIRROR_PING_PONG_ATSO 0 +#define MULTIPLE_AFI_WLAT 0 +#define NON_DES_CAL 0 +#define NUM_SHADOW_REGS 1 +#define QDRII 0 +#define QUARTER_RATE 0 +#define RDIMM 0 +#define READ_AFTER_WRITE_CALIBRATION 1 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504c9 +#define RLDRAM3 0 +#define RLDRAMII 0 +#define RLDRAMX 0 +#define RUNTIME_CAL_REPORT 0 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_ADDRESS_WIDTH 15 +#define RW_MGR_MEM_BANK_WIDTH 3 +#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 +#define RW_MGR_MEM_CLK_EN_WIDTH 1 +#define RW_MGR_MEM_CONTROL_WIDTH 1 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_ODT_WIDTH 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_MR0_BL 1 +#define RW_MGR_MR0_CAS_LATENCY 3 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 +#define SET_FIX_READ_LATENCY_ENABLE 0 +#define SKEW_CALIBRATION 0 +#define SKIP_PTAP_0_DQS_EN_CAL 1 +#define STATIC_FULL_CALIBRATION 1 +#define STATIC_SIM_FILESET 0 +#define STATIC_SKIP_MEM_INIT 0 +#define STRATIXV 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 99 +#define TRACKING_ERROR_TEST 0 +#define TRACKING_WATCH_TEST 0 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 99 +#define USE_DQS_TRACKING 1 +#define USE_SHADOW_REGS 0 +#define USE_USER_RDIMM_VALUE 0 + +#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/arch/arm/boards/terasic-sockit/Makefile b/arch/arm/boards/terasic-sockit/Makefile index 8c927fe291..ea898309d7 100644 --- a/arch/arm/boards/terasic-sockit/Makefile +++ b/arch/arm/boards/terasic-sockit/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += lowlevel.o board.o pbl-y += lowlevel.o diff --git a/arch/arm/boards/terasic-sockit/board.c b/arch/arm/boards/terasic-sockit/board.c index ec68315998..a3537fe6e3 100644 --- a/arch/arm/boards/terasic-sockit/board.c +++ b/arch/arm/boards/terasic-sockit/board.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <types.h> #include <driver.h> @@ -25,7 +27,7 @@ static int phy_fixup(struct phy_device *dev) static int socfpga_console_init(void) { - if (!of_machine_is_compatible("terasic,sockit")) + if (!of_machine_is_compatible("terasic,socfpga-cyclone5-sockit")) return 0; if (IS_ENABLED(CONFIG_PHYLIB)) diff --git a/arch/arm/boards/terasic-sockit/config.h b/arch/arm/boards/terasic-sockit/config.h deleted file mode 100644 index da84fa5f6b..0000000000 --- a/arch/arm/boards/terasic-sockit/config.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing */ diff --git a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c index c2ccc46d9b..8e5b02be2f 100644 --- a/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c +++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c @@ -27,9 +27,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include <mach/cyclone5-scan-manager.h> +#include <mach/socfpga/cyclone5-scan-manager.h> -static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -56,7 +56,7 @@ static const unsigned long SECT(iocsr_scan_chain0_table)[((CONFIG_HPS_IOCSR_SCAN 0x00001000, }; -static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x300C0000, 0x300000C0, @@ -113,7 +113,7 @@ static const unsigned long SECT(iocsr_scan_chain1_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000080, }; -static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -146,7 +146,7 @@ static const unsigned long SECT(iocsr_scan_chain2_table)[((CONFIG_HPS_IOCSR_SCAN 0x00000800, }; -static const unsigned long SECT(iocsr_scan_chain3_table)[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, 0x082000FF, 0x0A804001, diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c index 585c786598..9ce0fd4423 100644 --- a/arch/arm/boards/terasic-sockit/lowlevel.c +++ b/arch/arm/boards/terasic-sockit/lowlevel.c @@ -1,4 +1,4 @@ -#define SECT(name) __attribute__((section("terasic_sockit_" #name))) name +// SPDX-License-Identifier: GPL-2.0-only #include "sdram_config.h" #include "pinmux_config.c" @@ -9,7 +9,7 @@ #include "sequencer_auto_ac_init.c" #include "iocsr_config_cyclone5.c" -#include <mach/lowlevel.h> +#include <mach/socfpga/lowlevel.h> static inline void ledon(int led) { diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c index 9a1316d0df..bcf27dbe1e 100644 --- a/arch/arm/boards/terasic-sockit/pinmux_config.c +++ b/arch/arm/boards/terasic-sockit/pinmux_config.c @@ -29,7 +29,7 @@ #include <common.h> -static unsigned long SECT(sys_mgr_init_table)[] = { +static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c index 8044477e01..fe0764b0ce 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c @@ -28,7 +28,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ static const uint32_t ac_rom_init_size = 36; -static const uint32_t SECT(ac_rom_init)[36] = +static const uint32_t ac_rom_init[36] = { 0x20700000, 0x20780000, diff --git a/arch/arm/boards/tny-a926x/Makefile b/arch/arm/boards/tny-a926x/Makefile index d400788757..1ebe527d60 100644 --- a/arch/arm/boards/tny-a926x/Makefile +++ b/arch/arm/boards/tny-a926x/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o obj-$(CONFIG_AT91_BOOTSTRAP) += tny_a9263_bootstrap.o diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c index dab373009f..0a448aa822 100644 --- a/arch/arm/boards/tny-a926x/init.c +++ b/arch/arm/boards/tny-a926x/init.c @@ -1,42 +1,29 @@ -/* - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> +#include <mach/at91/hardware.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <linux/clk.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> -#include <mach/at91sam9_sdramc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> +#include <mach/at91/at91sam9_sdramc.h> #include <gpio.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> #include <spi/eeprom.h> static void tny_a9260_set_board_type(void) diff --git a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c index 7f52f824df..91bf68e798 100644 --- a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c @@ -7,14 +7,23 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> +AT91_ENTRY_FUNCTION(start_tny_a9260, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); + + barebox_arm_entry(AT91_CHIPSELECT_1, + at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), + NULL); +} -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_tny_a9g20, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c index 368c67744f..5739b0f2da 100644 --- a/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c +++ b/arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c @@ -6,11 +6,11 @@ #include <common.h> #include <bootstrap.h> -#include <mach/bootstrap.h> +#include <mach/at91/bootstrap.h> #ifdef CONFIG_MTD_DATAFLASH void * bootstrap_board_read_dataflash(void) { - return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864, NULL); } #endif diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c index 565ba438d2..d20ffe9c71 100644 --- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c @@ -7,11 +7,9 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -#include <mach/at91sam926x_board_init.h> -#include <mach/at91sam9263_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9263_matrix.h> #define MASTER_CLOCK 180 @@ -118,7 +116,7 @@ static void __bare_init tny_a9263_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_tny_a9263, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/toradex-colibri-t20/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile index d0347f2382..aeb4765cf6 100644 --- a/arch/arm/boards/toradex-colibri-t20/Makefile +++ b/arch/arm/boards/toradex-colibri-t20/Makefile @@ -1,9 +1,9 @@ -CFLAGS_pbl-entry.o := \ - -mcpu=arm7tdmi -march=armv4t \ - -fno-tree-switch-conversion -fno-jump-tables +# SPDX-License-Identifier: GPL-2.0-only + +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t soc := tegra20 lwl-y += entry.o obj-y += board.o extra-y += colibri-t20_256_hsmmc.bct colibri-t20_256_v11_nand.bct \ colibri-t20_256_v12_nand.bct colibri-t20_512_hsmmc.bct \ - colibri-t20_512_v11_nand.bct colibri-t20_512_v12_nand.bct
\ No newline at end of file + colibri-t20_512_v11_nand.bct colibri-t20_512_v12_nand.bct diff --git a/arch/arm/boards/toradex-colibri-t20/board.c b/arch/arm/boards/toradex-colibri-t20/board.c index 706198105c..0025e70614 100644 --- a/arch/arm/boards/toradex-colibri-t20/board.c +++ b/arch/arm/boards/toradex-colibri-t20/board.c @@ -1,18 +1,5 @@ -/* - * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Lucas Stach <l.stach@pengutronix.de> #include <common.h> #include <init.h> diff --git a/arch/arm/boards/toradex-colibri-t20/entry.c b/arch/arm/boards/toradex-colibri-t20/entry.c index 9557b13f95..af55689402 100644 --- a/arch/arm/boards/toradex-colibri-t20/entry.c +++ b/arch/arm/boards/toradex-colibri-t20/entry.c @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <common.h> -#include <mach/lowlevel.h> +#include <mach/tegra/lowlevel.h> extern char __dtb_tegra20_colibri_iris_start[]; diff --git a/arch/arm/boards/toshiba-ac100/Makefile b/arch/arm/boards/toshiba-ac100/Makefile index 2b6c09e279..702c86a924 100644 --- a/arch/arm/boards/toshiba-ac100/Makefile +++ b/arch/arm/boards/toshiba-ac100/Makefile @@ -1,5 +1,5 @@ -CFLAGS_pbl-entry.o := \ - -mcpu=arm7tdmi -march=armv4t \ - -fno-tree-switch-conversion -fno-jump-tables +# SPDX-License-Identifier: GPL-2.0-only + +CFLAGS_entry.pbl.o := -mcpu=arm7tdmi -march=armv4t lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/toshiba-ac100/board.c b/arch/arm/boards/toshiba-ac100/board.c index fd470f18fc..7fb70ca6c9 100644 --- a/arch/arm/boards/toshiba-ac100/board.c +++ b/arch/arm/boards/toshiba-ac100/board.c @@ -1,23 +1,12 @@ -/* - * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2011 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #include <common.h> #include <init.h> -#include <usb/ehci.h> -#include <mach/iomap.h> +#include <linux/usb/ehci.h> +#include <mach/tegra/iomap.h> static struct ehci_platform_data ehci_pdata = { .flags = EHCI_HAS_TT, diff --git a/arch/arm/boards/toshiba-ac100/entry.c b/arch/arm/boards/toshiba-ac100/entry.c index 56979c9ba1..1cb5b1c0d0 100644 --- a/arch/arm/boards/toshiba-ac100/entry.c +++ b/arch/arm/boards/toshiba-ac100/entry.c @@ -1,21 +1,8 @@ -/* - * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2013 Lucas Stach <l.stach@pengutronix.de> #include <common.h> -#include <mach/lowlevel.h> +#include <mach/tegra/lowlevel.h> extern char __dtb_tegra20_paz00_start[]; diff --git a/arch/arm/boards/tqma53/Makefile b/arch/arm/boards/tqma53/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/tqma53/Makefile +++ b/arch/arm/boards/tqma53/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c index 055ceeb03e..7d81594df8 100644 --- a/arch/arm/boards/tqma53/board.c +++ b/arch/arm/boards/tqma53/board.c @@ -1,17 +1,5 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix #include <environment.h> #include <bootsource.h> @@ -19,8 +7,8 @@ #include <init.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/bbu.h> +#include <asm/mach-types.h> +#include <mach/imx/bbu.h> static int tqma53_devices_init(void) { diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg index 50a8f27dc5..6aeff80de5 100644 --- a/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #define SETUP_512MIB_1GIB \ wm 32 0x63fd9018 0x00011740; \ wm 32 0x63fd9000 0xc3190000 diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg index 4c8eed40d2..2431d6f039 100644 --- a/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #define SETUP_512MIB_1GIB \ wm 32 0x63fd9018 0x00101740; \ wm 32 0x63fd9000 0x83190000 diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h index 4d16b0667a..a11855f926 100644 --- a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx53 loadaddr 0x70000000 -dcdofs 0x400 +ivtofs 0x400 /* IOMUX */ wm 32 0x53fa8554 0x00300000 diff --git a/arch/arm/boards/tqma53/flash-header.imxcfg b/arch/arm/boards/tqma53/flash-header.imxcfg index 3d52ff1dec..6981a230a5 100644 --- a/arch/arm/boards/tqma53/flash-header.imxcfg +++ b/arch/arm/boards/tqma53/flash-header.imxcfg @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx53 loadaddr 0x70000000 -dcdofs 0x400 +ivtofs 0x400 /* IOMUX */ wm 32 0x53fa8554 0x00300000 diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c index 97a7ac556e..898b251d66 100644 --- a/arch/arm/boards/tqma53/lowlevel.c +++ b/arch/arm/boards/tqma53/lowlevel.c @@ -1,12 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <debug_ll.h> #include <io.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx5.h> -#include <mach/imx53-regs.h> -#include <mach/generic.h> +#include <mach/imx/imx5.h> +#include <mach/imx/imx53-regs.h> +#include <mach/imx/generic.h> #include <image-metadata.h> extern char __dtb_imx53_mba53_start[]; diff --git a/arch/arm/boards/karo-tx51/Makefile b/arch/arm/boards/tqma6ulx/Makefile index 5afc8e23e0..01c7a259e9 100644 --- a/arch/arm/boards/karo-tx51/Makefile +++ b/arch/arm/boards/tqma6ulx/Makefile @@ -1,2 +1,2 @@ -obj-y += tx51.o +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma6ulx/board.c b/arch/arm/boards/tqma6ulx/board.c new file mode 100644 index 0000000000..c559568880 --- /dev/null +++ b/arch/arm/boards/tqma6ulx/board.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + */ +#define pr_fmt(fmt) "tqma6ul: " fmt + +#include <common.h> +#include <bootsource.h> +#include <init.h> +#include <mach/imx/generic.h> +#include <mach/imx/bbu.h> +#include <of.h> +#include <string.h> +#include <linux/clk.h> +#include <asm/optee.h> +#include <asm-generic/memory_layout.h> + +#include "tqma6ulx.h" + +static const struct of_device_id mba6ulx_of_match[] = { + { .compatible = "tq,imx6ul-tqma6ul2l" }, + { .compatible = "tq,imx6ul-tqma6ul2" }, + { .compatible = "tq,imx6ull-tqma6ull2" }, + { .compatible = "tq,imx6ull-tqma6ull2l" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, mba6ulx_of_match); + +#ifdef CONFIG_FIRMWARE_TQMA6UL_OPTEE + +static int mba6ulx_optee_fixup(void) +{ + struct device_node *overlay; + struct fdt_header *fdt; + struct device_node *root = of_get_root_node(); + int ret; + + if (!of_match_node(mba6ulx_of_match, root)) + return 0; + + fdt = (void*)OPTEE_OVERLAY_LOCATION; + overlay = of_unflatten_dtb(fdt, INT_MAX); + + if (IS_ERR(overlay)) + return PTR_ERR(overlay); + + /* register the overlay for fixing up the kernel device tree */ + ret = of_register_overlay(overlay); + if (ret) { + printf("cannot apply oftree overlay: %s\n", strerror(-ret)); + goto err; + } + + /* + * Apply the overlay to the live tree to enable OP-TEE support + * for barebox and to reserve the SDRAM regions occupied by + * OP-TEE + */ + of_overlay_apply_tree(root, overlay); + + return 0; +err: + of_delete_node(overlay); + + return ret; +} +postcore_initcall(mba6ulx_optee_fixup); + +#endif + +static int mba6ulx_probe(struct device *dev) +{ + int flags; + struct clk *clk; + + clk = clk_lookup("enet_ref_125m"); + if (IS_ERR(clk)) + pr_err("Cannot find enet_ref_125m: %pe\n", clk); + else + clk_enable(clk); + + /* the bootloader is stored in one of the two boot partitions */ + flags = bootsource_get_instance() == 1 ? BBU_HANDLER_FLAG_DEFAULT : 0; + imx6_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", flags); + + flags = bootsource_get_instance() == 0 ? BBU_HANDLER_FLAG_DEFAULT : 0; + imx6_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", flags); + + if (bootsource_get_instance() == 0) + of_device_enable_path("/chosen/environment-sd"); + else + of_device_enable_path("/chosen/environment-emmc"); + + return 0; +} + +static struct driver mba6ulx_board_driver = { + .name = "board-mba6ulx", + .probe = mba6ulx_probe, + .of_compatible = mba6ulx_of_match, +}; +device_platform_driver(mba6ulx_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(mba6ulx_of_match); diff --git a/arch/arm/boards/tqma6ulx/flash-header-imx6ul-tqma6ulx.imxcfg b/arch/arm/boards/tqma6ulx/flash-header-imx6ul-tqma6ulx.imxcfg new file mode 100644 index 0000000000..ac4b853ced --- /dev/null +++ b/arch/arm/boards/tqma6ulx/flash-header-imx6ul-tqma6ulx.imxcfg @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +loadaddr 0x80000000 +soc imx6 +ivtofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* This flash header contains support for the LGA Variant */ +/* + * ===================================================================== + * IOMUX + * ===================================================================== + */ +/* DDR IO TYPE: */ +wm 32 0x020E04B4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ +wm 32 0x020E04AC 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ +/* CLOCK: */ +wm 32 0x020E027C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */ +/* Control: */ +wm 32 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ +wm 32 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ +wm 32 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ +wm 32 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ +wm 32 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */ +wm 32 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */ +wm 32 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */ +wm 32 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ +/* Data Strobes: */ +wm 32 0x020E0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ +wm 32 0x020E0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */ +wm 32 0x020E0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */ +/* Data: */ +wm 32 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ +wm 32 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ +wm 32 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ +wm 32 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ +wm 32 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ +/* + * ===================================================================== + * DDR Controller Registers + * ===================================================================== + */ +wm 32 0x021B001C 0x00008000 /* MMDC_MDSCR - MMDC Core Special Command Register */ +/* + * ====================================================== + * Calibrations: + * ====================================================== + */ +wm 32 0x021B0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */ + +wm 32 0x021B080C 0x00130003 /* MMDC_MPWLDECTRL0 */ +wm 32 0x021B083C 0x41540154 /* MMDC_MPDGCTRL0 */ +wm 32 0x021B0848 0x40405050 /* MMDC_MPRDDLCTL */ +wm 32 0x021B0850 0x40404E4C /* MMDC_MPWRDLCTL */ +wm 32 0x021B081C 0x33333333 /* MMDC_MPRDDQBY0DL */ +wm 32 0x021B0820 0x33333333 /* MMDC_MPRDDQBY1DL */ +wm 32 0x021B082C 0xf3333333 /* MMDC_MPWRDQBY0DL */ +wm 32 0x021B0830 0xf3333333 /* MMDC_MPWRDQBY1DL */ +wm 32 0x021B08C0 0x00921012 /* MMDC_MPDCCR */ + +/* Complete calibration by forced measurement: */ +wm 32 0x021B08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */ + +/* + * ===================================================================== + * MMDC init: + * ===================================================================== + */ +wm 32 0x021B0004 0x0002002D /* MMDC0_MDPDC */ +wm 32 0x021B0008 0x00333030 /* MMDC0_MDOTC */ +wm 32 0x021B000C 0x676B52F3 /* MMDC0_MDCFG0 */ +wm 32 0x021B0010 0xB66D8B63 /* MMDC0_MDCFG1 */ +wm 32 0x021B0014 0x01FF00DB /* MMDC0_MDCFG2 */ +wm 32 0x021B0018 0x00201740 /* MMDC0_MDMISC */ +/* TODO: set configuration request again, also done by NXP */ +wm 32 0x021B001C 0x00008000 /* MMDC_MDSCR */ +wm 32 0x021B002C 0x000026D2 /* MMDC0_MDRWD; recommend to maintain the default values */ +wm 32 0x021B0030 0x006B1023 /* MMDC0_MDOR */ +wm 32 0x021B0040 0x00000047 /* CS0_END */ +wm 32 0x021B0000 0x83180000 /* MMDC0_MDCTL */ +/* Mode register writes for CS0 */ +wm 32 0x021B001C 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */ +wm 32 0x021B001C 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */ +wm 32 0x021B001C 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */ +wm 32 0x021B001C 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */ +wm 32 0x021B001C 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */ +/* Mode register writes for CS1, not used / needed */ +/* final DDR setup, before operation start: */ +wm 32 0x021B0020 0x00000800 /* MMDC0_MDREF */ +wm 32 0x021B0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */ +wm 32 0x021B0004 0x0002552D /* MMDC0_MDPDC now SDCTL power down enabled */ +wm 32 0x021B0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled */ +wm 32 0x021B001C 0x00000000 /* MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) */ + +/* Disable TZASC bypass */ +wm 32 0x020E4024 0x00000001 + +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/tqma6ulx/lowlevel.c b/arch/arm/boards/tqma6ulx/lowlevel.c new file mode 100644 index 0000000000..5fd997d2ec --- /dev/null +++ b/arch/arm/boards/tqma6ulx/lowlevel.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ +#define pr_fmt(fmt) "tqma6ul: " fmt + +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/iomux-mx6ul.h> +#include <asm/cache.h> +#include <pbl/i2c.h> +#include <boards/tq/tq_eeprom.h> +#include <tee/optee.h> + +#include "tqma6ulx.h" + +extern char __dtb_z_imx6ul_tqma6ul2_mba6ulx_start[]; +extern char __dtb_z_imx6ul_tqma6ul2l_mba6ulx_start[]; +extern char __dtb_z_imx6ull_tqma6ull2_mba6ulx_start[]; +extern char __dtb_z_imx6ull_tqma6ull2l_mba6ulx_start[]; + +static void setup_uart(void) +{ + imx6_ungate_all_peripherals(); + + /* + * Default pad configuration on this board, no explicit config needed + */ + imx6_uart_setup((void *)MX6_UART1_BASE_ADDR); + pbl_set_putc(imx_uart_putc, (void *)MX6_UART1_BASE_ADDR); + + pr_debug("\n"); + +} + +static void *read_eeprom(void) +{ + struct pbl_i2c *i2c; + struct tq_eeprom *eeprom; + void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; + void *fdt = __dtb_z_imx6ul_tqma6ul2l_mba6ulx_start; + + imx_setup_pad(iomux, MX6_PAD_UART2_TX_DATA__I2C4_SCL | MUX_PAD_CTRL(0x1b8b0)); + imx_setup_pad(iomux, MX6_PAD_UART2_RX_DATA__I2C4_SDA | MUX_PAD_CTRL(0x1b8b0)); + + i2c = imx6_i2c_early_init(IOMEM(MX6_I2C4_BASE_ADDR)); + + eeprom = pbl_tq_read_eeprom(i2c, 0x50, I2C_ADDR_16_BIT); + if (!eeprom) { + pr_err("Cannot read EEPROM\n"); + goto out; + } + + pr_info("Board: %s\n", eeprom->id); + + if (!strcmp(eeprom->id, "TQMa6UL2L-AB.0202")) + fdt = __dtb_z_imx6ul_tqma6ul2l_mba6ulx_start; + else + pr_err("Unknown board type\n"); +out: + return fdt; +} + +static void noinline start_mba6ulx(u32 r0) +{ + void *fdt; + int tee_size; + void *tee; + + setup_uart(); + + fdt = read_eeprom(); + + /* Enable normal/secure r/w for TZC380 region0 */ + writel(0xf0000000, 0x021D0108); + + /* + * Chainloading barebox will pass a device tree within the RAM in r0, + * skip OP-TEE early loading in this case + */ + if (IS_ENABLED(CONFIG_FIRMWARE_TQMA6UL_OPTEE) && + !(r0 > MX6_MMDC_P0_BASE_ADDR && + r0 < MX6_MMDC_P0_BASE_ADDR + SZ_256M)) { + get_builtin_firmware(mba6ul_optee_bin, &tee, &tee_size); + + memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000); + + start_optee_early(NULL, tee); + } + + imx6ul_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6ul_mba6ulx, r0, r1, r2) +{ + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + imx6_uart_setup_ll(); + putc_ll('>'); + } + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_mba6ulx(r0); +} diff --git a/arch/arm/boards/tqma6ulx/tqma6ulx.h b/arch/arm/boards/tqma6ulx/tqma6ulx.h new file mode 100644 index 0000000000..843ad00d31 --- /dev/null +++ b/arch/arm/boards/tqma6ulx/tqma6ulx.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * tqma6ulx.h - common defines between OP-TEE and barebox + * + * Copyright (c) 2019 Rouven Czerwinski <r.czerwinski@pengutronix.de>, Pengutronix + * + */ +#ifndef __TQMA6ULX_H_ +#define __TQMA6ULX_H_ + +/* MX6UL_MMDC_PORT0_BASE_ADDR + SZ_64M */ +#define OPTEE_OVERLAY_LOCATION 0x84000000 + +#endif // __TQMA6ULX_H_ diff --git a/arch/arm/boards/tqma6x/Makefile b/arch/arm/boards/tqma6x/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/tqma6x/Makefile +++ b/arch/arm/boards/tqma6x/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma6x/board.c b/arch/arm/boards/tqma6x/board.c index ecf8fa06af..a2363913e2 100644 --- a/arch/arm/boards/tqma6x/board.c +++ b/arch/arm/boards/tqma6x/board.c @@ -1,26 +1,9 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ - -#include <generated/mach-types.h> +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer, Pengutronix + +#include <asm/mach-types.h> #include <environment.h> #include <bootsource.h> -#include <partition.h> #include <common.h> #include <envfs.h> #include <linux/sizes.h> @@ -28,18 +11,19 @@ #include <gpio.h> #include <of.h> +#include <linux/mdio.h> +#include <linux/phy.h> #include <linux/micrel_phy.h> #include <mfd/stmpe-i2c.h> #include <asm/armlinux.h> #include <asm/io.h> -#include <mach/devices-imx6.h> -#include <mach/imx6-regs.h> -#include <mach/iomux-mx6.h> -#include <mach/generic.h> -#include <mach/imx6.h> -#include <mach/bbu.h> +#include <mach/imx/imx6-regs.h> +#include <mach/imx/iomux-mx6.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6.h> +#include <mach/imx/bbu.h> #define RQ7_GPIO_ENET_PHYADD2 IMX_GPIO_NR(6, 30) #define RQ7_GPIO_ENET_MODE0 IMX_GPIO_NR(6, 25) @@ -63,14 +47,14 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev) * min rx data delay, max rx/tx clock delay, * min rx/tx control delay */ - phy_write_mmd_indirect(dev, 4, 2, 0); - phy_write_mmd_indirect(dev, 5, 2, 0); - phy_write_mmd_indirect(dev, 8, 2, 0x003ff); + phy_write_mmd(dev, MDIO_MMD_WIS, 4, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 5, 0); + phy_write_mmd(dev, MDIO_MMD_WIS, 8, 0x003ff); return 0; } -static int tqma6x_enet_init(void) +static int tq_mba6x_enet_init(void) { if (!of_machine_is_compatible("tq,mba6x")) return 0; @@ -94,20 +78,25 @@ static int tqma6x_enet_init(void) return 0; } -fs_initcall(tqma6x_enet_init); +fs_initcall(tq_mba6x_enet_init); -static int tqma6x_env_init(void) +static int tqma6x_init(void) { - if (!of_machine_is_compatible("tq,mba6x")) - return 0; - - devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "m25p0.barebox"); - imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", BBU_HANDLER_FLAG_DEFAULT); imx6_bbu_internal_mmcboot_register_handler("emmc", "mmc2", 0); - device_detect_by_name("mmc2"); + device_detect_by_name("mmc2"); // eMMC + + return 0; +} + +static int tq_mba6x_env_init(void) +{ + if (!of_machine_is_compatible("tq,mba6x")) + return 0; + + tqma6x_init(); default_environment_path_set("/dev/mmc2.boot1"); @@ -115,4 +104,4 @@ static int tqma6x_env_init(void) return 0; } -late_initcall(tqma6x_env_init); +late_initcall(tq_mba6x_env_init); diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg index 192ebda743..e93d53ed79 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6dl-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6dl-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg index 1fd75a24b2..ec682e0109 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c index afbc1691eb..6e9c9bed0b 100644 --- a/arch/arm/boards/tqma6x/lowlevel.c +++ b/arch/arm/boards/tqma6x/lowlevel.c @@ -1,18 +1,8 @@ -/* - * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de> + #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -21,19 +11,17 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6.h> +#include <mach/imx/imx6.h> extern char __dtb_imx6q_mba6x_start[]; extern char __dtb_imx6dl_mba6x_start[]; -ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2) +ENTRY_FUNCTION_WITHSTACK(start_imx6q_mba6x, 0x00920000, r0, r1, r2) { void *fdt; imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000); - if (IS_ENABLED(CONFIG_DEBUG_LL)) { writel(0x2, 0x020e0338); imx6_uart_setup_ll(); @@ -47,14 +35,12 @@ ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2) barebox_arm_entry(0x10000000, SZ_1G, fdt); } -ENTRY_FUNCTION(start_imx6dl_mba6x, r0, r1, r2) +ENTRY_FUNCTION_WITHSTACK(start_imx6dl_mba6x, 0x00920000, r0, r1, r2) { void *fdt; imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000); - if (IS_ENABLED(CONFIG_DEBUG_LL)) { writel(0x2, 0x020e035c); imx6_uart_setup_ll(); diff --git a/arch/arm/boards/tqma8mpxl/Makefile b/arch/arm/boards/tqma8mpxl/Makefile new file mode 100644 index 0000000000..35d8640087 --- /dev/null +++ b/arch/arm/boards/tqma8mpxl/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/tqma8mpxl/board.c b/arch/arm/boards/tqma8mpxl/board.c new file mode 100644 index 0000000000..39d1bd24d4 --- /dev/null +++ b/arch/arm/boards/tqma8mpxl/board.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Holger Assmann <h.assmann@pengutronix.de> + */ + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iomux-mx8mp.h> +#include <gpio.h> +#include <envfs.h> + +static int tqma8mpxl_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + + return 0; +} + +static const struct of_device_id tqma8mpxl_of_match[] = { + { .compatible = "tq,imx8mp-tqma8mpdl-mba8mpxl"}, + { .compatible = "tq,imx8mp-tqma8mpql-mba8mpxl"}, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(tqma8mpxl_of_match); + +static struct driver tqma8mpxl_board_driver = { + .name = "board-tqma8mpxl", + .probe = tqma8mpxl_probe, + .of_compatible = DRV_OF_COMPAT(tqma8mpxl_of_match), +}; +device_platform_driver(tqma8mpxl_board_driver); diff --git a/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg b/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg new file mode 100644 index 0000000000..6ea2e6c68e --- /dev/null +++ b/arch/arm/boards/tqma8mpxl/flash-header-tqma8mpxl.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/tqma8mpxl/lowlevel.c b/arch/arm/boards/tqma8mpxl/lowlevel.c new file mode 100644 index 0000000000..e0a0f17d3a --- /dev/null +++ b/arch/arm/boards/tqma8mpxl/lowlevel.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <common.h> +#include <firmware.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <linux/sizes.h> +#include <mach/imx/atf.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/debug_ll.h> +#include <mfd/pca9450.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <soc/imx8m/ddr.h> + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART4_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART4_TXD__UART4_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART4_RXD__UART4_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* + * Kernel uses OD/OD freq for SOC + * To avoid timing risk from SOC to ARM,increase VDD_ARM to OD + * voltage 0.95v + */ + { PCA9450_BUCK2OUT_DVS0, 0x1C }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +static __noreturn noinline void tqma8mpxl_start(void) +{ + extern char __dtb_z_imx8mp_tqma8mpql_mba8mpxl_start[]; + + setup_uart(); + + if (current_el() == 3) { + extern struct dram_timing_info dram_timing_2gb_no_ecc; + + imx8mp_early_clock_init(); + + power_init_board(); + + imx8mp_ddr_init(&dram_timing_2gb_no_ecc, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); + } + + imx8mp_barebox_entry(__dtb_z_imx8mp_tqma8mpql_mba8mpxl_start); +} + +ENTRY_FUNCTION(start_tqma8mpxl, x0, x1, x2) +{ + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + tqma8mpxl_start(); +} diff --git a/arch/arm/boards/tqma8mpxl/lpddr4-timing.c b/arch/arm/boards/tqma8mpxl/lpddr4-timing.c new file mode 100644 index 0000000000..85e21bf69d --- /dev/null +++ b/arch/arm/boards/tqma8mpxl/lpddr4-timing.c @@ -0,0 +1,1131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> + * + * TQMa8MPxL.2GByte.RAM-Timing.0004.xlsx / 2.0 GHz + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1303 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x2b0000 }, + { 0x3d4000e8, 0x550048 }, + { 0x3d4000ec, 0x150048 }, + { 0x3d400100, 0x201e222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1001 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x2b0000 }, + { 0x3d4020e8, 0x550048 }, + { 0x3d4020ec, 0x150048 }, + { 0x3d402100, 0xa030305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1001 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x2b0000 }, + { 0x3d4030e8, 0x550048 }, + { 0x3d4030ec, 0x150048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x6 }, + { 0x100a6, 0x7 }, + { 0x100a7, 0x5 }, + { 0x110a0, 0x6 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x1 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x6 }, + { 0x120a2, 0x4 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x2 }, + { 0x120a6, 0x1 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x5 }, + { 0x130a3, 0x4 }, + { 0x130a4, 0x3 }, + { 0x130a5, 0x2 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0x600 }, + { 0x1014d, 0x600 }, + { 0x1104d, 0x600 }, + { 0x1114d, 0x600 }, + { 0x1204d, 0x600 }, + { 0x1214d, 0x600 }, + { 0x1304d, 0x600 }, + { 0x1314d, 0x600 }, + { 0x11004d, 0x600 }, + { 0x11014d, 0x600 }, + { 0x11104d, 0x600 }, + { 0x11114d, 0x600 }, + { 0x11204d, 0x600 }, + { 0x11214d, 0x600 }, + { 0x11304d, 0x600 }, + { 0x11314d, 0x600 }, + { 0x21004d, 0x600 }, + { 0x21014d, 0x600 }, + { 0x21104d, 0x600 }, + { 0x21114d, 0x600 }, + { 0x21204d, 0x600 }, + { 0x21214d, 0x600 }, + { 0x21304d, 0x600 }, + { 0x21314d, 0x600 }, + { 0x10049, 0x69a }, + { 0x10149, 0x69a }, + { 0x11049, 0x69a }, + { 0x11149, 0x69a }, + { 0x12049, 0x69a }, + { 0x12149, 0x69a }, + { 0x13049, 0x69a }, + { 0x13149, 0x69a }, + { 0x110049, 0x69a }, + { 0x110149, 0x69a }, + { 0x111049, 0x69a }, + { 0x111149, 0x69a }, + { 0x112049, 0x69a }, + { 0x112149, 0x69a }, + { 0x113049, 0x69a }, + { 0x113149, 0x69a }, + { 0x210049, 0x69a }, + { 0x210149, 0x69a }, + { 0x211049, 0x69a }, + { 0x211149, 0x69a }, + { 0x212049, 0x69a }, + { 0x212149, 0x69a }, + { 0x213049, 0x69a }, + { 0x213149, 0x69a }, + { 0x43, 0x21 }, + { 0x1043, 0x21 }, + { 0x2043, 0x21 }, + { 0x3043, 0x21 }, + { 0x4043, 0x21 }, + { 0x5043, 0x21 }, + { 0x6043, 0x21 }, + { 0x7043, 0x21 }, + { 0x8043, 0x21 }, + { 0x9043, 0x21 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x303c }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x2b }, + { 0x5401b, 0x4855 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x2b }, + { 0x54021, 0x4855 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x2b3f }, + { 0x54034, 0x5500 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x2b3f }, + { 0x5403a, 0x5500 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x303c }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x2b }, + { 0x5401b, 0x4855 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x2b }, + { 0x54021, 0x4855 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x2b00 }, + { 0x54034, 0x5500 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x2b00 }, + { 0x5403a, 0x5500 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x303c }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x2b }, + { 0x5401b, 0x4855 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x2b }, + { 0x54021, 0x4855 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x2b00 }, + { 0x54034, 0x5500 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x2b00 }, + { 0x5403a, 0x5500 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x303c }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x2b }, + { 0x5401b, 0x4855 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x2b }, + { 0x54021, 0x4855 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x2b3f }, + { 0x54034, 0x5500 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x2b3f }, + { 0x5403a, 0x5500 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2gb_no_ecc = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; + +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +#error +#endif diff --git a/arch/arm/boards/tqma93xx/Makefile b/arch/arm/boards/tqma93xx/Makefile new file mode 100644 index 0000000000..1bef9e284d --- /dev/null +++ b/arch/arm/boards/tqma93xx/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel.o lpddr4x_tqma93xxca_timing.o lpddr4x_tqma93xxla_timing.o +obj-y += board.o diff --git a/arch/arm/boards/tqma93xx/board.c b/arch/arm/boards/tqma93xx/board.c new file mode 100644 index 0000000000..b181784079 --- /dev/null +++ b/arch/arm/boards/tqma93xx/board.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 + +#define pr_fmt(fmt) "TQMa93xx: " fmt + +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <i2c/i2c.h> +#include <linux/clk.h> +#include <linux/kernel.h> +#include <environment.h> +#include <mfd/pca9450.h> +#include <deep-probe.h> +#include <mach/imx/bbu.h> + +static void tqma93xx_init_pmic(struct regmap *map) +{ + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + regmap_write(map, PCA9450_BUCK123_DVS, 0x29); + /* enable DVS control through PMIC_STBY_REQ */ + regmap_write(map, PCA9450_BUCK1CTRL, 0x59); + /* 0.9 V */ + regmap_write(map, PCA9450_BUCK1OUT_DVS0, 0x18); + regmap_write(map, PCA9450_BUCK3OUT_DVS0, 0x18); + /* set standby voltage to 0.65v */ + regmap_write(map, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + regmap_write(map, 0xa, 0x3); + + /* set WDOG_B_CFG to cold reset */ + regmap_write(map, PCA9450_RESET_CTRL, 0xA1); +} + +static int tqma93xx_probe(struct device *dev) +{ + pca9450_register_init_callback(tqma93xx_init_pmic); + + imx9_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", 0); + + return 0; +} + +static const struct of_device_id tqma93xx_of_match[] = { + { + .compatible = "tq,imx93-tqma9352", + }, + { /* sentinel */ }, +}; + +static struct driver tqma93xx_board_driver = { + .name = "board-tqma93xx", + .probe = tqma93xx_probe, + .of_compatible = tqma93xx_of_match, +}; +coredevice_platform_driver(tqma93xx_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(tqma93xx_of_match); diff --git a/arch/arm/boards/tqma93xx/lowlevel.c b/arch/arm/boards/tqma93xx/lowlevel.c new file mode 100644 index 0000000000..8d89ee530f --- /dev/null +++ b/arch/arm/boards/tqma93xx/lowlevel.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/generic.h> +#include <mach/imx/xload.h> +#include <asm/barebox-arm.h> +#include <soc/imx9/ddr.h> +#include <mach/imx/atf.h> +#include <mach/imx/xload.h> +#include <mach/imx/romapi.h> +#include <mach/imx/esdctl.h> +#include <pbl/i2c.h> +#include <boards/tq/tq_eeprom.h> + +extern char __dtb_z_imx93_tqma9352_mba93xxca_start[]; +extern char __dtb_z_imx93_tqma9352_mba93xxla_start[]; +extern struct dram_timing_info tqma93xxca_dram_timing; +extern struct dram_timing_info tqma93xxla_dram_timing; + +static int tqma93xx_get_formfactor(void) +{ + struct pbl_i2c *i2c; + struct tq_eeprom *eeprom; + phys_size_t ramsize; + int formfactor; + + i2c = imx93_i2c_early_init(IOMEM(MX9_I2C1_BASE_ADDR)); + + eeprom = pbl_tq_read_eeprom(i2c, 0x53, 0); + if (!eeprom) + return VARD_FORMFACTOR_TYPE_CONNECTOR; + + ramsize = tq_vard_ramsize(&eeprom->vard); + if (ramsize != SZ_1G) + pr_err("unsupported ram size 0x%08llx\n", ramsize); + + formfactor = tq_vard_get_formfactor(&eeprom->vard); + + switch (formfactor) { + case VARD_FORMFACTOR_TYPE_LGA: + pr_debug("LGA board type\n"); + break; + case VARD_FORMFACTOR_TYPE_CONNECTOR: + pr_debug("CONNECTOR board type\n"); + break; + default: + pr_err("Unknown formfactor\n"); + formfactor = VARD_FORMFACTOR_TYPE_CONNECTOR; + } + + return formfactor; +} + +static noinline void tqma93xx_continue(void) +{ + void *base = IOMEM(MX9_UART1_BASE_ADDR); + void *muxbase = IOMEM(MX9_IOMUXC_BASE_ADDR); + int formfactor; + void *fdt; + + writel(0x10, muxbase + 0x170); + writel(0x10, muxbase + 0x174); + writel(0x0, muxbase + 0x184); + writel(0xb9e, muxbase + 0x320); + writel(0xb9e, muxbase + 0x324); + + imx9_uart_setup(IOMEM(base)); + pbl_set_putc(lpuart32_putc, base + 0x10); + + formfactor = tqma93xx_get_formfactor(); + + if (current_el() == 3) { + switch (formfactor) { + case VARD_FORMFACTOR_TYPE_LGA: + imx93_ddr_init(&tqma93xxla_dram_timing, DRAM_TYPE_LPDDR4); + break; + case VARD_FORMFACTOR_TYPE_CONNECTOR: + imx93_ddr_init(&tqma93xxca_dram_timing, DRAM_TYPE_LPDDR4); + break; + } + + imx93_romapi_load_image(); + imx93_load_and_start_image_via_tfa(); + } + + switch (formfactor) { + case VARD_FORMFACTOR_TYPE_LGA: + fdt = __dtb_z_imx93_tqma9352_mba93xxla_start; + break; + case VARD_FORMFACTOR_TYPE_CONNECTOR: + fdt = __dtb_z_imx93_tqma9352_mba93xxca_start; + break; + } + + imx93_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx93_tqma93xx, r0, r1, r2) +{ + if (current_el() == 3) + imx93_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + tqma93xx_continue(); +} diff --git a/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxca_timing.c b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxca_timing.c new file mode 100644 index 0000000000..68d8da3b5b --- /dev/null +++ b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxca_timing.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 NXP + */ + +#include <common.h> +#include <soc/imx9/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44100001 }, + { 0x4e300000, 0x8000bf }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000412 }, + { 0x4e300084, 0x0 }, + { 0x4e300100, 0x24a0321b }, + { 0x4e300104, 0xa8ee001b }, + { 0x4e300108, 0x2f2e3233 }, + { 0x4e30010c, 0x85c18b }, + { 0x4e300114, 0x1002 }, + { 0x4e300124, 0x1c77071d }, + { 0x4e300160, 0x5402 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300250, 0x28 }, + { 0x4e300254, 0x0 }, + { 0x4e30025c, 0x400 }, + { 0x4e300260, 0x0 }, + { 0x4e300300, 0x14281114 }, + { 0x4e300304, 0x106110a }, + { 0x4e300308, 0xa200e3c }, + { 0x4e300f04, 0x80 }, + { 0x4e300800, 0x39300002 }, + { 0x4e300804, 0x1f1f1f1f }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x3a5 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xff }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1146 }, + { 0x5401c, 0x1108 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1146 }, + { 0x54022, 0x1108 }, + { 0x54024, 0x6 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3236 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x811 }, + { 0x54036, 0x11 }, + { 0x54037, 0x600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3236 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x811 }, + { 0x5403c, 0x11 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 } +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xff }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1146 }, + { 0x5401c, 0x1108 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1146 }, + { 0x54022, 0x1108 }, + { 0x54024, 0x6 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3236 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x811 }, + { 0x54036, 0x11 }, + { 0x54037, 0x600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3236 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x811 }, + { 0x5403c, 0x11 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 } +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x75 }, + { 0x2000c, 0xe9 }, + { 0x2000d, 0x91c }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info tqma93xxca_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, }, +}; diff --git a/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxla_timing.c b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxla_timing.c new file mode 100644 index 0000000000..7ca8c3aedc --- /dev/null +++ b/arch/arm/boards/tqma93xx/lpddr4x_tqma93xxla_timing.c @@ -0,0 +1,1482 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2022 NXP + */ + +/* generated from TQMa9xxxLA.DDR-Timing.Beta.0001.mex */ + +#include <common.h> +#include <soc/imx9/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44100001 }, + { 0x4e300000, 0x8000bf }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000412 }, + { 0x4e300084, 0x0 }, + { 0x4e300100, 0x24a0321b }, + { 0x4e300104, 0xa8ee001b }, + { 0x4e300108, 0x2f2e3233 }, + { 0x4e30010c, 0x85c18b }, + { 0x4e300114, 0x1002 }, + { 0x4e300124, 0x1c77071d }, + { 0x4e300160, 0x5402 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300250, 0x28 }, + { 0x4e300254, 0x0 }, + { 0x4e30025c, 0x400 }, + { 0x4e300260, 0x0 }, + { 0x4e300300, 0x14281114 }, + { 0x4e300304, 0x106110a }, + { 0x4e300308, 0xa200e3c }, + { 0x4e300f04, 0x80 }, + { 0x4e300800, 0x39300002 }, + { 0x4e300804, 0x1f1f1f1f }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x2 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x4 }, + { 0x100a4, 0x3 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x4 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x1 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x1005f, 0x5ff }, + { 0x1015f, 0x5ff }, + { 0x1105f, 0x5ff }, + { 0x1115f, 0x5ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x2002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x2007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x20056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x10049, 0xe00 }, + { 0x10149, 0xe00 }, + { 0x11049, 0xe00 }, + { 0x11149, 0xe00 }, + { 0x43, 0x60 }, + { 0x1043, 0x60 }, + { 0x2043, 0x60 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x2009b, 0x2 }, + { 0x20008, 0x3a5 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x10c }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x200fa, 0x2 }, + { 0x20019, 0x1 }, + { 0x200f0, 0x0 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x131f }, + { 0x54009, 0xff }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1146 }, + { 0x5401c, 0x1108 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1146 }, + { 0x54022, 0x1108 }, + { 0x54024, 0x6 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3236 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x811 }, + { 0x54036, 0x11 }, + { 0x54037, 0x600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3236 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x811 }, + { 0x5403c, 0x11 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xe94 }, + { 0x54004, 0x4 }, + { 0x54006, 0x15 }, + { 0x54008, 0x61 }, + { 0x54009, 0xff }, + { 0x5400b, 0x4 }, + { 0x5400c, 0x1 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x2080 }, + { 0x54012, 0x110 }, + { 0x54019, 0x36e4 }, + { 0x5401a, 0x32 }, + { 0x5401b, 0x1146 }, + { 0x5401c, 0x1108 }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x36e4 }, + { 0x54020, 0x32 }, + { 0x54021, 0x1146 }, + { 0x54022, 0x1108 }, + { 0x54024, 0x6 }, + { 0x54032, 0xe400 }, + { 0x54033, 0x3236 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x811 }, + { 0x54036, 0x11 }, + { 0x54037, 0x600 }, + { 0x54038, 0xe400 }, + { 0x54039, 0x3236 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x811 }, + { 0x5403c, 0x11 }, + { 0x5403d, 0x600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x30 }, + { 0x90051, 0x65a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x45a }, + { 0x90055, 0x9 }, + { 0x90056, 0x0 }, + { 0x90057, 0x448 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x179 }, + { 0x9005c, 0x1 }, + { 0x9005d, 0x618 }, + { 0x9005e, 0x109 }, + { 0x9005f, 0x40c0 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x8 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x4040 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x0 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x48 }, + { 0x9006b, 0x40 }, + { 0x9006c, 0x633 }, + { 0x9006d, 0x149 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x658 }, + { 0x90070, 0x109 }, + { 0x90071, 0x10 }, + { 0x90072, 0x4 }, + { 0x90073, 0x18 }, + { 0x90074, 0x0 }, + { 0x90075, 0x4 }, + { 0x90076, 0x78 }, + { 0x90077, 0x549 }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0xd49 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x159 }, + { 0x9007d, 0x94a }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x159 }, + { 0x90080, 0x441 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x42 }, + { 0x90084, 0x633 }, + { 0x90085, 0x149 }, + { 0x90086, 0x1 }, + { 0x90087, 0x633 }, + { 0x90088, 0x149 }, + { 0x90089, 0x0 }, + { 0x9008a, 0xe0 }, + { 0x9008b, 0x109 }, + { 0x9008c, 0xa }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x9 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x149 }, + { 0x90092, 0x9 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x159 }, + { 0x90095, 0x18 }, + { 0x90096, 0x10 }, + { 0x90097, 0x109 }, + { 0x90098, 0x0 }, + { 0x90099, 0x3c0 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x18 }, + { 0x9009c, 0x4 }, + { 0x9009d, 0x48 }, + { 0x9009e, 0x18 }, + { 0x9009f, 0x4 }, + { 0x900a0, 0x58 }, + { 0x900a1, 0xb }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x1 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, + { 0x900a7, 0x5 }, + { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900aa, 0x0 }, + { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, + { 0x900b3, 0x0 }, + { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x10 }, + { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x10 }, + { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, + { 0x900bf, 0xa }, + { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, + { 0x900c2, 0xc }, + { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, + { 0x900c5, 0x14 }, + { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, + { 0x900cb, 0xe }, + { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, + { 0x900d1, 0x18 }, + { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, + { 0x900d4, 0x8 }, + { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, + { 0x900d7, 0x10 }, + { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, + { 0x900da, 0x1ff8 }, + { 0x900db, 0x85a8 }, + { 0x900dc, 0x1e8 }, + { 0x900dd, 0x50 }, + { 0x900de, 0x798 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x60 }, + { 0x900e1, 0x7a0 }, + { 0x900e2, 0x16a }, + { 0x900e3, 0x8 }, + { 0x900e4, 0x8310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0x8 }, + { 0x900e7, 0xa310 }, + { 0x900e8, 0x168 }, + { 0x900e9, 0xa }, + { 0x900ea, 0x408 }, + { 0x900eb, 0x169 }, + { 0x900ec, 0x6e }, + { 0x900ed, 0x0 }, + { 0x900ee, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x408 }, + { 0x900f1, 0x169 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0x8310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x0 }, + { 0x900f6, 0xa310 }, + { 0x900f7, 0x168 }, + { 0x900f8, 0x1ff8 }, + { 0x900f9, 0x85a8 }, + { 0x900fa, 0x1e8 }, + { 0x900fb, 0x68 }, + { 0x900fc, 0x798 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x78 }, + { 0x900ff, 0x7a0 }, + { 0x90100, 0x16a }, + { 0x90101, 0x68 }, + { 0x90102, 0x790 }, + { 0x90103, 0x16a }, + { 0x90104, 0x8 }, + { 0x90105, 0x8b10 }, + { 0x90106, 0x168 }, + { 0x90107, 0x8 }, + { 0x90108, 0xab10 }, + { 0x90109, 0x168 }, + { 0x9010a, 0xa }, + { 0x9010b, 0x408 }, + { 0x9010c, 0x169 }, + { 0x9010d, 0x58 }, + { 0x9010e, 0x0 }, + { 0x9010f, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x408 }, + { 0x90112, 0x169 }, + { 0x90113, 0x0 }, + { 0x90114, 0x8b10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x1 }, + { 0x90117, 0xab10 }, + { 0x90118, 0x168 }, + { 0x90119, 0x0 }, + { 0x9011a, 0x1d8 }, + { 0x9011b, 0x169 }, + { 0x9011c, 0x80 }, + { 0x9011d, 0x790 }, + { 0x9011e, 0x16a }, + { 0x9011f, 0x18 }, + { 0x90120, 0x7aa }, + { 0x90121, 0x6a }, + { 0x90122, 0xa }, + { 0x90123, 0x0 }, + { 0x90124, 0x1e9 }, + { 0x90125, 0x8 }, + { 0x90126, 0x8080 }, + { 0x90127, 0x108 }, + { 0x90128, 0xf }, + { 0x90129, 0x408 }, + { 0x9012a, 0x169 }, + { 0x9012b, 0xc }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x68 }, + { 0x9012e, 0x9 }, + { 0x9012f, 0x0 }, + { 0x90130, 0x1a9 }, + { 0x90131, 0x0 }, + { 0x90132, 0x408 }, + { 0x90133, 0x169 }, + { 0x90134, 0x0 }, + { 0x90135, 0x8080 }, + { 0x90136, 0x108 }, + { 0x90137, 0x8 }, + { 0x90138, 0x7aa }, + { 0x90139, 0x6a }, + { 0x9013a, 0x0 }, + { 0x9013b, 0x8568 }, + { 0x9013c, 0x108 }, + { 0x9013d, 0xb7 }, + { 0x9013e, 0x790 }, + { 0x9013f, 0x16a }, + { 0x90140, 0x1f }, + { 0x90141, 0x0 }, + { 0x90142, 0x68 }, + { 0x90143, 0x8 }, + { 0x90144, 0x8558 }, + { 0x90145, 0x168 }, + { 0x90146, 0xf }, + { 0x90147, 0x408 }, + { 0x90148, 0x169 }, + { 0x90149, 0xd }, + { 0x9014a, 0x0 }, + { 0x9014b, 0x68 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x408 }, + { 0x9014e, 0x169 }, + { 0x9014f, 0x0 }, + { 0x90150, 0x8558 }, + { 0x90151, 0x168 }, + { 0x90152, 0x8 }, + { 0x90153, 0x3c8 }, + { 0x90154, 0x1a9 }, + { 0x90155, 0x3 }, + { 0x90156, 0x370 }, + { 0x90157, 0x129 }, + { 0x90158, 0x20 }, + { 0x90159, 0x2aa }, + { 0x9015a, 0x9 }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x104 }, + { 0x90164, 0x8 }, + { 0x90165, 0x448 }, + { 0x90166, 0x109 }, + { 0x90167, 0xf }, + { 0x90168, 0x7c0 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x0 }, + { 0x9016b, 0xe8 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x47 }, + { 0x9016e, 0x630 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0x618 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0xe0 }, + { 0x90175, 0x109 }, + { 0x90176, 0x0 }, + { 0x90177, 0x7c8 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0x8140 }, + { 0x9017b, 0x10c }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x478 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, + { 0x90026, 0x69 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x75 }, + { 0x2000c, 0xe9 }, + { 0x2000d, 0x91c }, + { 0x2000e, 0x2c }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x400fd, 0xf }, + { 0x400f1, 0xe }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3732mts 1D */ + .drate = 3732, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P0 3732mts 2D */ + .drate = 3732, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info tqma93xxla_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3732, }, +}; diff --git a/arch/arm/boards/tqmls1046a/Makefile b/arch/arm/boards/tqmls1046a/Makefile index 851a5dcb3d..4af7fc3602 100644 --- a/arch/arm/boards/tqmls1046a/Makefile +++ b/arch/arm/boards/tqmls1046a/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o start.o obj-y += board.o bbenv-y += defaultenv-tqmls1046a diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c index 028be890e0..36bcae6bc0 100644 --- a/arch/arm/boards/tqmls1046a/board.c +++ b/arch/arm/boards/tqmls1046a/board.c @@ -10,14 +10,14 @@ #include <linux/clk.h> #include <linux/clkdev.h> #include <soc/fsl/immap_lsch2.h> -#include <mach/bbu.h> -#include <mach/layerscape.h> +#include <mach/layerscape/bbu.h> +#include <mach/layerscape/layerscape.h> static int tqmls1046a_mem_init(void) { int ret; - if (!of_machine_is_compatible("tqc,tqmls1046a")) + if (!of_machine_is_compatible("tq,ls1046a-tqmls1046a")) return 0; arm_add_mem_device("ram0", 0x80000000, SZ_2G); @@ -36,7 +36,7 @@ static int tqmls1046a_postcore_init(void) enum bootsource bootsource; unsigned long sd_bbu_flags = 0, qspi_bbu_flags = 0; - if (!of_machine_is_compatible("tqc,tqmls1046a")) + if (!of_machine_is_compatible("tq,ls1046a-tqmls1046a")) return 0; defaultenv_append_directory(defaultenv_tqmls1046a); @@ -47,7 +47,7 @@ static int tqmls1046a_postcore_init(void) /* divide CGA1/CGA2 PLL by 24 to get QSPI interface clock */ out_be32(&scfg->qspi_cfg, 0x30100000); - bootsource = ls1046_bootsource_get(); + bootsource = ls1046a_bootsource_get(); switch (bootsource) { case BOOTSOURCE_MMC: diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c index f79f491ecc..4a1496078a 100644 --- a/arch/arm/boards/tqmls1046a/lowlevel.c +++ b/arch/arm/boards/tqmls1046a/lowlevel.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include <common.h> #include <debug_ll.h> -#include <image-metadata.h> #include <platform_data/mmc-esdhc-imx.h> #include <soc/fsl/fsl_ddr_sdram.h> #include <soc/fsl/immap_lsch2.h> @@ -9,157 +8,13 @@ #include <asm/barebox-arm.h> #include <asm/syscounter.h> #include <asm/cache.h> -#include <mach/errata.h> -#include <mach/lowlevel.h> -#include <mach/xload.h> -#include <mach/layerscape.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {1, 2100, 0, 8, 9, 0x09080806, 0x07060606,}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static void ddr_board_options(memctl_options_t *popts, - struct dimm_params *pdimm, - struct fsl_ddr_controller *c) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned long ddr_freq; - - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* - * Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = c->ddr_freq / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found for %lu MT/s\n", - ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - - popts->data_bus_width = 0; /* 64-bit data bus */ - popts->bstopre = 0; /* enable auto precharge */ - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR4_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR4_CDR_ODT_60ohm) | - DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x48; -} - -static struct dimm_params dimm_params[] = { - { - .n_ranks = 1, - .rank_density = 2147483648u, - .capacity = 2147483648u, - .primary_sdram_width = 64, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .bank_addr_bits = 2, - .bank_group_bits = 0, - .edc_config = 2, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 833, - .tckmax_ps = 1900, - .caslat_x = 0x000DFA00, // - .taa_ps = 13320, - .trcd_ps = 13320, - .trp_ps = 13320, - .tras_ps = 32000, - .trc_ps = 45320, - .trfc1_ps = 260000, - .trfc2_ps = 160000, - .trfc4_ps = 110000, - .tfaw_ps = 21000, - .trrds_ps = 3300, - .trrdl_ps = 4900, - .tccdl_ps = 5000, - .trfc_slr_ps = 3500000, - .refresh_rate_ps = 7800000, - }, -}; +#include <mach/layerscape/errata.h> +#include <mach/layerscape/lowlevel.h> +#include <mach/layerscape/xload.h> +#include <mach/layerscape/layerscape.h> static struct fsl_ddr_controller ddrc[] = { { - .dimm_slots_per_ctrl = ARRAY_SIZE(dimm_params), - .dimm_params = dimm_params, .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, .base = IOMEM(LSCH2_DDR_ADDR), .ddr_freq = LS1046A_DDR_FREQ, @@ -169,7 +24,6 @@ static struct fsl_ddr_controller ddrc[] = { .erratum_A009801 = 1, .erratum_A009942 = 1, .chip_selects_per_ctrl = 4, - .board_options = ddr_board_options, .fsl_ddr_config_reg = { .cs[0].bnds = 0x0000007F, .cs[0].config = 0x80010312, @@ -236,7 +90,7 @@ static struct fsl_ddr_controller ddrc[] = { }, }; -extern char __dtb_fsl_tqmls1046a_mbls10xxa_start[]; +extern char __dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start[]; static noinline __noreturn void tqmls1046a_r_entry(void) { @@ -244,19 +98,17 @@ static noinline __noreturn void tqmls1046a_r_entry(void) if (get_pc() >= membase) barebox_arm_entry(membase, 0x80000000 - SZ_64M, - __dtb_fsl_tqmls1046a_mbls10xxa_start); + __dtb_z_fsl_ls1046a_tqmls1046a_mbls10xxa_start); arm_cpu_lowlevel_init(); ls1046a_init_lowlevel(); - debug_ll_init(); + ls1046a_debug_ll_init(); udelay(500); putc_ll('>'); - IMD_USED_OF(fsl_tqmls1046a_mbls10xxa); - - fsl_ddr_set_memctl_regs(&ddrc[0], 0); + fsl_ddr_set_memctl_regs(&ddrc[0], 0, false); ls1046a_errata_post_ddr(); diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg index 0a04afa770..e4c293ab77 100644 --- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# #Configure QSPI clock 0957015c 40100000 #Configure Scratch register diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg index 2df229c56c..490d45af9e 100644 --- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# # RCW values # 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] # 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg index 72ab1cd7d7..645dc4fd22 100644 --- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +# # RCW values # 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] # 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] diff --git a/arch/arm/boards/turris-omnia/Makefile b/arch/arm/boards/turris-omnia/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/turris-omnia/Makefile +++ b/arch/arm/boards/turris-omnia/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/turris-omnia/board.c b/arch/arm/boards/turris-omnia/board.c deleted file mode 100644 index 40a8c178f1..0000000000 --- a/arch/arm/boards/turris-omnia/board.c +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/arm/boards/turris-omnia/lowlevel.c b/arch/arm/boards/turris-omnia/lowlevel.c index 7236211c40..97d57e6ce0 100644 --- a/arch/arm/boards/turris-omnia/lowlevel.c +++ b/arch/arm/boards/turris-omnia/lowlevel.c @@ -1,26 +1,16 @@ -/* - * Copyright (C) 2017 Pengutronix, Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2017 Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>, Pengutronix #include <common.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> #include <asm/io.h> extern char __dtb_armada_385_turris_omnia_bb_start[]; -ENTRY_FUNCTION(start_turris_omnia, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_turris_omnia, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/udoo-neo/Makefile b/arch/arm/boards/udoo-neo/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/udoo-neo/Makefile +++ b/arch/arm/boards/udoo-neo/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/udoo-neo/board.c b/arch/arm/boards/udoo-neo/board.c index 9bf480305d..d9b9517fc1 100644 --- a/arch/arm/boards/udoo-neo/board.c +++ b/arch/arm/boards/udoo-neo/board.c @@ -1,27 +1,117 @@ -/* - * Copyright (C) 2014 Pengutronix, Sascha Hauer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2, as published by the Free Software Foundation. +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Sascha Hauer, Pengutronix + +#include <common.h> +#include <deep-probe.h> +#include <gpio.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> + +/** + * Detects the board model by checking the R184 and R185 resistors. + * A mounted resistor (0Ohm) connects the GPIO to ground, so the + * GPIO value will be 0. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * FULL - Eth, WiFi, motion sensors, 1GB RAM -> R184 not mounted - R185 mounted + * EXTENDED - NO Eth, WiFi, motion sensors, 1GB RAM -> R184 not mounted - R185 not mounted + * BASE - Eth, NO WiFi, NO motion sensors, 512MB RAM -> R184 mounted - R185 mounted + * BASE KS - NO Eth, WiFi, NO motion sensors, 512MB RAM -> R184 mounted - R185 not mounted */ -#include <common.h> -#include <init.h> -#include <linux/clk.h> +enum imx6sx_udoneo_board_type { + UDOO_NEO_BASIC = 0, + UDOO_NEO_BASIC_KS = 1, + UDOO_NEO_FULL = 2, + UDOO_NEO_EXTENDED = 3, + UDOO_NEO_UNKNOWN, +}; + +#define GPIO_R184 IMX_GPIO_NR(4, 13) +#define GPIO_R185 IMX_GPIO_NR(4, 0) + +static enum imx6sx_udoneo_board_type imx6sx_udoneo_detect(struct device *dev) +{ + struct device_node *gpio_np = NULL; + int r184, r185; + int ret; + + gpio_np = of_find_node_by_name_address(NULL, "gpio@20a8000"); + if (gpio_np) { + ret = of_device_ensure_probed(gpio_np); + if (ret) { + dev_warn(dev, "Can't probe GPIO node\n"); + goto detect_error; + } + } else { + dev_warn(dev, "Can't get GPIO node\n"); + goto detect_error; + } + + ret = gpio_request(GPIO_R184, "version r184"); + if (ret) + goto detect_error; + + ret = gpio_request(GPIO_R185, "version r185"); + if (ret) + goto detect_error; -static int imx6sx_udoneo_coredevices_init(void) + ret = gpio_direction_input(GPIO_R184); + if (ret) + goto detect_error; + + ret = gpio_direction_input(GPIO_R185); + if (ret) + goto detect_error; + + r184 = gpio_get_value(GPIO_R184); + r185 = gpio_get_value(GPIO_R185); + + return r184 << 1 | r185 << 0; + +detect_error: + dev_warn(dev, "Board detection failed\n"); + + return UDOO_NEO_UNKNOWN; +} + +static int imx6sx_udoneo_probe(struct device *dev) { - if (!of_machine_is_compatible("fsl,imx6sx-udoo-neo")) - return 0; + enum imx6sx_udoneo_board_type type; + const char *model; + + type = imx6sx_udoneo_detect(dev); + switch (type) { + case UDOO_NEO_FULL: + model = "UDOO Neo Full"; + break; + case UDOO_NEO_EXTENDED: + model = "UDOO Neo Extended"; + break; + case UDOO_NEO_BASIC: + model = "UDOO Neo Basic"; + break; + default: + model = "UDOO Neo unknown"; + } + barebox_set_model(model); barebox_set_hostname("mx6sx-udooneo"); + imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc1.barebox", + BBU_HANDLER_FLAG_DEFAULT); + return 0; } -coredevice_initcall(imx6sx_udoneo_coredevices_init); + +static const struct of_device_id imx6sx_udoneo_of_match[] = { + { .compatible = "udoo,neofull" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(imx6sx_udoneo_of_match); + +static struct driver imx6sx_udoneo_driver = { + .name = "board-udoo-neo", + .probe = imx6sx_udoneo_probe, + .of_compatible = imx6sx_udoneo_of_match, +}; +postcore_platform_driver(imx6sx_udoneo_driver); diff --git a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg index 39f2a8a221..6246e17a73 100644 --- a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg +++ b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + /* * These values are taken from: * repository: https://github.com/UDOOboard/uboot-imx @@ -7,7 +9,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/udoo-neo/lowlevel.c b/arch/arm/boards/udoo-neo/lowlevel.c index bb6b7d8332..e8712b0c72 100644 --- a/arch/arm/boards/udoo-neo/lowlevel.c +++ b/arch/arm/boards/udoo-neo/lowlevel.c @@ -1,10 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/udoo/Makefile b/arch/arm/boards/udoo/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/udoo/Makefile +++ b/arch/arm/boards/udoo/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c index f0befaf3a9..f27e5a3c0b 100644 --- a/arch/arm/boards/udoo/board.c +++ b/arch/arm/boards/udoo/board.c @@ -1,42 +1,29 @@ -/* - * Copyright (C) 2014 Raphaël Poggi - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * based on arch/arm/boards/freescale-mx6-arm2/board.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Raphaël Poggi +// SPDX-FileCopyrightText: 2012 Steffen Trumtrar, Pengutronix + +/* based on arch/arm/boards/freescale-mx6-arm2/board.c */ #include <common.h> #include <init.h> #include <environment.h> -#include <mach/imx6-regs.h> +#include <mach/imx/imx6-regs.h> #include <gpio.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <linux/phy.h> #include <asm/io.h> #include <asm/mmu.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> #include <net.h> #include <linux/micrel_phy.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/iomux-mx6.h> #include <spi/spi.h> -#include <mach/spi.h> -#include <mach/usb.h> +#include <mach/imx/spi.h> +#include <mach/imx/usb.h> static iomux_v3_cfg_t udoo_enet_gpio_pads_1[] = { /* RGMII reset */ diff --git a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg index a0647a71a8..95ba1ddc41 100644 --- a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg +++ b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> /* MX6_IOM_DRAM_SDQS0 -> MX6_IOM_DRAM_SDQS7 */ wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 diff --git a/arch/arm/boards/udoo/lowlevel.c b/arch/arm/boards/udoo/lowlevel.c index 1f06f7e37f..2570239b96 100644 --- a/arch/arm/boards/udoo/lowlevel.c +++ b/arch/arm/boards/udoo/lowlevel.c @@ -1,6 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/usb-a926x/Makefile b/arch/arm/boards/usb-a926x/Makefile index 65cc4082fc..022b1a4ab6 100644 --- a/arch/arm/boards/usb-a926x/Makefile +++ b/arch/arm/boards/usb-a926x/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o obj-$(CONFIG_AT91_BOOTSTRAP) += usb_a9263_bootstrap.o diff --git a/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config b/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config index 49199ba391..f9159cb946 100644 --- a/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config +++ b/arch/arm/boards/usb-a926x/defaultenv-usb-a926x/config @@ -29,10 +29,6 @@ kernelimage=zImage #kernelimage=Image #kernelimage=Image.lzo -nand_device=atmel_nand -nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)" -rootfs_mtdblock_nand=6 - autoboot_timeout=3 bootargs="console=ttyS0,115200" diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c index 8969cbd3a8..1297b4fe7f 100644 --- a/arch/arm/boards/usb-a926x/init.c +++ b/arch/arm/boards/usb-a926x/init.c @@ -1,44 +1,31 @@ -/* - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> #include <common.h> #include <net.h> #include <init.h> #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <fs.h> #include <fcntl.h> #include <io.h> #include <envfs.h> -#include <mach/hardware.h> -#include <mach/at91sam926x.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91sam926x.h> #include <nand.h> #include <linux/sizes.h> #include <linux/mtd/nand.h> +#include <linux/mtd/rawnand.h> #include <linux/clk.h> -#include <mach/board.h> -#include <mach/at91sam9_smc.h> -#include <mach/at91sam9_sdramc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91sam9_smc.h> +#include <mach/at91/at91sam9_sdramc.h> #include <gpio.h> #include <led.h> -#include <mach/iomux.h> -#include <mach/at91_pmc.h> -#include <mach/at91_rstc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_rstc.h> #include <gpio_keys.h> #include <readkey.h> #include <spi/spi.h> @@ -408,7 +395,7 @@ device_initcall(usb_a9260_devices_init); #ifndef CONFIG_CONSOLE_NONE static int usb_a9260_console_init(void) { - struct device_d *dev; + struct device *dev; if (machine_is_usb_a9260()) { barebox_set_model("Calao USB-A9260"); diff --git a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c index 7f52f824df..66753669d6 100644 --- a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c @@ -7,14 +7,23 @@ #include <common.h> #include <init.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91sam9260.h> +#include <mach/at91/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9260.h> -#include <mach/hardware.h> +AT91_ENTRY_FUNCTION(start_usb_a9260, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); + + barebox_arm_entry(AT91_CHIPSELECT_1, + at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), + NULL); +} -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_usb_a9g20, r0, r1, r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c index 368c67744f..5739b0f2da 100644 --- a/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c +++ b/arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c @@ -6,11 +6,11 @@ #include <common.h> #include <bootstrap.h> -#include <mach/bootstrap.h> +#include <mach/at91/bootstrap.h> #ifdef CONFIG_MTD_DATAFLASH void * bootstrap_board_read_dataflash(void) { - return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864); + return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864, NULL); } #endif diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c index 2ad88d7f22..eda534c68e 100644 --- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c @@ -6,10 +6,9 @@ #include <linux/sizes.h> -#include <asm/barebox-arm.h> - -#include <mach/at91sam926x_board_init.h> -#include <mach/at91sam9263_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91sam926x_board_init.h> +#include <mach/at91/at91sam9263_matrix.h> #define MASTER_CLOCK 180 @@ -20,7 +19,7 @@ #endif #define MASTER_PLL_DIV 6 -static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg) +static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg, bool has_mem_128m) { /* Disable Watchdog */ cfg->wdt_mr = @@ -88,7 +87,7 @@ static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg (5 << 24) | /* Active to Precharge Delay */ (8 << 28); /* Exit Self Refresh to Active Delay */ - if (IS_ENABLED(CONFIG_AT91_HAVE_SRAM_128M)) + if (has_mem_128m) cfg->sdrc_cr |= AT91_SDRAMC_NC_10; else cfg->sdrc_cr |= AT91_SDRAMC_NC_9; @@ -106,7 +105,7 @@ static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg AT91_RSTC_RSTTYP_WATCHDOG; } -static void __bare_init usb_a9263_init(void) +static void __bare_init usb_a9263_init(bool has_mem_128m) { struct at91sam926x_board_cfg cfg; @@ -115,18 +114,27 @@ static void __bare_init usb_a9263_init(void) cfg.ebi_pio_is_peripha = true; cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA); - usb_a9263_board_config(&cfg); + usb_a9263_board_config(&cfg, has_mem_128m); at91sam9263_board_init(&cfg); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc), NULL); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +AT91_ENTRY_FUNCTION(start_usb_a9263, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE); + + usb_a9263_init(false); +} + +AT91_ENTRY_FUNCTION(start_usb_a9263_128m, r0, r1, r2) { arm_cpu_lowlevel_init(); arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE); - usb_a9263_init(); + usb_a9263_init(true); } diff --git a/arch/arm/boards/usi-topkick/Makefile b/arch/arm/boards/usi-topkick/Makefile index 01c7a259e9..458f520900 100644 --- a/arch/arm/boards/usi-topkick/Makefile +++ b/arch/arm/boards/usi-topkick/Makefile @@ -1,2 +1,3 @@ -obj-y += board.o +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o diff --git a/arch/arm/boards/usi-topkick/board.c b/arch/arm/boards/usi-topkick/board.c deleted file mode 100644 index 7dbe0aa943..0000000000 --- a/arch/arm/boards/usi-topkick/board.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright - * (C) 2013 Jason Cooper <jason@lakedaemon.net> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* empty */ diff --git a/arch/arm/boards/usi-topkick/lowlevel.c b/arch/arm/boards/usi-topkick/lowlevel.c index 4202138986..d9118f5d2c 100644 --- a/arch/arm/boards/usi-topkick/lowlevel.c +++ b/arch/arm/boards/usi-topkick/lowlevel.c @@ -1,28 +1,15 @@ -/* - * Copyright (C) 2014 - * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <mach/lowlevel.h> +#include <mach/mvebu/barebox-arm-head.h> +#include <mach/mvebu/lowlevel.h> extern char __dtb_kirkwood_topkick_bb_start[]; -ENTRY_FUNCTION(start_usi_topkick, r0, r1, r2) +ENTRY_FUNCTION_MVEBU(start_usi_topkick, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/Makefile b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/Makefile new file mode 100644 index 0000000000..35d8640087 --- /dev/null +++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/board.c b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/board.c new file mode 100644 index 0000000000..154931d534 --- /dev/null +++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/board.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Michael Kopfensteiner, VAHLE Automation GmbH + */ + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <deep-probe.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/imx/bbu.h> +#include <mach/imx/iomux-mx8mp.h> +#include <gpio.h> +#include <envfs.h> + +#define PHY_ID_ADIN1300 0x0283bc30 +#define PHY_ID_MODEL_MASK 0xfffffff0 + +/* + * This fixup is necessary to properly configure the ADIN1300 + * PHY on the SOM to properly communicate using RGMII. + * This fixup disables the PHY's internal 2ns RGMII receive clock + * delay. Without this configuration change, the system will + * be able to send Ethernet packages, but the MAC won't receive + * any response packages. + * + * This fixup is specific to the ADIN1300 PHY. This implementation + * was ported from Variscite's U-Boot sources. + */ +static int phy_fixup_adin1300(struct phy_device *dev) { + int ret; + + pr_debug("BOARD: applying PHY fixup for ADIN1300\n"); + + ret = mdiobus_write(dev->bus, dev->addr, 0x0010, 0xFF23); + if (ret) { + pr_warn("ADIN1300 PHY fixup: failed to write EXT_REG_PTR\n"); + return ret; + } + + ret = mdiobus_write(dev->bus, dev->addr, 0x0011, 0x0E01); + if (ret) { + pr_warn("ADIN1300 PHY fixup: failed to write EXT_REG_DATA\n"); + return ret; + } + + return 0; +} + +static int var_imx8mp_dart_cb_probe(struct device *dev) +{ + int emmc_bbu_flag = 0; + int sd_bbu_flag = 0; + + phy_register_fixup_for_uid(PHY_ID_ADIN1300, PHY_ID_MODEL_MASK, phy_fixup_adin1300); + + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) { + of_device_enable_path("/chosen/environment-sd"); + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag); + + return 0; +} + +static const struct of_device_id var_imx8mp_dart_cb_of_match[] = { + { .compatible = "variscite,imx8mp-var-dart" }, + { /* Sentinel */ } +}; +BAREBOX_DEEP_PROBE_ENABLE(var_imx8mp_dart_cb_of_match); + +static struct driver var_imx8mp_dart_cb_board_driver = { + .name = "board-var-imx8mp-dart-cb", + .probe = var_imx8mp_dart_cb_probe, + .of_compatible = var_imx8mp_dart_cb_of_match, +}; +coredevice_platform_driver(var_imx8mp_dart_cb_board_driver); diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/flash-header-imx8mp-dart.imxcfg b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/flash-header-imx8mp-dart.imxcfg new file mode 100644 index 0000000000..c3149a197f --- /dev/null +++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/flash-header-imx8mp-dart.imxcfg @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +soc imx8mp + +loadaddr 0x918000 +max_load_size 0x3f000 +ivtofs 0x0 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lowlevel.c b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lowlevel.c new file mode 100644 index 0000000000..c9907ebf0a --- /dev/null +++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lowlevel.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <pbl/i2c.h> +#include <pbl/pmic.h> +#include <linux/sizes.h> +#include <mach/imx/atf.h> +#include <mach/imx/xload.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8mp-regs.h> +#include <mach/imx/iomux-mx8mp.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mfd/pca9450.h> +#include <soc/imx8m/ddr.h> +#include <soc/fsl/fsl_udc.h> + +extern char __dtb_z_imx8mp_var_dart_dt8mcustomboard_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | MX8MP_PAD_CTL_FSEL) +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); + + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART1_TXD__UART1_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART1_RXD__UART1_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + +static void power_init_board(void) +{ + struct pbl_i2c *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); +} + +extern struct dram_timing_info var_dart_imx8mp_dram_timing; + +static void start_atf(void) +{ + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + imx8mm_early_clock_init(); + + power_init_board(); + + imx8mp_ddr_init(&var_dart_imx8mp_dram_timing, DRAM_TYPE_LPDDR4); + + imx8mp_load_and_start_image_via_tfa(); +} + +static __noreturn noinline void variscite_imx8mp_dart_cb_start(void) +{ + setup_uart(); + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(__dtb_z_imx8mp_var_dart_dt8mcustomboard_start); +} + +/* + * Power-on execution flow of nxp_imx8mp_vardart_start() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +ENTRY_FUNCTION(start_variscite_imx8mp_dart, r0, r1, r2) +{ + imx8mp_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + + variscite_imx8mp_dart_cb_start(); +} diff --git a/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lpddr4-timing.c b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lpddr4-timing.c new file mode 100644 index 0000000000..b85935ca05 --- /dev/null +++ b/arch/arm/boards/variscite-dt8mcustomboard-imx8mp/lpddr4-timing.c @@ -0,0 +1,1128 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * + * These sources have been migrated from Variscite's public U-Boot sources for + * the i.MX8MP DART CustomBoard (= DT8MCustomBoard) eval kit. Solely this + * comment and the header-includes have been adapted. + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info var_dart_imx8mp_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/variscite-mx6/Makefile b/arch/arm/boards/variscite-mx6/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/variscite-mx6/Makefile +++ b/arch/arm/boards/variscite-mx6/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/variscite-mx6/board.c b/arch/arm/boards/variscite-mx6/board.c index 267f68c6da..9eb3202528 100644 --- a/arch/arm/boards/variscite-mx6/board.c +++ b/arch/arm/boards/variscite-mx6/board.c @@ -1,22 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* * Copyright (C) 2013 Michael Burkey * Based on code (C) Sascha Hauer, Pengutronix * Based on code (C) Variscite, Ltd. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * */ #define pr_fmt(fmt) "var-som-mx6: " fmt @@ -29,17 +16,15 @@ #include <environment.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <partition.h> +#include <asm/mach-types.h> #include <asm/io.h> #include <asm/mmu.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <linux/sizes.h> -#include <mach/imx6.h> -#include <mach/devices-imx6.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/imx6.h> +#include <mach/imx/iomux-mx6.h> #include <spi/spi.h> -#include <mach/spi.h> +#include <mach/imx/spi.h> #include <i2c/i2c.h> #define ETH_PHY_RST IMX_GPIO_NR(1, 25) diff --git a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg index 2c82f2316f..34790120ac 100644 --- a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg +++ b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg @@ -1,9 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/imx6-ddr-regs.h> -#include <mach/imx6q-ddr-regs.h> +#include <mach/imx/imx6-ddr-regs.h> +#include <mach/imx/imx6q-ddr-regs.h> wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c index d75d770a7e..d0842b1579 100644 --- a/arch/arm/boards/variscite-mx6/lowlevel.c +++ b/arch/arm/boards/variscite-mx6/lowlevel.c @@ -1,20 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /* - * * Copyright (C) 2013 Michael Burkey * Based on code by Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ + #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> #include <linux/sizes.h> #include <io.h> @@ -23,7 +15,7 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6.h> +#include <mach/imx/imx6.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/variscite-som-mx7/Makefile b/arch/arm/boards/variscite-som-mx7/Makefile new file mode 100644 index 0000000000..5b7f460c6d --- /dev/null +++ b/arch/arm/boards/variscite-som-mx7/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de> +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/variscite-som-mx7/board.c b/arch/arm/boards/variscite-som-mx7/board.c new file mode 100644 index 0000000000..005228d107 --- /dev/null +++ b/arch/arm/boards/variscite-som-mx7/board.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de> + +#include <common.h> +#include <deep-probe.h> +#include <mach/imx/bbu.h> + +static int var_som_mx7_probe(struct device_d *dev) +{ + imx7_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", BBU_HANDLER_FLAG_DEFAULT); + return 0; +} + +static const struct of_device_id var_som_mx7_of_match[] = { + { .compatible = "variscite,var-som-mx7" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(var_som_mx7_of_match); + +static struct driver_d var_som_mx7_board_driver = { + .name = "board-var-som-mx7", + .probe = var_som_mx7_probe, + .of_compatible = DRV_OF_COMPAT(var_som_mx7_of_match), +}; +postcore_platform_driver(var_som_mx7_board_driver); diff --git a/arch/arm/boards/variscite-som-mx7/flash-header.imxcfg b/arch/arm/boards/variscite-som-mx7/flash-header.imxcfg new file mode 100644 index 0000000000..a8ed640cb2 --- /dev/null +++ b/arch/arm/boards/variscite-som-mx7/flash-header.imxcfg @@ -0,0 +1,100 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * SPDX-FileCopyrightText: 2014-2016 Freescale Semiconductor, Inc. + * SPDX-FileCopyrightText: 2016 Variscite Ltd. + * SPDX-FileCopyrightText: 2022 Gossen Metrawatt GmbH + * SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de> + */ + +soc imx7 +loadaddr 0x80000000 +ivtofs 0x400 + +#include <mach/imx/imx7-ddr-regs.h> + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Change DDR freq. to 400Mhz */ +wm 32 0x30360070 0x00703021 +wm 32 0x30360090 0x00000000 +wm 32 0x30360070 0x00603021 +check 32 until_all_bits_set 0x30360070 0x80000000 +wm 32 0x30389880 0x00000001 + + +wm 32 0x30340004 0x4F400005 /* Enable OCRAM EPDC */ +/* Clear then set bit30 to ensure exit from DDR retention */ +wm 32 0x30360388 0x40000000 +wm 32 0x30360384 0x40000000 + +wm 32 0x30391000 0x00000002 /* deassert presetn */ + +/* ddrc */ +wm 32 0x307a0000 0x01040001 /* mstr */ +wm 32 0x307a01a0 0x80400003 /* dfiupd0 */ +wm 32 0x307a01a4 0x00100020 /* dfiupd1 */ +wm 32 0x307a01a8 0x80100004 /* dfiupd2 */ +wm 32 0x307a0064 0x00400046 /* rfshtmg */ +wm 32 0x307a0490 0x00000001 /* pctrl_0 */ +wm 32 0x307a00d0 0x00020083 /* init0 */ +wm 32 0x307a00d4 0x00690000 /* init1 */ +wm 32 0x307a00dc 0x09300004 /* init3 */ +wm 32 0x307a00e0 0x04080000 /* init4 */ +wm 32 0x307a00e4 0x00100004 /* init5 */ +wm 32 0x307a00f4 0x0000033f /* rankctl */ +wm 32 0x307a0100 0x09081109 /* dramtmg0 */ +wm 32 0x307a0104 0x0007020d /* dramtmg1 */ +wm 32 0x307a0108 0x03040407 /* dramtmg2 */ +wm 32 0x307a010c 0x00002006 /* dramtmg3 */ +wm 32 0x307a0110 0x04020205 /* dramtmg4 */ +wm 32 0x307a0114 0x03030202 /* dramtmg5 */ +wm 32 0x307a0120 0x00000803 /* dramtmg8 */ +wm 32 0x307a0180 0x00800020 /* zqctl0 */ +wm 32 0x307a0190 0x02098204 /* dfitmg0 */ +wm 32 0x307a0194 0x00030303 /* dfitmg1 */ +wm 32 0x307a0200 0x00000016 /* addrmap0 */ +wm 32 0x307a0204 0x00080808 /* addrmap1 */ +wm 32 0x307a0210 0x00000f0f /* addrmap4 */ +wm 32 0x307a0214 0x07070707 /* addrmap5 */ +wm 32 0x307a0218 0x0F070707 /* addrmap6 */ +wm 32 0x307a0240 0x06000604 /* odtcfg */ +wm 32 0x307a0244 0x00000001 /* odtmap */ + +wm 32 0x30391000 0x00000000 /* deassert presetn */ + +/* ddr_phy */ +wm 32 0x30790000 0x17420f40 /* phy_con0 */ +wm 32 0x30790004 0x10210100 /* phy_con1 */ +wm 32 0x30790010 0x00060807 /* phy_con4 */ +wm 32 0x307900b0 0x1010007e /* mdll_con0 */ +wm 32 0x3079009c 0x00000d6e /* drvds_con0 */ +wm 32 0x30790020 0x08080808 /* offset_rd_con0 */ +wm 32 0x30790030 0x08080808 /* offset_wr_con0 */ +wm 32 0x30790050 0x01000010 /* cmd_sdll_con0 (OFFSETD_CON0) */ +wm 32 0x30790050 0x00000010 /* cmd_sdll_con0 (OFFSETD_CON0) */ +wm 32 0x307900c0 0x0e407304 /* zq_con0 */ +wm 32 0x307900c0 0x0e447304 /* zq_con0 */ +wm 32 0x307900c0 0x0e447306 /* zq_con0 */ + +check 32 until_all_bits_set 0x307900c4 0x1 + +wm 32 0x307900c0 0x0e447304 /* zq_con0 */ +wm 32 0x307900c0 0x0e407304 /* zq_con0 */ + + +wm 32 0x30384130 0x00000000 /* Disable Clock */ +wm 32 0x30340020 0x00000178 /* IOMUX_GRP_GRP8 - Start input to PHY */ +wm 32 0x30384130 0x00000002 /* Enable Clock */ +wm 32 0x30790018 0x0000000f /* ddr_phy lp_con0 */ + +check 32 until_all_bits_set 0x307a0004 0x1 diff --git a/arch/arm/boards/variscite-som-mx7/lowlevel.c b/arch/arm/boards/variscite-som-mx7/lowlevel.c new file mode 100644 index 0000000000..ef67fc3b5a --- /dev/null +++ b/arch/arm/boards/variscite-som-mx7/lowlevel.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2022 Roland Hieber, Pengutronix <rhi@pengutronix.de> + +#include <io.h> +#include <common.h> +#include <console.h> +#include <debug_ll.h> + +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> + +#include <linux/sizes.h> + +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/iomux-mx7.h> +#include <mach/imx/imx7-ccm-regs.h> + +static inline void setup_uart(void) +{ + imx7_early_setup_uart_clock(1); + + imx7_setup_pad(MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX); + + imx7_uart_setup_ll(); + + putc_ll('>'); +} + +ENTRY_FUNCTION_WITHSTACK(start_gome_e143_01, 0, r0, r1, r2) +{ + extern char __dtb_imx7d_gome_e143_01_start[]; + + imx7_cpu_lowlevel_init(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + relocate_to_current_adr(); + setup_c(); + + imx7d_barebox_entry(__dtb_imx7d_gome_e143_01_start + get_runtime_offset()); +} diff --git a/arch/arm/boards/versatile/Kconfig b/arch/arm/boards/versatile/Kconfig index 94cba3ba81..66492404e0 100644 --- a/arch/arm/boards/versatile/Kconfig +++ b/arch/arm/boards/versatile/Kconfig @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only if MACH_VERSATILEPB diff --git a/arch/arm/boards/versatile/Makefile b/arch/arm/boards/versatile/Makefile index 89232a7884..5a55d0017d 100644 --- a/arch/arm/boards/versatile/Makefile +++ b/arch/arm/boards/versatile/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_MACH_VERSATILEPB) += versatilepb.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/versatile/env/init/mtdparts-nor b/arch/arm/boards/versatile/env/init/mtdparts-nor deleted file mode 100644 index 20c2b994cc..0000000000 --- a/arch/arm/boards/versatile/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nor0.barebox)ro,512k(nor0.bareboxenv),4864k(nor0.kernel),256k(nor0.dtb),3M(nor0.update),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/versatile/lowlevel.c b/arch/arm/boards/versatile/lowlevel.c index beab04d234..04209dc12c 100644 --- a/arch/arm/boards/versatile/lowlevel.c +++ b/arch/arm/boards/versatile/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> @@ -5,7 +7,7 @@ extern char __dtb_versatile_pb_start[]; -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) +ENTRY_FUNCTION(start_versatile_pb, r0, r1, r2) { void *fdt; diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c index 8691a171e1..610aa90982 100644 --- a/arch/arm/boards/versatile/versatilepb.c +++ b/arch/arm/boards/versatile/versatilepb.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + /* * Copyright (C) 2010 B Labs Ltd, * http://l4dev.org @@ -5,29 +7,15 @@ * * Based on mach-nomadik * Copyright (C) 2009-2010 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * */ #include <common.h> #include <init.h> #include <asm/armlinux.h> #include <asm/system_info.h> -#include <generated/mach-types.h> -#include <mach/init.h> -#include <mach/platform.h> +#include <asm/mach-types.h> +#include <mach/versatile/platform.h> #include <environment.h> -#include <partition.h> #include <linux/sizes.h> #include <platform_data/eth-smc91111.h> @@ -36,6 +24,10 @@ static int vpb_console_init(void) char *hostname = "versatilepb-unknown"; char *model = "ARM Versatile PB"; + if (!of_machine_is_compatible("arm,versatile-pb") && + !of_machine_is_compatible("arm,versatile-ab")) + return 0; + if (cpu_is_arm926()) { hostname = "versatilepb-arm926"; model = "ARM Versatile PB (arm926)"; @@ -44,29 +36,10 @@ static int vpb_console_init(void) model = "ARM Versatile PB (arm1176)"; } + armlinux_set_architecture(MACH_TYPE_VERSATILE_PB); barebox_set_hostname(hostname); barebox_set_model(model); - versatile_register_uart(0); return 0; } console_initcall(vpb_console_init); - -static struct smc91c111_pdata net_pdata = { - .qemu_fixup = 1, -}; - -static int vpb_devices_init(void) -{ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0); - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self"); - devfs_add_partition("nor0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0"); - - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, VERSATILE_ETH_BASE, - 64 * 1024, IORESOURCE_MEM, &net_pdata); - - armlinux_set_architecture(MACH_TYPE_VERSATILE_PB); - - return 0; -} -device_initcall(vpb_devices_init); diff --git a/arch/arm/boards/vexpress/Kconfig b/arch/arm/boards/vexpress/Kconfig deleted file mode 100644 index 94cba3ba81..0000000000 --- a/arch/arm/boards/vexpress/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ - -if MACH_VERSATILEPB - -config ARCH_TEXT_BASE - hex - default 0x01000000 - -endif diff --git a/arch/arm/boards/vexpress/Makefile b/arch/arm/boards/vexpress/Makefile index 2da0494d49..720210d890 100644 --- a/arch/arm/boards/vexpress/Makefile +++ b/arch/arm/boards/vexpress/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += init.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/vexpress/init.c b/arch/arm/boards/vexpress/init.c index 946385393f..f2a1307e45 100644 --- a/arch/arm/boards/vexpress/init.c +++ b/arch/arm/boards/vexpress/init.c @@ -8,8 +8,8 @@ #include <init.h> #include <asm/armlinux.h> #include <asm/system_info.h> -#include <generated/mach-types.h> -#include <mach/devices.h> +#include <asm/mach-types.h> +#include <mach/vexpress/devices.h> #include <environment.h> #include <linux/sizes.h> #include <io.h> @@ -19,9 +19,33 @@ #define V2M_SYS_FLASH 0x03c -static int vexpress_core_init(void) +static int of_fixup_virtio_mmio(struct device_node *root, void *unused) +{ + struct device_node *barebox_root, *np, *parent; + + barebox_root = of_get_root_node(); + if (root == barebox_root) + return 0; + + for_each_compatible_node_from(np, barebox_root, NULL, "virtio,mmio") { + if (of_get_parent(np) == barebox_root) + parent = root; + else + parent = of_find_node_by_path_from(root, + of_get_parent(np)->full_name); + if (!parent) + return -EINVAL; + + of_copy_node(parent, np); + } + + return 0; +} + +static int vexpress_probe(struct device *dev) { char *hostname = "vexpress-unknown"; + int ret = 0; if (amba_is_arm_sp804(IOMEM(0x10011000))) { vexpress_a9_legacy_init(); @@ -42,35 +66,23 @@ static int vexpress_core_init(void) barebox_set_hostname(hostname); - return 0; -} -postcore_initcall(vexpress_core_init); - -static int of_fixup_virtio_mmio(struct device_node *root, void *unused) -{ - struct device_node *barebox_root, *np, *parent; - - barebox_root = of_get_root_node(); - if (root == barebox_root) - return 0; + ret = of_register_fixup(of_fixup_virtio_mmio, NULL); - for_each_compatible_node_from(np, barebox_root, NULL, "virtio,mmio") { - if (of_get_parent(np) == barebox_root) - parent = root; - else - parent = of_find_node_by_path_from(root, - of_get_parent(np)->full_name); - if (!parent) - return -EINVAL; + return ret; +} - of_copy_node(parent, np); - } +static const struct of_device_id vexpress_of_match[] = { + { .compatible = "arm,vexpress,v2p-ca9" }, + { .compatible = "arm,vexpress,v2p-ca15" }, + { .compatible = "arm,vexpress" }, + { /* Sentinel */}, +}; +MODULE_DEVICE_TABLE(of, vexpress_of_match); - return 0; -} +static struct driver vexpress_board_driver = { + .name = "board-vexpress", + .probe = vexpress_probe, + .of_compatible = vexpress_of_match, +}; -static int of_register_virtio_mmio_fixup(void) -{ - return of_register_fixup(of_fixup_virtio_mmio, NULL); -} -late_initcall(of_register_virtio_mmio_fixup); +postcore_platform_driver(vexpress_board_driver); diff --git a/arch/arm/boards/virt2real/Makefile b/arch/arm/boards/virt2real/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/virt2real/Makefile +++ b/arch/arm/boards/virt2real/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/virt2real/board.c b/arch/arm/boards/virt2real/board.c index b7f72171bb..caa2b53a68 100644 --- a/arch/arm/boards/virt2real/board.c +++ b/arch/arm/boards/virt2real/board.c @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #include <common.h> #include <init.h> diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c index a72334bb0e..d14907b768 100644 --- a/arch/arm/boards/virt2real/lowlevel.c +++ b/arch/arm/boards/virt2real/lowlevel.c @@ -1,19 +1,7 @@ -/* - * Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com> - * - * This file is part of barebox. - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> + +/* This file is part of barebox. */ #define __LOWLEVEL_INIT__ diff --git a/arch/arm/boards/vscom-baltos/Makefile b/arch/arm/boards/vscom-baltos/Makefile index 092c31d6b2..5678718188 100644 --- a/arch/arm/boards/vscom-baltos/Makefile +++ b/arch/arm/boards/vscom-baltos/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o obj-y += board.o diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c index 3f9b7d76bb..85cf241574 100644 --- a/arch/arm/boards/vscom-baltos/board.c +++ b/arch/arm/boards/vscom-baltos/board.c @@ -1,20 +1,6 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Raghavendra KH <r-khandenahally@ti.com> - * - * Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) +// SPDX-FileCopyrightText: 2012 Jan Luebbe <j.luebbe@pengutronix.de> /** * @file @@ -31,14 +17,14 @@ #include <net.h> #include <bootsource.h> #include <asm/armlinux.h> -#include <generated/mach-types.h> -#include <mach/am33xx-generic.h> -#include <mach/am33xx-silicon.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/gpmc.h> +#include <asm/mach-types.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/gpmc.h> #include <linux/err.h> -#include <mach/bbu.h> +#include <mach/omap/bbu.h> #include <libfile.h> #include <gpio.h> @@ -59,19 +45,66 @@ struct bsp_vs_hwparam { uint8_t MAC3[6]; } __attribute__ ((packed)); +static uint8_t get_dip_switch(uint16_t id, uint32_t rev) +{ + uint16_t maj, min; + uint8_t dip = 0; + int inputs[4]; + + maj = rev >> 16; + min = rev & 0xffff; + + if ((id == 220 || id == 222) && (maj == 1 && min == 2)) + id = 214; + + switch(id) { + case 214: + case 215: + inputs[0] = gpio_find_by_name("SW2_0_alt"); + inputs[1] = gpio_find_by_name("SW2_1_alt"); + inputs[2] = gpio_find_by_name("SW2_2_alt"); + inputs[3] = gpio_find_by_name("SW2_3_alt"); + dip = !gpio_get_value(inputs[0]); + dip += !gpio_get_value(inputs[1]) << 1; + dip += !gpio_get_value(inputs[2]) << 2; + dip += !gpio_get_value(inputs[3]) << 3; + break; + case 212: + case 221: + case 223: + case 224: + case 225: + case 226: + case 227: + case 230: + inputs[0] = gpio_find_by_name("SW2_0"); + inputs[1] = gpio_find_by_name("SW2_1"); + inputs[2] = gpio_find_by_name("SW2_2"); + inputs[3] = gpio_find_by_name("SW2_3"); + dip = !gpio_get_value(inputs[0]); + dip += !gpio_get_value(inputs[1]) << 1; + dip += !gpio_get_value(inputs[2]) << 2; + dip += !gpio_get_value(inputs[3]) << 3; + break; + } + + return dip; +} + static int baltos_read_eeprom(void) { struct bsp_vs_hwparam hw_param; - size_t size; char *buf, var_buf[32]; int rc; unsigned char mac_addr[6]; + uint8_t dip; + int mpcie_pwr_pin; if (!of_machine_is_compatible("vscom,onrisc")) return 0; rc = read_file_2("/dev/eeprom0", - &size, + NULL, (void *)&buf, sizeof(hw_param)); if (rc && rc != -EFBIG) @@ -113,16 +146,26 @@ static int baltos_read_eeprom(void) globalvar_add_simple("board.id", var_buf); /* enable mPCIe slot */ - gpio_direction_output(100, 1); + mpcie_pwr_pin = gpio_find_by_name("3G_PWR_EN"); + gpio_direction_output(mpcie_pwr_pin, 1); /* configure output signals of the external GPIO controller */ if (hw_param.SystemId == 210 || hw_param.SystemId == 211) { - gpio_direction_output(132, 0); - gpio_direction_output(133, 0); - gpio_direction_output(134, 0); - gpio_direction_output(135, 0); + int outs[4]; + outs[0] = gpio_find_by_name("GP_OUT0"); + outs[1] = gpio_find_by_name("GP_OUT1"); + outs[2] = gpio_find_by_name("GP_OUT2"); + outs[3] = gpio_find_by_name("GP_OUT3"); + gpio_direction_output(outs[0], 0); + gpio_direction_output(outs[1], 0); + gpio_direction_output(outs[2], 0); + gpio_direction_output(outs[3], 0); } + dip = get_dip_switch(hw_param.SystemId, hw_param.HwRev); + sprintf(var_buf, "%02x", dip); + globalvar_add_simple("board.dip", var_buf); + return 0; } environment_initcall(baltos_read_eeprom); diff --git a/arch/arm/boards/vscom-baltos/lowlevel.c b/arch/arm/boards/vscom-baltos/lowlevel.c index 98bbbaae16..aee0cde651 100644 --- a/arch/arm/boards/vscom-baltos/lowlevel.c +++ b/arch/arm/boards/vscom-baltos/lowlevel.c @@ -1,20 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <io.h> #include <linux/string.h> #include <debug_ll.h> +#include <mach/omap/debug_ll.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/am33xx-mux.h> -#include <mach/am33xx-generic.h> -#include <mach/wdt.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/am33xx-mux.h> +#include <mach/omap/am33xx-generic.h> static const struct am33xx_ddr_data ddr3_data = { .rd_slave_ratio0 = 0x38, @@ -66,7 +68,7 @@ static const struct am33xx_emif_regs ddr3_regs_256mb = { }; -extern char __dtb_am335x_baltos_minimal_start[]; +extern char __dtb_z_am335x_baltos_minimal_start[]; /** * @brief The basic entry point for board initialization. @@ -82,15 +84,9 @@ static noinline void baltos_sram_init(void) uint32_t sdram_size; void *fdt; - fdt = __dtb_am335x_baltos_minimal_start; + fdt = __dtb_z_am335x_baltos_minimal_start; - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - __raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); - __raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0); + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); /* Setup the PLLs and the clocks for the peripherals */ am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400); @@ -102,7 +98,7 @@ static noinline void baltos_sram_init(void) am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); am33xx_enable_uart0_pin_mux(); - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); + omap_debug_ll_init(); putc_ll('>'); am335x_barebox_entry(fdt); @@ -132,7 +128,7 @@ ENTRY_FUNCTION(start_am33xx_baltos_sdram, r0, r1, r2) */ __raw_writel(0x000010ff, AM33XX_PRM_RSTTIME); - fdt = __dtb_am335x_baltos_minimal_start; + fdt = __dtb_z_am335x_baltos_minimal_start; fdt += get_runtime_offset(); diff --git a/arch/arm/boards/wago-pfc-am35xx/Makefile b/arch/arm/boards/wago-pfc-am35xx/Makefile index 7bd3009f31..35ac0462cb 100644 --- a/arch/arm/boards/wago-pfc-am35xx/Makefile +++ b/arch/arm/boards/wago-pfc-am35xx/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + lwl-y += lowlevel.o ifdef CONFIG_OMAP_BUILD_IFT obj-y += board-mlo.o diff --git a/arch/arm/boards/wago-pfc-am35xx/board-mlo.c b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c index 7925c71a4b..c5ccdf7faf 100644 --- a/arch/arm/boards/wago-pfc-am35xx/board-mlo.c +++ b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c @@ -8,12 +8,12 @@ #include <init.h> #include <io.h> #include <linux/sizes.h> -#include <mach/omap3-silicon.h> -#include <mach/gpmc.h> -#include <mach/gpmc_nand.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/gpmc_nand.h> #include <errno.h> -#include <mach/omap3-devices.h> -#include <mach/generic.h> +#include <mach/omap/omap3-devices.h> +#include <mach/omap/generic.h> /* map first four erase blocks */ static struct omap_barebox_part pfc200_mlo_part = { @@ -48,7 +48,7 @@ static int pfc200_mem_init(void) } mem_initcall(pfc200_mem_init); -static struct gpmc_nand_platform_data nand_plat = { +__maybe_unused static struct gpmc_nand_platform_data nand_plat = { .cs = 0, .device_width = 8, .ecc_mode = OMAP_ECC_BCH8_CODE_HW_ROMCODE, @@ -62,8 +62,8 @@ static int pfc200_init_devices(void) * WP is made high and WAIT1 active Low */ gpmc_generic_init(0x10); -#endif omap_add_gpmc_nand_device(&nand_plat); +#endif omap_set_barebox_part(&pfc200_mlo_part); omap3_add_mmc1(NULL); diff --git a/arch/arm/boards/wago-pfc-am35xx/board.c b/arch/arm/boards/wago-pfc-am35xx/board.c index c0a039ba50..091e606e21 100644 --- a/arch/arm/boards/wago-pfc-am35xx/board.c +++ b/arch/arm/boards/wago-pfc-am35xx/board.c @@ -14,7 +14,7 @@ #include <linux/phy.h> #include <linux/micrel_phy.h> #include <asm/memory.h> -#include <mach/generic.h> +#include <mach/omap/generic.h> static int pfc200_mem_init(void) { diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c index 7da8fd0331..5429065c2d 100644 --- a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c +++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c @@ -10,22 +10,22 @@ #include <io.h> #include <linux/string.h> #include <debug_ll.h> +#include <mach/omap/debug_ll.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/wdt.h> -#include <mach/omap3-mux.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> -#include <mach/omap3-clock.h> -#include <mach/control.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/omap3-mux.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/omap3-clock.h> +#include <mach/omap/control.h> #include <asm/common.h> #include <asm-generic/memory_layout.h> -#include <mach/emif4.h> +#include <mach/omap/emif4.h> static void mux_config(void) { @@ -185,7 +185,7 @@ static noinline void pfc200_board_init(void) if (IS_ENABLED(CONFIG_DEBUG_LL)) { am33xx_uart_soft_reset(IOMEM(OMAP3_UART3_BASE)); - omap_uart_lowlevel_init(IOMEM(OMAP3_UART3_BASE)); + omap_debug_ll_init(); putc_ll('>'); } @@ -200,7 +200,7 @@ static noinline void pfc200_board_init(void) /* Dont reconfigure SDRAM while running in SDRAM */ if (!in_sdram) - am35xx_emif4_init(); + am35xx_emif4_init(IOMEM(OMAP3_SDRC_BASE)); barebox_arm_entry(0x80000000, SZ_256M, NULL); } diff --git a/arch/arm/boards/webasto-ccbv2/Makefile b/arch/arm/boards/webasto-ccbv2/Makefile new file mode 100644 index 0000000000..da63d2625f --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/webasto-ccbv2/board.c b/arch/arm/boards/webasto-ccbv2/board.c new file mode 100644 index 0000000000..6b2c8b8cb0 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/board.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ + +#include <common.h> +#include <init.h> +#include <mach/imx/generic.h> +#include <mach/imx/bbu.h> +#include <of.h> +#include <string.h> + +#include "ccbv2.h" + +static int ccbv2_probe(struct device *dev) +{ + struct device_node *overlay; + struct fdt_header *fdt; + int ret; + + /* the bootloader is stored in one of the two boot partitions */ + imx6_bbu_internal_mmcboot_register_handler("emmc", "/dev/mmc1", + BBU_HANDLER_FLAG_DEFAULT); + + if (of_machine_is_compatible("webasto,imx6ul-marvel")) + barebox_set_hostname("webasto-marvel"); + else + barebox_set_hostname("webasto-ccbv2"); + + if(!IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE)) + return 0; + + fdt = (void*)OPTEE_OVERLAY_LOCATION; + overlay = of_unflatten_dtb(fdt, INT_MAX); + + if (IS_ERR(overlay)) + return PTR_ERR(overlay); + + ret = of_register_overlay(overlay); + if (ret) { + printf("cannot apply oftree overlay: %s\n", strerror(-ret)); + goto err; + } + + return 0; +err: + of_delete_node(overlay); + return ret; + +} + +static const struct of_device_id ccbv2_of_match[] = { + { .compatible = "webasto,imx6ul-ccbv2" }, + { .compatible = "webasto,imx6ul-marvel" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ccbv2_of_match); + +static struct driver ccbv2_board_driver = { + .name = "board-imx6ul-ccbv2", + .probe = ccbv2_probe, + .of_compatible = ccbv2_of_match, +}; +postcore_platform_driver(ccbv2_board_driver); diff --git a/arch/arm/boards/webasto-ccbv2/ccbv2.h b/arch/arm/boards/webasto-ccbv2/ccbv2.h new file mode 100644 index 0000000000..bf43fe8410 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/ccbv2.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ccbv2.h - common defines between OP-TEE and barebox + * + * Copyright (c) 2019 Rouven Czerwinski <r.czerwinski@pengutronix.de>, Pengutronix + * + */ +#ifndef __CCBV2_H_ +#define __CCBV2_H_ + +/* MX6UL_MMDC_PORT0_BASE_ADDR + SZ_64M */ +#define OPTEE_OVERLAY_LOCATION 0x84000000 + + +#endif // __CCBV2_H_ diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg new file mode 100644 index 0000000000..ef73ec71db --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-256.imxcfg @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +loadaddr 0x80000000 +soc imx6 +ivtofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* IOMUX */ +/* DDR IO type */ +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +/* Clock */ +wm 32 0x020E027C 0x00000028 +/* Control */ +wm 32 0x020E0250 0x00000028 +wm 32 0x020E024C 0x00000028 +wm 32 0x020E0490 0x00000028 +wm 32 0x020E0288 0x00000028 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000028 +wm 32 0x020E0264 0x00000028 +wm 32 0x020E04A0 0x00000028 +/* Data strobe */ +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000028 +wm 32 0x020E0284 0x00000028 +/* Data */ +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000028 +wm 32 0x020E04A4 0x00000028 +wm 32 0x020E0244 0x00000028 +wm 32 0x020E0248 0x00000028 + +/* DDR Controller registers */ +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +/* Calibration values */ +wm 32 0x021B080C 0x000C0000 +wm 32 0x021B083C 0x01610162 +wm 32 0x021B0848 0x40405050 +wm 32 0x021B0850 0x4040544C +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +/* END of calibration values */ +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 + +/* MMDC init */ +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x3F4352F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +/* Consider reducing RALAT (currently set to 5) */ +wm 32 0x021B0018 0x00211740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x00431023 +wm 32 0x021B0040 0x00000047 +wm 32 0x021B0000 0x83180000 + +/* Mode registers writes for CS0 */ +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 + +/* Final DDR setup */ +wm 32 0x021B0020 0x00007800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002556D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 + +/* Disable TZASC bypass */ +wm 32 0x020E4024 0x00000001 + +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg new file mode 100644 index 0000000000..56ca917d10 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/flash-header-imx6ul-webasto-ccbv2-512.imxcfg @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +loadaddr 0x80000000 +soc imx6 +ivtofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +/* IOMUX */ +/* DDR IO type */ +wm 32 0x020E04B4 0x000C0000 +wm 32 0x020E04AC 0x00000000 +/* Clock */ +wm 32 0x020E027C 0x00000028 +/* Control */ +wm 32 0x020E0250 0x00000028 +wm 32 0x020E024C 0x00000028 +wm 32 0x020E0490 0x00000028 +wm 32 0x020E0288 0x00000028 +wm 32 0x020E0270 0x00000000 +wm 32 0x020E0260 0x00000028 +wm 32 0x020E0264 0x00000028 +wm 32 0x020E04A0 0x00000028 +/* Data strobe */ +wm 32 0x020E0494 0x00020000 +wm 32 0x020E0280 0x00000028 +wm 32 0x020E0284 0x00000028 +/* Data */ +wm 32 0x020E04B0 0x00020000 +wm 32 0x020E0498 0x00000028 +wm 32 0x020E04A4 0x00000028 +wm 32 0x020E0244 0x00000028 +wm 32 0x020E0248 0x00000028 + +/* DDR Controller registers */ +wm 32 0x021B001C 0x00008000 +wm 32 0x021B0800 0xA1390003 +/* Calibration values */ +wm 32 0x021B080C 0x00090000 +wm 32 0x021B083C 0x01580158 +wm 32 0x021B0848 0x40405050 +wm 32 0x021B0850 0x4040524C +wm 32 0x021B081C 0x33333333 +wm 32 0x021B0820 0x33333333 +wm 32 0x021B082C 0xf3333333 +wm 32 0x021B0830 0xf3333333 +/* END of calibration values */ +wm 32 0x021B08C0 0x00921012 +wm 32 0x021B08b8 0x00000800 + +/* MMDC init */ +wm 32 0x021B0004 0x0002002D +wm 32 0x021B0008 0x1b333030 +wm 32 0x021B000C 0x676B52F3 +wm 32 0x021B0010 0xB66D0B63 +wm 32 0x021B0014 0x01FF00DB +/* Consider reducing RALAT (currently set to 5) */ +wm 32 0x021B0018 0x00211740 +wm 32 0x021B001C 0x00008000 +wm 32 0x021B002C 0x000026D2 +wm 32 0x021B0030 0x006B1023 +wm 32 0x021B0040 0x0000004F +wm 32 0x021B0000 0x84180000 + +/* Mode registers writes for CS0 */ +wm 32 0x021B001C 0x02008032 +wm 32 0x021B001C 0x00008033 +wm 32 0x021B001C 0x00048031 +wm 32 0x021B001C 0x15208030 +wm 32 0x021B001C 0x04008040 + +/* Final DDR setup */ +wm 32 0x021B0020 0x00007800 +wm 32 0x021B0818 0x00000227 +wm 32 0x021B0004 0x0002556D +wm 32 0x021B0404 0x00011006 +wm 32 0x021B001C 0x00000000 + +/* Disable TZASC bypass */ +wm 32 0x020E4024 0x00000001 + +#include <mach/imx/habv4-imx6-gencsf.h> diff --git a/arch/arm/boards/webasto-ccbv2/lowlevel.c b/arch/arm/boards/webasto-ccbv2/lowlevel.c new file mode 100644 index 0000000000..7a198bd801 --- /dev/null +++ b/arch/arm/boards/webasto-ccbv2/lowlevel.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2019 Rouven Czerwinski, Pengutronix + */ + +#include <common.h> +#include <debug_ll.h> +#include <mach/imx/debug_ll.h> +#include <firmware.h> +#include <mach/imx/generic.h> +#include <asm/barebox-arm.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/iomux-mx6ul.h> +#include <asm/cache.h> +#include <tee/optee.h> + +#include "ccbv2.h" + +static void configure_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + imx6_ungate_all_peripherals(); + + imx_setup_pad(iomuxbase, MX6_PAD_LCD_DATA16__UART7_DCE_TX); + imx_setup_pad(iomuxbase, MX6_PAD_LCD_DATA17__UART7_DCE_RX); + + imx6_uart_setup((void *)MX6_UART7_BASE_ADDR); + + putc_ll('>'); + +} + +static void noinline start_ccbv2(u32 r0, unsigned long mem_size, char *fdt) +{ + int tee_size; + void *tee; + + /* Enable normal/secure r/w for TZC380 region0 */ + writel(0xf0000000, 0x021D0108); + + configure_uart(); + + /* + * Chainloading barebox will pass a device tree within the RAM in r0, + * skip OP-TEE early loading in this case + */ + if(IS_ENABLED(CONFIG_FIRMWARE_CCBV2_OPTEE) + && !(r0 > MX6_MMDC_P0_BASE_ADDR + && r0 < MX6_MMDC_P0_BASE_ADDR + mem_size)) { + get_builtin_firmware(ccbv2_optee_bin, &tee, &tee_size); + + memset((void *)OPTEE_OVERLAY_LOCATION, 0, 0x1000); + + start_optee_early(NULL, tee); + } + + imx6ul_barebox_entry(fdt); +} + +extern char __dtb_z_imx6ul_webasto_ccbv2_start[]; +ENTRY_FUNCTION(start_imx6ul_ccbv2_256m, r0, r1, r2) +{ + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_ccbv2(r0, SZ_256M, __dtb_z_imx6ul_webasto_ccbv2_start); +} + +ENTRY_FUNCTION(start_imx6ul_ccbv2_512m, r0, r1, r2) +{ + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_ccbv2(r0, SZ_512M, __dtb_z_imx6ul_webasto_ccbv2_start); +} + +extern char __dtb_z_imx6ul_webasto_marvel_start[]; +ENTRY_FUNCTION(start_imx6ul_marvel, r0, r1, r2) +{ + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + start_ccbv2(r0, SZ_512M, __dtb_z_imx6ul_webasto_marvel_start); +} diff --git a/arch/arm/boards/wolfvision-pf5/.gitignore b/arch/arm/boards/wolfvision-pf5/.gitignore new file mode 100644 index 0000000000..f458f794b5 --- /dev/null +++ b/arch/arm/boards/wolfvision-pf5/.gitignore @@ -0,0 +1 @@ +sdram-init.bin diff --git a/arch/arm/boards/wolfvision-pf5/Makefile b/arch/arm/boards/wolfvision-pf5/Makefile new file mode 100644 index 0000000000..b37b6c870b --- /dev/null +++ b/arch/arm/boards/wolfvision-pf5/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/wolfvision-pf5/board.c b/arch/arm/boards/wolfvision-pf5/board.c new file mode 100644 index 0000000000..797f51bc2e --- /dev/null +++ b/arch/arm/boards/wolfvision-pf5/board.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Board code for the WolfVision PF5 mainboard. + * + * Copyright (C) 2024 WolfVision GmbH. + */ +#include <common.h> +#include <deep-probe.h> +#include <globalvar.h> +#include <init.h> + +#include <boards/wolfvision/common.h> +#include <mach/rockchip/bbu.h> + +#define PF5_IO_EXPANDER_FILENAME "rk3568-wolfvision-pf5-io-expander.dtbo" +#define PF5_IO_EXPANDER_DATA __dtbo_rk3568_wolfvision_pf5_io_expander_start + +enum { + PF5_HWID_CHANNEL_MAINBOARD = 1, + PF5_HWID_CHANNEL_MODULE = 2, +}; + +extern char PF5_IO_EXPANDER_DATA[]; + +static const struct wv_rk3568_extension pf5_extensions[] = { + { + .adc_chan = PF5_HWID_CHANNEL_MAINBOARD, + .name = "mainboard", + .overlays = { + [0] = { .name = "PF5 DC V1.0 A", }, + [4] = { .name = "PF5 DC V1.1 A", }, + }, + }, + { + .adc_chan = PF5_HWID_CHANNEL_MODULE, + .name = "module", + .overlays = { + [0] = { .name = "PF5 IO Expander V1.0 A", + .filename = PF5_IO_EXPANDER_FILENAME, + .data = PF5_IO_EXPANDER_DATA, + }, + [16] = { .name = "no", }, + }, + }, +}; + +static int pf5_probe(struct device *dev) +{ + char *pf5_overlays = NULL; + int ret; + + barebox_set_model("WolfVision PF5"); + barebox_set_hostname("PF5"); + + ret = wolfvision_register_ethaddr(); + if (ret) + pr_warning("failed to register MAC addresses\n"); + + rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/mmc0"); + + ret = wolfvision_rk3568_detect_hw( + pf5_extensions, ARRAY_SIZE(pf5_extensions), &pf5_overlays); + if (ret) + pr_warning("failed to detect HW\n"); + + if (pf5_overlays) + globalvar_set("of.overlay.filepattern", pf5_overlays); + + free(pf5_overlays); + + return 0; +} + +static const struct of_device_id pf5_of_match[] = { + { + .compatible = "wolfvision,rk3568-pf5", + }, + { /* sentinel */ }, +}; + +static struct driver_d pf5_board_driver = { + .name = "board-wolfvision-pf5", + .probe = pf5_probe, + .of_compatible = pf5_of_match, +}; +coredevice_platform_driver(pf5_board_driver); + +BAREBOX_DEEP_PROBE_ENABLE(pf5_of_match); diff --git a/arch/arm/boards/wolfvision-pf5/lowlevel.c b/arch/arm/boards/wolfvision-pf5/lowlevel.c new file mode 100644 index 0000000000..c20ca4ae13 --- /dev/null +++ b/arch/arm/boards/wolfvision-pf5/lowlevel.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/rockchip/hardware.h> +#include <mach/rockchip/atf.h> +#include <debug_ll.h> +#include <mach/rockchip/rockchip.h> + +extern char __dtb_rk3568_wolfvision_pf5_start[]; + +ENTRY_FUNCTION(start_rk3568_wolfvision_pf5, r0, r1, r2) +{ + /* + * Enable vccio4 1.8V and vccio5 1.8V + * FIXME: This is done by the io-domain driver as well, but there + * currently is no mechanism to make sure the driver gets probed + * before its consumers. Remove this setup once this issue is + * resolved. + */ + writel(RK_SETBITS(0x30), 0xfdc20140); + + /* + * Image execution starts at 0x0, but this is used for ATF and + * OP-TEE later, so move away from here. + */ + if (current_el() == 3) + relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS); + else + relocate_to_current_adr(); + + setup_c(); + + rk3568_barebox_entry(__dtb_rk3568_wolfvision_pf5_start); +} diff --git a/arch/arm/boards/xilinx-zcu102/Makefile b/arch/arm/boards/xilinx-zcu102/Makefile new file mode 100644 index 0000000000..d83a4793aa --- /dev/null +++ b/arch/arm/boards/xilinx-zcu102/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/xilinx-zcu102/board.c b/arch/arm/boards/xilinx-zcu102/board.c new file mode 100644 index 0000000000..3ef668fdff --- /dev/null +++ b/arch/arm/boards/xilinx-zcu102/board.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <driver.h> +#include <init.h> +#include <mach/zynqmp/zynqmp-bbu.h> +#include <deep-probe.h> + +static int zcu102_probe(struct device *dev) +{ + return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN", + BBU_HANDLER_FLAG_DEFAULT); +} + +static const struct of_device_id zcu102_of_match[] = { + { .compatible = "xlnx,zynqmp-zcu102-revA" }, + { .compatible = "xlnx,zynqmp-zcu102-revB" }, + { /* sentinel */ }, +}; +BAREBOX_DEEP_PROBE_ENABLE(zcu102_of_match); + +static struct driver zcu102_board_driver = { + .name = "board-zynqmp-zcu102", + .probe = zcu102_probe, + .of_compatible = zcu102_of_match, +}; +coredevice_platform_driver(zcu102_board_driver); diff --git a/arch/arm/boards/xilinx-zcu102/lowlevel.c b/arch/arm/boards/xilinx-zcu102/lowlevel.c new file mode 100644 index 0000000000..4b72c0ec43 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu102/lowlevel.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <debug_ll.h> +#include <asm/barebox-arm.h> + +ENTRY_FUNCTION_WITHSTACK(start_zynqmp_zcu102, 0x80000000, x0, x1, x2) +{ + extern char __dtb_z_zynqmp_zcu102_revB_start[]; + + /* Assume that the first stage boot loader configured the UART */ + putc_ll('>'); + + barebox_arm_entry(0, SZ_2G, runtime_address(__dtb_z_zynqmp_zcu102_revB_start)); +} diff --git a/arch/arm/boards/xilinx-zcu104/Makefile b/arch/arm/boards/xilinx-zcu104/Makefile index 884d6e63b0..297f77d57a 100644 --- a/arch/arm/boards/xilinx-zcu104/Makefile +++ b/arch/arm/boards/xilinx-zcu104/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-or-later +obj-y += board.o lwl-y += lowlevel.o lowlevel_init.o diff --git a/arch/arm/boards/xilinx-zcu104/board.c b/arch/arm/boards/xilinx-zcu104/board.c new file mode 100644 index 0000000000..26dc6c9613 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu104/board.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 Michael Tretter <m.tretter@pengutronix.de> + */ + +#include <common.h> +#include <init.h> +#include <mach/zynqmp/zynqmp-bbu.h> + +static int zcu104_register_update_handler(void) +{ + if (!of_machine_is_compatible("xlnx,zynqmp-zcu104")) + return 0; + + return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN", + BBU_HANDLER_FLAG_DEFAULT); +} +device_initcall(zcu104_register_update_handler); diff --git a/arch/arm/boards/xilinx-zcu106/Makefile b/arch/arm/boards/xilinx-zcu106/Makefile new file mode 100644 index 0000000000..297f77d57a --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +obj-y += board.o +lwl-y += lowlevel.o lowlevel_init.o diff --git a/arch/arm/boards/xilinx-zcu106/board.c b/arch/arm/boards/xilinx-zcu106/board.c new file mode 100644 index 0000000000..3c8c3d21f2 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/board.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch <michael.riesch@wolfvision.net> + * + * Based on the barebox ZCU104 board support code. + */ + +#include <common.h> +#include <init.h> +#include <mach/zynqmp/zynqmp-bbu.h> + +static int zcu106_register_update_handler(void) +{ + if (!of_machine_is_compatible("xlnx,zynqmp-zcu106")) + return 0; + + return zynqmp_bbu_register_handler("SD", "/boot/BOOT.BIN", + BBU_HANDLER_FLAG_DEFAULT); +} +device_initcall(zcu106_register_update_handler); diff --git a/arch/arm/boards/xilinx-zcu106/lowlevel.c b/arch/arm/boards/xilinx-zcu106/lowlevel.c new file mode 100644 index 0000000000..ccc8d61418 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/lowlevel.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, WolfVision GmbH + * Author: Michael Riesch <michael.riesch@wolfvision.net> + * + * Based on the barebox ZCU104 board support code. + */ + +#include <common.h> +#include <debug_ll.h> +#include <asm/barebox-arm.h> + +extern char __dtb_zynqmp_zcu106_revA_start[]; + +void zynqmp_zcu106_start(uint32_t, uint32_t, uint32_t); + +void noinline zynqmp_zcu106_start(uint32_t r0, uint32_t r1, uint32_t r2) +{ + /* Assume that the first stage boot loader configured the UART */ + putc_ll('>'); + + barebox_arm_entry(0, SZ_2G, + __dtb_zynqmp_zcu106_revA_start + global_variable_offset()); +} diff --git a/arch/arm/boards/xilinx-zcu106/lowlevel_init.S b/arch/arm/boards/xilinx-zcu106/lowlevel_init.S new file mode 100644 index 0000000000..f3d55dcef2 --- /dev/null +++ b/arch/arm/boards/xilinx-zcu106/lowlevel_init.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +/* The DRAM is already setup */ +#define STACK_TOP 0x80000000 + +ENTRY_PROC(start_zynqmp_zcu106) + mov x0, #STACK_TOP + mov sp, x0 + b zynqmp_zcu106_start +ENTRY_PROC_END(start_zynqmp_zcu106) diff --git a/arch/arm/boards/zii-common/Makefile b/arch/arm/boards/zii-common/Makefile index fcc5cdf97d..7488148cff 100644 --- a/arch/arm/boards/zii-common/Makefile +++ b/arch/arm/boards/zii-common/Makefile @@ -1 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o switch-cmd.o pn-fixup.o +bbenv-y += defaultenv-zii-common diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c index eafb5a3aa8..96f9243591 100644 --- a/arch/arm/boards/zii-common/board.c +++ b/arch/arm/boards/zii-common/board.c @@ -1,23 +1,13 @@ -/* - * Copyright (C) 2019 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Zodiac Inflight Innovation #include <common.h> +#include <fs.h> #include <globalvar.h> #include <init.h> -#include <fs.h> -#include <net.h> #include <linux/nvmem-consumer.h> +#include <net.h> +#include <restart.h> static int rdu_eth_register_ethaddr(struct device_node *np) { @@ -78,7 +68,7 @@ late_initcall(rdu_ethernet_init); static int rdu_networkconfig(void) { static char *rdu_netconfig; - struct device_d *sp_dev; + struct device *sp_dev; if (!of_machine_is_compatible("zii,imx8mq-ultra") && !of_machine_is_compatible("zii,imx6q-zii-rdu2") && @@ -103,6 +93,8 @@ static int rdu_networkconfig(void) } late_initcall(rdu_networkconfig); +#ifdef CONFIG_PCI_IMX6 + #define I210_CFGWORD_PCIID_157B 0x157b1a11 static int rdu_i210_invm(void) { @@ -129,6 +121,11 @@ static int rdu_i210_invm(void) val = I210_CFGWORD_PCIID_157B; pwrite(fd, &val, sizeof(val), 0); + shutdown_barebox(); + restart_machine(); + return 0; } late_initcall(rdu_i210_invm); + +#endif diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/net b/arch/arm/boards/zii-common/defaultenv-zii-common/boot/net index 4090c2f4a9..8b07cbbc99 100644 --- a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/boot/net +++ b/arch/arm/boards/zii-common/defaultenv-zii-common/boot/net @@ -2,8 +2,13 @@ path="/mnt/tftp" -# clear seat network config -global.linux.bootargs.rdu_network= +# +# Clear seat network config. Some boards don't have that config, so +# check that it is set first +# +if [ -n ${global.linux.bootargs.rdu_network} ]; then + global.linux.bootargs.rdu_network= +fi global.bootm.image="${path}/${global.user}-linux-${global.hostname}" @@ -21,4 +26,4 @@ if [ -f "${initramfs}" ]; then global.bootm.initrd="$initramfs" else global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" -fi
\ No newline at end of file +fi diff --git a/arch/arm/boards/zii-common/pn-fixup.c b/arch/arm/boards/zii-common/pn-fixup.c index a665199917..3c69f1a022 100644 --- a/arch/arm/boards/zii-common/pn-fixup.c +++ b/arch/arm/boards/zii-common/pn-fixup.c @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2019 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Zodiac Inflight Innovation #include <common.h> #include <init.h> @@ -22,7 +11,7 @@ char *zii_read_part_number(const char *cell_name, size_t cell_size) { struct device_node *np; - np = of_find_node_by_name(NULL, "device-info"); + np = of_find_node_by_name_address(NULL, "device-info"); if (!np) { pr_warn("No device information found\n"); return ERR_PTR(-ENOENT); diff --git a/arch/arm/boards/zii-common/pn-fixup.h b/arch/arm/boards/zii-common/pn-fixup.h index 925e8ad634..657221dc2e 100644 --- a/arch/arm/boards/zii-common/pn-fixup.h +++ b/arch/arm/boards/zii-common/pn-fixup.h @@ -1,16 +1,5 @@ -/* - * Copyright (C) 2019 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2019 Zodiac Inflight Innovation #ifndef __ZII_PN_FIXUP__ #define __ZII_PN_FIXUP__ diff --git a/arch/arm/boards/zii-common/switch-cmd.c b/arch/arm/boards/zii-common/switch-cmd.c index 2b9c34bfac..6aa1c391f4 100644 --- a/arch/arm/boards/zii-common/switch-cmd.c +++ b/arch/arm/boards/zii-common/switch-cmd.c @@ -1,16 +1,6 @@ -/* - * Copyright (C) 2018 Zodiac Inflight Innovation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2018 Zodiac Inflight Innovation + #include <command.h> #include <common.h> #include <i2c/i2c.h> @@ -18,30 +8,60 @@ static int do_rdu2_switch_reset(void) { - struct i2c_client client; + struct device_node *np; + struct i2c_client *client; + int ret; u8 reg; - client.adapter = i2c_get_adapter(1); - if (!client.adapter) + np = of_find_compatible_node(NULL, NULL, "zii,rave-wdt"); + if (!np) { + pr_err("No switch watchdog node found\n"); return -ENODEV; + } + + if (!of_device_is_available(np)) { + /* + * If switch watchdog device is not available assume + * it was removed for a reason and switch reset + * command should be a no-op + */ + return 0; + } + + client = of_find_i2c_device_by_node(np); + if (!client) { + pr_err("No switch watchdog I2C device found\n"); + return -ENODEV; + } - /* address of the switch watchdog microcontroller */ - client.addr = 0x38; reg = 0x78; + /* set switch reset time to 100ms */ - i2c_write_reg(&client, 0x0a, ®, 1); + ret = i2c_write_reg(client, 0x0a, ®, 1); + if (ret < 0) { + pr_err("Failed to set switch reset time\n"); + return ret; + } /* reset the switch */ reg = 0x01; - i2c_write_reg(&client, 0x0d, ®, 1); + ret = i2c_write_reg(client, 0x0d, ®, 1); + if (ret < 0) { + pr_err("Failed to reset the switch\n"); + return ret; + } /* issue dummy command to work around firmware bug */ - i2c_read_reg(&client, 0x01, ®, 1); + ret = i2c_read_reg(client, 0x01, ®, 1); + if (ret < 0) { + pr_err("Failed to issue a dummy command\n"); + return ret; + } return 0; } static int do_rdu1_switch_reset(void) { - struct device_d *sp_dev = get_device_by_name("sp"); + struct device *sp_dev = get_device_by_name("sp"); struct rave_sp *sp = sp_dev->parent->priv; u8 cmd[] = { [0] = RAVE_SP_CMD_RESET_ETH_SWITCH, @@ -57,7 +77,8 @@ static int do_rdu1_switch_reset(void) static int do_rave_switch_reset(int argc, char *argv[]) { if (of_machine_is_compatible("zii,imx6q-zii-rdu2") || - of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + of_machine_is_compatible("zii,imx6qp-zii-rdu2") || + of_machine_is_compatible("zii,imx8mq-ultra")) return do_rdu2_switch_reset(); if (of_machine_is_compatible("zii,imx51-rdu1")) diff --git a/arch/arm/boards/zii-imx51-rdu1/Makefile b/arch/arm/boards/zii-imx51-rdu1/Makefile index 604b3621be..96663f9ae8 100644 --- a/arch/arm/boards/zii-imx51-rdu1/Makefile +++ b/arch/arm/boards/zii-imx51-rdu1/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o -CFLAGS_pbl-lowlevel.o := -fno-tree-switch-conversion -fno-jump-tables lwl-y += lowlevel.o +bbenv-y += defaultenv-rdu1 diff --git a/arch/arm/boards/zii-imx51-rdu1/board.c b/arch/arm/boards/zii-imx51-rdu1/board.c index f739f3b7b4..b72219b4bc 100644 --- a/arch/arm/boards/zii-imx51-rdu1/board.c +++ b/arch/arm/boards/zii-imx51-rdu1/board.c @@ -16,18 +16,17 @@ */ #include <common.h> +#include <envfs.h> #include <init.h> #include <environment.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> #include <libfile.h> -#include <mach/imx5.h> +#include <mach/imx/imx5.h> #include <net.h> #include <linux/crc8.h> #include <linux/sizes.h> #include <linux/nvmem-consumer.h> -#include <envfs.h> - static int zii_rdu1_init(void) { const char *hostname; @@ -49,6 +48,9 @@ static int zii_rdu1_init(void) BBU_HANDLER_FLAG_DEFAULT | IMX_BBU_FLAG_PARTITION_STARTS_AT_HEADER); + defaultenv_append_directory(defaultenv_zii_common); + defaultenv_append_directory(defaultenv_rdu1); + return 0; } coredevice_initcall(zii_rdu1_init); @@ -95,7 +97,7 @@ static int zii_rdu1_load_config(void) file = "shadow copy in RAVE SP EEPROM"; root = of_get_root_node(); - np = of_find_node_by_name(root, "eeprom@a4"); + np = of_find_node_by_name_address(root, "eeprom@a4"); if (!np) return -ENODEV; diff --git a/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/boot/nfs b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/boot/nfs new file mode 100644 index 0000000000..0a2fa07b16 --- /dev/null +++ b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/boot/nfs @@ -0,0 +1,6 @@ +#!/bin/sh + +# clear seat network config (not implemented on RDU1 yet) +#global.linux.bootargs.rdu_network= + +boot /mnt/nfs diff --git a/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/boot/rdu-default b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/boot/rdu-default new file mode 100644 index 0000000000..97cc1dcdea --- /dev/null +++ b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/boot/rdu-default @@ -0,0 +1,14 @@ +#!/bin/sh + +sp.usb_power=1 +usb +if [ "$bootsource" = "spi" ]; then + boot disk1.0 || boot disk2.0 +else + detect mmc0 + if [ "$mmc0.boot" = "boot0" ]; then + boot mmc0.0 + else + boot mmc0.1 + fi +fi diff --git a/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/network/eth0-discover b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/network/eth0-discover new file mode 100644 index 0000000000..ce35613ef1 --- /dev/null +++ b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +sp.usb_power=1 +usb diff --git a/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/nv/autoboot_abort_key b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/nv/autoboot_abort_key new file mode 100644 index 0000000000..55920c9a58 --- /dev/null +++ b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/nv/autoboot_abort_key @@ -0,0 +1 @@ +ctrl-c
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/nv/boot.default b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/nv/boot.default new file mode 100644 index 0000000000..9076a1e64e --- /dev/null +++ b/arch/arm/boards/zii-imx51-rdu1/defaultenv-rdu1/nv/boot.default @@ -0,0 +1 @@ +rdu-default
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg index 76f4c6b59b..6d40976b83 100644 --- a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg +++ b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg @@ -1,6 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 diff --git a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c index c7bb044e0d..2418fe69ae 100644 --- a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c +++ b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c @@ -1,9 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <debug_ll.h> -#include <mach/clock-imx51_53.h> -#include <mach/iomux-mx51.h> +#include <mach/imx/debug_ll.h> +#include <mach/imx/clock-imx51_53.h> +#include <mach/imx/iomux-mx51.h> #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile index c6285362f2..31b592bd36 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/Makefile +++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-rdu2 diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index 63367a419a..88912a5108 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <envfs.h> @@ -19,8 +9,8 @@ #include <gpio.h> #include <i2c/i2c.h> #include <init.h> -#include <mach/bbu.h> -#include <mach/imx6.h> +#include <mach/imx/bbu.h> +#include <mach/imx/imx6.h> #include <net.h> #include <linux/nvmem-consumer.h> #include "../zii-common/pn-fixup.h" @@ -127,8 +117,11 @@ static int rdu2_devices_init(void) { struct i2c_client client; - if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && - !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + if (of_machine_is_compatible("zii,imx6q-zii-rdu2")) + barebox_set_hostname("rdu2"); + else if (of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + barebox_set_hostname("rdu2p"); + else return 0; client.adapter = i2c_get_adapter(1); @@ -146,13 +139,13 @@ static int rdu2_devices_init(void) i2c_write_reg(&client, 0x2e, ®, 1); } - barebox_set_hostname("rdu2"); - imx6_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox", BBU_HANDLER_FLAG_DEFAULT); imx6_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc3", 0); + imx6_bbu_internal_mmc_register_handler("SD", "/dev/mmc1", 0); + defaultenv_append_directory(defaultenv_zii_common); defaultenv_append_directory(defaultenv_rdu2); return 0; @@ -161,7 +154,7 @@ device_initcall(rdu2_devices_init); static int rdu2_fixup_egalax_ts(struct device_node *root, void *context) { - struct device_node *np; + struct device_node *np, *aliases; /* * The 32" unit has a EETI eGalax touchscreen instead of the @@ -180,8 +173,12 @@ static int rdu2_fixup_egalax_ts(struct device_node *root, void *context) return -ENODEV; of_device_enable(np); - of_property_write_u32(np->parent, "clock-frequency", 200000); + aliases = of_find_node_by_path_from(root, "/aliases"); + if (!aliases) + return -ENODEV; + + of_property_write_string(aliases, "touchscreen0", np->full_name); return 0; } @@ -202,19 +199,19 @@ static int rdu2_fixup_dsa(struct device_node *root, void *context) if (!switch_np) return -ENODEV; - np = of_find_node_by_name(switch_np, "port@2"); + np = of_find_node_by_name_address(switch_np, "port@2"); if (!np) return -ENODEV; of_delete_node(np); - np = of_find_node_by_name(root, "i210@0"); + np = of_find_node_by_name_address(root, "i210@0"); if (!np) return -ENODEV; i210_handle = of_node_create_phandle(np); - np = of_find_node_by_name(switch_np, "port@0"); + np = of_find_node_by_name_address(switch_np, "port@0"); if (!np) return -ENODEV; @@ -268,7 +265,7 @@ static int rdu2_fixup_lvds(struct device_node *root, /* * LVDS panels need the correct timings */ - np = of_find_node_by_name(root, "panel"); + np = of_find_node_by_name_address(root, "panel"); if (!np) return -ENODEV; @@ -283,7 +280,7 @@ static int rdu2_fixup_lvds(struct device_node *root, * Delete all mode entries, which aren't suited for the * current display */ - np = of_find_node_by_name(np, "display-timings"); + np = of_find_node_by_name_address(np, "display-timings"); if (!np) return -ENODEV; @@ -308,7 +305,7 @@ static int rdu2_fixup_lvds(struct device_node *root, if (fixup->type == IT_DUAL_LVDS) of_set_property(np, "fsl,dual-channel", NULL, 0, 1); - np = of_find_node_by_name(np, "lvds-channel@0"); + np = of_find_node_by_name_address(np, "lvds-channel@0"); if (!np) return -ENODEV; diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/net b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/net deleted file mode 100644 index 4090c2f4a9..0000000000 --- a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/net +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/sh - -path="/mnt/tftp" - -# clear seat network config -global.linux.bootargs.rdu_network= - -global.bootm.image="${path}/${global.user}-linux-${global.hostname}" - -oftree="${path}/${global.user}-oftree-${global.hostname}" -if [ -f "${oftree}" ]; then - global.bootm.oftree="$oftree" -fi - -nfsroot="/home/${global.user}/nfsroot/${global.hostname}" - -ip_route_get -b ${global.net.server} global.linux.bootargs.dyn.ip - -initramfs="${path}/${global.user}-initramfs-${global.hostname}" -if [ -f "${initramfs}" ]; then - global.bootm.initrd="$initramfs" -else - global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp" -fi
\ No newline at end of file diff --git a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default index f391d91eba..e3406d5543 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default +++ b/arch/arm/boards/zii-imx6q-rdu2/defaultenv-rdu2/boot/rdu-default @@ -2,6 +2,10 @@ backlight0.brightness=0 if [ "$bootsource" = "spi-nor" ]; then + echo Boot source is SPI NOR, booting SD card firmware with rootfs on SD card + boot mmc1 +elif [ "$bootsource" = "mmc" ] && [ "$bootsource_instance" = "1" ]; then + echo Boot source is SD card, booting SD card firmware with rootfs on SD card boot mmc1 else detect mmc3 diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg index a4abe197e4..0b37ab248f 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg +++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg @@ -1,4 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx6 loadaddr 0x00907000 max_load_size 0x31000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c index 87e634509f..5c94b120d3 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c +++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c @@ -1,25 +1,16 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <common.h> -#include <mach/esdctl.h> -#include <mach/generic.h> -#include <mach/imx6.h> -#include <mach/xload.h> -#include <mach/iomux-mx6.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx6.h> +#include <mach/imx/xload.h> +#include <mach/imx/iomux-mx6.h> #include <asm/barebox-arm.h> struct reginit { diff --git a/arch/arm/boards/zii-imx7d-dev/Makefile b/arch/arm/boards/zii-imx7d-dev/Makefile index e1baed17ba..da63d2625f 100644 --- a/arch/arm/boards/zii-imx7d-dev/Makefile +++ b/arch/arm/boards/zii-imx7d-dev/Makefile @@ -1,3 +1,4 @@ -CFLAGS_pbl-lowlevel.o := -fno-tree-switch-conversion -fno-jump-tables +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/zii-imx7d-dev/board.c b/arch/arm/boards/zii-imx7d-dev/board.c index 89f0515306..2d7b589908 100644 --- a/arch/arm/boards/zii-imx7d-dev/board.c +++ b/arch/arm/boards/zii-imx7d-dev/board.c @@ -9,11 +9,11 @@ #include <init.h> #include <io.h> #include <gpio.h> -#include <mach/imx7-regs.h> +#include <mach/imx/imx7-regs.h> #include <mfd/imx7-iomuxc-gpr.h> #include <environment.h> #include <envfs.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> static void zii_imx7d_rpu2_init_fec(void) { @@ -33,7 +33,7 @@ static void zii_imx7d_rpu2_init_fec(void) static int zii_imx7d_rpu2_coredevices_init(void) { - if (!of_machine_is_compatible("zii,imx7d-zii-rpu2") && + if (!of_machine_is_compatible("zii,imx7d-rpu2") && !of_machine_is_compatible("zii,imx7d-rmu2")) return 0; @@ -48,3 +48,17 @@ static int zii_imx7d_rpu2_coredevices_init(void) } coredevice_initcall(zii_imx7d_rpu2_coredevices_init); +static int zii_imx7d_dev_init(void) +{ + if (of_machine_is_compatible("zii,imx7d-rpu2")) + barebox_set_hostname("rpu2"); + else if (of_machine_is_compatible("zii,imx7d-rmu2")) + barebox_set_hostname("rmu2"); + else + return 0; + + defaultenv_append_directory(defaultenv_zii_common); + + return 0; +} +late_initcall(zii_imx7d_dev_init); diff --git a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg index 46f3d95048..053680f76d 100644 --- a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg +++ b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg @@ -1,6 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg> +#include <mach/imx/flash-header/imx7d-ddr-sabresd.imxcfg> diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c index 3bacfd0c7d..2b2ad6aa84 100644 --- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c @@ -9,31 +9,24 @@ #include <io.h> #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx7-ccm-regs.h> -#include <mach/iomux-mx7.h> -#include <mach/debug_ll.h> +#include <mach/imx/imx7-ccm-regs.h> +#include <mach/imx/iomux-mx7.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> -#include <mach/esdctl.h> +#include <mach/imx/esdctl.h> extern char __dtb_z_imx7d_zii_rpu2_start[]; extern char __dtb_z_imx7d_zii_rmu2_start[]; static inline void setup_uart(void) { - void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR); - void __iomem *ccm = IOMEM(MX7_CCM_BASE_ADDR); + /* FIXME: Below UART2 is muxed, not UART1 */ + imx7_early_setup_uart_clock(1); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2)); - writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M, - ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART2)); - - mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); + imx7_setup_pad(MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX); imx7_uart_setup_ll(); diff --git a/arch/arm/boards/zii-imx8mq-dev/Makefile b/arch/arm/boards/zii-imx8mq-dev/Makefile index d0148b5067..8894e40b5a 100644 --- a/arch/arm/boards/zii-imx8mq-dev/Makefile +++ b/arch/arm/boards/zii-imx8mq-dev/Makefile @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o ddr_init.o ddrphy_train.o bbenv-y += defaultenv-imx8mq-zii-dev diff --git a/arch/arm/boards/zii-imx8mq-dev/board.c b/arch/arm/boards/zii-imx8mq-dev/board.c index 144adb9cef..3581c7251d 100644 --- a/arch/arm/boards/zii-imx8mq-dev/board.c +++ b/arch/arm/boards/zii-imx8mq-dev/board.c @@ -10,24 +10,194 @@ #include <init.h> #include <asm/memory.h> #include <linux/sizes.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> +#include "../zii-common/pn-fixup.h" + +#define LRU_FLAG_EGALAX BIT(0) +#define LRU_FLAG_NO_DEB BIT(1) + +struct zii_imx8mq_dev_lru_fixup { + struct zii_pn_fixup fixup; + unsigned int flags; +}; static int zii_imx8mq_dev_init(void) { if (!of_machine_is_compatible("zii,imx8mq-ultra")) return 0; - barebox_set_hostname("imx8mq-zii-rdu3"); + if (of_machine_is_compatible("zii,imx8mq-ultra-zest")) + barebox_set_hostname("zest"); + if (of_machine_is_compatible("zii,imx8mq-ultra-rmb3")) + barebox_set_hostname("rmb3"); - imx8mq_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", 0); + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", + BBU_HANDLER_FLAG_DEFAULT); + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1", 0); if (bootsource_get_instance() == 0) of_device_enable_path("/chosen/environment-emmc"); else of_device_enable_path("/chosen/environment-sd"); + defaultenv_append_directory(defaultenv_zii_common); defaultenv_append_directory(defaultenv_imx8mq_zii_dev); return 0; } device_initcall(zii_imx8mq_dev_init); + +static int zii_imx8mq_dev_fixup_egalax_ts(struct device_node *root, void *ctx) +{ + struct device_node *np, * aliases; + + /* + * The 27" unit has a EETI eGalax touchscreen instead of the + * Synaptics RMI4 found on other units. + */ + pr_info("Enabling eGalax touchscreen instead of RMI4\n"); + + np = of_find_compatible_node(root, NULL, "syna,rmi4-i2c"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + np = of_find_compatible_node(root, NULL, "eeti,exc3000"); + if (!np) + return -ENODEV; + + of_device_enable(np); + + aliases = of_find_node_by_path_from(root, "/aliases"); + if (!aliases) + return -ENODEV; + + of_property_write_string(aliases, "touchscreen0", np->full_name); + + return 0; +} + +static int zii_imx8mq_dev_fixup_deb_internal(void) +{ + struct device_node *np, *aliases; + struct device *dev; + + /* + * In the internal DT remove the complete FEC hierarchy and move the + * i210 to be the eth0 interface to allow network boot to work without + * rewriting all the boot scripts. + */ + aliases = of_find_node_by_path("/aliases"); + if (!aliases) + return -ENODEV; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-fec"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + of_property_write_string(aliases, "ethernet1", np->full_name); + + dev = of_find_device_by_node(np); + if (!dev) + return -ENODEV; + + unregister_device(dev); + + np = of_find_node_by_name_address(NULL, "i210@0"); + if (!np) + return -ENODEV; + + of_property_write_string(aliases, "ethernet0", np->full_name); + + /* Refresh the internal aliases list from the patched DT */ + of_alias_scan(); + + /* + * Disable switch watchdog to make rave_reset_switch a no-op + */ + np = of_find_compatible_node(NULL, NULL, "zii,rave-wdt"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + return 0; +} + +static int zii_imx8mq_dev_fixup_deb(struct device_node *root, void *ctx) +{ + struct device_node *np, *aliases; + struct property *pp; + + /* + * In the kernel DT remove all devices from the DEB, which isn't + * present on this system. + */ + np = of_find_compatible_node(root, NULL, "marvell,mv88e6085"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + np = of_find_compatible_node(root, NULL, "zii,rave-wdt"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + aliases = of_find_node_by_path_from(root, "/aliases"); + if (!aliases) + return -ENODEV; + + pp = of_find_property(aliases, "ethernet-switch0", NULL); + if (!pp) + return -ENODEV; + + of_delete_property(pp); + + return 0; +} + +static void zii_imx8mq_dev_lru_fixup(const struct zii_pn_fixup *context) +{ + const struct zii_imx8mq_dev_lru_fixup *fixup = + container_of(context, struct zii_imx8mq_dev_lru_fixup, fixup); + + if (fixup->flags & LRU_FLAG_EGALAX) + of_register_fixup(zii_imx8mq_dev_fixup_egalax_ts, NULL); + + if (fixup->flags & LRU_FLAG_NO_DEB) { + zii_imx8mq_dev_fixup_deb_internal(); + of_register_fixup(zii_imx8mq_dev_fixup_deb, NULL); + } +} + +#define ZII_IMX8MQ_DEV_LRU_FIXUP(__pn, __flags) \ + { \ + { __pn, zii_imx8mq_dev_lru_fixup }, \ + __flags \ + } + +static const struct zii_imx8mq_dev_lru_fixup zii_imx8mq_dev_lru_fixups[] = { + ZII_IMX8MQ_DEV_LRU_FIXUP("00-5131-02", LRU_FLAG_EGALAX), + ZII_IMX8MQ_DEV_LRU_FIXUP("00-5131-03", LRU_FLAG_EGALAX), + ZII_IMX8MQ_DEV_LRU_FIXUP("00-5170-01", LRU_FLAG_NO_DEB), +}; + +/* + * This initcall needs to be executed before coredevices, so we have a chance + * to fix up the devices with the correct information. + */ +static int zii_imx8mq_dev_process_fixups(void) +{ + if (!of_machine_is_compatible("zii,imx8mq-ultra")) + return 0; + + zii_process_lru_fixups(zii_imx8mq_dev_lru_fixups); + + return 0; +} +postmmu_initcall(zii_imx8mq_dev_process_fixups); diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr.h b/arch/arm/boards/zii-imx8mq-dev/ddr.h index 1293ad3f34..a395211e62 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddr.h +++ b/arch/arm/boards/zii-imx8mq-dev/ddr.h @@ -8,7 +8,7 @@ */ #include <common.h> #include <io.h> -#include <mach/imx8-ddrc.h> +#include <soc/imx8m/ddr.h> /* * Code generated by i.MX8 M DDR Tool doesn't have any prefixes in the @@ -20,10 +20,3 @@ void zii_imx8mq_rdu3_ddr_init(void); void zii_imx8mq_rdu3_ddr_cfg_phy(void); - -#define FW_1D_IMAGE lpddr4_pmu_train_1d_imem_bin, \ - lpddr4_pmu_train_1d_dmem_bin -#define FW_2D_IMAGE lpddr4_pmu_train_2d_imem_bin, \ - lpddr4_pmu_train_2d_dmem_bin - - diff --git a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c index 7a955193fd..2d4133fb13 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddr_init.c +++ b/arch/arm/boards/zii-imx8mq-dev/ddr_init.c @@ -81,6 +81,7 @@ void ddr_init(void) reg32_write(0x3d400200,0x17); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); + reg32_write(0x3d40021c,0xf0f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x7070707); @@ -177,7 +178,7 @@ void ddr_init(void) reg32_write(DDRC_SWCTL(0), 0x0000); /* * ------------------- 9 ------------------- - * Set DFIMISC.dfi_init_start to 1 + * Set DFIMISC.dfi_init_start to 1 * ----------------------------------------- */ reg32_write(DDRC_DFIMISC(0), 0x00000030); @@ -222,4 +223,4 @@ void ddr_init(void) /* enable DDR auto-refresh mode */ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; reg32_write(DDRC_RFSHCTL3(0), tmp); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c index 1b30ff7257..bac7d0a517 100644 --- a/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c +++ b/arch/arm/boards/zii-imx8mq-dev/ddrphy_train.c @@ -11,6 +11,8 @@ void ddr_cfg_phy(void) { unsigned int tmp, tmp_t; + ddr_get_firmware(DRAM_TYPE_LPDDR4); + //Init DDRPHY register... reg32_write(0x3c080440,0x2); reg32_write(0x3c080444,0x3); @@ -142,7 +144,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 1D training image - ddr_load_train_code(FW_1D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_1D_IMAGE); //configure DDRPHY-FW DMEM structure @clock0... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -187,7 +189,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //configure DDRPHY-FW DMEM structure @clock1... reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -256,7 +258,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //set the PHY input clock to the desired frequency for pstate 0 reg32_write(0x3038a088,0x7070000); @@ -289,7 +291,7 @@ void ddr_cfg_phy(void) { //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); //load the 2D training image - ddr_load_train_code(FW_2D_IMAGE); + imx8m_ddr_load_train_code(DRAM_TYPE_LPDDR4, FW_2D_IMAGE); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xc80); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); @@ -330,7 +332,7 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); + imx8m_wait_ddrphy_training_complete(); //Halt MPU reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); @@ -932,4 +934,4 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); //disable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -}
\ No newline at end of file +} diff --git a/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/network/eth0-discover b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/network/eth0-discover new file mode 100644 index 0000000000..00f3120115 --- /dev/null +++ b/arch/arm/boards/zii-imx8mq-dev/defaultenv-imx8mq-zii-dev/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +# reset switch to clear DSA config +rave_reset_switch diff --git a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg index aff8321b9a..f82759f849 100644 --- a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg +++ b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg @@ -1,5 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 + +#include <mach/imx/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 795c98cb66..4184748cd8 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -5,21 +5,23 @@ */ #include <common.h> +#include <firmware.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx8-ccm-regs.h> -#include <mach/iomux-mx8.h> -#include <mach/imx8-ddrc.h> -#include <mach/xload.h> +#include <mach/imx/imx8m-ccm-regs.h> +#include <mach/imx/iomux-mx8mq.h> +#include <soc/imx8m/ddr.h> +#include <mach/imx/xload.h> #include <io.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> #include <asm/cache.h> #include <asm/sections.h> #include <asm/mmu.h> -#include <mach/atf.h> -#include <mach/esdctl.h> +#include <mach/imx/atf.h> +#include <mach/imx/esdctl.h> #include "ddr.h" @@ -27,19 +29,14 @@ static void setup_uart(void) { - void __iomem *iomux = IOMEM(MX8MQ_IOMUXC_BASE_ADDR); - void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR); + void __iomem *uart = IOMEM(MX8M_UART1_BASE_ADDR); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_CLR(CCM_CCGR_UART1)); - writel(CCM_TARGET_ROOTn_ENABLE | UART1_CLK_ROOT__25M_REF_CLK, - ccm + CCM_TARGET_ROOTn(UART1_CLK_ROOT)); - writel(CCM_CCGR_SETTINGn_NEEDED(0), - ccm + CCM_CCGRn_SET(CCM_CCGR_UART1)); + imx8m_early_setup_uart_clock(); - imx_setup_pad(iomux, IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL); + imx8m_uart_setup(uart); - imx8_uart_setup_ll(); + pbl_set_putc(imx_uart_putc, uart); putc_ll('>'); } @@ -66,21 +63,10 @@ static __noreturn void ddr_helper_halt(void) static void zii_imx8mq_dev_sram_setup(void) { - enum bootsource src = BOOTSOURCE_UNKNOWN; - int instance = BOOTSOURCE_INSTANCE_UNKNOWN; - int ret = -ENOTSUPP; - ddr_init(); if (running_as_ddr_helper()) ddr_helper_halt(); - - imx8_get_boot_source(&src, &instance); - - if (src == BOOTSOURCE_MMC) - ret = imx8_esdhc_start_image(instance); - - BUG_ON(ret); } enum zii_platform_imx8mq_type { @@ -125,6 +111,8 @@ static __noreturn noinline void zii_imx8mq_dev_start(void) unsigned int system_type; void *fdt; + setup_uart(); + if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { /* * We assume that we were just loaded by MaskROM into @@ -142,13 +130,8 @@ static __noreturn noinline void zii_imx8mq_dev_start(void) * initialization routine, it is EL2 which means we'll skip * loadting ATF blob again */ - if (current_el() == 3) { - const u8 *bl31; - size_t bl31_size; - - get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); - imx8mq_atf_load_bl31(bl31, bl31_size); - } + if (current_el() == 3) + imx8mq_load_and_start_image_via_tfa(); system_type = get_system_type(); @@ -191,7 +174,7 @@ static __noreturn noinline void zii_imx8mq_dev_start(void) * * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * 5. BL31 exits EL3 into EL2 at address MX8M_ATF_BL33_BASE_ADDR, * executing start_nxp_imx8mq_evk() the third time * * 6. Standard barebox boot flow continues @@ -201,9 +184,6 @@ ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2) imx8mq_cpu_lowlevel_init(); relocate_to_current_adr(); setup_c(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); zii_imx8mq_dev_start(); } diff --git a/arch/arm/boards/zii-vf610-dev/Makefile b/arch/arm/boards/zii-vf610-dev/Makefile index 3c3a3f2387..a1a8318e15 100644 --- a/arch/arm/boards/zii-vf610-dev/Makefile +++ b/arch/arm/boards/zii-vf610-dev/Makefile @@ -1,4 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o -CFLAGS_pbl-lowlevel.o := -fno-tree-switch-conversion -fno-jump-tables lwl-y += lowlevel.o bbenv-y += defaultenv-zii-vf610-dev diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index 1d10f12f63..675f13b882 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -1,17 +1,7 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <init.h> @@ -20,7 +10,7 @@ #include <linux/clk.h> #include <dt-bindings/clock/vf610-clock.h> #include <envfs.h> -#include <mach/bbu.h> +#include <mach/imx/bbu.h> static int expose_signals(const struct gpio *signals, @@ -141,6 +131,7 @@ static int zii_vf610_dev_set_hostname(void) } } + defaultenv_append_directory(defaultenv_zii_common); defaultenv_append_directory(defaultenv_zii_vf610_dev); return 0; } @@ -161,6 +152,14 @@ static int zii_vf610_dev_register_bbu(void) return ret; } + ret = vf610_bbu_internal_mmc_register_handler("SD", + "/dev/mmc1", + 0); + if (ret) { + pr_err("Failed to register SD BBU handler\n"); + return ret; + } + return 0; } late_initcall(zii_vf610_dev_register_bbu); @@ -185,4 +184,4 @@ static int zii_vf610_register_emmc_bbu(void) return 0; } -late_initcall(zii_vf610_register_emmc_bbu);
\ No newline at end of file +late_initcall(zii_vf610_register_emmc_bbu); diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg index 7076a6431f..aace9e9226 100644 --- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg +++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + soc vf610 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 -#include <mach/vf610-iomux-regs.h> -#include <mach/vf610-ddrmc-regs.h> +#include <mach/imx/vf610-iomux-regs.h> +#include <mach/imx/vf610-ddrmc-regs.h> -#include <mach/flash-header/vf610-ddr-pll2-400mhz.imxcfg> -#include <mach/flash-header/vf610-iomux-ddr-default.imxcfg> -#include <mach/flash-header/vf610-ddr-cr-default.imxcfg> +#include <mach/imx/flash-header/vf610-ddr-pll2-400mhz.imxcfg> +#include <mach/imx/flash-header/vf610-iomux-ddr-default.imxcfg> +#include <mach/imx/flash-header/vf610-ddr-cr-default.imxcfg> wm 32 DDRMC_CR26 0x0c300068 wm 32 DDRMC_CR31 0x006c0200 @@ -19,7 +21,7 @@ wm 32 DDRMC_CR73 0x0a010100 */ wm 32 DDRMC_CR73 0x0a010100 -#include <mach/flash-header/vf610-ddr-phy-default.imxcfg> +#include <mach/imx/flash-header/vf610-ddr-phy-default.imxcfg> wm 32 DDRMC_CR00 DDRMC_CR00_DRAM_CLASS_DDR3_START diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index 9b57581d1b..e45e31f7d8 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -1,28 +1,19 @@ -/* - * Copyright (C) 2016 Zodiac Inflight Innovation - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2016 Zodiac Inflight Innovation + +/* Author: Andrey Smirnov <andrew.smirnov@gmail.com> */ #include <common.h> #include <linux/sizes.h> -#include <mach/generic.h> +#include <mach/imx/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/esdctl.h> -#include <mach/vf610-regs.h> -#include <mach/clock-vf610.h> -#include <mach/iomux-vf610.h> +#include <mach/imx/esdctl.h> +#include <mach/imx/vf610-regs.h> +#include <mach/imx/clock-vf610.h> +#include <mach/imx/iomux-vf610.h> #include <debug_ll.h> +#include <mach/imx/debug_ll.h> static inline void setup_uart(void) { diff --git a/arch/arm/boards/zylonite/Makefile b/arch/arm/boards/zylonite/Makefile index 01c7a259e9..da63d2625f 100644 --- a/arch/arm/boards/zylonite/Makefile +++ b/arch/arm/boards/zylonite/Makefile @@ -1,2 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c index bd72cd1992..04cb34754c 100644 --- a/arch/arm/boards/zylonite/board.c +++ b/arch/arm/boards/zylonite/board.c @@ -1,20 +1,5 @@ -/* - * (C) 2014 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Robert Jarzmik <robert.jarzmik@free.fr> #include <common.h> @@ -23,7 +8,6 @@ #include <fs.h> #include <gpio.h> #include <init.h> -#include <partition.h> #include <led.h> #include <platform_data/eth-smc91111.h> #include <platform_data/mtd-nand-mrvl.h> @@ -32,16 +16,14 @@ #include <linux/clkdev.h> #include <linux/sizes.h> -#include <mach/devices.h> -#include <mach/mfp-pxa3xx.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/devices.h> +#include <mach/pxa/mfp-pxa3xx.h> +#include <mach/pxa/pxa-regs.h> #include <asm/armlinux.h> #include <asm/io.h> #include <asm/mmu.h> -#include <generated/mach-types.h> - -#include "zylonite.h" +#include <asm/mach-types.h> static struct smc91c111_pdata smsc91x_pdata; static struct mrvl_nand_platform_data nand_pdata = { diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c index 5b95d879fa..972fd34761 100644 --- a/arch/arm/boards/zylonite/lowlevel.c +++ b/arch/arm/boards/zylonite/lowlevel.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <linux/sizes.h> #include <asm/barebox-arm-head.h> diff --git a/arch/arm/boards/zylonite/zylonite.h b/arch/arm/boards/zylonite/zylonite.h deleted file mode 100644 index d39ab72d3d..0000000000 --- a/arch/arm/boards/zylonite/zylonite.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef _ZYLONITE_H_ -#define _ZYLONITE_H_ - - -#endif /* _ZYLONITE_H */ |