diff options
Diffstat (limited to 'arch/arm/boards')
38 files changed, 575 insertions, 342 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index d6fc17cc25..013229db71 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ obj-$(CONFIG_MACH_CANON_A1100) += canon-a1100/ +obj-$(CONFIG_MACH_CM_FX6) += cm-fx6/ obj-$(CONFIG_MACH_NITROGEN6X) += boundarydevices-nitrogen6x/ obj-$(CONFIG_MACH_CCMX51) += ccxmx51/ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c index 0fda01363c..2069ab3764 100644 --- a/arch/arm/boards/animeo_ip/init.c +++ b/arch/arm/boards/animeo_ip/init.c @@ -346,6 +346,7 @@ static void animeo_ip_shutdown(void) animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US0)); animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US1)); } +postdevshutdown_exitcall(animeo_ip_shutdown); static int animeo_ip_console_init(void) { @@ -353,7 +354,6 @@ static int animeo_ip_console_init(void) usart0 = at91_register_uart(1, ATMEL_UART_RTS); usart1 = at91_register_uart(2, ATMEL_UART_RTS); - board_shutdown = animeo_ip_shutdown; barebox_set_model("Somfy Animeo IP"); barebox_set_hostname("animeoip"); diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c index 5e569bcc9a..c866043e8b 100644 --- a/arch/arm/boards/chumby_falconwing/falconwing.c +++ b/arch/arm/boards/chumby_falconwing/falconwing.c @@ -83,7 +83,7 @@ static struct imx_fb_platformdata fb_mode = { .mode_list = &falconwing_vmode, .mode_cnt = 1, /* the NMA35 is a 24 bit display, but only 18 bits are connected */ - .ld_intf_width = STMLCDIF_18BIT, + .ld_intf_width = 18, .enable = chumby_fb_enable, .fixed_screen = (void *)(0x40000000 + SZ_64M - MAX_FB_SIZE), .fixed_screen_size = MAX_FB_SIZE, diff --git a/arch/arm/boards/cm-fx6/Makefile b/arch/arm/boards/cm-fx6/Makefile new file mode 100644 index 0000000000..3a773bbf7b --- /dev/null +++ b/arch/arm/boards/cm-fx6/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o +extra-y += flash-header-mx6-cm-fx6.dcd.S flash-header-mx6-cm-fx6.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/cm-fx6/board.c b/arch/arm/boards/cm-fx6/board.c new file mode 100644 index 0000000000..edef18f8ac --- /dev/null +++ b/arch/arm/boards/cm-fx6/board.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2015 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <environment.h> +#include <mach/imx6-regs.h> +#include <mach/bbu.h> +#include <asm/armlinux.h> +#include <linux/phy.h> +#include <mach/generic.h> +#include <linux/sizes.h> +#include <mach/imx6.h> +#include <net.h> + +static int phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* Ar8031 phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, 0xd, 0x3); + phy_write(phydev, 0xe, 0x805d); + phy_write(phydev, 0xd, 0x4003); + val = phy_read(phydev, 0xe); + val &= ~(0x1 << 8); + phy_write(phydev, 0xe, val); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, 0xd, 0x7); + phy_write(phydev, 0xe, 0x8016); + phy_write(phydev, 0xd, 0x4007); + + val = phy_read(phydev, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, 0x1d, 0x5); + val = phy_read(phydev, 0x1e); + val |= 0x0100; + phy_write(phydev, 0x1e, val); + + return 0; +} + +#define PHY_ID_AR8031 0x004dd074 + +static int cm_fx6_eeprom_init(void) +{ + struct cdev *cdev; + u8 mac[6]; + int ret; + + if (!of_machine_is_compatible("compulab,cm-fx6")) + return 0; + + cdev = cdev_by_name("eeprom0"); + if (!cdev) + return -ENODEV; + + ret = cdev_read(cdev, mac, 6, 4, 0); + if (ret < 0) + return ret; + + eth_register_ethaddr(0, mac); + + return 0; +} +late_initcall(cm_fx6_eeprom_init); + +static int cm_fx6_devices_init(void) +{ + if (!of_machine_is_compatible("compulab,cm-fx6")) + return 0; + + if (IS_ENABLED(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff, phy_fixup); + + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0", + BBU_HANDLER_FLAG_DEFAULT); + + return 0; +} +coredevice_initcall(cm_fx6_devices_init); diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg new file mode 100644 index 0000000000..400a870154 --- /dev/null +++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg @@ -0,0 +1,3 @@ +soc imx6 +loadaddr 0x00907000 +dcdofs 0x400 diff --git a/arch/arm/boards/cm-fx6/lowlevel.c b/arch/arm/boards/cm-fx6/lowlevel.c new file mode 100644 index 0000000000..fd86e159aa --- /dev/null +++ b/arch/arm/boards/cm-fx6/lowlevel.c @@ -0,0 +1,369 @@ +#define pr_fmt(fmt) "cm-fx6: " fmt + +#include <common.h> +#include <linux/sizes.h> +#include <mach/generic.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <debug_ll.h> +#include <io.h> +#include <mach/imx6-mmdc.h> +#include <mach/imx6-ddr-regs.h> +#include <mach/imx6.h> +#include <mach/xload.h> +#include <mach/esdctl.h> +#include <serial/imx-uart.h> + +enum ddr_config { + DDR_16BIT_256MB, + DDR_32BIT_512MB, + DDR_32BIT_1GB, + DDR_64BIT_1GB, + DDR_64BIT_2GB, + DDR_64BIT_4GB, + DDR_UNKNOWN, +}; + +static void __udelay(int us) +{ + volatile int i; + + for (i = 0; i < us * 4; i++); +} + +/* + * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to + * Freescale QRM, but this is exactly the value used by the automatic + * calibration script and it works also in all our tests, so we leave + * it as is at this point. + */ +#define CM_FX6_DDR_IOMUX_CFG \ + .dram_sdqs0 = 0x00000038, \ + .dram_sdqs1 = 0x00000038, \ + .dram_sdqs2 = 0x00000038, \ + .dram_sdqs3 = 0x00000038, \ + .dram_sdqs4 = 0x00000038, \ + .dram_sdqs5 = 0x00000038, \ + .dram_sdqs6 = 0x00000038, \ + .dram_sdqs7 = 0x00000038, \ + .dram_dqm0 = 0x00000038, \ + .dram_dqm1 = 0x00000038, \ + .dram_dqm2 = 0x00000038, \ + .dram_dqm3 = 0x00000038, \ + .dram_dqm4 = 0x00000038, \ + .dram_dqm5 = 0x00000038, \ + .dram_dqm6 = 0x00000038, \ + .dram_dqm7 = 0x00000038, \ + .dram_cas = 0x00000038, \ + .dram_ras = 0x00000038, \ + .dram_sdclk_0 = 0x00000038, \ + .dram_sdclk_1 = 0x00000038, \ + .dram_sdcke0 = 0x00003000, \ + .dram_sdcke1 = 0x00003000, \ + .dram_reset = 0x00000038, \ + .dram_sdba2 = 0x00000000, \ + .dram_sdodt0 = 0x00000038, \ + .dram_sdodt1 = 0x00000038, + +#define CM_FX6_GPR_IOMUX_CFG \ + .grp_b0ds = 0x00000038, \ + .grp_b1ds = 0x00000038, \ + .grp_b2ds = 0x00000038, \ + .grp_b3ds = 0x00000038, \ + .grp_b4ds = 0x00000038, \ + .grp_b5ds = 0x00000038, \ + .grp_b6ds = 0x00000038, \ + .grp_b7ds = 0x00000038, \ + .grp_addds = 0x00000038, \ + .grp_ddrmode_ctl = 0x00020000, \ + .grp_ddrpke = 0x00000000, \ + .grp_ddrmode = 0x00020000, \ + .grp_ctlds = 0x00000038, \ + .grp_ddr_type = 0x000C0000, + +static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG }; +static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG }; +static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG }; +static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG }; + +static struct mx6_mmdc_calibration cm_fx6_calib_s = { + .p0_mpwldectrl0 = 0x005B0061, + .p0_mpwldectrl1 = 0x004F0055, + .p0_mpdgctrl0 = 0x0314030C, + .p0_mpdgctrl1 = 0x025C0268, + .p0_mprddlctl = 0x42464646, + .p0_mpwrdlctl = 0x36322C34, +}; + +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = { + .cs1_mirror = 1, + .cs_density = 16, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = { + .mem_speed = 800, + .density = 4, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1800, + .trcmin = 5200, + .trasmin = 3600, + .SRT = 0, +}; + +static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset) +{ + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + switch (dram_config) { + case DDR_16BIT_256MB: + cm_fx6_sysinfo_s.dsize = 0; + cm_fx6_sysinfo_s.ncs = 1; + break; + case DDR_32BIT_512MB: + cm_fx6_sysinfo_s.dsize = 1; + cm_fx6_sysinfo_s.ncs = 1; + break; + case DDR_32BIT_1GB: + cm_fx6_sysinfo_s.dsize = 1; + cm_fx6_sysinfo_s.ncs = 2; + break; + default: + pr_err("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s); + __udelay(100); +} + +static struct mx6_mmdc_calibration cm_fx6_calib_q = { + .p0_mpwldectrl0 = 0x00630068, + .p0_mpwldectrl1 = 0x0068005D, + .p0_mpdgctrl0 = 0x04140428, + .p0_mpdgctrl1 = 0x037C037C, + .p0_mprddlctl = 0x3C30303A, + .p0_mpwrdlctl = 0x3A344038, + .p1_mpwldectrl0 = 0x0035004C, + .p1_mpwldectrl1 = 0x00170026, + .p1_mpdgctrl0 = 0x0374037C, + .p1_mpdgctrl1 = 0x0350032C, + .p1_mprddlctl = 0x30322A3C, + .p1_mpwrdlctl = 0x48304A3E, +}; + +static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = { + .cs_density = 16, + .cs1_mirror = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 0, + .ralat = 5, + .walat = 1, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = { + .mem_speed = 1066, + .density = 4, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1324, + .trcmin = 59500, + .trasmin = 9750, + .SRT = 0, +}; + +static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset) +{ + if (reset) + ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2; + + cm_fx6_ddr3_cfg_q.rowaddr = 14; + switch (dram_config) { + case DDR_16BIT_256MB: + cm_fx6_sysinfo_q.dsize = 0; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_32BIT_512MB: + cm_fx6_sysinfo_q.dsize = 1; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_64BIT_1GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 1; + break; + case DDR_64BIT_2GB: + cm_fx6_sysinfo_q.cs_density = 8; + cm_fx6_ddr3_cfg_q.density = 2; + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 2; + break; + case DDR_64BIT_4GB: + cm_fx6_sysinfo_q.dsize = 2; + cm_fx6_sysinfo_q.ncs = 2; + cm_fx6_ddr3_cfg_q.rowaddr = 15; + break; + default: + pr_err("Tried to setup invalid DDR configuration\n"); + hang(); + } + + mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q); + __udelay(100); +} + +static unsigned long cm_fx6_spl_dram_init(void) +{ + unsigned long bank1_size, bank2_size; + int cpu_type = __imx6_cpu_type(); + + if (cpu_type == IMX6_CPUTYPE_IMX6S) { + mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s); + + spl_mx6s_dram_init(DDR_32BIT_1GB, false); + bank1_size = get_ram_size((long int *)0x10000000, 0x80000000); + bank2_size = get_ram_size((long int *)0x80000000, 0x80000000); + if (bank1_size == 0x20000000) { + if (bank2_size == 0x20000000) + return SZ_1G; + + spl_mx6s_dram_init(DDR_32BIT_512MB, true); + return SZ_512M; + } + + spl_mx6s_dram_init(DDR_16BIT_256MB, true); + bank1_size = get_ram_size((long int *)0x10000000, 0x80000000); + if (bank1_size == 0x10000000) + return SZ_256M; + } else if (cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) { + mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q); + + spl_mx6q_dram_init(DDR_64BIT_4GB, false); + bank1_size = get_ram_size((long int *)0x10000000, 0x80000000); + if (bank1_size == 0x80000000) + return SZ_2G; + + if (bank1_size == 0x40000000) { + bank2_size = get_ram_size((long int *)0x90000000, + 0x40000000); + if (bank2_size == 0x40000000) { + /* Don't do a full reset here */ + spl_mx6q_dram_init(DDR_64BIT_2GB, false); + return SZ_2G; + } else { + spl_mx6q_dram_init(DDR_64BIT_1GB, true); + return SZ_1G; + } + } + + spl_mx6q_dram_init(DDR_32BIT_512MB, true); + bank1_size = get_ram_size((long int *)0x10000000, 0x80000000); + if (bank1_size == 0x20000000) + return SZ_512M; + + spl_mx6q_dram_init(DDR_16BIT_256MB, true); + bank1_size = get_ram_size((long int *)0x10000000, 0x80000000); + if (bank1_size == 0x10000000) + return SZ_256M; + } + + return 0; +} + +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + writel(0x4, iomuxbase + 0x01f8); + + imx6_ungate_all_peripherals(); + imx6_uart_setup((void *)MX6_UART4_BASE_ADDR); + pbl_set_putc(imx_uart_putc, (void *)MX6_UART4_BASE_ADDR); + + pr_debug("\n"); +} + +static void cm_fx6_init(void) +{ + unsigned long sdram_size; + + setup_uart(); + + if (get_pc() > 0x10000000) + return; + + sdram_size = cm_fx6_spl_dram_init(); + + pr_debug("SDRAM init finished. SDRAM size 0x%08lx\n", sdram_size); + + imx6_esdhc_start_image(2); + pr_info("Loading image from SPI flash\n"); + imx6_spi_start_image(0); +} + +extern char __dtb_imx6q_cm_fx6_start[]; +extern char __dtb_imx6dl_cm_fx6_start[]; + +static noinline void cm_fx6_start(void) +{ + int cpu_type = __imx6_cpu_type(); + + cm_fx6_init(); + + if (cpu_type == IMX6_CPUTYPE_IMX6S) + imx6q_barebox_entry(__dtb_imx6dl_cm_fx6_start); + else + imx6q_barebox_entry(__dtb_imx6q_cm_fx6_start); +} + +ENTRY_FUNCTION(start_imx6_cm_fx6, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + cm_fx6_start(); +} + +extern char __dtb_imx6q_utilite_start[]; +extern char __dtb_imx6dl_utilite_value_start[]; + +static noinline void utilite_start(void) +{ + int cpu_type = __imx6_cpu_type(); + + cm_fx6_init(); + + if (cpu_type == IMX6_CPUTYPE_IMX6S) + /* FIXME: This needs a specialized utilite value dts */ + imx6q_barebox_entry(__dtb_imx6dl_cm_fx6_start); + else + imx6q_barebox_entry(__dtb_imx6q_utilite_start); +} + +ENTRY_FUNCTION(start_imx6_utilite, r0, r1, r2) +{ + arm_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + utilite_start(); +} diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index 81356e61c0..96c7fbe4bf 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -38,7 +38,6 @@ #include <mach/devices-imx6.h> #include <mach/imx6-regs.h> #include <mach/iomux-mx6.h> -#include <mach/imx6-mmdc.h> #include <mach/generic.h> #include <mach/imx6.h> #include <mach/bbu.h> diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c index b9b498e463..a22f66a11b 100644 --- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c +++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c @@ -19,7 +19,6 @@ #include <asm/mmu.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -#include <mach/imx6-mmdc.h> #include <mach/imx6-regs.h> #include <mach/generic.h> diff --git a/arch/arm/boards/embest-riotboard/lowlevel.c b/arch/arm/boards/embest-riotboard/lowlevel.c index 59010da511..d26bc98bbb 100644 --- a/arch/arm/boards/embest-riotboard/lowlevel.c +++ b/arch/arm/boards/embest-riotboard/lowlevel.c @@ -7,7 +7,6 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6-mmdc.h> #include <mach/imx6.h> extern char __dtb_imx6s_riotboard_start[]; diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c index d77a6c7156..fc1237588f 100644 --- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c @@ -226,7 +226,7 @@ static struct imx_fb_platformdata mx28_evk_fb_pdata = { .mode_list = mx28_evk_vmodes, .mode_cnt = ARRAY_SIZE(mx28_evk_vmodes), .dotclk_delay = 0, /* no adaption required */ - .ld_intf_width = STMLCDIF_24BIT, /* full 24 bit */ + .ld_intf_width = 24, .bits_per_pixel = 32, .fixed_screen = NULL, .enable = mx28_evk_fb_enable, diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index edf081140c..d40f99bb93 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -164,8 +164,8 @@ static int sabrelite_devices_init(void) armlinux_set_architecture(3769); - imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", - BBU_HANDLER_FLAG_DEFAULT); + imx6_bbu_internal_spi_i2c_register_handler("spiflash", + "/dev/spinor0.barebox", BBU_HANDLER_FLAG_DEFAULT); return 0; } diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index 67fd50849d..f40f0d1591 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -110,7 +110,7 @@ static struct imx_fb_platform_data neso_fb_data = { .framebuffer_ovl = (void *)0xa7f00000, }; -#ifdef CONFIG_USB +#if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI) static void neso_usbh_init(void) { uint32_t temp; @@ -130,7 +130,11 @@ static void neso_usbh_init(void) gpio_set_value(USBH2_PHY_CS_GPIO, 0); mdelay(10); ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, + MX27_USB_OTG_BASE_ADDR + 0x400, NULL); } +#else +static void neso_usbh_init(void) { } #endif static int neso_devices_init(void) @@ -266,10 +270,7 @@ static int neso_devices_init(void) imx27_add_nand(&nand_info); imx27_add_fb(&neso_fb_data); -#ifdef CONFIG_USB neso_usbh_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); -#endif imx27_add_fec(&fec_info); diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c index ded7a3797e..d27d9e4ddf 100644 --- a/arch/arm/boards/guf-vincell/board.c +++ b/arch/arm/boards/guf-vincell/board.c @@ -16,235 +16,18 @@ #include <common.h> #include <environment.h> -#include <fcntl.h> -#include <fec.h> -#include <fs.h> #include <init.h> -#include <nand.h> -#include <net.h> -#include <partition.h> #include <linux/sizes.h> #include <bbu.h> #include <gpio.h> #include <io.h> -#include <i2c/i2c.h> #include <linux/clk.h> -#include <usb/fsl_usb2.h> -#include <generated/mach-types.h> - -#include <mach/imx53-regs.h> -#include <mach/iomux-mx53.h> #include <mach/devices-imx53.h> #include <mach/generic.h> -#include <mach/imx-nand.h> #include <mach/iim.h> -#include <mach/imx-nand.h> #include <mach/bbu.h> -#include <mach/imx-flash-header.h> #include <mach/imx5.h> -#include <mach/usb.h> - -#include <asm/armlinux.h> -#include <asm/mmu.h> - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, -}; - -static iomux_v3_cfg_t vincell_pads[] = { - MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD, - MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC, - MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD, - MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS, - MX53_PAD_GPIO_8__CAN1_RXCAN, - MX53_PAD_GPIO_7__CAN1_TXCAN, - MX53_PAD_KEY_ROW4__CAN2_RXCAN, - MX53_PAD_KEY_COL4__CAN2_TXCAN, - MX53_PAD_GPIO_3__CCM_CLKO2, - MX53_PAD_KEY_COL1__ECSPI1_MISO, - MX53_PAD_KEY_ROW0__ECSPI1_MOSI, - MX53_PAD_GPIO_19__ECSPI1_RDY, - MX53_PAD_KEY_COL0__ECSPI1_SCLK, - MX53_PAD_KEY_ROW1__GPIO4_9, /* ECSPI1_SS0 */ - MX53_PAD_KEY_COL2__GPIO4_10, /* ECSPI1_SS1 */ - MX53_PAD_KEY_ROW2__GPIO4_11, /* ECSPI1_SS2 */ - MX53_PAD_KEY_COL3__GPIO4_12, /* ECSPI1_SS3 */ - MX53_PAD_CSI0_DAT10__ECSPI2_MISO, - MX53_PAD_EIM_CS1__ECSPI2_MOSI, - MX53_PAD_EIM_A25__ECSPI2_RDY, - MX53_PAD_DISP0_DAT19__ECSPI2_SCLK, - MX53_PAD_DISP0_DAT18__GPIO5_12, /* ECSPI2_SS0 */ - MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, - MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, - MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, - MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, - MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, - MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, - MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, - MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7, - MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8, - MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9, - MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10, - MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11, - MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12, - MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13, - MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14, - MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15, - MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, - MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, - MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, - MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1, - MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2, - MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3, - MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, - MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, - MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, - MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, - MX53_PAD_EIM_A16__EMI_WEIM_A_16, - MX53_PAD_EIM_A17__EMI_WEIM_A_17, - MX53_PAD_EIM_A18__EMI_WEIM_A_18, - MX53_PAD_EIM_A19__EMI_WEIM_A_19, - MX53_PAD_EIM_A20__EMI_WEIM_A_20, - MX53_PAD_EIM_CS0__EMI_WEIM_CS_0, - MX53_PAD_EIM_D16__EMI_WEIM_D_16, - MX53_PAD_EIM_D17__EMI_WEIM_D_17, - MX53_PAD_EIM_D18__EMI_WEIM_D_18, - MX53_PAD_EIM_D19__EMI_WEIM_D_19, - MX53_PAD_EIM_D20__EMI_WEIM_D_20, - MX53_PAD_EIM_D21__EMI_WEIM_D_21, - MX53_PAD_EIM_D22__EMI_WEIM_D_22, - MX53_PAD_EIM_D23__EMI_WEIM_D_23, - MX53_PAD_EIM_D24__EMI_WEIM_D_24, - MX53_PAD_EIM_D25__EMI_WEIM_D_25, - MX53_PAD_EIM_D26__EMI_WEIM_D_26, - MX53_PAD_EIM_D27__EMI_WEIM_D_27, - MX53_PAD_EIM_D28__EMI_WEIM_D_28, - MX53_PAD_EIM_D29__EMI_WEIM_D_29, - MX53_PAD_EIM_D30__EMI_WEIM_D_30, - MX53_PAD_EIM_D31__EMI_WEIM_D_31, - MX53_PAD_EIM_EB0__EMI_WEIM_EB_0, - MX53_PAD_EIM_EB1__EMI_WEIM_EB_1, - MX53_PAD_EIM_OE__EMI_WEIM_OE, - MX53_PAD_EIM_RW__EMI_WEIM_RW, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - MX53_PAD_DI0_PIN4__ESDHC1_WP, - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_SD2_CLK__GPIO1_10, - MX53_PAD_SD2_DATA3__GPIO1_12, - MX53_PAD_GPIO_2__GPIO1_2, - MX53_PAD_GPIO_4__GPIO1_4, - MX53_PAD_PATA_DATA0__GPIO2_0, - MX53_PAD_PATA_DATA1__GPIO2_1, - MX53_PAD_PATA_DATA10__GPIO2_10, - MX53_PAD_PATA_DATA11__GPIO2_11, - MX53_PAD_PATA_DATA13__GPIO2_13, - MX53_PAD_PATA_DATA14__GPIO2_14, - MX53_PAD_PATA_DATA15__GPIO2_15, - MX53_PAD_PATA_DATA2__GPIO2_2, - MX53_PAD_PATA_DATA3__GPIO2_3, - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_PATA_DATA4__PATA_DATA_4, - MX53_PAD_PATA_DATA5__GPIO2_5, - MX53_PAD_PATA_DATA6__GPIO2_6, - MX53_PAD_PATA_DATA7__GPIO2_7, - MX53_PAD_PATA_DATA8__GPIO2_8, - MX53_PAD_PATA_DATA9__GPIO2_9, - MX53_PAD_GPIO_10__GPIO4_0, - MX53_PAD_GPIO_11__GPIO4_1, - MX53_PAD_GPIO_12__GPIO4_2, - MX53_PAD_DISP0_DAT8__GPIO4_29, - MX53_PAD_GPIO_13__GPIO4_3, - MX53_PAD_DISP0_DAT16__GPIO5_10, - MX53_PAD_DISP0_DAT17__GPIO5_11, - MX53_PAD_CSI0_PIXCLK__GPIO5_18, - MX53_PAD_CSI0_MCLK__GPIO5_19, - MX53_PAD_CSI0_DATA_EN__GPIO5_20, - MX53_PAD_CSI0_VSYNC__GPIO5_21, - MX53_PAD_CSI0_DAT4__GPIO5_22, - MX53_PAD_CSI0_DAT5__GPIO5_23, - MX53_PAD_CSI0_DAT6__GPIO5_24, - MX53_PAD_DISP0_DAT14__GPIO5_8, - MX53_PAD_DISP0_DAT15__GPIO5_9, - MX53_PAD_PATA_DIOW__GPIO6_17, - MX53_PAD_PATA_DMACK__GPIO6_18, - MX53_PAD_GPIO_17__GPIO7_12, - MX53_PAD_GPIO_18__GPIO7_13, - MX53_PAD_PATA_RESET_B__GPIO7_4, - MX53_PAD_PATA_IORDY__GPIO7_5, - MX53_PAD_PATA_DA_0__GPIO7_6, - MX53_PAD_PATA_DA_2__GPIO7_8, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - MX53_PAD_GPIO_5__I2C3_SCL, - MX53_PAD_GPIO_6__I2C3_SDA, - MX53_PAD_KEY_COL0__KPP_COL_0, - MX53_PAD_KEY_COL1__KPP_COL_1, - MX53_PAD_KEY_COL2__KPP_COL_2, - MX53_PAD_KEY_COL3__KPP_COL_3, - MX53_PAD_GPIO_19__KPP_COL_5, - MX53_PAD_GPIO_9__KPP_COL_6, - MX53_PAD_SD2_DATA1__KPP_COL_7, - MX53_PAD_KEY_ROW0__KPP_ROW_0, - MX53_PAD_KEY_ROW1__KPP_ROW_1, - MX53_PAD_KEY_ROW2__KPP_ROW_2, - MX53_PAD_KEY_ROW3__KPP_ROW_3, - MX53_PAD_SD2_CMD__KPP_ROW_5, - MX53_PAD_SD2_DATA2__KPP_ROW_6, - MX53_PAD_SD2_DATA0__KPP_ROW_7, - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX53_PAD_DISP0_DAT8__PWM1_PWMO, - MX53_PAD_DISP0_DAT9__PWM2_PWMO, - MX53_PAD_PATA_INTRQ__UART2_CTS, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_CSI0_DAT17__UART4_CTS, - MX53_PAD_CSI0_DAT16__UART4_RTS, - MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, - MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, - MX53_PAD_CSI0_DAT19__UART5_CTS, - MX53_PAD_CSI0_DAT18__UART5_RTS, - MX53_PAD_CSI0_DAT15__UART5_RXD_MUX, - MX53_PAD_CSI0_DAT14__UART5_TXD_MUX, - MX53_PAD_GPIO_0__USBOH3_USBH1_PWR, - MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK, - MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0, - MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1, - MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2, - MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3, - MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4, - MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5, - MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6, - MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7, - MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR, - MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT, - MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP, - MX53_PAD_GPIO_1__WDOG2_WDOG_B, -}; #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) @@ -255,77 +38,19 @@ static void vincell_fec_reset(void) gpio_set_value(LOCO_FEC_PHY_RST, 1); } -static struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("da9053", 0x48), - }, -}; - -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - static int vincell_devices_init(void) { writel(0, MX53_M4IF_BASE_ADDR + 0xc); - console_flush(); - imx53_init_lowlevel(1000); - clk_set_rate(clk_lookup("nfc_podf"), 66666667); - - imx53_add_nand(&nand_info); - imx51_iim_register_fec_ethaddr(); - imx53_add_fec(&fec_info); - imx53_add_mmc0(NULL); - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - imx53_add_i2c0(NULL); - - add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX53_OTG_BASE_ADDR, 0x200, - IORESOURCE_MEM, &usb_pdata); + clk_set_rate(clk_lookup("emi_slow_podf"), 133333334); + clk_set_rate(clk_lookup("nfc_podf"), 33333334); vincell_fec_reset(); - armlinux_set_architecture(3297); - - devfs_add_partition("nand0", SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_1M + SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - imx53_bbu_internal_nand_register_handler("nand", - BBU_HANDLER_FLAG_DEFAULT, 3 * SZ_128K); - - return 0; -} - -device_initcall(vincell_devices_init); - -static int vincell_part_init(void) -{ - devfs_add_partition("disk0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", 0x80000, 0x80000, DEVFS_PARTITION_FIXED, "env0"); - - return 0; -} -late_initcall(vincell_part_init); - -static int vincell_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(vincell_pads, ARRAY_SIZE(vincell_pads)); - - barebox_set_model("Garz & Fricke VINCELL"); - barebox_set_hostname("vincell"); - - imx53_add_uart1(); + BBU_HANDLER_FLAG_DEFAULT, SZ_512K); return 0; } -console_initcall(vincell_console_init); +coredevice_initcall(vincell_devices_init); diff --git a/arch/arm/boards/guf-vincell/env/boot/nand-ubi b/arch/arm/boards/guf-vincell/env/boot/nand-ubi deleted file mode 100644 index 510ac119b4..0000000000 --- a/arch/arm/boards/guf-vincell/env/boot/nand-ubi +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -bootargs-root-ubi -r root -m nand0.root diff --git a/arch/arm/boards/guf-vincell/env/init/mtdparts-nand b/arch/arm/boards/guf-vincell/env/init/mtdparts-nand deleted file mode 100644 index 4fffefca8b..0000000000 --- a/arch/arm/boards/guf-vincell/env/init/mtdparts-nand +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - -mtdparts="512k(nand0.barebox)ro,512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/guf-vincell/env/nv/hostname b/arch/arm/boards/guf-vincell/env/nv/hostname deleted file mode 100644 index 922106e9f4..0000000000 --- a/arch/arm/boards/guf-vincell/env/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -vincell diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c index 629529d90a..a72eaf8b81 100644 --- a/arch/arm/boards/guf-vincell/lowlevel.c +++ b/arch/arm/boards/guf-vincell/lowlevel.c @@ -1,7 +1,9 @@ #include <common.h> +#include <debug_ll.h> #include <io.h> #include <init.h> #include <mach/imx53-regs.h> +#include <mach/clock-imx51_53.h> #include <mach/imx5.h> #include <mach/iomux-v3.h> #include <mach/esdctl-v4.h> @@ -9,7 +11,6 @@ #include <mach/generic.h> #include <asm/barebox-arm.h> #include <asm/barebox-arm-head.h> -#include <io.h> #define IOMUX_PADCTL_DDRI_DDR (1 << 9) @@ -122,31 +123,56 @@ void disable_watchdog(void) writew(0x0, MX53_WDOG2_BASE_ADDR + 8); } -void sdram_init(void); - -void __bare_init __naked barebox_arm_reset_vector(void) +static noinline void imx53_guf_vincell_init(void *fdt) { + void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR; u32 r; imx5_cpu_lowlevel_init(); arm_setup_stack(0xf8020000 - 8); + writel(0x0088494c, ccm + MX5_CCM_CBCDR); + writel(0x02b12f0a, ccm + MX5_CCM_CSCMR2); + imx53_ungate_all_peripherals(); + + imx53_init_lowlevel_early(800); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c); + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278); + imx53_uart_setup_ll(); + putc_ll('>'); + } + /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); - if (r > 0x70000000 && r < 0xf0000000) - imx53_barebox_entry(NULL); + if (!(r > 0x70000000 && r < 0xf0000000)) { + disable_watchdog(); + configure_dram_iomux(); + imx_esdctlv4_init(); + } + + imx53_barebox_entry(fdt); +} + +extern char __dtb_imx53_guf_vincell_lt_start[]; + +ENTRY_FUNCTION(start_imx53_guf_vincell_lt, r0, r1, r2) +{ + void *fdt; - /* Setup a preliminary stack */ - r = 0xf8000000 + 0x60000 - 16; - __asm__ __volatile__("mov sp, %0" : : "r"(r)); + fdt = __dtb_imx53_guf_vincell_lt_start - get_runtime_offset(); - disable_watchdog(); + imx53_guf_vincell_init(fdt); +} - configure_dram_iomux(); +extern char __dtb_imx53_guf_vincell_start[]; - imx5_init_lowlevel(); +ENTRY_FUNCTION(start_imx53_guf_vincell, r0, r1, r2) +{ + void *fdt; - imx_esdctlv4_init(); + fdt = __dtb_imx53_guf_vincell_start - get_runtime_offset(); - imx53_barebox_entry(NULL); + imx53_guf_vincell_init(fdt); } diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index 9b86d1c883..d67607b717 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -195,7 +195,7 @@ static struct imx_fb_platformdata tx28_fb_pdata = { .mode_list = tx28evk_vmodes, .mode_cnt = ARRAY_SIZE(tx28evk_vmodes), .dotclk_delay = 0, /* no adaption required */ - .ld_intf_width = STMLCDIF_24BIT, /* full 24 bit */ + .ld_intf_width = 24, .fixed_screen = (void *)(0x40000000 + SZ_128M - MAX_FB_SIZE), .fixed_screen_size = MAX_FB_SIZE, .enable = tx28_fb_enable, diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg index 481e085477..62a24ed0df 100644 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg @@ -1,5 +1,7 @@ -#define SETUP_1GIB_2GIB \ +#define SETUP_MDCFG0 \ wm 32 0x021b000c 0x54597955; \ + +#define SETUP_MDOR_MDASP_MDCTL \ wm 32 0x021b0030 0x00591023; \ wm 32 0x021b0040 0x00000027; \ wm 32 0x021b0000 0x831a0000 diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg index b21bd894b0..bab726d147 100644 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg +++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg @@ -1,5 +1,7 @@ -#define SETUP_1GIB_2GIB \ +#define SETUP_MDCFG0 \ wm 32 0x021b000c 0x3a3f7975; \ + +#define SETUP_MDOR_MDASP_MDCTL \ wm 32 0x021b0030 0x003f1023; \ wm 32 0x021b0040 0x00000017; \ wm 32 0x021b0000 0xc21a0000 diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg index 858b6d754b..512f6cbd47 100644 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg +++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg @@ -1,6 +1,7 @@ - -#define SETUP_1GIB_2GIB \ +#define SETUP_MDCFG0 \ wm 32 0x021b000c 0x54597955; \ + +#define SETUP_MDOR_MDASP_MDCTL \ wm 32 0x021b0030 0x00591023; \ wm 32 0x021b0040 0x00000027; \ wm 32 0x021b0000 0xc31a0000 diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h index aecaf160bb..a03b8dc0fa 100644 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h +++ b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h @@ -58,7 +58,8 @@ wm 32 0x021b002c 0x000026d2 wm 32 0x021b0008 0x09444040 wm 32 0x021b0004 0x00025576 -SETUP_1GIB_2GIB +SETUP_MDCFG0 +SETUP_MDOR_MDASP_MDCTL wm 32 0x021b001c 0x04088032 wm 32 0x021b001c 0x0408803a diff --git a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c index d85a1ab0a1..09ab6452ba 100644 --- a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c @@ -21,7 +21,6 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6-mmdc.h> #include <mach/imx6.h> static inline void setup_uart(void) diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg index e414b6e612..75dc982432 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg @@ -1,7 +1,7 @@ #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x565c9b85 -#define SETUP_1GIB_2GIB_4GIB \ +#define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000027; \ wm 32 0x021b0000 0x831a0000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg index f6061f25b4..1f1fbe542c 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg @@ -1,7 +1,7 @@ #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x3c409b85 -#define SETUP_1GIB_2GIB_4GIB \ +#define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ wm 32 0x021b0000 0xc21a0000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg index 2bfa836c4f..aa01c056be 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg @@ -1,7 +1,7 @@ #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x565c9b85 -#define SETUP_1GIB_2GIB_4GIB \ +#define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000027; \ wm 32 0x021b0000 0xC31A0000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg index 491f89357c..c8d33cfacc 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg @@ -1,7 +1,7 @@ #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x8c929b85 -#define SETUP_1GIB_2GIB_4GIB \ +#define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000047; \ wm 32 0x021b0000 0xC41A0000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h index 98b3c1869b..93291e9836 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h @@ -78,7 +78,7 @@ wm 32 0x021b001c 0x00008000 wm 32 0x021b002c 0x000026d2 wm 32 0x021b0030 0x003F1023 -SETUP_1GIB_2GIB_4GIB +SETUP_MDASP_MDCTL wm 32 0x021b001c 0x04088032 wm 32 0x021b001c 0x0408803a diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg index dfd4336f06..e76867004a 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -1,7 +1,7 @@ #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x8c929b85 -#define SETUP_S_DL_512MB_1GB \ +#define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ wm 32 0x021b0000 0xc21a0000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h index 8fbd66141a..337488bdf0 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h @@ -78,7 +78,7 @@ wm 32 0x021b001c 0x00008000 wm 32 0x021b002c 0x000026d2 wm 32 0x021b0030 0x003F1023 -SETUP_S_DL_512MB_1GB +SETUP_MDASP_MDCTL wm 32 0x021b001c 0x04088032 wm 32 0x021b001c 0x0408803a diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg index 2e428f9fd0..6a46cd958f 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg @@ -1,7 +1,7 @@ #define SETUP_MDCFG0 \ wm 32 0x021b000c 0x565c9b85 -#define SETUP_S_DL_512MB_1GB \ +#define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ wm 32 0x021b0000 0x83190000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c index cd37f88e05..82c0244631 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c @@ -22,7 +22,6 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6-mmdc.h> #include <mach/imx6.h> static inline void setup_uart(void) diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index 948bfa5147..64c1c53f67 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -124,13 +124,19 @@ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_128mb, am335x_phytec_phycore_s PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J128M16125IT_256MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_1024mb, am335x_phytec_phycore_som_mlo, PHYCORE_IM8G16D3FBBG15EI_1024MB); PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som); PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi); +PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_eeprom_sdram, am335x_phytec_phycore_som_no_eeprom); +PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_no_eeprom_sdram, am335x_phytec_phycore_som_no_spi_no_eeprom); /* phyflex-som */ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_256mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K128M16JT_256MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_512mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K256M16HA_512MB); PHYTEC_ENTRY(start_am33xx_phytec_phyflex_sdram, am335x_phytec_phyflex_som); +PHYTEC_ENTRY(start_am33xx_phytec_phyflex_no_spi_sdram, am335x_phytec_phyflex_som_no_spi); +PHYTEC_ENTRY(start_am33xx_phytec_phyflex_no_eeprom_sdram, am335x_phytec_phyflex_som_no_eeprom); +PHYTEC_ENTRY(start_am33xx_phytec_phyflex_no_spi_no_eeprom_sdram, am335x_phytec_phyflex_som_no_spi_no_eeprom); /* phycard-som */ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycard_sram_256mb, am335x_phytec_phycard_som_mlo, PHYCARD_NT5CB128M16BP_256MB); diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h index 3dcee207ee..698b0732b0 100644 --- a/arch/arm/boards/phytec-som-am335x/ram-timings.h +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -29,6 +29,7 @@ enum { PHYCORE_MT41J64M1615IT_128MB, PHYCORE_MT41J256M16HA15EIT_512MB, PHYCORE_MT41J512M8125IT_2x512MB, + PHYCORE_IM8G16D3FBBG15EI_1024MB, PHYCARD_NT5CB128M16BP_256MB, }; @@ -133,7 +134,7 @@ struct am335x_sdram_timings physom_timings[] = { }, }, - /* 1024MB */ + /* 2x512MB */ [PHYCORE_MT41J512M8125IT_2x512MB] = { .regs = { .emif_read_latency = 0x7, @@ -152,6 +153,25 @@ struct am335x_sdram_timings physom_timings[] = { }, }, + /* 1024MB */ + [PHYCORE_IM8G16D3FBBG15EI_1024MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAE4DB, + .emif_tim2 = 0x268F7FDA, + .emif_tim3 = 0x501F88BF, + .sdram_config = 0x61C053B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30 + }, + .data = { + .rd_slave_ratio0 = 0x33, + .wr_dqs_slave_ratio0 = 0x4a, + .fifo_we_slave_ratio0 = 0xa4, + .wr_slave_ratio0 = 0x85, + }, + }, + /* 256MB */ [PHYCARD_NT5CB128M16BP_256MB] = { .regs = { diff --git a/arch/arm/boards/tqma6x/board.c b/arch/arm/boards/tqma6x/board.c index 97cce60c70..9c52c8ae7a 100644 --- a/arch/arm/boards/tqma6x/board.c +++ b/arch/arm/boards/tqma6x/board.c @@ -38,7 +38,6 @@ #include <mach/devices-imx6.h> #include <mach/imx6-regs.h> #include <mach/iomux-mx6.h> -#include <mach/imx6-mmdc.h> #include <mach/generic.h> #include <mach/imx6.h> #include <mach/bbu.h> diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c index aec84b176b..52afee4b75 100644 --- a/arch/arm/boards/tqma6x/lowlevel.c +++ b/arch/arm/boards/tqma6x/lowlevel.c @@ -21,7 +21,6 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6-mmdc.h> #include <mach/imx6.h> extern char __dtb_imx6q_mba6x_start[]; diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c index b0b930d438..5cb738acb2 100644 --- a/arch/arm/boards/variscite-mx6/lowlevel.c +++ b/arch/arm/boards/variscite-mx6/lowlevel.c @@ -23,7 +23,6 @@ #include <asm/sections.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <mach/imx6-mmdc.h> #include <mach/imx6.h> static inline void setup_uart(void) |