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-rw-r--r--arch/arm/boards/avnet-zedboard/flash_header.c4
-rw-r--r--arch/arm/boards/beaglebone/lowlevel.c2
-rw-r--r--arch/arm/boards/friendlyarm-tiny210/lowlevel.c2
-rw-r--r--arch/arm/boards/phytec-som-am335x/ram-timings.h11
-rw-r--r--arch/arm/boards/phytec-som-rk3288/lowlevel.c11
5 files changed, 21 insertions, 9 deletions
diff --git a/arch/arm/boards/avnet-zedboard/flash_header.c b/arch/arm/boards/avnet-zedboard/flash_header.c
index ea20524..d9eb35b 100644
--- a/arch/arm/boards/avnet-zedboard/flash_header.c
+++ b/arch/arm/boards/avnet-zedboard/flash_header.c
@@ -52,10 +52,10 @@ struct zynq_flash_header __flash_header_section flash_header = {
.enc_stat = 0x0,
.user = 0x0,
.flash_offset = 0x8c0,
- .length = barebox_image_size,
+ .length = (unsigned int)&_barebox_image_size,
.res0 = 0x0,
.start_of_exec = 0x0,
- .total_len = barebox_image_size,
+ .total_len = (unsigned int)&_barebox_image_size,
.res1 = 0x1,
.checksum = 0x0,
.res2 = 0x0,
diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c
index 100f64f..a56b4b6 100644
--- a/arch/arm/boards/beaglebone/lowlevel.c
+++ b/arch/arm/boards/beaglebone/lowlevel.c
@@ -41,6 +41,7 @@ static const struct am33xx_emif_regs ddr2_regs = {
.emif_tim1 = 0x0666B3C9,
.emif_tim2 = 0x243631CA,
.emif_tim3 = 0x0000033F,
+ .ocp_config = 0x00141414,
.sdram_config = 0x41805332,
.sdram_config2 = 0x41805332,
.sdram_ref_ctrl = 0x0000081A,
@@ -97,6 +98,7 @@ static const struct am33xx_emif_regs ddr3_regs = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
+ .ocp_config = 0x00141414,
.zq_config = 0x50074BE4,
.sdram_config = 0x61C05332,
.sdram_config2 = 0x0,
diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
index 3ab8d66..fea00ef 100644
--- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
+++ b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c
@@ -97,7 +97,7 @@ void __bare_init barebox_arm_reset_vector(void)
debug_led(1, 1);
if (! load_stage2((void*)(ld_var(_text) - 16),
- ld_var(_barebox_image_size) + 16)) {
+ barebox_image_size + 16)) {
debug_led(3, 1);
while (1) { } /* hang */
}
diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h
index 9576d26..4ea654d 100644
--- a/arch/arm/boards/phytec-som-am335x/ram-timings.h
+++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h
@@ -45,6 +45,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -66,6 +67,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -87,6 +89,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -106,6 +109,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x262F7FDA,
.emif_tim3 = 0x501F82BF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C05232,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -125,6 +129,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
@@ -144,6 +149,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C053B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
@@ -163,6 +169,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAE4DB,
.emif_tim2 = 0x268F7FDA,
.emif_tim3 = 0x501F88BF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C053B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30
@@ -182,6 +189,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -203,6 +211,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x266B7FDA,
.emif_tim3 = 0x501F867F,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C05332,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -222,6 +231,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x26437FDA,
.emif_tim3 = 0x501F83FF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C052B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
@@ -241,6 +251,7 @@ struct am335x_sdram_timings physom_timings[] = {
.emif_tim1 = 0x0AAAD4DB,
.emif_tim2 = 0x268F7FDA,
.emif_tim3 = 0x501F88BF,
+ .ocp_config = 0x003d3d3d,
.sdram_config = 0x61C053B2,
.zq_config = 0x50074BE4,
.sdram_ref_ctrl = 0x00000C30,
diff --git a/arch/arm/boards/phytec-som-rk3288/lowlevel.c b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
index 7804a55..7649ef8 100644
--- a/arch/arm/boards/phytec-som-rk3288/lowlevel.c
+++ b/arch/arm/boards/phytec-som-rk3288/lowlevel.c
@@ -30,14 +30,13 @@ ENTRY_FUNCTION(start_rk3288_phycore_som, r0, r1, r2)
if (IS_ENABLED(CONFIG_DEBUG_LL)) {
struct rk3288_grf * const grf = (void *)RK3288_GRF_BASE;
- rk_clrsetreg(&grf->gpio4c_iomux,
- GPIO4C1_MASK << GPIO4C1_SHIFT |
- GPIO4C0_MASK << GPIO4C0_SHIFT,
- GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
- GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
+ rk_clrsetreg(&grf->gpio7ch_iomux,
+ GPIO7C7_MASK << GPIO7C7_SHIFT |
+ GPIO7C6_MASK << GPIO7C6_SHIFT,
+ GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+ GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
INIT_LL();
}
-
fdt = __dtb_rk3288_phycore_som_start - get_runtime_offset();
barebox_arm_entry(0x0, SZ_1G, fdt);