diff options
Diffstat (limited to 'arch/arm/boards')
53 files changed, 982 insertions, 1006 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index bb269418ef..a4219d7f77 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MACH_AT91SAM9N12EK) += at91sam9n12ek/ obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ +obj-$(CONFIG_MACH_NITROGEN6X) += boundarydevices-nitrogen6x/ obj-$(CONFIG_MACH_CCMX51) += ccxmx51/ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ obj-$(CONFIG_MACH_CHUMBY) += chumby_falconwing/ @@ -78,7 +79,7 @@ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ -obj-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += solidrun-carrier-1/ +obj-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += solidrun-hummingboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/ diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c index e684222bc7..ca64d6df83 100644 --- a/arch/arm/boards/animeo_ip/init.c +++ b/arch/arm/boards/animeo_ip/init.c @@ -328,7 +328,7 @@ device_initcall(animeo_ip_devices_init); static struct device_d *usart0, *usart1; -static void animeo_ip_shutdown_uart(void *base) +static void animeo_ip_shutdown_uart(void __iomem *base) { #define ATMEL_US_BRGR 0x0020 writel(0, base + ATMEL_US_BRGR); diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/Makefile b/arch/arm/boards/boundarydevices-nitrogen6x/Makefile new file mode 100644 index 0000000000..177c5d81a5 --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-nitrogen6x-1g.dcd.o +extra-y += flash-header-nitrogen6x-1g.dcd.S flash-header-nitrogen6x-1g.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/board.c b/arch/arm/boards/boundarydevices-nitrogen6x/board.c new file mode 100644 index 0000000000..1c4b49563f --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/board.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Lucas Stach, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <environment.h> +#include <mach/bbu.h> +#include <linux/phy.h> +#include <linux/micrel_phy.h> +#include <mach/imx6.h> + +static int nitrogen6x_devices_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") && + !of_machine_is_compatible("fsl,imx6q-nitrogen6x")) + return 0; + + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0); + + return 0; +} +device_initcall(nitrogen6x_devices_init); + +static int ksz9021rn_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x09, 0x0f00); + + /* do same as linux kernel */ + /* min rx data delay */ + phy_write(dev, 0x0b, 0x8105); + phy_write(dev, 0x0c, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + phy_write(dev, 0x0b, 0x8104); + phy_write(dev, 0x0c, 0xf0f0); + phy_write(dev, 0x0b, 0x104); + + return 0; +} + +static int nitrogen6x_coredevices_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") && + !of_machine_is_compatible("fsl,imx6q-nitrogen6x")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + return 0; +} +coredevice_initcall(nitrogen6x_coredevices_init); + +static int nitrogen6x_postcore_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") && + !of_machine_is_compatible("fsl,imx6q-nitrogen6x")) + return 0; + + imx6_init_lowlevel(); + + barebox_set_hostname("nitrogen6x"); + + return 0; +} +postcore_initcall(nitrogen6x_postcore_init); diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/env/config-board b/arch/arm/boards/boundarydevices-nitrogen6x/env/config-board new file mode 100644 index 0000000000..4cabac63dd --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc1,115200" diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg new file mode 100644 index 0000000000..60a39fe870 --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg @@ -0,0 +1,106 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 +wm 32 0x020e056c 0x00020030 +wm 32 0x020e0578 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e0594 0x00020030 +wm 32 0x020e057c 0x00020030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0798 0x000c0000 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b0018 0x00081740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b000c 0x555a7975 +wm 32 0x021b0010 0xff538e64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x005b0e21 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0040 0x00000027 +wm 32 0x021b0000 0x831a0000 +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x00428039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0800 0xa1380003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00022227 +wm 32 0x021b4818 0x00022227 +wm 32 0x021b083c 0x434b0350 +wm 32 0x021b0840 0x034c0359 +wm 32 0x021b483c 0x434b0350 +wm 32 0x021b4840 0x03650348 +wm 32 0x021b0848 0x4436383b +wm 32 0x021b4848 0x39393341 +wm 32 0x021b0850 0x35373933 +wm 32 0x021b4850 0x48254A36 +wm 32 0x021b080c 0x001f001f +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 +wm 32 0x021b4810 0x00440044 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b001c 0x00000000 +wm 32 0x021b0404 0x00011006 +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff +/* enable AXI cache for VDOA/VPU/IPU */ +wm 32 0x020e0010 0xf00000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f diff --git a/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c new file mode 100644 index 0000000000..5b11084670 --- /dev/null +++ b/arch/arm/boards/boundarydevices-nitrogen6x/lowlevel.c @@ -0,0 +1,30 @@ +#include <common.h> +#include <sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +extern char __dtb_imx6q_nitrogen6x_start[]; + +ENTRY_FUNCTION(start_imx6q_nitrogen6x_1g, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6q_nitrogen6x_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} + +extern char __dtb_imx6dl_nitrogen6x_start[]; + +ENTRY_FUNCTION(start_imx6dl_nitrogen6x_1g, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6dl_nitrogen6x_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/dfi-fs700-m60/Makefile b/arch/arm/boards/dfi-fs700-m60/Makefile index 28d4f296c3..2d0ec7c1ce 100644 --- a/arch/arm/boards/dfi-fs700-m60/Makefile +++ b/arch/arm/boards/dfi-fs700-m60/Makefile @@ -1,5 +1,4 @@ obj-y += board.o -obj-y += flash-header-fs700-m60-6s.dcd.o flash-header-fs700-m60-6q.dcd.o -extra-y += flash-header-fs700-m60-6s.dcd.S flash-header-fs700-m60-6q.dcd.S -extra-y += flash-header-fs700-m60-6s.dcd flash-header-fs700-m60-6q.dcd +extra-y += flash-header-fs700-m60-6s.dcd.S flash-header-fs700-m60-6q-nanya.dcd.S flash-header-fs700-m60-6q-micron.dcd.S +extra-y += flash-header-fs700-m60-6s.dcd flash-header-fs700-m60-6q-nanya.dcd flash-header-fs700-m60-6q-micron.dcd lwl-y += lowlevel.o diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c index 96f1b0e9dc..cefb6ce6a6 100644 --- a/arch/arm/boards/dfi-fs700-m60/board.c +++ b/arch/arm/boards/dfi-fs700-m60/board.c @@ -19,6 +19,9 @@ #define pr_fmt(fmt) "dfi-fs700-m60: " fmt #include <generated/mach-types.h> +#include <environment.h> +#include <bootsource.h> +#include <globalvar.h> #include <common.h> #include <sizes.h> #include <envfs.h> @@ -36,6 +39,37 @@ #include <mach/generic.h> #include <mach/bbu.h> +/* + * This board can have 512MiB, 1GiB or 2GiB of SDRAM. The actual amount of SDRAM + * is detected using mirror detection in lowlevel init and is stored in the first + * SDRAM address from the lowlevel code. + */ +static int dfi_fs700_m60_mem_init(void) +{ + u32 memsize; + + if (!of_machine_is_compatible("dfi,fs700-m60")) + return 0; + + memsize = *(u32 *)0x10000000; + + /* play safe if we find some corrupted amount of SDRAM */ + switch (memsize) { + case SZ_512M: + case SZ_1G: + case SZ_2G: + break; + default: + pr_err("unknown SDRAM size 0x%08x defaulting to 512MiB\n", memsize); + memsize = SZ_512M; + } + + arm_add_mem_device("ram0", 0x10000000, memsize); + + return 0; +} +mem_initcall(dfi_fs700_m60_mem_init); + static int ar8031_phy_fixup(struct phy_device *dev) { u16 val; @@ -64,13 +98,22 @@ static int ar8031_phy_fixup(struct phy_device *dev) static int dfi_fs700_m60_init(void) { + unsigned flag_spi = 0, flag_mmc = 0; + if (!of_machine_is_compatible("dfi,fs700-m60")) return 0; phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); + if (bootsource_get() == BOOTSOURCE_SPI) + flag_spi |= BBU_HANDLER_FLAG_DEFAULT; + else + flag_mmc |= BBU_HANDLER_FLAG_DEFAULT; + imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.boot0", - BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0); + flag_mmc, NULL, 0, 0); + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0", + flag_spi, NULL, 0, 0); armlinux_set_architecture(MACH_TYPE_MX6Q_SABRESD); diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg index f88157f9b8..835d0c7d4c 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg @@ -1,128 +1,104 @@ loadaddr 0x27800000 soc imx6 dcdofs 0x400 -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 - -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 - -wm 32 0x020e0514 0x00020030 wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 - +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e0528 0x00020030 wm 32 0x020e056c 0x00020030 wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 - wm 32 0x020e057c 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e058c 0x00000000 wm 32 0x020e0590 0x00003000 +wm 32 0x020e0594 0x00020030 wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 - wm 32 0x020e059c 0x00003030 wm 32 0x020e05a0 0x00003030 +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +wm 32 0x020e05c4 0x00020030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 wm 32 0x020e0784 0x00000030 wm 32 0x020e0788 0x00000030 - +wm 32 0x020e078c 0x00000030 wm 32 0x020e0794 0x00000030 +wm 32 0x020e0798 0x000c0000 wm 32 0x020e079c 0x00000030 wm 32 0x020e07a0 0x00000030 wm 32 0x020e07a4 0x00000030 - wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 - -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000C0000 - wm 32 0x021b081c 0x33333333 wm 32 0x021b0820 0x33333333 wm 32 0x021b0824 0x33333333 wm 32 0x021b0828 0x33333333 - wm 32 0x021b481c 0x33333333 wm 32 0x021b4820 0x33333333 wm 32 0x021b4824 0x33333333 wm 32 0x021b4828 0x33333333 - wm 32 0x021b0018 0x00081740 - wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555A7974 -wm 32 0x021b0010 0xDB538F64 -wm 32 0x021b0014 0x01FF00DB -wm 32 0x021b002c 0x000026D2 - -wm 32 0x021b0030 0x005A1023 +wm 32 0x021b000c 0x555a7974 +wm 32 0x021b0010 0xdb538f64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x005a1023 wm 32 0x021b0008 0x09444040 wm 32 0x021b0004 0x00025576 wm 32 0x021b0040 0x00000027 -wm 32 0x021b0000 0x831A0000 - +wm 32 0x021b0000 0x831a0000 wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803A +wm 32 0x021b001c 0x0408803a wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803B +wm 32 0x021b001c 0x0000803b wm 32 0x021b001c 0x00428031 wm 32 0x021b001c 0x00428039 wm 32 0x021b001c 0x19308030 wm 32 0x021b001c 0x19308038 - wm 32 0x021b001c 0x04008040 wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xA1380003 -wm 32 0x021b4800 0xA1380003 +wm 32 0x021b0800 0xa1380003 +wm 32 0x021b4800 0xa1380003 wm 32 0x021b0020 0x00005800 wm 32 0x021b0818 0x00022227 wm 32 0x021b4818 0x00022227 - -wm 32 0x021b083c 0x434B0350 -wm 32 0x021b0840 0x034C0359 -wm 32 0x021b483c 0x434B0350 +wm 32 0x021b083c 0x434b0350 +wm 32 0x021b0840 0x034c0359 +wm 32 0x021b483c 0x434b0350 wm 32 0x021b4840 0x03650348 -wm 32 0x021b0848 0x4436383B +wm 32 0x021b0848 0x4436383b wm 32 0x021b4848 0x39393341 wm 32 0x021b0850 0x35373933 -wm 32 0x021b4850 0x48254A36 - -wm 32 0x021b080c 0x001F001F -wm 32 0x021b0810 0x001F001F - +wm 32 0x021b4850 0x48254a36 +wm 32 0x021b080c 0x001f001f +wm 32 0x021b0810 0x001f001f wm 32 0x021b480c 0x00440044 wm 32 0x021b4810 0x00440044 - wm 32 0x021b08b8 0x00000800 wm 32 0x021b48b8 0x00000800 - wm 32 0x021b001c 0x00000000 wm 32 0x021b0404 0x00011006 - -wm 32 0x020c4068 0x00C03F3F -wm 32 0x020c406c 0x0030FC03 -wm 32 0x020c4070 0x0FFFC000 -wm 32 0x020c4074 0x3FF00000 -wm 32 0x020c4078 0x00FFF300 -wm 32 0x020c407c 0x0F0000C3 -wm 32 0x020c4080 0x000003FF - - -wm 32 0x020e0010 0xF00000CF - -wm 32 0x020e0018 0x007F007F -wm 32 0x020e001c 0x007F007F +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff +wm 32 0x020e0010 0xf00000cf +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg new file mode 100644 index 0000000000..e5bc762b48 --- /dev/null +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg @@ -0,0 +1,102 @@ +loadaddr 0x27800000 +soc imx6 +dcdofs 0x400 + +wm 32 0x020e0798 0x000C0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 + +wm 32 0x021b0800 0xA1390003 +wm 32 0x021b080c 0x001F001F +wm 32 0x021b0810 0x001F001F +wm 32 0x021b480c 0x001F001F +wm 32 0x021b4810 0x001F001F + +wm 32 0x021b083c 0x43260335 +wm 32 0x021b0840 0x031A030B +wm 32 0x021b483c 0x4323033B +wm 32 0x021b4840 0x0323026F + +wm 32 0x021b0848 0x483D4545 +wm 32 0x021b4848 0x44433E48 + +wm 32 0x021b0850 0x41444840 +wm 32 0x021b4850 0x4835483E + +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 + +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 + +wm 32 0x021b000c 0x8A8F7955 +wm 32 0x021b0010 0xFF328F64 +wm 32 0x021b0014 0x01FF00DB + +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b002c 0x000026D2 + +wm 32 0x021b0030 0x008F1023 +wm 32 0x021b0040 0x00000047 +wm 32 0x021b0000 0x841A0000 + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x04008040 + +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 + +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg index 9f5b14f860..25cef4ac16 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg @@ -15,40 +15,40 @@ wm 32 0x020e04b4 0x00000030 wm 32 0x020e04b8 0x00000030 wm 32 0x020e076c 0x00000030 wm 32 0x020e0750 0x00020000 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 +wm 32 0x020e04bc 0x00000028 +wm 32 0x020e04c0 0x00000028 +wm 32 0x020e04c4 0x00000028 +wm 32 0x020e04c8 0x00000028 wm 32 0x020e0760 0x00020000 -wm 32 0x020e0764 0x00000030 -wm 32 0x020e0770 0x00000030 -wm 32 0x020e0778 0x00000030 -wm 32 0x020e077c 0x00000030 -wm 32 0x020e0470 0x00000030 -wm 32 0x020e0474 0x00000030 -wm 32 0x020e0478 0x00000030 -wm 32 0x020e047c 0x00000030 +wm 32 0x020e0764 0x00000028 +wm 32 0x020e0770 0x00000028 +wm 32 0x020e0778 0x00000028 +wm 32 0x020e077c 0x00000028 +wm 32 0x020e0470 0x00000028 +wm 32 0x020e0474 0x00000028 +wm 32 0x020e0478 0x00000028 +wm 32 0x020e047c 0x00000028 wm 32 0x021b0800 0xa1390003 wm 32 0x021b080c 0x001f001f wm 32 0x021b0810 0x001f001f -wm 32 0x021b083c 0x42190219 -wm 32 0x021b0840 0x017b0177 -wm 32 0x021b0848 0x4b4d4e4d -wm 32 0x021b0850 0x3f3e2d36 +wm 32 0x021b083c 0x421c0216 +wm 32 0x021b0840 0x017b017a +wm 32 0x021b0848 0x4b4a4e4c +wm 32 0x021b0850 0x3f3f3334 wm 32 0x021b081c 0x33333333 wm 32 0x021b0820 0x33333333 wm 32 0x021b0824 0x33333333 wm 32 0x021b0828 0x33333333 wm 32 0x021b08b8 0x00000800 -wm 32 0x021b0004 0x0002002d +wm 32 0x021b0004 0x00020025 wm 32 0x021b0008 0x00333030 -wm 32 0x021b000c 0x3f435313 +wm 32 0x021b000c 0x676b5313 wm 32 0x021b0010 0xb66e8b63 wm 32 0x021b0014 0x01ff00db wm 32 0x021b0018 0x00001740 wm 32 0x021b001c 0x00008000 wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x00431023 +wm 32 0x021b0030 0x006b1023 wm 32 0x021b0040 0x00000027 wm 32 0x021b0000 0x84190000 wm 32 0x021b001c 0x04008032 @@ -58,6 +58,6 @@ wm 32 0x021b001c 0x05208030 wm 32 0x021b001c 0x04008040 wm 32 0x021b0020 0x00005800 wm 32 0x021b0818 0x00011117 -wm 32 0x021b0004 0x0002556d +wm 32 0x021b0004 0x00025565 wm 32 0x021b0404 0x00011006 wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c index 2995bd4db7..5d1e5f409e 100644 --- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c +++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c @@ -35,6 +35,8 @@ static inline void early_uart_init(void) writel(0x0000047f, MX6_UART1_BASE_ADDR + 0xa4); writel(0x0000c34f, MX6_UART1_BASE_ADDR + 0xa8); writel(0x00000001, MX6_UART1_BASE_ADDR + 0x80); + + putc_ll('>'); } static inline void early_uart_init_6q(void) @@ -59,20 +61,83 @@ static inline void early_uart_init_6s(void) early_uart_init(); } +static inline unsigned int memsize_512M_1G(void) +{ + volatile u32 *a = (u32 *)0x10000000; + volatile u32 *b = (u32 *)0x30000000; + u32 size; + + *a = 0x55555555; + *b = 0xaaaaaaaa; + + if (*a == 0xaaaaaaaa) + size = SZ_512M; + else + size = SZ_1G; + + *a = size; + + return size; +} + +static inline unsigned int memsize_1G_2G(void) +{ + volatile u32 *a = (u32 *)0x10000000; + volatile u32 *b = (u32 *)0x50000000; + u32 size; + + *a = 0x55555555; + *b = 0xaaaaaaaa; + + if (*a == 0xaaaaaaaa) + size = SZ_1G; + else + size = SZ_2G; + + *a = size; + + return size; +} + extern char __dtb_imx6q_dfi_fs700_m60_6q_start[]; -ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q, r0, r1, r2) +ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_nanya, r0, r1, r2) +{ + uint32_t fdt; + int i; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00940000 - 8); + + for (i = 0x68; i <= 0x80; i += 4) + writel(0xffffffff, MX6_CCM_BASE_ADDR + i); + + early_uart_init_6q(); + + fdt = (uint32_t)__dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, memsize_1G_2G(), fdt); +} + +ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_micron, r0, r1, r2) { uint32_t fdt; + int i; arm_cpu_lowlevel_init(); arm_setup_stack(0x00940000 - 8); + for (i = 0x68; i <= 0x80; i += 4) + writel(0xffffffff, MX6_CCM_BASE_ADDR + i); + early_uart_init_6q(); fdt = (uint32_t)__dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset(); + *(uint32_t *)0x10000000 = SZ_1G; + barebox_arm_entry(0x10000000, SZ_1G, fdt); } @@ -94,5 +159,5 @@ ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2) fdt = (uint32_t)__dtb_imx6dl_dfi_fs700_m60_6s_start - get_runtime_offset(); - barebox_arm_entry(0x10000000, SZ_1G, fdt); + barebox_arm_entry(0x10000000, memsize_512M_1G(), fdt); } diff --git a/arch/arm/boards/dmo-mx6-realq7/board.c b/arch/arm/boards/dmo-mx6-realq7/board.c index 1753bddd51..8a49beee2f 100644 --- a/arch/arm/boards/dmo-mx6-realq7/board.c +++ b/arch/arm/boards/dmo-mx6-realq7/board.c @@ -74,7 +74,7 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev) static int realq7_enet_init(void) { - if (!of_machine_is_compatible("dmo,imx6q-realq7")) + if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) return 0; mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); @@ -100,7 +100,7 @@ fs_initcall(realq7_enet_init); static int realq7_env_init(void) { - if (!of_machine_is_compatible("dmo,imx6q-realq7")) + if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) return 0; imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", @@ -113,7 +113,7 @@ late_initcall(realq7_env_init); static int realq7_console_init(void) { - if (!of_machine_is_compatible("dmo,imx6q-realq7")) + if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) return 0; barebox_set_hostname("eDM-QMX6"); diff --git a/arch/arm/boards/dmo-mx6-realq7/lowlevel.c b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c index f47575e991..de7cc98efe 100644 --- a/arch/arm/boards/dmo-mx6-realq7/lowlevel.c +++ b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c @@ -15,6 +15,7 @@ #include <common.h> #include <sizes.h> #include <io.h> +#include <debug_ll.h> #include <asm/sections.h> #include <asm/mmu.h> #include <asm/barebox-arm-head.h> @@ -136,26 +137,37 @@ static void sdram_init(void) writel(0x0000047f, 0x021e80a4); writel(0x0000c34f, 0x021e80a8); writel(0x00000001, 0x021e8080); + putc_ll('>'); } -extern char __dtb_imx6q_dmo_realq7_start[]; +extern char __dtb_imx6q_dmo_edmqmx6_start[]; +extern char __dtb_imx6q_dmo_edmqmx6_end[]; ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2) { - uint32_t fdt; + unsigned long fdt, sdram = 0x10000000; arm_cpu_lowlevel_init(); arm_setup_stack(0x00940000 - 8); + fdt = (unsigned long)__dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset(); + if (get_pc() < 0x10000000) { sdram_init(); mmdc_do_write_level_calibration(); mmdc_do_dqs_calibration(); - } - fdt = (uint32_t)__dtb_imx6q_dmo_realq7_start - get_runtime_offset(); + /* + * Copy the devicetree blob to sdram so that the barebox code finds it + * inside valid SDRAM instead of SRAM. + */ + memcpy((void *)sdram, (void *)fdt, + __dtb_imx6q_dmo_edmqmx6_start - + __dtb_imx6q_dmo_edmqmx6_end); + fdt = sdram; + } - barebox_arm_entry(0x10000000, SZ_2G, fdt); + barebox_arm_entry(sdram, SZ_2G, fdt); } diff --git a/arch/arm/boards/efika-mx-smartbook/env/config b/arch/arm/boards/efika-mx-smartbook/env/config index 46aff49088..c63c6a1fa5 100644 --- a/arch/arm/boards/efika-mx-smartbook/env/config +++ b/arch/arm/boards/efika-mx-smartbook/env/config @@ -20,7 +20,7 @@ global.autoboot_timeout=1 #global.boot.default=net # base bootargs -global.linux.bootargs.base="console=ttymxc0,115200 console=tty1" +global.linux.bootargs.base="console=tty1" # suitable for 800MHz global linux.bootargs.lpj="lpj=3997696" diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 11d990dfd9..f0bf2c7fd5 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -127,12 +127,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ - arm_setup_stack(STACK_BASE + STACK_SIZE - 12); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12); - imx25_barebox_boot_nand_external(); -#endif + imx25_barebox_boot_nand_external(0); + } out: imx25_barebox_entry(0); } diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index a85b00d910..f8e3c23540 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -123,12 +123,13 @@ barebox_arm_reset_vector: 1: sdram_init -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND /* Setup a temporary stack in SDRAM */ ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4; + mov r0, #0 b imx27_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ ret: b imx27_barebox_entry diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index a667e4c5eb..b8ba3c8716 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -130,18 +130,19 @@ void __bare_init __naked barebox_arm_reset_vector(void) writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - - imx35_barebox_boot_nand_external(); -#endif + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } + out: imx35_barebox_entry(0); } diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S index 174262d193..4ca4c82d32 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -97,12 +97,14 @@ barebox_arm_reset_vector: ldr r3, ESDCTL_DELAY5 str r3, [r0, #0x30] -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND + /* Setup a temporary stack in SRAM */ ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 + mov r0, #0 b imx25_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ ret: b imx25_barebox_entry diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S index 2844465f39..6d37f35a2e 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -154,12 +154,13 @@ barebox_arm_reset_vector: ldr r3, =ESDCTL_DELAY_LINE5 str r3, [r0, #0x30] -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND /* Setup a temporary stack in internal SRAM */ ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 + mov r0, #0 b imx35_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ b imx35_barebox_entry diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c index 8dc81d811a..bfe5338bcd 100644 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ b/arch/arm/boards/freescale-mx51-pdk/board.c @@ -141,21 +141,14 @@ static void babbage_power_init(void) /* Configure VGEN3 and VCAM regulators to use external PNP */ val = 0x208; mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); - udelay(200); -#define GPIO_LAN8700_RESET (1 * 32 + 14) - /* Reset the ethernet controller over GPIO */ - gpio_direction_output(GPIO_LAN8700_RESET, 0); + udelay(200); /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = 0x49249; mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); udelay(200); - - gpio_set_value(GPIO_LAN8700_RESET, 1); - - mdelay(50); } extern char flash_header_imx51_babbage_start[]; diff --git a/arch/arm/boards/freescale-mx53-loco/lowlevel.c b/arch/arm/boards/freescale-mx53-loco/lowlevel.c index 7556a2e35f..c9e057ae67 100644 --- a/arch/arm/boards/freescale-mx53-loco/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-loco/lowlevel.c @@ -15,3 +15,16 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2) imx53_barebox_entry(fdt); } + +extern char __dtb_imx53_qsrb_start[]; + +ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx53_qsrb_start - get_runtime_offset(); + + imx53_barebox_entry(fdt); +} diff --git a/arch/arm/boards/freescale-mx53-vmx53/board.c b/arch/arm/boards/freescale-mx53-vmx53/board.c index b38db713ed..d0cc495a5d 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/board.c +++ b/arch/arm/boards/freescale-mx53-vmx53/board.c @@ -30,6 +30,9 @@ extern char flash_header_imx53_vmx53_end[]; static int vmx53_late_init(void) { + if (!of_machine_is_compatible("voipac,imx53-dmm-668")) + return 0; + armlinux_set_architecture(MACH_TYPE_VMX53); barebox_set_model("Voipac VMX53"); diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index badfd9e69c..85c61510fa 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -51,6 +51,10 @@ static iomux_v3_cfg_t sabrelite_enet_gpio_pads[] = { static int sabrelite_mem_init(void) { + if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && + !of_machine_is_compatible("fsl,imx6dl-sabrelite")) + return 0; + arm_add_mem_device("ram0", 0x10000000, SZ_1G); return 0; @@ -76,6 +80,10 @@ static int ksz9021rn_phy_fixup(struct phy_device *dev) static int sabrelite_ksz9021rn_setup(void) { + if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && + !of_machine_is_compatible("fsl,imx6dl-sabrelite")) + return 0; + mxc_iomux_v3_setup_multiple_pads(sabrelite_enet_gpio_pads, ARRAY_SIZE(sabrelite_enet_gpio_pads)); @@ -116,7 +124,8 @@ static void sabrelite_ehci_init(void) static int sabrelite_devices_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabrelite")) + if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && + !of_machine_is_compatible("fsl,imx6dl-sabrelite")) return 0; sabrelite_ehci_init(); @@ -132,7 +141,8 @@ device_initcall(sabrelite_devices_init); static int sabrelite_coredevices_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabrelite")) + if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && + !of_machine_is_compatible("fsl,imx6dl-sabrelite")) return 0; phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, @@ -143,7 +153,8 @@ coredevice_initcall(sabrelite_coredevices_init); static int sabrelite_postcore_init(void) { - if (!of_machine_is_compatible("fsl,imx6q-sabrelite")) + if (!of_machine_is_compatible("fsl,imx6q-sabrelite") && + !of_machine_is_compatible("fsl,imx6dl-sabrelite")) return 0; imx6_init_lowlevel(); diff --git a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c index b36a39c23e..14a7f322f7 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c @@ -5,7 +5,7 @@ extern char __dtb_imx6q_sabrelite_start[]; -ENTRY_FUNCTION(start_imx6_sabrelite, r0, r1, r2) +ENTRY_FUNCTION(start_imx6q_sabrelite, r0, r1, r2) { uint32_t fdt; @@ -15,3 +15,16 @@ ENTRY_FUNCTION(start_imx6_sabrelite, r0, r1, r2) barebox_arm_entry(0x10000000, SZ_1G, fdt); } + +extern char __dtb_imx6dl_sabrelite_start[]; + +ENTRY_FUNCTION(start_imx6dl_sabrelite, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6dl_sabrelite_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index d5298c1836..4c0de9caed 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -306,18 +306,19 @@ void __bare_init __naked barebox_arm_reset_vector(void) r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */ setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00); -#ifdef CONFIG_NAND_IMX_BOOT - /* Speed up NAND controller by adjusting the NFC divider */ - r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r0 &= ~(0xf << 28); - r0 |= 0x1 << 28; - writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r0 &= ~(0xf << 28); + r0 |= 0x1 << 28; + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } - imx35_barebox_boot_nand_external(); -#endif out: imx35_barebox_entry(0); } diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 386751d5ef..d26ee73ef1 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -86,12 +86,13 @@ void __bare_init __naked barebox_arm_reset_vector(void) ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx27_barebox_boot_nand_external() */ - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx27_barebox_boot_nand_external() */ + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + + imx27_barebox_boot_nand_external(0); + } - imx27_barebox_boot_nand_external(); -#endif out: imx27_barebox_entry(0); } diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S index 09ca4a477e..471390f328 100644 --- a/arch/arm/boards/imx21ads/lowlevel_init.S +++ b/arch/arm/boards/imx21ads/lowlevel_init.S @@ -118,12 +118,13 @@ barebox_arm_reset_vector: ldr r1, =0x6419a007 str r1, [r0] -#ifdef CONFIG_NAND_IMX_BOOT +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND { + /* Setup a temporary stack in SRAM */ ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4 b imx21_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ ret: mov r0, #0xc0000000 diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index 337ae01d6c..59c81b2faa 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -17,6 +17,8 @@ * */ +#define pr_fmt(fmt) "tx25: " fmt + #include <common.h> #include <init.h> #include <driver.h> @@ -31,131 +33,69 @@ #include <partition.h> #include <generated/mach-types.h> #include <mach/imx-nand.h> -#include <fec.h> -#include <nand.h> #include <mach/iomux-mx25.h> #include <mach/generic.h> #include <mach/iim.h> #include <linux/err.h> #include <mach/devices-imx25.h> +#include <mach/bbu.h> #include <asm/mmu.h> -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, - .phy_addr = 0x1f, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static iomux_v3_cfg_t karo_tx25_padsd_fec[] = { - MX25_PAD_D11__GPIO_4_9, /* FEC PHY power on pin */ - MX25_PAD_D13__GPIO_4_7, /* FEC reset */ - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, -}; - #define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9) #define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7) +static struct gpio fec_gpios[] = { + { + .gpio = TX25_FEC_PWR_GPIO, + .flags = GPIOF_OUT_INIT_LOW, + .label = "fec-pwr", + }, { + .gpio = TX25_FEC_RST_GPIO, + .flags = GPIOF_OUT_INIT_LOW, + .label = "fec-rst", + }, +}; + static void noinline gpio_fec_active(void) { - mxc_iomux_v3_setup_multiple_pads(karo_tx25_padsd_fec, - ARRAY_SIZE(karo_tx25_padsd_fec)); + int ret; /* power down phy, put into reset */ - gpio_direction_output(TX25_FEC_PWR_GPIO, 0); - gpio_direction_output(TX25_FEC_RST_GPIO, 0); + ret = gpio_request_array(fec_gpios, ARRAY_SIZE(fec_gpios)); + if (ret) { + pr_err("Failed to request fec gpios: %s\n", strerror(-ret)); + return; + } udelay(10); - /* power up phy, get out of reset */ - gpio_direction_output(TX25_FEC_PWR_GPIO, 1); - gpio_direction_output(TX25_FEC_RST_GPIO, 1); + /* power up phy, but leave in reset */ + gpio_set_value(TX25_FEC_PWR_GPIO, 1); udelay(100); - /* apply a reset to the powered phy again */ - gpio_direction_output(TX25_FEC_RST_GPIO, 0); - udelay(100); - gpio_direction_output(TX25_FEC_RST_GPIO, 1); + /* FEC driver picks up the reset gpio later */ + gpio_free(TX25_FEC_RST_GPIO); } -static int tx25_devices_init(void) +static int tx25_init(void) { - gpio_fec_active(); - - imx25_iim_register_fec_ethaddr(); - imx25_add_fec(&fec_info); - - if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) - nand_info.width = 2; + if (!of_machine_is_compatible("karo,imx25-tx25")) + return 0; - imx25_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - add_mem_device("sram0", 0x78000000, 128 * 1024, - IORESOURCE_MEM_WRITEABLE); + gpio_fec_active(); + barebox_set_hostname("tx25"); armlinux_set_architecture(MACH_TYPE_TX25); armlinux_set_serial(imx_uid()); - return 0; -} + imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot", + BBU_HANDLER_FLAG_DEFAULT); -device_initcall(tx25_devices_init); - -static iomux_v3_cfg_t tx25_pads[] = { - MX25_PAD_D12__GPIO_4_8, - MX25_PAD_D10__GPIO_4_10, - MX25_PAD_NF_CE0__NF_CE0, - MX25_PAD_NFWE_B__NFWE_B, - MX25_PAD_NFRE_B__NFRE_B, - MX25_PAD_NFALE__NFALE, - MX25_PAD_NFCLE__NFCLE, - MX25_PAD_NFWP_B__NFWP_B, - MX25_PAD_NFRB__NFRB, - MX25_PAD_D7__D7, - MX25_PAD_D6__D6, - MX25_PAD_D5__D5, - MX25_PAD_D4__D4, - MX25_PAD_D3__D3, - MX25_PAD_D2__D2, - MX25_PAD_D1__D1, - MX25_PAD_D0__D0, - MX25_PAD_UART1_TXD__UART1_TXD, - MX25_PAD_UART1_RXD__UART1_RXD, - MX25_PAD_UART1_CTS__UART1_CTS, - MX25_PAD_UART1_RTS__UART1_RTS, -}; - -static int tx25_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(tx25_pads, ARRAY_SIZE(tx25_pads)); - - barebox_set_model("Ka-Ro TX25"); - barebox_set_hostname("tx25"); - - imx25_add_uart0(); return 0; } -console_initcall(tx25_console_init); +console_initcall(tx25_init); static iomux_v3_cfg_t tx25_lcdc_gpios[] = { MX25_PAD_A18__GPIO_2_4, /* LCD Reset (active LOW) */ @@ -232,6 +172,12 @@ static struct imx_fb_platform_data tx25_fb_data = { static int tx25_init_fb(void) { + if (!IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX)) + return 0; + + if (!of_machine_is_compatible("karo,imx25-tx25")) + return 0; + tx25_fb_enable(0); mxc_iomux_v3_setup_multiple_pads(tx25_lcdc_gpios, diff --git a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand index 4fffefca8b..e2dcfab49a 100644 --- a/arch/arm/boards/karo-tx25/env/init/mtdparts-nand +++ b/arch/arm/boards/karo-tx25/env/init/mtdparts-nand @@ -5,7 +5,7 @@ if [ "$1" = menu ]; then exit fi -mtdparts="512k(nand0.barebox)ro,512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +mtdparts="512k(nand0.barebox),512k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" kernelname="mxc_nand" mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index 742100d0ab..be27bc7bd3 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -75,7 +75,7 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, writel(esdctl, esdctlreg); } -void __bare_init __naked barebox_arm_reset_vector(void) +static void __bare_init karo_tx25_common_init(uint32_t fdt) { uint32_t r; @@ -157,12 +157,21 @@ void __bare_init __naked barebox_arm_reset_vector(void) setup_sdram(0x80000000, ESDCTLVAL, ESDCFGVAL); setup_sdram(0x90000000, ESDCTLVAL, ESDCFGVAL); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx25_barebox_boot_nand_external() */ - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8); + imx25_barebox_boot_nand_external(fdt); - imx25_barebox_boot_nand_external(); -#endif out: - imx25_barebox_entry(0); + imx25_barebox_entry(fdt); +} + +extern char __dtb_imx25_karo_tx25_start[]; + +ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2) +{ + uint32_t fdt; + + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8); + + fdt = (uint32_t)__dtb_imx25_karo_tx25_start - get_runtime_offset(); + + karo_tx25_common_init(fdt); } diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c index b81a24f0cd..cd894c25ce 100644 --- a/arch/arm/boards/pcm037/lowlevel.c +++ b/arch/arm/boards/pcm037/lowlevel.c @@ -125,12 +125,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); #endif -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); - imx31_barebox_boot_nand_external(); -#else - imx31_barebox_entry(0); -#endif + imx31_barebox_boot_nand_external(0); + } else { + imx31_barebox_entry(0); + } } diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c index 0ea293981b..4f55af8264 100644 --- a/arch/arm/boards/pcm038/lowlevel.c +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -93,12 +93,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -#ifdef CONFIG_NAND_IMX_BOOT - /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); - imx27_barebox_boot_nand_external(); -#endif + imx27_barebox_boot_nand_external(0); + } out: imx27_barebox_entry(0); } diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index ebd6b29543..8376bb4f00 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -182,18 +182,19 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* enable Auto-Refresh */ writel(0x00002000, esdctl_base + IMX_ESDCTL1); -#ifdef CONFIG_NAND_IMX_BOOT - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - - imx35_barebox_boot_nand_external(); -#endif + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } + out: imx35_barebox_entry(0); } diff --git a/arch/arm/boards/phycard-i.MX27/Makefile b/arch/arm/boards/phycard-i.MX27/Makefile index bbff2893ff..34492bb127 100644 --- a/arch/arm/boards/phycard-i.MX27/Makefile +++ b/arch/arm/boards/phycard-i.MX27/Makefile @@ -1,3 +1,3 @@ -lwl-y += lowlevel_init.o +lwl-y += lowlevel.o obj-y += pca100.o diff --git a/arch/arm/boards/phycard-i.MX27/env/config b/arch/arm/boards/phycard-i.MX27/env/config deleted file mode 100644 index 959631184c..0000000000 --- a/arch/arm/boards/phycard-i.MX27/env/config +++ /dev/null @@ -1,48 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" -rootfs_mtdblock_nand=7 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - - diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c new file mode 100644 index 0000000000..5b3bdafa71 --- /dev/null +++ b/arch/arm/boards/phycard-i.MX27/lowlevel.c @@ -0,0 +1,103 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <config.h> +#include <asm/barebox-arm-head.h> +#include <mach/imx27-regs.h> +#include <mach/imx-pll.h> +#include <mach/esdctl.h> +#include <mach/imx-nand.h> + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +static void sdram_init(void) +{ + int i; + + /* + * DDR on CSD0 + */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + + for (i = 0; i < 8; i++) + writel(0, 0xa0000f00); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writeb(0xda, 0xa0000033); + writeb(0xff, 0xa1000000); + + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); +} + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + unsigned long r; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); + + /* ahb lite ip interface */ + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0xa0000000 && r < 0xc0000000) + imx27_barebox_entry(0); + + /* 399 MHz */ + writel(IMX_PLL_PD(0) | + IMX_PLL_MFD(51) | + IMX_PLL_MFI(7) | + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0); + + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + writel(IMX_PLL_PD(1) | + IMX_PLL_MFD(12) | + IMX_PLL_MFI(9) | + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0); + + writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | + MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | + MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | + MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | + MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | + MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | + MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | + MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR); + + sdram_init(); + + imx27_barebox_boot_nand_external(0); +} diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S deleted file mode 100644 index 992fa8291b..0000000000 --- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S +++ /dev/null @@ -1,119 +0,0 @@ -/* - * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia - * Applications Processor Reference Manual, Rev. 0.2". - * - */ - -#include <config.h> -#include <mach/imx27-regs.h> -#include <mach/imx-pll.h> -#include <mach/esdctl.h> -#include <asm/barebox-arm-head.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - - -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) - -.macro sdram_init - /* - * DDR on CSD0 - */ - /* Enable DDR SDRAM operation */ - writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - - /* Set the driving strength */ - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) - writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) - writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) - - /* Initial reset */ - writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0) - - /* precharge CSD0 all banks */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - - ldr r0, =0xa0000f00 - mov r1, #0 - mov r2, #8 -1: - str r1, [r0] - subs r2, #1 - bne 1b - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - ldr r0, =0xA0000033 - mov r1, #0xda - strb r1, [r0] - ldr r0, =0xA1000000 - mov r1, #0xff - strb r1, [r0] - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) -.endm - - .section ".text_bare_init","ax" - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) - writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) - writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) - - /* skip sdram initialization if we run from ram */ - cmp pc, #0xa0000000 - bls 1f - cmp pc, #0xc0000000 - bhi 1f - - b imx27_barebox_entry - -1: - /* 399 MHz */ - writel(IMX_PLL_PD(0) | - IMX_PLL_MFD(51) | - IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) - - /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ - writel(IMX_PLL_PD(1) | - IMX_PLL_MFD(12) | - IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) - - writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | - MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | - MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | - MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | - MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | - MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | - MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | - MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR) - - sdram_init - -#ifdef CONFIG_NAND_IMX_BOOT - ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */ - - b imx27_barebox_boot_nand_external -#endif /* CONFIG_NAND_IMX_BOOT */ - -ret: - b imx27_barebox_entry - diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c index 2ff1b79329..4b355bcc6a 100644 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -21,6 +21,7 @@ #include <mach/imx27-regs.h> #include <fec.h> #include <gpio.h> +#include <sizes.h> #include <asm/armlinux.h> #include <asm/sections.h> #include <generated/mach-types.h> @@ -36,97 +37,10 @@ #include <gpio.h> #include <asm/mmu.h> #include <usb/ulpi.h> +#include <mach/bbu.h> #include <mach/iomux-mx27.h> #include <mach/devices-imx27.h> -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 1, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct imx_fb_videomode imxfb_mode[] = { - { - .mode = { - .name = "Primeview-PD050VL1", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 40000, /* in ps (25MHz) */ - .hsync_len = 32, - .left_margin = 112, - .right_margin = 36, - .vsync_len = 2, - .upper_margin = 33, - .lower_margin = 33, - }, - .pcr = 0xF0C88080, - .bpp = 16, - }, { - .mode = { - .name = "Primeview-PD035VL1", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 40000, /* in ps (25 MHz) */ - .hsync_len = 30, - .left_margin = 98, - .right_margin = 36, - .vsync_len = 2, - .upper_margin = 15, - .lower_margin = 33, - }, - .pcr = 0xF0C88080, - .bpp = 16, - }, { - .mode = { - .name = "Primeview-PD104SLF", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, /* in ps (40,0 MHz) */ - .hsync_len = 40, - .left_margin = 174, - .right_margin = 174, - .vsync_len = 4, - .upper_margin = 24, - .lower_margin = 23, - }, - .pcr = 0xF0C88080, - .bpp = 16, - }, { - .mode = { - .name = "Primeview-PM070WL4", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 31250, /* in ps (32 MHz) */ - .hsync_len = 40, - .left_margin = 174, - .right_margin = 174, - .vsync_len = 2, - .upper_margin = 33, - .lower_margin = 23, - }, - .pcr = 0xF0C88080, - .bpp = 16, - }, -}; - -static struct imx_fb_platform_data pca100_fb_data = { - .mode = imxfb_mode, - .num_modes = ARRAY_SIZE(imxfb_mode), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00040060, -}; - -#ifdef CONFIG_USB static void pca100_usb_register(void) { mdelay(10); @@ -141,7 +55,6 @@ static void pca100_usb_register(void) ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); } -#endif static void pca100_usb_init(void) { @@ -178,38 +91,7 @@ static void pca100_usb_init(void) static int pca100_devices_init(void) { int i; - struct device_d *nand; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - PD25_PF_CSPI1_RDY, - PD26_PF_CSPI1_SS2, - PD27_PF_CSPI1_SS1, - PD28_PF_CSPI1_SS0, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, /* USB host 2 */ PA0_PF_USBH2_CLK, PA1_PF_USBH2_DIR, @@ -223,13 +105,6 @@ static int pca100_devices_init(void) PD23_AF_USBH2_DATA2, PD24_AF_USBH2_DATA1, PD26_AF_USBH2_DATA5, - /* SDHC */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, PC7_PF_USBOTG_DATA5, PC8_PF_USBOTG_DATA6, PC9_PF_USBOTG_DATA0, @@ -242,33 +117,6 @@ static int pca100_devices_init(void) PE2_PF_USBOTG_DIR, PE24_PF_USBOTG_CLK, PE25_PF_USBOTG_DATA7, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA26_PF_PS, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA31_PF_OE_ACD, - /* external I2C */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, }; pca100_usb_init(); @@ -277,21 +125,11 @@ static int pca100_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - imx27_add_nand(&nand_info); - imx27_add_fec(&fec_info); - imx27_add_mmc1(NULL); - imx27_add_fb(&pca100_fb_data); - -#ifdef CONFIG_USB - pca100_usb_register(); -#endif - - nand = get_device_by_name("nand0"); - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); + if (IS_ENABLED(CONFIG_USB)) + pca100_usb_register(); - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); + imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot", + BBU_HANDLER_FLAG_DEFAULT); armlinux_set_architecture(2149); @@ -305,7 +143,6 @@ static int pca100_console_init(void) barebox_set_model("Phytec phyCARD-i.MX27"); barebox_set_hostname("phycard-imx27"); - imx27_add_uart0(); return 0; } diff --git a/arch/arm/boards/solidrun-carrier-1/Makefile b/arch/arm/boards/solidrun-carrier-1/Makefile deleted file mode 100644 index d243c8f1a3..0000000000 --- a/arch/arm/boards/solidrun-carrier-1/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o flash-header-solidrun-carrier-1.dcd.o -extra-y += flash-header-solidrun-carrier-1.dcd.S flash-header-solidrun-carrier-1.dcd -lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-carrier-1/lowlevel.c b/arch/arm/boards/solidrun-carrier-1/lowlevel.c deleted file mode 100644 index aa94716496..0000000000 --- a/arch/arm/boards/solidrun-carrier-1/lowlevel.c +++ /dev/null @@ -1,18 +0,0 @@ -#include <common.h> -#include <sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -extern char __dtb_imx6dl_cubox_i_carrier_1_start[]; - -ENTRY_FUNCTION(start_imx6dl_cubox_i_carrier_1, r0, r1, r2) -{ - uint32_t fdt; - - __barebox_arm_head(); - - arm_cpu_lowlevel_init(); - - fdt = (uint32_t)__dtb_imx6dl_cubox_i_carrier_1_start - get_runtime_offset(); - barebox_arm_entry(0x10000000, SZ_512M, fdt); -} diff --git a/arch/arm/boards/solidrun-hummingboard/Makefile b/arch/arm/boards/solidrun-hummingboard/Makefile new file mode 100644 index 0000000000..8b4754e1c1 --- /dev/null +++ b/arch/arm/boards/solidrun-hummingboard/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-solidrun-hummingboard.dcd.o +extra-y += flash-header-solidrun-hummingboard.dcd.S flash-header-solidrun-hummingboard.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-carrier-1/board.c b/arch/arm/boards/solidrun-hummingboard/board.c index f520303b73..afc5c867b2 100644 --- a/arch/arm/boards/solidrun-carrier-1/board.c +++ b/arch/arm/boards/solidrun-hummingboard/board.c @@ -60,9 +60,9 @@ static int ar8035_phy_fixup(struct phy_device *dev) return 0; } -static int carrier1_device_init(void) +static int hummingboard_device_init(void) { - if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1")) + if (!of_machine_is_compatible("solidrun,hummingboard")) return 0; phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); @@ -73,17 +73,17 @@ static int carrier1_device_init(void) return 0; } -device_initcall(carrier1_device_init); +device_initcall(hummingboard_device_init); -static int carrier1_lwl_init(void) +static int hummingboard_lwl_init(void) { - if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1")) + if (!of_machine_is_compatible("solidrun,hummingboard")) return 0; - barebox_set_hostname("carrier-1"); + barebox_set_hostname("hummingboard"); imx6_init_lowlevel(); return 0; } -postcore_initcall(carrier1_lwl_init); +postcore_initcall(hummingboard_lwl_init); diff --git a/arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg b/arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg index b1856b49ce..b1856b49ce 100644 --- a/arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg +++ b/arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg diff --git a/arch/arm/boards/solidrun-hummingboard/lowlevel.c b/arch/arm/boards/solidrun-hummingboard/lowlevel.c new file mode 100644 index 0000000000..049a8a41be --- /dev/null +++ b/arch/arm/boards/solidrun-hummingboard/lowlevel.c @@ -0,0 +1,16 @@ +#include <common.h> +#include <sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> + +extern char __dtb_imx6dl_hummingboard_start[]; + +ENTRY_FUNCTION(start_imx6dl_hummingboard, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx6dl_hummingboard_start - get_runtime_offset(); + barebox_arm_entry(0x10000000, SZ_512M, fdt); +} diff --git a/arch/arm/boards/tqma53/Makefile b/arch/arm/boards/tqma53/Makefile index d44f697718..01c7a259e9 100644 --- a/arch/arm/boards/tqma53/Makefile +++ b/arch/arm/boards/tqma53/Makefile @@ -1,3 +1,2 @@ obj-y += board.o -lwl-y += flash_header.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c index cc98de9bcb..958e5ad1f0 100644 --- a/arch/arm/boards/tqma53/board.c +++ b/arch/arm/boards/tqma53/board.c @@ -13,255 +13,32 @@ * */ -#include <common.h> #include <environment.h> -#include <fcntl.h> -#include <fec.h> -#include <fs.h> +#include <bootsource.h> +#include <common.h> #include <init.h> -#include <nand.h> -#include <net.h> -#include <partition.h> -#include <sizes.h> -#include <gpio.h> -#include <mci.h> -#include <io.h> #include <asm/armlinux.h> -#include <asm/mmu.h> #include <generated/mach-types.h> -#include <mach/imx53-regs.h> -#include <mach/iomux-mx53.h> -#include <mach/devices-imx53.h> -#include <mach/generic.h> -#include <mach/imx-nand.h> -#include <mach/iim.h> -#include <mach/imx5.h> - -#define TQMA53_EMMC_DSR 0x0100u - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, -}; - -static iomux_v3_cfg_t tqma53_pads[] = { - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW2__CAN1_RXCAN, - MX53_PAD_KEY_COL2__CAN1_TXCAN, - MX53_PAD_KEY_ROW4__CAN2_RXCAN, - MX53_PAD_KEY_COL4__CAN2_TXCAN, - MX53_PAD_GPIO_19__CCM_CLKO, - MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK, - MX53_PAD_SD1_DATA0__CSPI_MISO, - MX53_PAD_SD1_CMD__CSPI_MOSI, - MX53_PAD_SD1_CLK__CSPI_SCLK, - MX53_PAD_SD1_DATA1__CSPI_SS0, - MX53_PAD_SD1_DATA2__CSPI_SS1, - MX53_PAD_SD1_DATA3__CSPI_SS2, - MX53_PAD_EIM_D17__ECSPI1_MISO, - MX53_PAD_EIM_D18__ECSPI1_MOSI, - MX53_PAD_EIM_D16__ECSPI1_SCLK, - MX53_PAD_EIM_EB2__ECSPI1_SS0, - MX53_PAD_EIM_D19__ECSPI1_SS1, - MX53_PAD_EIM_D24__ECSPI1_SS2, - MX53_PAD_EIM_D25__ECSPI1_SS3, - MX53_PAD_GPIO_4__ESDHC2_CD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - MX53_PAD_GPIO_2__ESDHC2_WP, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_FEC_MDC__FEC_MDC, - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_RXD0__FEC_RDATA_0, - MX53_PAD_FEC_RXD1__FEC_RDATA_1, - MX53_PAD_FEC_CRS_DV__FEC_RX_DV, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_TXD0__FEC_TDATA_0, - MX53_PAD_FEC_TXD1__FEC_TDATA_1, - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_GPIO_7__FIRI_RXD, - MX53_PAD_GPIO_8__FIRI_TXD, - MX53_PAD_GPIO_0__GPIO1_0, - MX53_PAD_GPIO_3__GPIO1_3, - MX53_PAD_PATA_DATA14__GPIO2_14, - MX53_PAD_PATA_DATA15__GPIO2_15, - MX53_PAD_EIM_CS0__GPIO2_23, - MX53_PAD_EIM_OE__GPIO2_25, - MX53_PAD_EIM_RW__GPIO2_26, - MX53_PAD_EIM_LBA__GPIO2_27, - MX53_PAD_PATA_DATA5__GPIO2_5, - MX53_PAD_PATA_DATA6__GPIO2_6, - MX53_PAD_PATA_DATA7__GPIO2_7, - MX53_PAD_EIM_DA11__GPIO3_11, - MX53_PAD_EIM_DA12__GPIO3_12, - MX53_PAD_EIM_DA13__GPIO3_13, - MX53_PAD_EIM_DA14__GPIO3_14, - MX53_PAD_EIM_D20__GPIO3_20, - MX53_PAD_EIM_D21__GPIO3_21, - MX53_PAD_EIM_D22__GPIO3_22, - MX53_PAD_EIM_D28__GPIO3_28, - MX53_PAD_EIM_D29__GPIO3_29, - MX53_PAD_EIM_WAIT__GPIO5_0, - MX53_PAD_PATA_DA_1__GPIO7_7, - MX53_PAD_PATA_DA_2__GPIO7_8, - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - MX53_PAD_GPIO_5__I2C3_SCL, - MX53_PAD_GPIO_6__I2C3_SDA, - MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10, - MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11, - MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, - MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, - MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, - MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, - MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, - MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, - MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, - MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4, - MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5, - MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6, - MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7, - MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8, - MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9, - MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN, - MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, - MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, - MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK, - MX53_PAD_EIM_DA10__IPU_DI1_PIN15, - MX53_PAD_EIM_D23__IPU_DI1_PIN2, - MX53_PAD_EIM_EB3__IPU_DI1_PIN3, - MX53_PAD_EIM_DA15__IPU_DI1_PIN4, - MX53_PAD_EIM_CS1__IPU_DI1_PIN6, - MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0, - MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1, - MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10, - MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11, - MX53_PAD_EIM_A17__IPU_DISP1_DAT_12, - MX53_PAD_EIM_A18__IPU_DISP1_DAT_13, - MX53_PAD_EIM_A19__IPU_DISP1_DAT_14, - MX53_PAD_EIM_A20__IPU_DISP1_DAT_15, - MX53_PAD_EIM_A21__IPU_DISP1_DAT_16, - MX53_PAD_EIM_A22__IPU_DISP1_DAT_17, - MX53_PAD_EIM_A23__IPU_DISP1_DAT_18, - MX53_PAD_EIM_A24__IPU_DISP1_DAT_19, - MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2, - MX53_PAD_EIM_D31__IPU_DISP1_DAT_20, - MX53_PAD_EIM_D30__IPU_DISP1_DAT_21, - MX53_PAD_EIM_D26__IPU_DISP1_DAT_22, - MX53_PAD_EIM_D27__IPU_DISP1_DAT_23, - MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3, - MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4, - MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5, - MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6, - MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7, - MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8, - MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9, - MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, - MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, - MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, - MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, - MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, - MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, - MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, - MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, - MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, - MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, - MX53_PAD_GPIO_18__OWIRE_LINE, - MX53_PAD_GPIO_1__PWM2_PWMO, - MX53_PAD_GPIO_16__SPDIF_IN1, - MX53_PAD_GPIO_17__SPDIF_OUT1, - MX53_PAD_PATA_DMACK__UART1_RXD_MUX, - MX53_PAD_PATA_DIOW__UART1_TXD_MUX, - MX53_PAD_PATA_INTRQ__UART2_CTS, - MX53_PAD_PATA_DIOR__UART2_RTS, - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - - /* SD2 card detect */ - MX53_PAD_GPIO_4__GPIO1_4, - /* SD2 write protect */ - MX53_PAD_GPIO_2__GPIO1_2, - /* phy reset */ - MX53_PAD_PATA_DA_0__GPIO7_6, -}; - -#define GPIO_FEC_NRESET IMX_GPIO_NR(7, 6) - -#define GPIO_SD2_CD IMX_GPIO_NR(1, 4) -#define GPIO_SD2_WP IMX_GPIO_NR(1, 2) - -static struct esdhc_platform_data tqma53_sd2_data = { - .cd_gpio = GPIO_SD2_CD, - .wp_gpio = GPIO_SD2_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -static struct esdhc_platform_data tqma53_sd3_data = { - .cd_type = ESDHC_CD_PERMANENT, - .wp_type = ESDHC_WP_NONE, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - .use_dsr = 1, - .dsr_val = TQMA53_EMMC_DSR, -}; - static int tqma53_devices_init(void) { - gpio_direction_output(GPIO_FEC_NRESET, 0); - mdelay(1); - gpio_set_value(GPIO_FEC_NRESET, 1); - - imx53_iim_register_fec_ethaddr(); - imx53_add_fec(&fec_info); - imx53_add_mmc1(&tqma53_sd2_data); - imx53_add_mmc2(&tqma53_sd3_data); - - armlinux_set_architecture(MACH_TYPE_TQMA53); - - return 0; -} -device_initcall(tqma53_devices_init); - -static int tqma53_part_init(void) -{ - devfs_add_partition("disk0", 0x00000, SZ_1M, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", SZ_1M, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); - - return 0; -} -late_initcall(tqma53_part_init); + char *of_env_path = "/chosen/environment-emmc"; -static int tqma53_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(tqma53_pads, ARRAY_SIZE(tqma53_pads)); + if (!of_machine_is_compatible("tq,tqma53")) + return 0; barebox_set_model("TQ tqma53"); barebox_set_hostname("tqma53"); - imx53_add_uart1(); + if (bootsource_get() == BOOTSOURCE_MMC && + bootsource_get_instance() == 1) + of_env_path = "/chosen/environment-sd"; + + of_device_enable_path(of_env_path); + + armlinux_set_architecture(MACH_TYPE_TQMA53); return 0; } -console_initcall(tqma53_console_init); +device_initcall(tqma53_devices_init); diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg new file mode 100644 index 0000000000..50a8f27dc5 --- /dev/null +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-1gib.imxcfg @@ -0,0 +1,5 @@ +#define SETUP_512MIB_1GIB \ + wm 32 0x63fd9018 0x00011740; \ + wm 32 0x63fd9000 0xc3190000 + +#include "flash-header-tq-tqma53.h" diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg new file mode 100644 index 0000000000..4c8eed40d2 --- /dev/null +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53-512mib.imxcfg @@ -0,0 +1,5 @@ +#define SETUP_512MIB_1GIB \ + wm 32 0x63fd9018 0x00101740; \ + wm 32 0x63fd9000 0x83190000 + +#include "flash-header-tq-tqma53.h" diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h new file mode 100644 index 0000000000..4d16b0667a --- /dev/null +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h @@ -0,0 +1,61 @@ +soc imx53 +loadaddr 0x70000000 +dcdofs 0x400 + +/* IOMUX */ +wm 32 0x53fa8554 0x00300000 +wm 32 0x53fa8558 0x00300040 +wm 32 0x53fa8560 0x00300000 +wm 32 0x53fa8564 0x00300040 +wm 32 0x53fa8568 0x00300040 +wm 32 0x53fa8570 0x00300000 +wm 32 0x53fa8574 0x00300000 +wm 32 0x53fa8578 0x00300000 +wm 32 0x53fa857c 0x00300040 +wm 32 0x53fa8580 0x00300040 +wm 32 0x53fa8584 0x00300000 +wm 32 0x53fa8588 0x00300000 +wm 32 0x53fa8590 0x00300040 +wm 32 0x53fa8594 0x00300000 +wm 32 0x53fa86f0 0x00300000 +wm 32 0x53fa86f4 0x00000000 +wm 32 0x53fa86fc 0x00000000 +wm 32 0x53fa8714 0x00000000 +wm 32 0x53fa8718 0x00300000 +wm 32 0x53fa871c 0x00300000 +wm 32 0x53fa8720 0x00300000 +wm 32 0x53fa8724 0x04000000 +wm 32 0x53fa8728 0x00300000 +wm 32 0x53fa872c 0x00300000 +/* ESDCTL */ +wm 32 0x63fd9088 0x35343535 +wm 32 0x63fd9090 0x4d444c44 +wm 32 0x63fd907c 0x01370138 +wm 32 0x63fd9080 0x013b013c +wm 32 0x63fd90f8 0x00000800 + +SETUP_512MIB_1GIB + +wm 32 0x63fd900c 0x9f5152e3 +wm 32 0x63fd9010 0xb68e8a63 +wm 32 0x63fd9014 0x01ff00db +wm 32 0x63fd902c 0x000026d2 +/* Engcm12377 / errata sheet 03/2013 */ +wm 32 0x63fd9030 0x009f0e23 +wm 32 0x63fd9008 0x12273030 +wm 32 0x63fd9004 0x0002002d +wm 32 0x63fd901c 0x00008032 +wm 32 0x63fd901c 0x00008033 +wm 32 0x63fd901c 0x00028031 +wm 32 0x63fd901c 0x052080b0 +wm 32 0x63fd901c 0x04008040 +wm 32 0x63fd901c 0x0000803a +wm 32 0x63fd901c 0x0000803b +wm 32 0x63fd901c 0x00028039 +wm 32 0x63fd901c 0x05208138 +wm 32 0x63fd901c 0x04008048 +wm 32 0x63fd9020 0x00005800 +/* prevent reserved value, use default TZQ_CS */ +wm 32 0x63fd9040 0x05380003 +wm 32 0x63fd9058 0x00022227 +wm 32 0x63fd901C 0x00000000 diff --git a/arch/arm/boards/tqma53/flash_header.c b/arch/arm/boards/tqma53/flash_header.c deleted file mode 100644 index ea649af394..0000000000 --- a/arch/arm/boards/tqma53/flash_header.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <common.h> -#include <asm/byteorder.h> -#include <asm/barebox-arm-head.h> -#include <mach/imx-flash-header.h> - -void __naked __flash_header_start go(void) -{ - barebox_arm_head(); -} - -struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = { - /* IOMUX */ - { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), }, - { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), }, - /* ESDCTL */ - { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), }, - { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), }, - { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), }, - { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), }, - { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), }, -#ifdef CONFIG_MACH_TQMA53_1GB_RAM - /* sync with u-boot: add WALAT for 4 chip variant */ - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), }, -#else - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00101740), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x83190000), }, -#endif - { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), }, - { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), }, - { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), }, - { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, - /* Engcm12377 / errata sheet 03/2013 */ - { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e23), }, - { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), }, - { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), }, - { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, - /* prevent reserved value, use default TZQ_CS */ - { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x05380003), }, - { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), }, - { .addr = cpu_to_be32(0x63fd901C), .val = cpu_to_be32(0x00000000), }, -}; - -#define APP_DEST 0x70000000 - -struct imx_flash_header_v2 __flash_header_section flash_header = { - .header.tag = IVT_HEADER_TAG, - .header.length = cpu_to_be16(32), - .header.version = IVT_VERSION, - - .entry = APP_DEST + 0x1000, - .dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd), - .boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data), - .self = APP_DEST + 0x400, - - .boot_data.start = APP_DEST, - .boot_data.size = DCD_BAREBOX_SIZE, - - .dcd.header.tag = DCD_HEADER_TAG, - .dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)), - .dcd.header.version = DCD_VERSION, - - .dcd.command.tag = DCD_COMMAND_WRITE_TAG, - .dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)), - .dcd.command.param = DCD_COMMAND_WRITE_PARAM, -}; diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c index a6eaa46dd2..320a03e7b9 100644 --- a/arch/arm/boards/tqma53/lowlevel.c +++ b/arch/arm/boards/tqma53/lowlevel.c @@ -1,11 +1,65 @@ #include <common.h> +#include <debug_ll.h> +#include <io.h> #include <mach/esdctl.h> #include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> #include <mach/imx5.h> -void __naked barebox_arm_reset_vector(void) +extern char __dtb_imx53_mba53_start[]; + +static inline void setup_uart(void __iomem *base) +{ + /* Enable UART for lowlevel debugging purposes */ + writel(0x00000000, base + 0x80); + writel(0x00004027, base + 0x84); + writel(0x00000704, base + 0x88); + writel(0x00000a81, base + 0x90); + writel(0x0000002b, base + 0x9c); + writel(0x0001046a, base + 0xb0); + writel(0x0000047f, base + 0xa4); + writel(0x0000a2c1, base + 0xa8); + writel(0x00000001, base + 0x80); +} + +static void __noreturn start_imx53_tqma53_common(uint32_t fdt) +{ + if (IS_ENABLED(CONFIG_DEBUG_LL)) { + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x278); + writel(0x3, MX53_IOMUXC_BASE_ADDR + 0x27c); + setup_uart((void *)MX53_UART2_BASE_ADDR); + putc_ll('>'); + } + + imx53_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2) { + uint32_t fdt; + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xf8020000 - 8); + imx53_init_lowlevel_early(800); - imx53_barebox_entry(0); + + fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset(); + + start_imx53_tqma53_common(fdt); +} + +ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0xf8020000 - 8); + + imx53_init_lowlevel_early(800); + + fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset(); + + start_imx53_tqma53_common(fdt); } |