diff options
Diffstat (limited to 'arch/arm/boards')
107 files changed, 1581 insertions, 111 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index c5dc41526b..91f17374c9 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -123,6 +123,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ +obj-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2/ obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/ obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ @@ -156,9 +157,12 @@ obj-$(CONFIG_MACH_QEMU_VIRT64) += qemu-virt64/ obj-$(CONFIG_MACH_WARP7) += element14-warp7/ obj-$(CONFIG_MACH_VF610_TWR) += freescale-vf610-twr/ obj-$(CONFIG_MACH_XILINX_ZCU104) += xilinx-zcu104/ +obj-$(CONFIG_MACH_ZII_COMMON) += zii-common/ obj-$(CONFIG_MACH_ZII_RDU1) += zii-imx51-rdu1/ obj-$(CONFIG_MACH_ZII_RDU2) += zii-imx6q-rdu2/ obj-$(CONFIG_MACH_ZII_IMX8MQ_DEV) += zii-imx8mq-dev/ obj-$(CONFIG_MACH_ZII_VF610_DEV) += zii-vf610-dev/ obj-$(CONFIG_MACH_ZII_IMX7D_RPU2) += zii-imx7d-rpu2/ obj-$(CONFIG_MACH_WAGO_PFC_AM35XX) += wago-pfc-am35xx/ +obj-$(CONFIG_MACH_LS1046ARDB) += ls1046ardb/ +obj-$(CONFIG_MACH_TQMLS1046A) += tqmls1046a/
\ No newline at end of file diff --git a/arch/arm/boards/animeo_ip/lowlevel.c b/arch/arm/boards/animeo_ip/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/animeo_ip/lowlevel.c +++ b/arch/arm/boards/animeo_ip/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c index c76d04b905..2a93428462 100644 --- a/arch/arm/boards/archosg9/lowlevel.c +++ b/arch/arm/boards/archosg9/lowlevel.c @@ -66,9 +66,9 @@ static noinline void archosg9_init_lowlevel(void) omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); } -void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c index a5c9058552..030c3dbf04 100644 --- a/arch/arm/boards/at91rm9200ek/lowlevel.c +++ b/arch/arm/boards/at91rm9200ek/lowlevel.c @@ -21,7 +21,7 @@ void static inline access_sdram(void) writel(0x00000000, AT91_CHIPSELECT_1); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { u32 r; int i; diff --git a/arch/arm/boards/at91sam9260ek/lowlevel.c b/arch/arm/boards/at91sam9260ek/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/at91sam9260ek/lowlevel.c +++ b/arch/arm/boards/at91sam9260ek/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c index 33aa9430dc..0d7f6d6590 100644 --- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c +++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c @@ -117,7 +117,7 @@ static void __bare_init at91sam9261ek_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c index 478ff11e1d..1d83cdf0bf 100644 --- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c +++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/hardware.h> #include <mach/at91sam9_ddrsdr.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c index d5940b987a..4ccbb93557 100644 --- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c +++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9g45.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c index 47079336e6..f57e439b9e 100644 --- a/arch/arm/boards/at91sam9n12ek/lowlevel.c +++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/avnet-zedboard/lowlevel.c b/arch/arm/boards/avnet-zedboard/lowlevel.c index 7770bcb7cf..cf3c4ebd0c 100644 --- a/arch/arm/boards/avnet-zedboard/lowlevel.c +++ b/arch/arm/boards/avnet-zedboard/lowlevel.c @@ -27,7 +27,7 @@ #define PLL_DDR_LOCK (1 << 1) #define PLL_IO_LOCK (1 << 2) -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { /* open sesame */ writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK); diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c index 5f4297ea4c..744ce59eaa 100644 --- a/arch/arm/boards/canon-a1100/lowlevel.c +++ b/arch/arm/boards/canon-a1100/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/chumby_falconwing/lowlevel.c b/arch/arm/boards/chumby_falconwing/lowlevel.c index bfc76cc7d4..50bacc620f 100644 --- a/arch/arm/boards/chumby_falconwing/lowlevel.c +++ b/arch/arm/boards/chumby_falconwing/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm.h> #include <mach/imx23-regs.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_64M, NULL); diff --git a/arch/arm/boards/clep7212/lowlevel.c b/arch/arm/boards/clep7212/lowlevel.c index ac715065f1..231329025b 100644 --- a/arch/arm/boards/clep7212/lowlevel.c +++ b/arch/arm/boards/clep7212/lowlevel.c @@ -20,7 +20,7 @@ # define CLPS711X_CPU_PLL_MULT 40 #endif -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c index c94cb355e2..e4ccbdb2a3 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c +++ b/arch/arm/boards/crystalfontz-cfa10036/hwdetect.c @@ -26,6 +26,8 @@ #include <asm/armlinux.h> +#include "hwdetect.h" + enum board_type { BOARD_ID_CFA10036 = 0, BOARD_ID_CFA10037 = 1, diff --git a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c index 3c7248ef65..50dbcdc150 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c +++ b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm.h> #include <mach/imx28-regs.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2d) { arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_128M, NULL); diff --git a/arch/arm/boards/dss11/lowlevel.c b/arch/arm/boards/dss11/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/dss11/lowlevel.c +++ b/arch/arm/boards/dss11/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 7ae8a18e06..555dd44445 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -30,7 +30,7 @@ #include <asm-generic/memory_layout.h> #include <asm/system.h> -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r; register uint32_t loops = 0x20000; diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index aca77a7fbf..be78b48bd0 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -30,7 +30,7 @@ #include <asm-generic/memory_layout.h> #include <asm/system.h> -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c index ad89076329..e09f58e29c 100644 --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c @@ -3,7 +3,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); arm_setup_stack(0x20000000 - 16); diff --git a/arch/arm/boards/freescale-mx23-evk/lowlevel.c b/arch/arm/boards/freescale-mx23-evk/lowlevel.c index b260f3a7fa..13c7435cd6 100644 --- a/arch/arm/boards/freescale-mx23-evk/lowlevel.c +++ b/arch/arm/boards/freescale-mx23-evk/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm.h> #include <mach/imx23-regs.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(IMX_MEMORY_BASE, SZ_32M, NULL); diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c index 88c461da73..c929d274f2 100644 --- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-smd/lowlevel.c @@ -4,7 +4,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); diff --git a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c index 665c31b324..ccbdd13795 100644 --- a/arch/arm/boards/friendlyarm-mini6410/lowlevel.c +++ b/arch/arm/boards/friendlyarm-mini6410/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm-head.h> #include <mach/s3c-iomap.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL); diff --git a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c index 4b9ba87d70..17a7cf1591 100644 --- a/arch/arm/boards/friendlyarm-tiny210/lowlevel.c +++ b/arch/arm/boards/friendlyarm-tiny210/lowlevel.c @@ -53,7 +53,8 @@ static inline void __bare_init debug_led(int led, bool state) #define ADDR_V210_SDMMC_BASE 0xD0037488 #define ADDR_CopySDMMCtoMem 0xD0037F98 -int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block, uint16_t block_count) +static int __bare_init s5p_irom_load_mmc(void *dest, uint32_t start_block, + uint16_t block_count) { typedef uint32_t (*func_t) (int32_t, uint32_t, uint16_t, uint32_t*, int8_t); uint32_t chbase = readl(ADDR_V210_SDMMC_BASE); @@ -78,7 +79,7 @@ static __bare_init bool load_stage2(void *dest, size_t size) return s5p_irom_load_mmc(dest, 1, (size+ 511) / 512); } -void __bare_init barebox_arm_reset_vector(void) +void __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c index 665c31b324..ccbdd13795 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c +++ b/arch/arm/boards/friendlyarm-tiny6410/lowlevel.c @@ -4,7 +4,7 @@ #include <asm/barebox-arm-head.h> #include <mach/s3c-iomap.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(S3C_SDRAM_BASE, SZ_128M, NULL); diff --git a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c index e066a43dbe..39179c83d8 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c +++ b/arch/arm/boards/friendlyarm-tiny6410/tiny6410.c @@ -21,6 +21,8 @@ #include <mach/s3c-generic.h> #include <mach/iomux.h> +#include "tiny6410.h" + static const unsigned tiny6410_pin_usage[] = { /* UART0 */ GPA2_GPIO | GPIO_IN | ENABLE_PU, /* CTS not connected */ diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 66d76ae795..e84ae2c415 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -158,9 +158,8 @@ static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_ad #define UNALIGNED_ACCESS_ENABLE #define LOW_INT_LATENCY_ENABLE -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - u32 r0, r1; void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR; int i; diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 98512a976c..6c22784599 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -32,7 +32,7 @@ #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r; int i; diff --git a/arch/arm/boards/haba-knx/lowlevel.c b/arch/arm/boards/haba-knx/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/haba-knx/lowlevel.c +++ b/arch/arm/boards/haba-knx/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/highbank/lowlevel.c b/arch/arm/boards/highbank/lowlevel.c index 83f4c7ad15..6363ec96df 100644 --- a/arch/arm/boards/highbank/lowlevel.c +++ b/arch/arm/boards/highbank/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm.h> #include <asm/system_info.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x00000000, SZ_512M, NULL); diff --git a/arch/arm/boards/imx233-olinuxino/lowlevel.c b/arch/arm/boards/imx233-olinuxino/lowlevel.c index 5f36c17e52..07a2a0e293 100644 --- a/arch/arm/boards/imx233-olinuxino/lowlevel.c +++ b/arch/arm/boards/imx233-olinuxino/lowlevel.c @@ -115,7 +115,7 @@ static const uint32_t pad_setup[] = { /* Fine-tune the DRAM configuration. */ -void imx23_olinuxino_adjust_memory_params(uint32_t *dram_vals) +static void imx23_olinuxino_adjust_memory_params(uint32_t *dram_vals) { /* Enable Auto Precharge. */ dram_vals[3] |= 1 << 8; diff --git a/arch/arm/boards/karo-tx51/lowlevel.c b/arch/arm/boards/karo-tx51/lowlevel.c index ad89076329..e09f58e29c 100644 --- a/arch/arm/boards/karo-tx51/lowlevel.c +++ b/arch/arm/boards/karo-tx51/lowlevel.c @@ -3,7 +3,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); arm_setup_stack(0x20000000 - 16); diff --git a/arch/arm/boards/kindle3/kindle3.c b/arch/arm/boards/kindle3/kindle3.c index e06b3d70ce..1d966ff55a 100644 --- a/arch/arm/boards/kindle3/kindle3.c +++ b/arch/arm/boards/kindle3/kindle3.c @@ -86,7 +86,7 @@ BAREBOX_MAGICVAR_NAMED(global_atags_revision16, global.board.revision16, /* The Kindle3 Kernel expects two custom ATAGs, ATAG_REVISION16 describing * the board and ATAG_SERIAL16 to identify the individual device. */ -struct tag *kindle3_append_atags(struct tag *params) +static struct tag *kindle3_append_atags(struct tag *params) { params = setup_16char_tag(params, ATAG_SERIAL16, get_env_16char_tag("global.board.serial16")); @@ -152,6 +152,7 @@ static int kindle3_devices_init(void) } device_initcall(kindle3_devices_init); +#define FIVEWAY_PAD_CTL (PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS) static iomux_v3_cfg_t kindle3_pads[] = { /* UART1 */ MX35_PAD_RXD1__UART1_RXD_MUX, @@ -183,12 +184,11 @@ static iomux_v3_cfg_t kindle3_pads[] = { MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY, /* fiveway device: up, down, left, right, select */ - MX35_PAD_ATA_DATA14__GPIO2_27, - MX35_PAD_ATA_DATA15__GPIO2_28, - MX35_PAD_TX5_RX0__GPIO1_10, - MX35_PAD_ATA_BUFF_EN__GPIO2_30, - IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, - PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_DVS), + IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, FIVEWAY_PAD_CTL), + IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, FIVEWAY_PAD_CTL), /* Volume keys: up, down */ MX35_PAD_SCKR__GPIO1_4, diff --git a/arch/arm/boards/kindle3/lowlevel.c b/arch/arm/boards/kindle3/lowlevel.c index 58e6318f65..689767f8d6 100644 --- a/arch/arm/boards/kindle3/lowlevel.c +++ b/arch/arm/boards/kindle3/lowlevel.c @@ -31,7 +31,7 @@ #include <asm-generic/memory_layout.h> #include <asm/system.h> -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; diff --git a/arch/arm/boards/ls1046ardb/Makefile b/arch/arm/boards/ls1046ardb/Makefile new file mode 100644 index 0000000000..03ac4ecca3 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/Makefile @@ -0,0 +1,4 @@ +lwl-y += lowlevel.o +obj-y += board.o +lwl-y += start.o +bbenv-y += defaultenv-ls1046ardb diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c new file mode 100644 index 0000000000..483040957e --- /dev/null +++ b/arch/arm/boards/ls1046ardb/board.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <init.h> +#include <envfs.h> +#include <asm/memory.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <asm/system.h> + +static int rdb_mem_init(void) +{ + if (!of_machine_is_compatible("fsl,ls1046a-rdb")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, 0x80000000); + arm_add_mem_device("ram1", 0x880000000, 3ULL * SZ_2G); + + printf("Current EL: %d\n", current_el()); + + return 0; +} +mem_initcall(rdb_mem_init); + +static int rdb_postcore_init(void) +{ + if (!of_machine_is_compatible("fsl,ls1046a-rdb")) + return 0; + + defaultenv_append_directory(defaultenv_ls1046ardb); + + return 0; +} + +postcore_initcall(rdb_postcore_init); diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth4.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth4.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth4.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth5.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth5.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth5.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth6.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth6.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth6.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth7.mode b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth7.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/defaultenv-ls1046ardb/nv/dev.eth7.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c new file mode 100644 index 0000000000..6de16063a7 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/lowlevel.c @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <debug_ll.h> +#include <ddr_spd.h> +#include <platform_data/mmc-esdhc-imx.h> +#include <i2c/i2c-early.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <soc/fsl/immap_lsch2.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/syscounter.h> +#include <asm/cache.h> +#include <mach/errata.h> +#include <mach/lowlevel.h> +#include <mach/xload.h> +#include <mach/layerscape.h> + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, + {2, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, + {2, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, + {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, + {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,}, + {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,}, + {} +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + +static void ddr_board_options(memctl_options_t *popts, + struct dimm_params *pdimm, + struct fsl_ddr_controller *c) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + unsigned long ddr_freq; + + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = c->ddr_freq / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64-bit data bus */ + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR4_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR4_CDR_ODT_80ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x61; +} + +extern char __dtb_fsl_ls1046a_rdb_start[]; + +static struct spd_eeprom spd_eeprom[] = { + { + /* filled during runtime */ + }, +}; + +static struct dimm_params dimm_params[] = { + { + /* filled during runtime */ + }, +}; + +static struct fsl_ddr_controller ddrc[] = { + { + .dimm_slots_per_ctrl = ARRAY_SIZE(dimm_params), + .spd_installed_dimms = spd_eeprom, + .dimm_params = dimm_params, + .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, + .base = IOMEM(LSCH2_DDR_ADDR), + .ddr_freq = LS1046A_DDR_FREQ, + .erratum_A008511 = 1, + .erratum_A009803 = 1, + .erratum_A010165 = 1, + .erratum_A009801 = 1, + .erratum_A009942 = 1, + .chip_selects_per_ctrl = 4, + .board_options = ddr_board_options, + }, +}; + +static struct fsl_ddr_info ls1046a_info = { + .num_ctrls = ARRAY_SIZE(ddrc), + .c = ddrc, +}; + +static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize) +{ + unsigned long membase = LS1046A_DDR_SDRAM_BASE; + struct fsl_i2c *i2c; + int ret; + + if (get_pc() >= membase) { + if (memsize + membase >= 0x100000000) + memsize = 0x100000000 - membase; + + barebox_arm_entry(membase, 0x80000000 - SZ_1M * 67, + __dtb_fsl_ls1046a_rdb_start); + } + + arm_cpu_lowlevel_init(); + debug_ll_init(); + ls1046a_init_lowlevel(); + + i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR)); + ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom); + if (ret) { + pr_err("Cannot read SPD EEPROM: %d\n", ret); + goto err; + } + + memsize = fsl_ddr_sdram(&ls1046a_info); + + ls1046a_errata_post_ddr(); + + ls1046a_esdhc_start_image(memsize, 0, 0); + +err: + pr_err("Booting failed\n"); + + while (1); +} + +void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2); + +__noreturn void ls1046ardb_entry(unsigned long r0, unsigned long r1, unsigned long r2) +{ + relocate_to_current_adr(); + setup_c(); + + ls1046ardb_r_entry(r0); +} diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg new file mode 100644 index 0000000000..5478217524 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg @@ -0,0 +1,22 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg new file mode 100644 index 0000000000..735d46c9f9 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg @@ -0,0 +1,26 @@ +#QSPI clk +0957015c 40100000 +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009e +0957041c 0000009e +09570420 0000009e +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff +#Change endianness +09550000 000f400c diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg new file mode 100644 index 0000000000..ccedf87e84 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_emmc.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150012 0e000000 00000000 00000000 +11335559 40000012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003000 00000096 00000001 diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg new file mode 100644 index 0000000000..7b9be0ad3f --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_qspi.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150010 0e000000 00000000 00000000 +11335559 40005012 40025000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 diff --git a/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg new file mode 100644 index 0000000000..d3b152282f --- /dev/null +++ b/arch/arm/boards/ls1046ardb/ls1046ardb_rcw_sd.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c150012 0e000000 00000000 00000000 +11335559 40005012 60040000 c1000000 +00000000 00000000 00000000 00238800 +20124000 00003101 00000096 00000001 diff --git a/arch/arm/boards/ls1046ardb/start.S b/arch/arm/boards/ls1046ardb/start.S new file mode 100644 index 0000000000..466782b278 --- /dev/null +++ b/arch/arm/boards/ls1046ardb/start.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +#define STACK_TOP 0x10020000 + +ENTRY_PROC(start_ls1046ardb) + mov x3, #STACK_TOP + mov sp, x3 + b ls1046ardb_entry +ENTRY_PROC_END(start_ls1046ardb) diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c index 1c52b3e36b..abf9e7a98a 100644 --- a/arch/arm/boards/lubbock/lowlevel.c +++ b/arch/arm/boards/lubbock/lowlevel.c @@ -169,7 +169,7 @@ static inline void pxa2xx_dram_init(void) } } -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { unsigned long pssr = PSPR; unsigned long pc = get_pc(); diff --git a/arch/arm/boards/mainstone/lowlevel.c b/arch/arm/boards/mainstone/lowlevel.c index 89839415d4..31f9d76513 100644 --- a/arch/arm/boards/mainstone/lowlevel.c +++ b/arch/arm/boards/mainstone/lowlevel.c @@ -241,7 +241,7 @@ static inline void pxa2xx_dram_init(void) } } -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { unsigned long pssr = PSPR; unsigned long pc = get_pc(); diff --git a/arch/arm/boards/mioa701/lowlevel.c b/arch/arm/boards/mioa701/lowlevel.c index bfb8bad1cc..ee0546ea63 100644 --- a/arch/arm/boards/mioa701/lowlevel.c +++ b/arch/arm/boards/mioa701/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0xa0000000, SZ_64M, NULL); diff --git a/arch/arm/boards/module-mb7707/lowlevel.c b/arch/arm/boards/module-mb7707/lowlevel.c index 0258be6e4b..055e432c1c 100644 --- a/arch/arm/boards/module-mb7707/lowlevel.c +++ b/arch/arm/boards/module-mb7707/lowlevel.c @@ -26,7 +26,7 @@ #define MB7707_SRAM_BASE 0x40000000 #define MB7707_SRAM_SIZE SZ_128M -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c index 02b7ab3c7a..c93f76265c 100644 --- a/arch/arm/boards/mx31moboard/lowlevel.c +++ b/arch/arm/boards/mx31moboard/lowlevel.c @@ -102,7 +102,7 @@ static noinline __noreturn void mx31moboard_startup(void) } -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/nhk8815/lowlevel.c b/arch/arm/boards/nhk8815/lowlevel.c index 33a785fee0..a9ccf1fff5 100644 --- a/arch/arm/boards/nhk8815/lowlevel.c +++ b/arch/arm/boards/nhk8815/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x0, SZ_64M, NULL); diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index ffbe14836f..6451e5d414 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -89,7 +89,7 @@ static void nxp_imx8mq_evk_sram_setup(void) */ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx8mq_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c index 318bb9aeb1..fb99ea9278 100644 --- a/arch/arm/boards/omap343xdsp/lowlevel.c +++ b/arch/arm/boards/omap343xdsp/lowlevel.c @@ -548,9 +548,9 @@ static int sdp343x_board_init(void) return 0; } -void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap3_save_bootinfo(data); + omap3_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c index d8a1b9f61d..e06ece2560 100644 --- a/arch/arm/boards/omap3evm/lowlevel.c +++ b/arch/arm/boards/omap3evm/lowlevel.c @@ -161,9 +161,9 @@ static int omap3_evm_board_init(void) return 0; } -void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap3_save_bootinfo(data); + omap3_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c index 005485ba45..006fb627dd 100644 --- a/arch/arm/boards/panda/lowlevel.c +++ b/arch/arm/boards/panda/lowlevel.c @@ -79,9 +79,9 @@ static void noinline panda_init_lowlevel(void) omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1210); } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c index 1e96c0893f..09994e4492 100644 --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -77,7 +77,7 @@ static void sdram_init(int sdram) MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } -void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) +static void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt, int sdram) { unsigned long r; diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c index 27b56b1e0c..54d8eaaddf 100644 --- a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c @@ -48,7 +48,7 @@ struct sdrc_config { /********************************************************************* * init_sdram_ddr() - Init DDR controller. *********************************************************************/ -void init_sdram_ddr(void) +static void init_sdram_ddr(void) { /* reset sdrc controller */ writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG)); @@ -67,7 +67,7 @@ void init_sdram_ddr(void) /********************************************************************* * config_sdram_ddr() - Init DDR on dev board. *********************************************************************/ -void config_sdram_ddr(u8 cs, u8 cfg) +static void config_sdram_ddr(u8 cs, u8 cfg) { writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs)); @@ -252,9 +252,9 @@ static int pcaal1_board_init(void) return 0; } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap3_save_bootinfo(data); + omap3_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c index 170ca6896b..c49c4ca841 100644 --- a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c @@ -89,9 +89,9 @@ static noinline void pcaaxl2_init_lowlevel(void) sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c index a3ba1c05dd..19296e5dac 100644 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -31,7 +31,7 @@ #define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r; volatile int v; diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index 5e2f335efa..6bfa0acce3 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -35,7 +35,7 @@ #define CCM_PDR0_399 0x00011000 #define CCM_PDR0_532 0x00001000 -void __bare_init __naked barebox_arm_reset_vector(void) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c index 02297adb95..6511dae9d4 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -139,9 +139,9 @@ static void noinline pcm049_init_lowlevel(void) sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ } -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { - omap4_save_bootinfo(data); + omap4_save_bootinfo((void *)r0); arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index cfee13f3e7..e42e7a6fcc 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -83,7 +83,7 @@ static void phytec_imx8mq_som_sram_setup(void) */ ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) { - arm_cpu_lowlevel_init(); + imx8mq_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c index 0ab34b0db6..7127d39943 100644 --- a/arch/arm/boards/pm9261/lowlevel_init.c +++ b/arch/arm/boards/pm9261/lowlevel_init.c @@ -111,7 +111,7 @@ static void __bare_init pm9261_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c index 32850b2981..daeb183831 100644 --- a/arch/arm/boards/pm9263/lowlevel_init.c +++ b/arch/arm/boards/pm9263/lowlevel_init.c @@ -132,7 +132,7 @@ static void __bare_init pm9263_board_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c index 67454bde26..12cf950685 100644 --- a/arch/arm/boards/pm9g45/lowlevel.c +++ b/arch/arm/boards/pm9g45/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/qemu-virt64/lowlevel.c b/arch/arm/boards/qemu-virt64/lowlevel.c index a60c4b0426..629e2e9f6e 100644 --- a/arch/arm/boards/qemu-virt64/lowlevel.c +++ b/arch/arm/boards/qemu-virt64/lowlevel.c @@ -10,7 +10,7 @@ #include <asm/barebox-arm.h> #include <asm/system_info.h> -void barebox_arm_reset_vector(void) +void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); arm_setup_stack(0x40000000 + SZ_2G - SZ_16K); diff --git a/arch/arm/boards/qil-a926x/lowlevel.c b/arch/arm/boards/qil-a926x/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/qil-a926x/lowlevel.c +++ b/arch/arm/boards/qil-a926x/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index 60cea7f8e9..bc877f853a 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -197,6 +197,8 @@ const struct rpi_model rpi_models_new_scheme[] = { RPI_MODEL(BCM2835_BOARD_REV_ZERO_W, "Zero W", rpi_b_plus_init), RPI_MODEL(BCM2837B0_BOARD_REV_3B_PLUS, "Model 3 B+", rpi_b_plus_init ), RPI_MODEL(BCM2837B0_BOARD_REV_3A_PLUS, "Nodel 3 A+", rpi_b_plus_init), + RPI_MODEL(0xf, "Unknown model", NULL), + RPI_MODEL(BCM2837B0_BOARD_REV_CM3_PLUS, "Compute Module 3+", NULL), }; static int rpi_board_rev = 0; diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ b/arch/arm/boards/sama5d3xek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d4_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c index b791f2a03c..0e25270142 100644 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ b/arch/arm/boards/sama5d4ek/lowlevel.c @@ -13,7 +13,7 @@ #include <mach/at91sam9_ddrsdr.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/stm32mp157c-dk2/Makefile b/arch/arm/boards/stm32mp157c-dk2/Makefile new file mode 100644 index 0000000000..092c31d6b2 --- /dev/null +++ b/arch/arm/boards/stm32mp157c-dk2/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c new file mode 100644 index 0000000000..cbfe21db6a --- /dev/null +++ b/arch/arm/boards/stm32mp157c-dk2/board.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <linux/sizes.h> +#include <init.h> +#include <asm/memory.h> +#include <mach/stm32.h> + +static int dk2_postcore_init(void) +{ + if (!of_machine_is_compatible("st,stm32mp157c-dk2")) + return 0; + + arm_add_mem_device("ram0", STM32_DDR_BASE, SZ_512M); + + return 0; +} +mem_initcall(dk2_postcore_init); diff --git a/arch/arm/boards/stm32mp157c-dk2/lowlevel.c b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c new file mode 100644 index 0000000000..b8e5959bef --- /dev/null +++ b/arch/arm/boards/stm32mp157c-dk2/lowlevel.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <mach/stm32.h> +#include <debug_ll.h> + +extern char __dtb_stm32mp157c_dk2_start[]; + +ENTRY_FUNCTION(start_stm32mp157c_dk2, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_stm32mp157c_dk2_start + get_runtime_offset(); + + barebox_arm_entry(STM32_DDR_BASE, SZ_512M, fdt); +} diff --git a/arch/arm/boards/telit-evk-pro3/lowlevel.c b/arch/arm/boards/telit-evk-pro3/lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/telit-evk-pro3/lowlevel.c +++ b/arch/arm/boards/telit-evk-pro3/lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c index 8566d27a0a..868df9d6c8 100644 --- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c @@ -118,7 +118,7 @@ static void __bare_init tny_a9263_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/tqmls1046a/Makefile b/arch/arm/boards/tqmls1046a/Makefile new file mode 100644 index 0000000000..851a5dcb3d --- /dev/null +++ b/arch/arm/boards/tqmls1046a/Makefile @@ -0,0 +1,3 @@ +lwl-y += lowlevel.o start.o +obj-y += board.o +bbenv-y += defaultenv-tqmls1046a diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c new file mode 100644 index 0000000000..5d6d5ad62c --- /dev/null +++ b/arch/arm/boards/tqmls1046a/board.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <init.h> +#include <envfs.h> +#include <asm/memory.h> +#include <linux/sizes.h> +#include <linux/clk.h> +#include <linux/clkdev.h> + +static int tqmls1046a_mem_init(void) +{ + if (!of_machine_is_compatible("tqc,tqmls1046a")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, SZ_2G); + + return 0; +} +mem_initcall(tqmls1046a_mem_init); + +static int tqmls1046a_postcore_init(void) +{ + if (!of_machine_is_compatible("tqc,tqmls1046a")) + return 0; + + defaultenv_append_directory(defaultenv_tqmls1046a); + + return 0; +} + +postcore_initcall(tqmls1046a_postcore_init); diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth4.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth4.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth4.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth5.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth5.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth5.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth6.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth6.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth6.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth7.mode b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth7.mode new file mode 100644 index 0000000000..7a68b11da8 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/defaultenv-tqmls1046a/nv/dev.eth7.mode @@ -0,0 +1 @@ +disabled diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c new file mode 100644 index 0000000000..044d6a418d --- /dev/null +++ b/arch/arm/boards/tqmls1046a/lowlevel.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <debug_ll.h> +#include <platform_data/mmc-esdhc-imx.h> +#include <soc/fsl/fsl_ddr_sdram.h> +#include <soc/fsl/immap_lsch2.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <asm/syscounter.h> +#include <asm/cache.h> +#include <mach/errata.h> +#include <mach/lowlevel.h> +#include <mach/xload.h> +#include <mach/layerscape.h> + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {1, 2100, 0, 8, 9, 0x09080806, 0x07060606,}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +static void ddr_board_options(memctl_options_t *popts, + struct dimm_params *pdimm, + struct fsl_ddr_controller *c) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + unsigned long ddr_freq; + + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* + * Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = c->ddr_freq / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + popts->data_bus_width = 0; /* 64-bit data bus */ + popts->bstopre = 0; /* enable auto precharge */ + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR4_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR4_CDR_ODT_60ohm) | + DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; + + /* optimize cpo for erratum A-009942 */ + popts->cpo_sample = 0x61; +} + +static struct dimm_params dimm_params[] = { + { + .n_ranks = 1, + .rank_density = 2147483648u, + .capacity = 2147483648u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .bank_addr_bits = 2, + .bank_group_bits = 0, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 833, + .tckmax_ps = 1900, + .caslat_x = 0x000DFA00, // + .taa_ps = 13320, + .trcd_ps = 13320, + .trp_ps = 13320, + .tras_ps = 32000, + .trc_ps = 45320, + .trfc1_ps = 260000, + .trfc2_ps = 160000, + .trfc4_ps = 110000, + .tfaw_ps = 21000, + .trrds_ps = 3300, + .trrdl_ps = 4900, + .tccdl_ps = 5000, + .trfc_slr_ps = 3500000, + .refresh_rate_ps = 7800000, + }, +}; + +static struct fsl_ddr_controller ddrc[] = { + { + .dimm_slots_per_ctrl = ARRAY_SIZE(dimm_params), + .dimm_params = dimm_params, + .memctl_opts.ddrtype = SDRAM_TYPE_DDR4, + .base = IOMEM(LSCH2_DDR_ADDR), + .ddr_freq = LS1046A_DDR_FREQ, + .erratum_A008511 = 1, + .erratum_A009803 = 1, + .erratum_A010165 = 1, + .erratum_A009801 = 1, + .erratum_A009942 = 1, + .chip_selects_per_ctrl = 4, + .board_options = ddr_board_options, + }, +}; + +static struct fsl_ddr_info ls1046a_info = { + .num_ctrls = ARRAY_SIZE(ddrc), + .c = ddrc, +}; + +extern char __dtb_fsl_tqmls1046a_mbls10xxa_start[]; + +static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize) +{ + unsigned long membase = LS1046A_DDR_SDRAM_BASE; + + if (get_pc() >= membase) { + if (memsize + membase >= 0x100000000) + memsize = 0x100000000 - membase; + + barebox_arm_entry(membase, 0x80000000, + __dtb_fsl_tqmls1046a_mbls10xxa_start); + } + + arm_cpu_lowlevel_init(); + debug_ll_init(); + ls1046a_init_lowlevel(); + + memsize = fsl_ddr_sdram(&ls1046a_info); + + ls1046a_errata_post_ddr(); + + ls1046a_esdhc_start_image(memsize, 0, 0); + + pr_err("Booting failed\n"); + + while (1); +} + +void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2); + +__noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned long r2) +{ + relocate_to_current_adr(); + setup_c(); + + tqmls1046a_r_entry(r0); +} diff --git a/arch/arm/boards/tqmls1046a/start.S b/arch/arm/boards/tqmls1046a/start.S new file mode 100644 index 0000000000..12b785af54 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/start.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +#define STACK_TOP 0x10020000 + +ENTRY_PROC(start_tqmls1046a) + mov x3, #STACK_TOP + mov sp, x3 + b tqmls1046a_entry +ENTRY_PROC_END(start_tqmls1046a) + diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg new file mode 100644 index 0000000000..32865ca2d0 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg @@ -0,0 +1,33 @@ +#Configure QSPI clock +0957015c 40100000 +#Configure Scratch register +09570600 00000000 +09570604 40010000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009c +0957041c 0000009c +09570420 0000009c +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link (errata A-010477) +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#PEX gen3 equalization preset values (errata A-008851) +894008bc 01000000 +89400154 47474747 +89400158 47474747 +894008bc 00000000 +895008bc 01000000 +89500154 47474747 +89500158 47474747 +895008bc 00000000 +896008bc 01000000 +89600154 47474747 +89600158 47474747 +896008bc 00000000 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg new file mode 100644 index 0000000000..7ac1398123 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg @@ -0,0 +1,35 @@ +#Configure Scratch register +09570600 00000000 +09570604 10000000 +#Disable CCI barrier tranaction +09570178 0000e010 +09180000 00000008 +#USB PHY frequency sel +09570418 0000009c +0957041c 0000009c +09570420 0000009c +#Serdes SATA +09eb1300 80104e20 +09eb08dc 00502880 +#PEX gen3 link (errata A-010477) +09570158 00000300 +89400890 01048000 +89500890 01048000 +89600890 01048000 +#PEX gen3 equalization preset values (errata A-008851) +894008bc 01000000 +89400154 47474747 +89400158 47474747 +894008bc 00000000 +895008bc 01000000 +89500154 47474747 +89500158 47474747 +895008bc 00000000 +896008bc 01000000 +89600154 47474747 +89600158 47474747 +896008bc 00000000 +#Alt base register +09570158 00001000 +#flush PBI data +096100c0 000fffff diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg new file mode 100644 index 0000000000..6c72d001c3 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg @@ -0,0 +1,84 @@ +# RCW values +# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] +# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] +# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00] +# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100] +# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00] +# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000] +# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00] +# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110] +# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000] +# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011] +# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001] +# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11] +# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11] +# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00] +# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00] +# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01] +# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01] +# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00] +# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0] +# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0] +# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10] +# 192:195 - PBI_SRC : 6 [0x6 / 0b0110] +# 201:201 - BOOT_HO : 0 [0x0 / 0b0] +# 202:202 - SB_EN : 0 [0x0 / 0b0] +# 203:211 - IFC_MODE : 64 [0x40 / 0b001000000] +# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110] +# 230:231 - DRAM_LAT : 1 [0x1 / 0b01] +# 232:232 - DDR_RATE : 0 [0x0 / 0b0] +# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0] +# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0] +# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0] +# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0] +# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0] +# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000] +# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000] +# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000] +# 354:356 - UART_EXT : 0 [0x0 / 0b000] +# 357:359 - IRQ_EXT : 0 [0x0 / 0b000] +# 360:362 - SPI_EXT : 0 [0x0 / 0b000] +# 363:365 - SDHC_EXT : 0 [0x0 / 0b000] +# 366:368 - UART_BASE : 5 [0x5 / 0b101] +# 369:369 - ASLEEP : 0 [0x0 / 0b0] +# 370:370 - RTC : 0 [0x0 / 0b0] +# 371:371 - SDHC_BASE : 0 [0x0 / 0b0] +# 372:372 - IRQ_OUT : 1 [0x1 / 0b1] +# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000] +# 382:383 - SPI_BASE : 0 [0x0 / 0b00] +# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001] +# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000] +# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000] +# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001] +# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0] +# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0] +# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00] +# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0] +# 416:418 - EC1 : 0 [0x0 / 0b000] +# 419:421 - EC2 : 0 [0x0 / 0b000] +# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01] +# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0] +# 425:425 - EM1 : 0 [0x0 / 0b0] +# 426:426 - EM2 : 0 [0x0 / 0b0] +# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1] +# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0] +# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0] +# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0] +# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01] +# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10] +# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1] +# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00] +# 441:443 - IIC2_BASE : 0 [0x0 / 0b000] +# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0] +# 445:447 - IIC2_EXT : 2 [0x2 / 0b010] +# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000] +# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001] + + +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c140010 0e000000 00000000 00000000 +33335559 f0005002 60040000 c1000000 +00000000 00000000 00000000 00028800 +20004000 01103202 00000096 00000001 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg new file mode 100644 index 0000000000..395c75c7d0 --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg @@ -0,0 +1,84 @@ +# RCW values +# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] +# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] +# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00] +# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100] +# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00] +# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000] +# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00] +# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110] +# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000] +# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011] +# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001] +# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11] +# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11] +# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00] +# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00] +# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01] +# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01] +# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00] +# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0] +# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0] +# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10] +# 192:195 - PBI_SRC : 4 [0x4 / 0b0100] +# 201:201 - BOOT_HO : 0 [0x0 / 0b0] +# 202:202 - SB_EN : 0 [0x0 / 0b0] +# 203:211 - IFC_MODE : 37 [0x25 / 0b000100101] +# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110] +# 230:231 - DRAM_LAT : 1 [0x1 / 0b01] +# 232:232 - DDR_RATE : 0 [0x0 / 0b0] +# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0] +# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0] +# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0] +# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0] +# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0] +# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000] +# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000] +# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000] +# 354:356 - UART_EXT : 0 [0x0 / 0b000] +# 357:359 - IRQ_EXT : 0 [0x0 / 0b000] +# 360:362 - SPI_EXT : 0 [0x0 / 0b000] +# 363:365 - SDHC_EXT : 0 [0x0 / 0b000] +# 366:368 - UART_BASE : 5 [0x5 / 0b101] +# 369:369 - ASLEEP : 0 [0x0 / 0b0] +# 370:370 - RTC : 0 [0x0 / 0b0] +# 371:371 - SDHC_BASE : 0 [0x0 / 0b0] +# 372:372 - IRQ_OUT : 1 [0x1 / 0b1] +# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000] +# 382:383 - SPI_BASE : 0 [0x0 / 0b00] +# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001] +# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000] +# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000] +# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001] +# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0] +# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0] +# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00] +# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0] +# 416:418 - EC1 : 0 [0x0 / 0b000] +# 419:421 - EC2 : 0 [0x0 / 0b000] +# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01] +# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0] +# 425:425 - EM1 : 0 [0x0 / 0b0] +# 426:426 - EM2 : 0 [0x0 / 0b0] +# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1] +# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0] +# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0] +# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0] +# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01] +# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10] +# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1] +# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00] +# 441:443 - IIC2_BASE : 0 [0x0 / 0b000] +# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0] +# 445:447 - IIC2_EXT : 2 [0x2 / 0b010] +# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000] +# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001] + + +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c140010 0e000000 00000000 00000000 +33335559 f0005002 40025000 c1000000 +00000000 00000000 00000000 00028800 +20004000 01103202 00000096 00000001 diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg new file mode 100644 index 0000000000..4ef6d576ed --- /dev/null +++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg @@ -0,0 +1,84 @@ +# RCW values +# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00] +# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110] +# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00] +# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100] +# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00] +# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000] +# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00] +# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110] +# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000] +# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011] +# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001] +# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11] +# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11] +# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00] +# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00] +# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01] +# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01] +# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00] +# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0] +# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0] +# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10] +# 192:195 - PBI_SRC : 6 [0x6 / 0b0110] +# 201:201 - BOOT_HO : 0 [0x0 / 0b0] +# 202:202 - SB_EN : 0 [0x0 / 0b0] +# 203:211 - IFC_MODE : 64 [0x40 / 0b001000000] +# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110] +# 230:231 - DRAM_LAT : 1 [0x1 / 0b01] +# 232:232 - DDR_RATE : 0 [0x0 / 0b0] +# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0] +# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0] +# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0] +# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0] +# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0] +# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000] +# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000] +# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000] +# 354:356 - UART_EXT : 0 [0x0 / 0b000] +# 357:359 - IRQ_EXT : 0 [0x0 / 0b000] +# 360:362 - SPI_EXT : 0 [0x0 / 0b000] +# 363:365 - SDHC_EXT : 0 [0x0 / 0b000] +# 366:368 - UART_BASE : 5 [0x5 / 0b101] +# 369:369 - ASLEEP : 0 [0x0 / 0b0] +# 370:370 - RTC : 0 [0x0 / 0b0] +# 371:371 - SDHC_BASE : 0 [0x0 / 0b0] +# 372:372 - IRQ_OUT : 1 [0x1 / 0b1] +# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000] +# 382:383 - SPI_BASE : 0 [0x0 / 0b00] +# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001] +# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000] +# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000] +# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001] +# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0] +# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0] +# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00] +# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0] +# 416:418 - EC1 : 0 [0x0 / 0b000] +# 419:421 - EC2 : 0 [0x0 / 0b000] +# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01] +# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0] +# 425:425 - EM1 : 0 [0x0 / 0b0] +# 426:426 - EM2 : 0 [0x0 / 0b0] +# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1] +# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0] +# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0] +# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0] +# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01] +# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10] +# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1] +# 439:440 - EVDD_VSEL : 2 [0x2 / 0b10] +# 441:443 - IIC2_BASE : 0 [0x0 / 0b000] +# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0] +# 445:447 - IIC2_EXT : 1 [0x1 / 0b001] +# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000] +# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001] + + +#PBL preamble and RCW header +aa55aa55 01ee0100 +# RCW +0c140010 0e000000 00000000 00000000 +33335559 f0005002 60040000 c1000000 +00000000 00000000 00000000 00028800 +20004000 01103301 00000096 00000001 diff --git a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c index b16ef31bf0..25352672d7 100644 --- a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c @@ -14,7 +14,7 @@ #include <mach/at91sam9260.h> #include <mach/hardware.h> -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c index a7dd2b2ada..b362fcf7d4 100644 --- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c @@ -122,7 +122,7 @@ static void __bare_init usb_a9263_init(void) NULL); } -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/versatile/lowlevel.c b/arch/arm/boards/versatile/lowlevel.c index 33a785fee0..a9ccf1fff5 100644 --- a/arch/arm/boards/versatile/lowlevel.c +++ b/arch/arm/boards/versatile/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x0, SZ_64M, NULL); diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c index 8ec3d04fef..264ebee893 100644 --- a/arch/arm/boards/virt2real/lowlevel.c +++ b/arch/arm/boards/virt2real/lowlevel.c @@ -26,7 +26,7 @@ #define VIRT2REAL_SRAM_BASE 0x82000000 #define VIRT2REAL_SRAM_SIZE SZ_16M -void __naked __bare_init barebox_arm_reset_vector(void) +void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/boards/zii-common/Makefile b/arch/arm/boards/zii-common/Makefile new file mode 100644 index 0000000000..fcc5cdf97d --- /dev/null +++ b/arch/arm/boards/zii-common/Makefile @@ -0,0 +1 @@ +obj-y += board.o switch-cmd.o pn-fixup.o diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c new file mode 100644 index 0000000000..20ec64d2d4 --- /dev/null +++ b/arch/arm/boards/zii-common/board.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2019 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <globalvar.h> +#include <init.h> +#include <fs.h> + +static int rdu_networkconfig(void) +{ + static char *rdu_netconfig; + struct device_d *sp_dev; + + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2") && + !of_machine_is_compatible("zii,imx51-rdu1")) + return 0; + + sp_dev = get_device_by_name("sp"); + if (!sp_dev) { + pr_warn("no sp device found, network config not available!\n"); + return -ENODEV; + } + + rdu_netconfig = basprintf("ip=%s:::%s::eth0:", + dev_get_param(sp_dev, "ipaddr"), + dev_get_param(sp_dev, "netmask")); + + globalvar_add_simple_string("linux.bootargs.rdu_network", + &rdu_netconfig); + + return 0; +} +late_initcall(rdu_networkconfig); + +#define I210_CFGWORD_PCIID_157B 0x157b1a11 +static int rdu_i210_invm(void) +{ + int fd; + u32 val; + + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2") && + !of_machine_is_compatible("zii,imx8mq-ultra")) + return 0; + + fd = open("/dev/e1000-invm0", O_RDWR); + if (fd < 0) { + pr_err("could not open e1000 iNVM device!\n"); + return fd; + } + + pread(fd, &val, sizeof(val), 0); + if (val == I210_CFGWORD_PCIID_157B) { + pr_debug("i210 already programmed correctly\n"); + return 0; + } + + val = I210_CFGWORD_PCIID_157B; + pwrite(fd, &val, sizeof(val), 0); + + return 0; +} +late_initcall(rdu_i210_invm); diff --git a/arch/arm/boards/zii-common/pn-fixup.c b/arch/arm/boards/zii-common/pn-fixup.c new file mode 100644 index 0000000000..a665199917 --- /dev/null +++ b/arch/arm/boards/zii-common/pn-fixup.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2019 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <linux/nvmem-consumer.h> + +#include "pn-fixup.h" + +char *zii_read_part_number(const char *cell_name, size_t cell_size) +{ + struct device_node *np; + + np = of_find_node_by_name(NULL, "device-info"); + if (!np) { + pr_warn("No device information found\n"); + return ERR_PTR(-ENOENT); + } + + return nvmem_cell_get_and_read(np, cell_name, cell_size); +} diff --git a/arch/arm/boards/zii-common/pn-fixup.h b/arch/arm/boards/zii-common/pn-fixup.h new file mode 100644 index 0000000000..39b848bd00 --- /dev/null +++ b/arch/arm/boards/zii-common/pn-fixup.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2019 Zodiac Inflight Innovation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ZII_PN_FIXUP__ +#define __ZII_PN_FIXUP__ + +struct zii_pn_fixup { + const char *pn; + void (*callback) (const struct zii_pn_fixup *fixup); +}; + +char *zii_read_part_number(const char *, size_t); +/** + * __zii_process_fixups - Process array of ZII part number based fixups + * + * @__fixups: Array of part number base fixups + * @__cell_name: Name of the NVMEM cell containing the part number + * @__cell_size: Size of the NVMEM cell containing the part number + * + * NOTE: Keeping this code as a marcro allows us to avoid restricting + * the type of __fixups to an array of struct zii_pn_fixup. This is + * really convenient becuase it allows us to do things like + * + * struct zii_foo_fixup { + * struct zii_pn_fixup parent; + * type1 custom_field_1 + * type2 custom_field_2 + * ... + * }; + * + * ... + * + * const struct zii_foo_fixup foo_fixups[] = { + * { fixup1 }, + * { fixup2 }, + * { fixup3 }, + * }; + * + * ... + * + * __zii_process_fixups(foo_fixups, "blah", BLAH_LENGTH); + * + * which allows us to have the most compact definition of array of + * fixups + */ +#define __zii_process_fixups(__fixups, __cell_name, __cell_size) \ + do { \ + char *__pn = zii_read_part_number(__cell_name, \ + __cell_size); \ + const struct zii_pn_fixup *__fixup; \ + unsigned int __i; \ + bool __match_found = false; \ + \ + if (WARN_ON(IS_ERR(__pn))) \ + break; \ + \ + for (__i = 0; __i < ARRAY_SIZE(__fixups); __i++) { \ + __fixup = \ + (const struct zii_pn_fixup *) &__fixups[__i]; \ + \ + if (strstr(__pn, __fixup->pn)) { \ + pr_debug("%s->%pS\n", __func__, \ + __fixup->callback); \ + __match_found = true; \ + __fixup->callback(__fixup); \ + } \ + } \ + if (!__match_found) \ + pr_err("No config fixups found for P/N %s!\n", __pn); \ + free(__pn); \ + } while (0) + +#define DDS_PART_NUMBER_SIZE 15 +#define LRU_PART_NUMBER_SIZE 15 + +#define zii_process_dds_fixups(_fixups) \ + __zii_process_fixups(_fixups, "dds-part-number", DDS_PART_NUMBER_SIZE) + +#define zii_process_lru_fixups(_fixups) \ + __zii_process_fixups(_fixups, "lru-part-number", LRU_PART_NUMBER_SIZE) + +#endif /* __ZII_PN_FIXUP__ */ diff --git a/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c b/arch/arm/boards/zii-common/switch-cmd.c index bdba46fb36..30438053a1 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/switch-cmd.c +++ b/arch/arm/boards/zii-common/switch-cmd.c @@ -11,19 +11,16 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <common.h> #include <command.h> +#include <common.h> #include <i2c/i2c.h> +#include <linux/mfd/rave-sp.h> -static int do_rave_switch_reset(int argc, char *argv[]) +static int do_rdu2_switch_reset(void) { struct i2c_client client; u8 reg; - if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && - !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) - return -ENODEV; - client.adapter = i2c_get_adapter(1); if (!client.adapter) return -ENODEV; @@ -42,8 +39,35 @@ static int do_rave_switch_reset(int argc, char *argv[]) return 0; } +static int do_rdu1_switch_reset(void) +{ + struct device_d *sp_dev = get_device_by_name("sp"); + struct rave_sp *sp = sp_dev->priv; + u8 cmd[] = { + [0] = RAVE_SP_CMD_RESET_ETH_SWITCH, + [1] = 0 + }; + + if (IS_ENABLED(CONFIG_RAVE_SP_CORE)) + return rave_sp_exec(sp, cmd, sizeof(cmd), NULL, 0); + else + return -ENODEV; +} + +static int do_rave_switch_reset(int argc, char *argv[]) +{ + if (of_machine_is_compatible("zii,imx6q-zii-rdu2") || + of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + return do_rdu2_switch_reset(); + + if (of_machine_is_compatible("zii,imx51-rdu1")) + return do_rdu1_switch_reset(); + + return -ENODEV; +} + BAREBOX_CMD_START(rave_reset_switch) .cmd = do_rave_switch_reset, - BAREBOX_CMD_DESC("reset ethernet switch on RDU2") + BAREBOX_CMD_DESC("reset ethernet switch on RDU") BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP) BAREBOX_CMD_END diff --git a/arch/arm/boards/zii-imx6q-rdu2/Makefile b/arch/arm/boards/zii-imx6q-rdu2/Makefile index 10dfba3a3c..c6285362f2 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/Makefile +++ b/arch/arm/boards/zii-imx6q-rdu2/Makefile @@ -1,3 +1,3 @@ -obj-y += board.o switch-cmd.o +obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-rdu2 diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c index 6352f49c5a..6adb0b1c6f 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/board.c +++ b/arch/arm/boards/zii-imx6q-rdu2/board.c @@ -23,6 +23,30 @@ #include <mach/imx6.h> #include <net.h> #include <linux/nvmem-consumer.h> +#include "../zii-common/pn-fixup.h" + +enum rdu2_lcd_interface_type { + IT_SINGLE_LVDS, + IT_DUAL_LVDS, + IT_EDP +}; + +enum rdu2_lvds_busformat { + BF_NONE, + BF_JEIDA, + BF_SPWG +}; + +#define RDU2_LRU_FLAG_EGALAX BIT(0) +#define RDU2_LRU_FLAG_NO_FEC BIT(1) + +struct rdu2_lru_fixup { + struct zii_pn_fixup fixup; + unsigned int flags; + enum rdu2_lcd_interface_type type; + enum rdu2_lvds_busformat bus_format; + const char *compatible; +}; #define RDU2_DAC1_RESET IMX_GPIO_NR(1, 0) #define RDU2_DAC2_RESET IMX_GPIO_NR(1, 2) @@ -190,31 +214,254 @@ static int rdu2_ethernet_init(void) } late_initcall(rdu2_ethernet_init); -#define I210_CFGWORD_PCIID_157B 0x157b1a11 -static int rdu2_i210_invm(void) +static int rdu2_fixup_egalax_ts(struct device_node *root, void *context) { - int fd; - u32 val; + struct device_node *np; - if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && - !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) - return 0; + /* + * The 32" unit has a EETI eGalax touchscreen instead of the + * Synaptics RMI4 found on other units. + */ + pr_info("Enabling eGalax touchscreen instead of RMI4\n"); - fd = open("/dev/e1000-invm0", O_RDWR); - if (fd < 0) { - pr_err("could not open e1000 iNVM device!\n"); - return fd; + np = of_find_compatible_node(root, NULL, "syna,rmi4-i2c"); + if (!np) + return -ENODEV; + + of_device_disable(np); + + np = of_find_compatible_node(root, NULL, "eeti,exc3000"); + if (!np) + return -ENODEV; + + of_device_enable(np); + of_property_write_u32(np->parent, "clock-frequency", 200000); + + + return 0; +} + +static int rdu2_fixup_dsa(struct device_node *root, void *context) +{ + struct device_node *switch_np, *np; + phandle i210_handle; + + /* + * The 12.1" unit has no FEC connection, so we need to rewrite + * the i210 port into the CPU port and delete the FEC port, + * which is part of the common setup. + */ + pr_info("Rewriting i210 switch port into CPU port\n"); + + switch_np = of_find_compatible_node(root, NULL, "marvell,mv88e6085"); + if (!switch_np) + return -ENODEV; + + np = of_find_node_by_name(switch_np, "port@2"); + if (!np) + return -ENODEV; + + of_delete_node(np); + + np = of_find_node_by_name(root, "i210@0"); + if (!np) + return -ENODEV; + + i210_handle = of_node_create_phandle(np); + + np = of_find_node_by_name(switch_np, "port@0"); + if (!np) + return -ENODEV; + + of_property_write_u32(np, "ethernet", i210_handle); + of_property_write_string(np, "label", "cpu"); + + return 0; +} + +static int rdu2_fixup_edp(struct device_node *root) +{ + const bool kernel_fixup = root != NULL; + struct device_node *np; + + if (kernel_fixup) { + /* + * Kernel DT fixup needs this additional step + */ + pr_info("Found eDP display, enabling parallel output " + "and eDP bridge.\n"); + np = of_find_compatible_node(root, NULL, + "fsl,imx-parallel-display"); + if (!np) + return -ENODEV; + + of_device_enable(np); } - pread(fd, &val, sizeof(val), 0); - if (val == I210_CFGWORD_PCIID_157B) { - pr_debug("i210 already programmed correctly\n"); - return 0; + np = of_find_compatible_node(root, NULL, "toshiba,tc358767"); + if (!np) + return -ENODEV; + + of_device_enable(np); + + return 0; +} + +static int rdu2_fixup_lvds(struct device_node *root, + const struct rdu2_lru_fixup *fixup) +{ + const bool kernel_fixup = root != NULL; + struct device_node *np; + + /* + * LVDS panels need the correct compatible + */ + pr_info("Found LVDS display, enabling %s channel LDB and " + "panel with compatible \"%s\".\n", + fixup->type == IT_DUAL_LVDS ? "dual" : "single", + fixup->compatible); + /* + * LVDS panels need the correct timings + */ + np = of_find_node_by_name(root, "panel"); + if (!np) + return -ENODEV; + + if (kernel_fixup) { + of_device_enable(np); + of_property_write_string(np, "compatible", fixup->compatible); + } else { + struct device_node *child, *tmp; + + of_device_enable_and_register(np); + /* + * Delete all mode entries, which aren't suited for the + * current display + */ + np = of_find_node_by_name(np, "display-timings"); + if (!np) + return -ENODEV; + + for_each_child_of_node_safe(np, tmp, child) { + if (!of_device_is_compatible(child, + fixup->compatible)) + of_delete_node(child); + } } + /* + * enable LDB channel 0 and set correct interface mode + */ + np = of_find_compatible_node(root, NULL, "fsl,imx6q-ldb"); + if (!np) + return -ENODEV; + + if (kernel_fixup) + of_device_enable(np); + else + of_device_enable_and_register(np); + + if (fixup->type == IT_DUAL_LVDS) + of_set_property(np, "fsl,dual-channel", NULL, 0, 1); + + np = of_find_node_by_name(np, "lvds-channel@0"); + if (!np) + return -ENODEV; + + of_device_enable(np); + + if (!kernel_fixup) { + of_property_write_string(np, "fsl,data-mapping", + fixup->bus_format == BF_SPWG ? + "spwg" : "jeida"); + } + + return 0; +} + +static int rdu2_fixup_display(struct device_node *root, void *context) +{ + const struct rdu2_lru_fixup *fixup = context; + /* + * If the panel is eDP, just enable the parallel output and + * eDP bridge + */ + if (fixup->type == IT_EDP) + return rdu2_fixup_edp(root); + + return rdu2_fixup_lvds(root, context); +} + +static void rdu2_lru_fixup(const struct zii_pn_fixup *context) +{ + const struct rdu2_lru_fixup *fixup = + container_of(context, struct rdu2_lru_fixup, fixup); + + WARN_ON(rdu2_fixup_display(NULL, (void *)context)); + of_register_fixup(rdu2_fixup_display, (void *)context); + + if (fixup->flags & RDU2_LRU_FLAG_EGALAX) + of_register_fixup(rdu2_fixup_egalax_ts, NULL); + + if (fixup->flags & RDU2_LRU_FLAG_NO_FEC) + of_register_fixup(rdu2_fixup_dsa, NULL); +} + +#define RDU2_LRU_FIXUP(__pn, __flags, __panel) \ + { \ + { __pn, rdu2_lru_fixup }, \ + __flags, \ + __panel \ + } + +#define RDU2_PANEL_10P1 IT_SINGLE_LVDS, BF_SPWG, "innolux,g121i1-l01" +#define RDU2_PANEL_11P6 IT_EDP, BF_NONE, NULL +#define RDU2_PANEL_12P1 IT_SINGLE_LVDS, BF_SPWG, "nec,nl12880bc20-05" +#define RDU2_PANEL_13P3 IT_DUAL_LVDS, BF_JEIDA, "auo,g133han01" +#define RDU2_PANEL_15P6 IT_DUAL_LVDS, BF_SPWG, "nlt,nl192108ac18-02d" +#define RDU2_PANEL_18P5 IT_DUAL_LVDS, BF_SPWG, "auo,g185han01" +#define RDU2_PANEL_32P0 IT_DUAL_LVDS, BF_SPWG, "auo,p320hvn03" + +static const struct rdu2_lru_fixup rdu2_lru_fixups[] = { + RDU2_LRU_FIXUP("00-5122-01", RDU2_LRU_FLAG_NO_FEC, RDU2_PANEL_12P1), + RDU2_LRU_FIXUP("00-5122-02", RDU2_LRU_FLAG_NO_FEC, RDU2_PANEL_12P1), + RDU2_LRU_FIXUP("00-5120-01", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5120-02", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5120-51", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5120-52", 0, RDU2_PANEL_10P1), + RDU2_LRU_FIXUP("00-5123-01", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-02", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-03", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-51", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-52", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5123-53", 0, RDU2_PANEL_11P6), + RDU2_LRU_FIXUP("00-5124-01", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5124-02", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5124-03", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5124-53", 0, RDU2_PANEL_13P3), + RDU2_LRU_FIXUP("00-5127-01", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5127-02", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5127-03", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5127-53", 0, RDU2_PANEL_15P6), + RDU2_LRU_FIXUP("00-5125-01", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5125-02", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5125-03", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5125-53", 0, RDU2_PANEL_18P5), + RDU2_LRU_FIXUP("00-5132-01", RDU2_LRU_FLAG_EGALAX, RDU2_PANEL_32P0), + RDU2_LRU_FIXUP("00-5132-02", RDU2_LRU_FLAG_EGALAX, RDU2_PANEL_32P0), +}; + +/* + * This initcall needs to be executed before coredevices, so we have a chance + * to fix up the internal DT with the correct display information. + */ +static int rdu2_process_fixups(void) +{ + if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") && + !of_machine_is_compatible("zii,imx6qp-zii-rdu2")) + return 0; - val = I210_CFGWORD_PCIID_157B; - pwrite(fd, &val, sizeof(val), 0); + zii_process_lru_fixups(rdu2_lru_fixups); return 0; } -late_initcall(rdu2_i210_invm); +postmmu_initcall(rdu2_process_fixups); diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 059e4c9efd..0fd2ddfca5 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -145,7 +145,7 @@ ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2) unsigned int system_type; void *fdt; - arm_cpu_lowlevel_init(); + imx8mq_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index a8fa1ef61f..1296f70317 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -123,6 +123,7 @@ static int zii_vf610_dev_set_hostname(void) const char *hostname; } boards[] = { { "zii,vf610spu3", "spu3" }, + { "zii,vf610spb4", "spb4" }, { "zii,vf610cfu1", "cfu1" }, { "zii,vf610dev-b", "dev-rev-b" }, { "zii,vf610dev-c", "dev-rev-c" }, @@ -168,7 +169,8 @@ static int zii_vf610_register_emmc_bbu(void) int ret; if (!of_machine_is_compatible("zii,vf610spu3") && - !of_machine_is_compatible("zii,vf610cfu1")) + !of_machine_is_compatible("zii,vf610cfu1") && + !of_machine_is_compatible("zii,vf610spb4")) return 0; ret = vf610_bbu_internal_mmcboot_register_handler("eMMC", diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index d19318026c..79588ac381 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -41,6 +41,7 @@ enum zii_platform_vf610_type { ZII_PLATFORM_VF610_SSMB_SPU3 = 0x03, ZII_PLATFORM_VF610_CFU1 = 0x04, ZII_PLATFORM_VF610_DEV_REV_C = 0x05, + ZII_PLATFORM_VF610_SPB4 = 0x06, }; static unsigned int get_system_type(void) @@ -77,7 +78,8 @@ extern char __dtb_vf610_zii_dev_rev_b_start[]; extern char __dtb_vf610_zii_dev_rev_c_start[]; extern char __dtb_vf610_zii_cfu1_start[]; extern char __dtb_vf610_zii_ssmb_spu3_start[]; -extern char __dtb_vf610_zii_scu4_aib_rev_c_start[]; +extern char __dtb_vf610_zii_scu4_aib_start[]; +extern char __dtb_vf610_zii_spb4_start[]; ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) { @@ -121,7 +123,7 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) fdt = __dtb_vf610_zii_dev_rev_b_start; break; case ZII_PLATFORM_VF610_SCU4_AIB: - fdt = __dtb_vf610_zii_scu4_aib_rev_c_start; + fdt = __dtb_vf610_zii_scu4_aib_start; break; case ZII_PLATFORM_VF610_DEV_REV_C: fdt = __dtb_vf610_zii_dev_rev_c_start; @@ -132,6 +134,9 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) case ZII_PLATFORM_VF610_SSMB_SPU3: fdt = __dtb_vf610_zii_ssmb_spu3_start; break; + case ZII_PLATFORM_VF610_SPB4: + fdt = __dtb_vf610_zii_spb4_start; + break; } vf610_barebox_entry(fdt + get_runtime_offset()); diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c index 9f1aa6641c..5b95d879fa 100644 --- a/arch/arm/boards/zylonite/lowlevel.c +++ b/arch/arm/boards/zylonite/lowlevel.c @@ -3,7 +3,7 @@ #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> -void __naked barebox_arm_reset_vector(void) +void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { arm_cpu_lowlevel_init(); barebox_arm_entry(0x80000000, SZ_64M, NULL); |