diff options
Diffstat (limited to 'arch/arm/boards')
26 files changed, 466 insertions, 29 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 30f4c299f1..b2fea4a40f 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -1,4 +1,5 @@ # keep sorted by CONFIG_* macro name. +obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/ obj-$(CONFIG_MACH_AFI_GF) += afi-gf/ obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/ obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/ diff --git a/arch/arm/boards/advantech-mx6/Makefile b/arch/arm/boards/advantech-mx6/Makefile new file mode 100644 index 0000000000..01c7a259e9 --- /dev/null +++ b/arch/arm/boards/advantech-mx6/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/advantech-mx6/board.c b/arch/arm/boards/advantech-mx6/board.c new file mode 100644 index 0000000000..4a30a845f1 --- /dev/null +++ b/arch/arm/boards/advantech-mx6/board.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <init.h> +#include <platform_data/eth-fec.h> +#include <bootsource.h> +#include <mach/bbu.h> + +static int ar8035_phy_fixup(struct phy_device *dev) +{ + u16 val; + + /* Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(dev, 0xd, 0x3); + phy_write(dev, 0xe, 0x805d); + phy_write(dev, 0xd, 0x4003); + + val = phy_read(dev, 0xe); + phy_write(dev, 0xe, val & ~BIT(8)); + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(dev, 0xd, 0x7); + phy_write(dev, 0xe, 0x8016); + phy_write(dev, 0xd, 0x4007); + + val = phy_read(dev, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(dev, 0xe, val); + + /* introduce tx clock delay */ + phy_write(dev, 0x1d, 0x5); + val = phy_read(dev, 0x1e); + val |= 0x0100; + phy_write(dev, 0x1e, val); + + return 0; +} + +static int advantech_mx6_devices_init(void) +{ + int ret; + char *environment_path, *envdev; + + if (!of_machine_is_compatible("advantech,imx6dl-rom-7421")) + return 0; + + phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + environment_path = basprintf("/chosen/environment-sd%d", + bootsource_get_instance() + 1); + if (bootsource_get_instance() + 1 == 4) + envdev = "eMMC"; + else if (bootsource_get_instance() + 1 == 2) + envdev = "microSD"; + else + envdev = "MMC"; + break; + case BOOTSOURCE_SPI: + envdev = "SPI"; + environment_path = basprintf("/chosen/environment-spi"); + break; + default: + environment_path = basprintf("/chosen/environment-sd4"); + envdev = "MMC"; + break; + } + + if (environment_path) { + ret = of_device_enable_path(environment_path); + if (ret < 0) + pr_warn("Failed to enable env partition '%s' (%d)\n", + environment_path, ret); + free(environment_path); + } + + pr_notice("Using environment in %s\n", envdev); + + imx6_bbu_internal_mmc_register_handler("mmc3", "/dev/mmc3", + BBU_HANDLER_FLAG_DEFAULT); + + return 0; +} +device_initcall(advantech_mx6_devices_init); diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg new file mode 100644 index 0000000000..996ecc708d --- /dev/null +++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg @@ -0,0 +1,66 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0774 0x000C0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00000030 +wm 32 0x020e04b8 0x00000030 +wm 32 0x020e076c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e04bc 0x00000030 +wm 32 0x020e04c0 0x00000030 +wm 32 0x020e04c4 0x00000030 +wm 32 0x020e04c8 0x00000030 +wm 32 0x020e0760 0x00020000 +wm 32 0x020e0764 0x00000030 +wm 32 0x020e0770 0x00000030 +wm 32 0x020e0778 0x00000030 +wm 32 0x020e077c 0x00000030 +wm 32 0x020e0470 0x00000030 +wm 32 0x020e0474 0x00000030 +wm 32 0x020e0478 0x00000030 +wm 32 0x020e047c 0x00000030 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b080c 0x001F001F +wm 32 0x021b0810 0x001F001F +wm 32 0x021b083c 0x42480248 +wm 32 0x021b0840 0x022C0234 +wm 32 0x021b0848 0x3E404244 +wm 32 0x021b0850 0x30302C30 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b0004 0x0002002D +wm 32 0x021b0008 0x00333030 +wm 32 0x021b000c 0x3F435333 +wm 32 0x021b0010 0xB68E8B63 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00001740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x00431023 +wm 32 0x021b0040 0x00000017 +wm 32 0x021b0000 0x83190000 +wm 32 0x021b001c 0x04008032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x05208030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b0004 0x0002556D +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 +wm 32 0x020e0010 0xF00000CF +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F diff --git a/arch/arm/boards/advantech-mx6/lowlevel.c b/arch/arm/boards/advantech-mx6/lowlevel.c new file mode 100644 index 0000000000..8921cd4dd8 --- /dev/null +++ b/arch/arm/boards/advantech-mx6/lowlevel.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2018 Christoph Fritz <chf.fritz@googlemail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <debug_ll.h> +#include <common.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <image-metadata.h> +#include <mach/generic.h> +#include <mach/esdctl.h> +#include <mach/iomux-mx6.h> +#include <linux/sizes.h> + +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + imx6_ungate_all_peripherals(); + + imx_setup_pad(iomuxbase, MX6Q_PAD_CSI0_DAT10__UART1_TXD); + + imx6_uart_setup_ll(); + + putc_ll('>'); +} + +extern char __dtb_imx6dl_advantech_rom_7421_start[]; + +ENTRY_FUNCTION(start_advantech_imx6dl_rom_7421, r0, r1, r2) +{ + imx6_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + imx6q_barebox_entry(__dtb_imx6dl_advantech_rom_7421_start); +} diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index 043a93461b..d93c940e3d 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -132,7 +132,7 @@ static int realq7_device_init(void) } break; default: - case BOOTSOURCE_SPI: + case BOOTSOURCE_SPI_NOR: of_device_enable_path("/chosen/environment-spi"); break; } diff --git a/arch/arm/boards/dfi-fs700-m60/board.c b/arch/arm/boards/dfi-fs700-m60/board.c index bef4612d9e..2cb8e3106f 100644 --- a/arch/arm/boards/dfi-fs700-m60/board.c +++ b/arch/arm/boards/dfi-fs700-m60/board.c @@ -105,7 +105,7 @@ static int dfi_fs700_m60_init(void) phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK, ar8031_phy_fixup); - if (bootsource_get() == BOOTSOURCE_SPI) + if (bootsource_get() == BOOTSOURCE_SPI_NOR) flag_spi |= BBU_HANDLER_FLAG_DEFAULT; else flag_mmc |= BBU_HANDLER_FLAG_DEFAULT; diff --git a/arch/arm/boards/freescale-vf610-twr/lowlevel.c b/arch/arm/boards/freescale-vf610-twr/lowlevel.c index deabe4e371..8fec9f4b91 100644 --- a/arch/arm/boards/freescale-vf610-twr/lowlevel.c +++ b/arch/arm/boards/freescale-vf610-twr/lowlevel.c @@ -3,6 +3,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +#include <mach/esdctl.h> #include <mach/vf610-regs.h> #include <mach/clock-vf610.h> #include <mach/iomux-vf610.h> @@ -13,27 +14,21 @@ static inline void setup_uart(void) void __iomem *iomuxbase = IOMEM(VF610_IOMUXC_BASE_ADDR); vf610_ungate_all_peripherals(); - - /* - * VF610_PAD_PTB4__UART1_TX - */ - writel(VF610_UART_PAD_CTRL | (2 << 20), iomuxbase + 0x0068); - writel(0, iomuxbase + 0x0380); - + vf610_setup_pad(iomuxbase, VF610_PAD_PTB4__UART1_TX); vf610_uart_setup_ll(); + + putc_ll('>'); } extern char __dtb_vf610_twr_start[]; ENTRY_FUNCTION(start_vf610_twr, r0, r1, r2) { - void *fdt; vf610_cpu_lowlevel_init(); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); - fdt = __dtb_vf610_twr_start + get_runtime_offset(); - barebox_arm_entry(0x80000000, SZ_128M, fdt); + vf610_barebox_entry(__dtb_vf610_twr_start + get_runtime_offset()); } diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 717a22963a..34a0fe4183 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -28,6 +28,7 @@ #include <gpio.h> #include <init.h> #include <of.h> +#include <i2c/i2c.h> #include <mach/bbu.h> #include <platform_data/eth-fec.h> #include <mfd/imx6q-iomuxc-gpr.h> @@ -51,6 +52,14 @@ #define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) +#define DA9062_I2C_ADDRESS 0x58 + +#define DA9062_BUCK1_CFG 0x9e +#define DA9062_BUCK2_CFG 0x9d +#define DA9062_BUCK3_CFG 0xa0 +#define DA9062_BUCK4_CFG 0x9f +#define DA9062_BUCKx_MODE_SYNCHRONOUS (2 << 6) + static void phyflex_err006282_workaround(void) { /* @@ -66,7 +75,7 @@ static void phyflex_err006282_workaround(void) mdelay(2); gpio_set_value(MX6_PHYFLEX_ERR006282, 0); - if (cpu_is_mx6q() || cpu_is_mx6d()) + if (cpu_is_mx6q() || cpu_is_mx6d() || cpu_is_mx6qp() || cpu_is_mx6dp()) mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD); else if (cpu_is_mx6dl() || cpu_is_mx6s()) mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11); @@ -96,6 +105,45 @@ int ksz8081_phy_fixup(struct phy_device *phydev) return 0; } +static int phycore_da9062_setup_buck_mode(void) +{ + struct i2c_adapter *adapter = NULL; + struct i2c_client client; + unsigned char value; + int bus = 0; + int ret; + + adapter = i2c_get_adapter(bus); + if (!adapter) + return -ENODEV; + + client.adapter = adapter; + client.addr = DA9062_I2C_ADDRESS; + + value = DA9062_BUCKx_MODE_SYNCHRONOUS; + + ret = i2c_write_reg(&client, DA9062_BUCK1_CFG, &value, 1); + if (ret != 1) + goto err_out; + + ret = i2c_write_reg(&client, DA9062_BUCK2_CFG, &value, 1); + if (ret != 1) + goto err_out; + + ret = i2c_write_reg(&client, DA9062_BUCK3_CFG, &value, 1); + if (ret != 1) + goto err_out; + + ret = i2c_write_reg(&client, DA9062_BUCK4_CFG, &value, 1); + if (ret != 1) + goto err_out; + + return 0; + +err_out: + return ret; +} + static int physom_imx6_devices_init(void) { int ret; @@ -125,8 +173,12 @@ static int physom_imx6_devices_init(void) } else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") + || of_machine_is_compatible("phytec,imx6qp-pcm058-nand") || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { + if (phycore_da9062_setup_buck_mode()) + pr_err("Setting PMIC BUCK mode failed\n"); + barebox_set_hostname("phyCORE-i.MX6"); default_environment_path = "/chosen/environment-spinor"; default_envdev = "SPI NOR flash"; @@ -152,7 +204,7 @@ static int physom_imx6_devices_init(void) environment_path = basprintf("/chosen/environment-nand"); envdev = "NAND flash"; break; - case BOOTSOURCE_SPI: + case BOOTSOURCE_SPI_NOR: environment_path = basprintf("/chosen/environment-spinor"); envdev = "SPI NOR flash"; break; @@ -184,7 +236,8 @@ static int physom_imx6_devices_init(void) defaultenv_append_directory(defaultenv_physom_imx6); /* Overwrite file /env/init/automount */ - if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") + if (of_machine_is_compatible("phytec,imx6qp-pcm058-nand") + || of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc new file mode 100644 index 0000000000..7ba1d0d0cf --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/boot/emmc @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/mnt/emmc/zImage" +global.bootm.oftree="/mnt/emmc/oftree" +global.linux.bootargs.dyn.root="root=/dev/mmcblk1p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc new file mode 100644 index 0000000000..f0d019c3ee --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/emmc @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ -f /mnt/mmc3/android ]; then + # configure here the android specific stuff + global linux.bootargs.sec="selinux=0 enforcing=0" +fi + +global.bootm.image="/mnt/mmc3/zImage" +global.bootm.oftree="/mnt/mmc3/oftree" +global.linux.bootargs.dyn.root="root=/dev/mmcblk3p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc index 332fc26ad0..3e175122dd 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc @@ -1,5 +1,10 @@ #!/bin/sh -global.bootm.image="/mnt/mmc/linuximage" +if [ -f /mnt/mmc/android ]; then + # configure here the android specific stuff + global linux.bootargs.sec="selinux=0 enforcing=0" +fi + +global.bootm.image="/mnt/mmc/zImage" global.bootm.oftree="/mnt/mmc/oftree" global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand index a23aa21cc7..0c2b1cbe4c 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand @@ -1,5 +1,12 @@ #!/bin/sh -global.bootm.image="/dev/nand0.kernel.bb" -global.bootm.oftree="/dev/nand0.oftree.bb" +[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root + +if [ -e /dev/nand0.root.ubi.system ]; then + # configure here the android specific stuff + global linux.bootargs.sec="selinux=0 enforcing=0" +fi + +global.bootm.image="/dev/nand0.root.ubi.kernel" +global.bootm.oftree="/dev/nand0.root.ubi.oftree" global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount index 4b223d8037..fea64d627e 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount @@ -7,3 +7,8 @@ automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' mkdir -p /mnt/mmc automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' + +if [ -e /dev/mmc3 ]; then + mkdir -p /mnt/mmc3 + automount -d /mnt/mmc3 'mmc3.probe=1 && [ -e /dev/mmc3.0 ] && mount /dev/mmc3.0 /mnt/mmc3' +fi diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg new file mode 100644 index 0000000000..bf95d0f6ae --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib-32bit.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x84190000 + +#include "flash-header-phytec-pcm058dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg new file mode 100644 index 0000000000..bf85f0a19c --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp-1gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x555A7955 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831A0000 + +#include "flash-header-phytec-pcm058qp.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h new file mode 100644 index 0000000000..6e7b740a6f --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h @@ -0,0 +1,112 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +/* NOC setup */ +wm 32 0x00bb0008 0x00000000 +wm 32 0x00bb000c 0x2891E41A +wm 32 0x00bb0038 0x00000564 +wm 32 0x00bb0014 0x00000040 +wm 32 0x00bb0028 0x00000020 +wm 32 0x00bb002c 0x00000020 + +wm 32 0x020e0798 0x000C0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00000028 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00140014 +wm 32 0x021b0810 0x00230018 +wm 32 0x021b480c 0x000A001E +wm 32 0x021b4810 0x000A0015 +wm 32 0x021b083c 0x43080314 +wm 32 0x021b0840 0x02680300 +wm 32 0x021b483c 0x430C0318 +wm 32 0x021b4840 0x03000254 +wm 32 0x021b0848 0x3A323234 +wm 32 0x021b4848 0x3E3C3242 +wm 32 0x021b0850 0x2A2E3632 +wm 32 0x021b4850 0x3C323E34 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xFF328F64 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00011740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x003F1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00048039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0890 0x00400c58 +wm 32 0x021b0400 0x14420000 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 +wm 32 0x020e0010 0xf00000ff +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F +wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg index 156eea971e..7b64e5d2fd 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 + wm 32 0x021b000c 0x41447525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000027; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg index e76867004a..04c489d7e8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x8c929b85 + wm 32 0x021b000c 0x2d307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index 405529ddf8..b0f3faa0b7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -74,7 +74,7 @@ wm 32 MX6_MMDC_P0_MDOTC 0x09444040 SETUP_MDCFG0 -wm 32 MX6_MMDC_P0_MDCFG1 0xff538f64 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b64 wm 32 MX6_MMDC_P0_MDCFG2 0x01ff0124 wm 32 MX6_MMDC_P0_MDMISC 0x00091740 wm 32 MX6_MMDC_P0_MDSCR 0x00008000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg index 26fe2b2f7d..ebe5a968b1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 + wm 32 0x021b000c 0x2D307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x0000000B; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg index babb0dfe24..5f1585a40b 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 + wm 32 0x021b000c 0x2D307525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x0000000F; \ diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg index 6a46cd958f..5ff3ec69d7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg @@ -1,5 +1,5 @@ #define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 + wm 32 0x021b000c 0x41447525 #define SETUP_MDASP_MDCTL \ wm 32 0x021b0040 0x00000017; \ diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 12c3cfa642..f9d70c7450 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -107,8 +107,10 @@ PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_sub PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra, SZ_1G, false); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_1gib, imx6dl_phytec_phycore_som_nand, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6qp_som_nand_1gib, imx6qp_phytec_phycore_som_nand, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c index 22ffdf85ea..6b9c719c6d 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c +++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c @@ -284,13 +284,13 @@ static noinline void rdu2_sram_setup(void) relocate_to_current_adr(); setup_c(); - if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0) + if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP) write_regs(imx6qp_dcd, ARRAY_SIZE(imx6qp_dcd)); else write_regs(imx6q_dcd, ARRAY_SIZE(imx6q_dcd)); imx6_get_boot_source(&bootsrc, &instance); - if (bootsrc == BOOTSOURCE_SPI) + if (bootsrc == BOOTSOURCE_SPI_NOR) imx6_spi_start_image(0); else imx6_esdhc_start_image(instance); @@ -304,10 +304,10 @@ ENTRY_FUNCTION(start_imx6_zii_rdu2, r0, r1, r2) * When still running in SRAM, we need to setup the DRAM now and load * the remaining image. */ - if (get_pc() < MX6_MMDC_PORT0_BASE_ADDR) + if (get_pc() < MX6_MMDC_PORT01_BASE_ADDR) rdu2_sram_setup(); - if (__imx6_cpu_revision() == IMX_CHIP_REV_2_0) + if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP) imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start + get_runtime_offset()); else diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c index c6663c1415..f3d67501ab 100644 --- a/arch/arm/boards/zii-vf610-dev/lowlevel.c +++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c @@ -18,6 +18,7 @@ #include <mach/generic.h> #include <asm/barebox-arm-head.h> #include <asm/barebox-arm.h> +#include <mach/esdctl.h> #include <mach/vf610-regs.h> #include <mach/clock-vf610.h> #include <mach/iomux-vf610.h> @@ -133,5 +134,5 @@ ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2) break; } - barebox_arm_entry(0x80000000, SZ_512M, fdt + get_runtime_offset()); + vf610_barebox_entry(fdt + get_runtime_offset()); } |