diff options
Diffstat (limited to 'arch/arm/dts/rk3568.dtsi')
-rw-r--r-- | arch/arm/dts/rk3568.dtsi | 1110 |
1 files changed, 0 insertions, 1110 deletions
diff --git a/arch/arm/dts/rk3568.dtsi b/arch/arm/dts/rk3568.dtsi deleted file mode 100644 index 0f19d3f0c0..0000000000 --- a/arch/arm/dts/rk3568.dtsi +++ /dev/null @@ -1,1110 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -#include <dt-bindings/clock/rk3568-cru.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "rockchip,rk3568"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - clocks = <&scmi_clk 0>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <900000 900000 1150000>; - clock-latency-ns = <40000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <900000 900000 1150000>; - opp-suspend; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <900000 900000 1150000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <975000 975000 1150000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1050000 1050000 1150000>; - }; - - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - }; - }; - - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - }; - - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - pinctrl-0 = <&clk32k_out0>; - pinctrl-names = "default"; - #clock-cells = <0>; - }; - - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - usbdrd30: usbdrd { - compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usbdrd_dwc3: dwc3@fcc00000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_USB3OTG0>; - reset-names = "usb3-otg"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,xhci-trb-ent-quirk; - }; - }; - - usbhost30: usbhost { - compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usbhost_dwc3: dwc3@fd000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_USB3OTG1>; - reset-names = "usb3-host"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,xhci-trb-ent-quirk; - }; - }; - - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0x80000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd100000>; - mbi-ranges = <296 24>; - msi-controller; - }; - - usb_host0_ehci: usb@fd800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd800000 0x0 0x40000>; - interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fd840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd840000 0x0 0x40000>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fd880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd880000 0x0 0x40000>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fd8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd8c0000 0x0 0x40000>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb2phy0: usb2-phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&usb2phy0>; - clock-output-names = "usb480m_phy"; - rockchip,usbgrf = <&usb2phy0_grf>; - status = "disabled"; - - u2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - usb2phy1: usb2-phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - rockchip,usbgrf = <&usb2phy1_grf>; - status = "disabled"; - - u2phy1_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - combphy0_us: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; - reset-names = "combphy-apb", "combphy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - status = "disabled"; - }; - - combphy1_usq: phy@fe830000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe830000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, - <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <24000000>; - resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; - reset-names = "combphy-apb", "combphy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - status = "disabled"; - }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc70000 0x0 0x1000>; - }; - - pipe_phy_grf1: syscon@fdc80000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; - }; - - usb2phy1_grf: syscon@fdca8000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca8000 0x0 0x8000>; - }; - - pipegrf: syscon@fdc50000 { - compatible = "rockchip,rk3568-pipegrf", "syscon"; - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; - }; - - grf: syscon@fdc60000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc60000 0x0 0x10000>; - }; - - pmucru: clock-controller@fdd00000 { - compatible = "rockchip,rk3568-pmucru"; - reg = <0x0 0xfdd00000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - rockchip,grf = <&grf>; - }; - - cru: clock-controller@fdd20000 { - compatible = "rockchip,rk3568-cru"; - reg = <0x0 0xfdd20000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - rockchip,grf = <&grf>; - }; - - i2c0: i2c@fdd40000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfdd40000 0x0 0x1000>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fdd50000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfdd50000 0x0 0x100>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 0>, <&dmac0 1>; - pinctrl-0 = <&uart0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm0: pwm@fdd70000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70000 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fdd70010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70010 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fdd70020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70020 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fdd70030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70030 0x0 0x10>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, - <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC2>; - reset-names = "reset"; - status = "disabled"; - }; - - gmac1: ethernet@fe010000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe010000 0x0 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, - <&cru PCLK_XPCS>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, - <&cru PCLK_XPCS>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, - <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc1: mmc@fe2c0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, - <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <150000000>; - resets = <&cru SRST_SDMMC1>; - reset-names = "reset"; - status = "disabled"; - }; - - sdhci: mmc@fe310000 { - compatible = "rockchip,rk3568-dwcmshc"; - reg = <0x0 0xfe310000 0x0 0x10000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - dmac0: dmac@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dmac@fe550000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe550000 0x0 0x4000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fe5a0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5a0000 0x0 0x1000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c1_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@fe5b0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5b0000 0x0 0x1000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@fe5c0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5c0000 0x0 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@fe5d0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5d0000 0x0 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fe5e0000 { - compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5e0000 0x0 0x1000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@fe600000 { - compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; - reg = <0x0 0xfe600000 0x0 0x100>; - interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; - clock-names = "tclk", "pclk"; - }; - - uart1: serial@fe650000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe650000 0x0 0x100>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - pinctrl-0 = <&uart1m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@fe660000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe660000 0x0 0x100>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 4>, <&dmac0 5>; - pinctrl-0 = <&uart2m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@fe670000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe670000 0x0 0x100>; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - pinctrl-0 = <&uart3m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@fe680000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe680000 0x0 0x100>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - pinctrl-0 = <&uart4m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@fe690000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe690000 0x0 0x100>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - pinctrl-0 = <&uart5m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@fe6a0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6a0000 0x0 0x100>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - pinctrl-0 = <&uart6m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@fe6b0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6b0000 0x0 0x100>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - pinctrl-0 = <&uart7m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@fe6c0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6c0000 0x0 0x100>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - pinctrl-0 = <&uart8m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@fe6d0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6d0000 0x0 0x100>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 18>, <&dmac0 19>; - pinctrl-0 = <&uart9m0_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@fe6e0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@fe6e0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@fe6e0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@fe6e0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@fe6f0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@fe6f0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@fe6f0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@fe6f0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@fe700000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@fe700010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@fe700020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@fe700030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "active"; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: saradc@fe720000 { - compatible = "rockchip,rk3568-saradc"; - reg = <0x0 0xfe720000 0x0 0x100>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@fdd60000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfdd60000 0x0 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@fe740000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe740000 0x0 0x100>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@fe750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@fe760000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe760000 0x0 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@fe770000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe770000 0x0 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3568-pinctrl.dtsi" |