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-rw-r--r--arch/arm/dts/socfpga_arria10_achilles.dts48
1 files changed, 13 insertions, 35 deletions
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
index 4c6460fb60..fbfdc9a882 100644
--- a/arch/arm/dts/socfpga_arria10_achilles.dts
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -15,7 +15,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
-#include <arm/socfpga_arria10.dtsi>
+#include <arm/intel/socfpga/socfpga_arria10.dtsi>
/ {
model = "Reflex SOCFPGA Arria 10 Achilles";
@@ -106,44 +106,22 @@
};
};
};
+};
- bootstate: bootstate {
- compatible = "barebox,bootstate";
- backend-type = "state"; // or "nv", or "efivar"
- backend = <&state>;
-
- system0 {
- default_attempts = <3>;
- };
-
- system1 {
- default_attempts = <3>;
- };
+&osc1 {
+ clock-frequency = <25000000>;
+};
- factory {
- default_attempts = <3>;
- };
- };
+&cb_intosc_hs_div2_clk {
+ clock-frequency = <0>;
+};
- soc {
- clkmgr@ffd04000 {
- clocks {
- osc1 {
- clock-frequency = <25000000>;
- };
+&cb_intosc_ls_clk {
+ clock-frequency = <60000000>;
+};
- cb_intosc_hs_div2_clk {
- clock-frequency = <0>;
- };
- cb_intosc_ls_clk {
- clock-frequency = <60000000>;
- };
- f2s_free_clk {
- clock-frequency = <200000000>;
- };
- };
- };
- };
+&f2s_free_clk {
+ clock-frequency = <200000000>;
};
&gmac1 {