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-rw-r--r--arch/arm/dts/Makefile11
-rw-r--r--arch/arm/dts/imx51-zii-rdu1.dts21
-rw-r--r--arch/arm/dts/imx51-zii-scu2-mezz.dts11
-rw-r--r--arch/arm/dts/imx51-zii-scu3-esb.dts12
-rw-r--r--arch/arm/dts/imx6qdl-zii-rdu2.dtsi16
-rw-r--r--arch/arm/dts/imx7d-ddrc.dtsi15
-rw-r--r--arch/arm/dts/imx7d-zii-rpu2.dts613
-rw-r--r--arch/arm/dts/imx8mq-ddrc.dtsi17
-rw-r--r--arch/arm/dts/imx8mq-evk.dts7
-rw-r--r--arch/arm/dts/imx8mq.dtsi127
-rw-r--r--arch/arm/dts/vf610-twr.dts1
-rw-r--r--arch/arm/dts/vf610-zii-cfu1-rev-a.dts209
-rw-r--r--arch/arm/dts/vf610-zii-cfu1.dts10
-rw-r--r--arch/arm/dts/vf610-zii-dev.dtsi1
-rw-r--r--arch/arm/dts/vf610-zii-spu3-rev-a.dts142
-rw-r--r--arch/arm/dts/vf610-zii-ssmb-spu3.dts5
-rw-r--r--arch/arm/dts/vf610.dtsi12
17 files changed, 834 insertions, 396 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7ec10bf200..1caeca35b4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -103,15 +103,20 @@ pbl-dtb-$(CONFIG_MACH_VEXPRESS) += vexpress-v2p-ca15.dtb.o
pbl-dtb-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o
pbl-dtb-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o
pbl-dtb-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o
-pbl-dtb-$(CONFIG_MACH_ZII_RDU1) += imx51-zii-rdu1.dtb.o
+pbl-dtb-$(CONFIG_MACH_ZII_RDU1) += \
+ imx51-zii-rdu1.dtb.o \
+ imx51-zii-scu2-mezz.dtb.o \
+ imx51-zii-scu3-esb.dtb.o
pbl-dtb-$(CONFIG_MACH_ZII_RDU2) += imx6q-zii-rdu2.dtb.o imx6qp-zii-rdu2.dtb.o
pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
vf610-zii-dev-rev-b.dtb.o \
vf610-zii-dev-rev-c.dtb.o \
- vf610-zii-cfu1-rev-a.dtb.o \
- vf610-zii-spu3-rev-a.dtb.o \
+ vf610-zii-cfu1.dtb.o \
+ vf610-zii-ssmb-spu3.dtb.o \
vf610-zii-scu4-aib-rev-c.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
+pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
+
clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/arm/dts/imx51-zii-rdu1.dts b/arch/arm/dts/imx51-zii-rdu1.dts
index bde565fe08..93bb344f51 100644
--- a/arch/arm/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/dts/imx51-zii-rdu1.dts
@@ -53,37 +53,16 @@
&uart3 {
rave-sp {
- #address-cells = <1>;
- #size-cells = <1>;
-
watchdog {
nvmem-cells = <&boot_source>;
nvmem-cell-names = "boot-source";
};
- eeprom@a3 {
- compatible = "zii,rave-sp-eeprom";
- reg = <0xa3 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- zii,eeprom-name = "dds-eeprom";
- };
-
eeprom@a4 {
- compatible = "zii,rave-sp-eeprom";
- reg = <0xa4 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- zii,eeprom-name = "main-eeprom";
-
boot_source: boot-source@83 {
reg = <0x83 1>;
};
};
-
- backlight {
- compatible = "zii,rave-sp-backlight";
- };
};
};
diff --git a/arch/arm/dts/imx51-zii-scu2-mezz.dts b/arch/arm/dts/imx51-zii-scu2-mezz.dts
new file mode 100644
index 0000000000..68a374bb2b
--- /dev/null
+++ b/arch/arm/dts/imx51-zii-scu2-mezz.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ */
+
+#include <arm/imx51-zii-scu2-mezz.dts>
+
+&iim {
+ barebox,provide-mac-address = <&fec 1 9>;
+};
diff --git a/arch/arm/dts/imx51-zii-scu3-esb.dts b/arch/arm/dts/imx51-zii-scu3-esb.dts
new file mode 100644
index 0000000000..c83bf17316
--- /dev/null
+++ b/arch/arm/dts/imx51-zii-scu3-esb.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ */
+
+
+#include <arm/imx51-zii-scu3-esb.dts>
+
+&iim {
+ barebox,provide-mac-address = <&fec 1 9>;
+};
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index a74fb47831..f63b5d2ed7 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -66,19 +66,7 @@
nvmem-cell-names = "boot-source";
};
- eeprom@a3 {
- compatible = "zii,rave-sp-eeprom";
- reg = <0xa3 0x4000>;
- zii,eeprom-name = "dds-eeprom";
- };
-
eeprom@a4 {
- compatible = "zii,rave-sp-eeprom";
- reg = <0xa4 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- zii,eeprom-name = "main-eeprom";
-
boot_source: boot-source@83 {
reg = <0x83 1>;
};
@@ -91,10 +79,6 @@
reg = <0x190 6>;
};
};
-
- backlight {
- compatible = "zii,rave-sp-backlight";
- };
};
};
diff --git a/arch/arm/dts/imx7d-ddrc.dtsi b/arch/arm/dts/imx7d-ddrc.dtsi
new file mode 100644
index 0000000000..b4cd597be9
--- /dev/null
+++ b/arch/arm/dts/imx7d-ddrc.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Include file to switch board DTS form using hardcoded memory node
+ * to dynamic memory size detection based on DDR controller settings
+ */
+
+/ {
+ /delete-node/ memory;
+};
+
+&aips2 {
+ ddrc@307a0000 {
+ compatible = "fsl,imx7d-ddrc";
+ reg = <0x307a0000 0x10000>;
+ };
+}; \ No newline at end of file
diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts
new file mode 100644
index 0000000000..6fba73f437
--- /dev/null
+++ b/arch/arm/dts/imx7d-zii-rpu2.dts
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <arm/imx7d.dtsi>
+
+#include "imx7d-ddrc.dtsi"
+
+/ {
+ model = "ZII RPU2 Board";
+ compatible = "zii,imx7d-zii-rpu2","fsl,imx7d";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pinctrl_leds_debug>;
+ pinctrl-names = "default";
+
+ debug {
+ label = "zii:green:debug1";
+ gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg2_vbus: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_sd1_vmmc: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SD1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ enable-active-high;
+ };
+
+ reg_can1_3v3: regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "can1-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_can2_3v3: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "can2-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_vref_1v8: regulator@6 {
+ compatible = "regulator-fixed";
+ reg = <6>;
+ regulator-name = "vref-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ wlreg_on: fixedregulator@100 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "wlreg_on";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "GEN_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v_main: regulator-5p0v-main {
+ compatible = "regulator-fixed";
+ regulator-name = "5V_MAIN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&adc1 {
+ vref-supply = <&reg_vref_1v8>;
+ status = "okay";
+};
+
+&adc2 {
+ vref-supply = <&reg_vref_1v8>;
+ status = "okay";
+};
+
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <884736000>;
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+
+ nor_flash: nor-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xc0000>;
+ };
+
+ partition@c0000 {
+ label = "barebox-environment";
+ reg = <0xc0000 0x40000>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&port_fec1>;
+ status = "okay";
+
+ mdio1: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ switch0: switch0@0 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ eeprom-length = <512>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "eth_cu_1000_1";
+ };
+ port@1 {
+ reg = <1>;
+ label = "eth_cu_1000_2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "pic";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ port_fec1: port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&fec1>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port_fec2: port@6 {
+ reg = <6>;
+ label = "data";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&port_fec1>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ nameplate_eeprom: at24c04@50 {
+ compatible = "atmel,24c04";
+ #address-cells=<1>;
+ #size-cells=<1>;
+ reg = <0x50>;
+ };
+
+ sandbox_eeprom: at24c04@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pfuze3000@08 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&sdma {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+ status = "okay";
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ nvmem-cells = <&boot_source>;
+ nvmem-cell-names = "boot-source";
+ };
+
+ eeprom@a3 {
+ compatible = "zii,rave-sp-eeprom";
+ reg = <0xa3 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ zii,eeprom-name = "main-eeprom";
+
+ boot_source: boot-source@83 {
+ reg = <0x83 1>;
+ };
+ };
+ };
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&wdog1 {
+ fsl,wdog_b;
+};
+
+
+&iomuxc {
+ pinctrl_leds_debug: debuggrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 /* HB_LED */
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
+ MX7D_PAD_SD2_WP__ENET1_MDC 0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
+ MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f
+ MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f
+ MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
+ MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f
+ MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
+ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f
+ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
+ MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
+ MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
+ MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
+ MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
+ MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
+ >;
+ };
+};
+
diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi
new file mode 100644
index 0000000000..26d3da8579
--- /dev/null
+++ b/arch/arm/dts/imx8mq-ddrc.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Include file to switch board DTS form using hardcoded memory node
+ * to dynamic memory size detection based on DDR controller settings
+ */
+
+/ {
+
+ /delete-node/ memory@40000000;
+
+ peripherals@0 {
+ ddrc@3d400000 {
+ compatible = "fsl,imx8mq-ddrc";
+ reg = <0x3d400000 0x400000>;
+ };
+ };
+};
+
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 3ac13baa18..a6e724e2e2 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "imx8mq.dtsi"
+#include "imx8mq-ddrc.dtsi"
/ {
model = "NXP i.MX8MQ EVK";
@@ -16,11 +17,6 @@
stdout-path = &uart1;
};
- memory@40000000 {
- device_type = "memory";
- reg = <0x00000000 0x40000000 0 0xc0000000>;
- };
-
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -43,6 +39,7 @@
<&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
<&pinctrl_fec1_phy_reset>;
phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index c67438a48e..f89bee200e 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
#include "imx8mq-pinfunc.h"
/* first 128 KiB of memory are owned by ATF */
@@ -96,6 +97,7 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ #cooling-cells = <2>;
};
A53_1: cpu@1 {
@@ -214,6 +216,89 @@
#interrupt-cells = <2>;
};
+ tmu: tmu@30260000 {
+ compatible = "fsl,imx8mq-tmu";
+ reg = <0x30260000 0x10000>;
+ interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000023
+ 0x00000001 0x00000029
+ 0x00000002 0x0000002f
+ 0x00000003 0x00000035
+ 0x00000004 0x0000003d
+ 0x00000005 0x00000043
+ 0x00000006 0x0000004b
+ 0x00000007 0x00000051
+ 0x00000008 0x00000057
+ 0x00000009 0x0000005f
+ 0x0000000a 0x00000067
+ 0x0000000b 0x0000006f
+
+ 0x00010000 0x0000001b
+ 0x00010001 0x00000023
+ 0x00010002 0x0000002b
+ 0x00010003 0x00000033
+ 0x00010004 0x0000003b
+ 0x00010005 0x00000043
+ 0x00010006 0x0000004b
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005d
+ 0x00010009 0x00000067
+ 0x0001000a 0x00000070
+
+ 0x00020000 0x00000017
+ 0x00020001 0x00000023
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000037
+ 0x00020004 0x00000041
+ 0x00020005 0x0000004b
+ 0x00020006 0x00000057
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006f
+
+ 0x00030000 0x00000015
+ 0x00030001 0x00000021
+ 0x00030002 0x0000002d
+ 0x00030003 0x00000039
+ 0x00030004 0x00000045
+ 0x00030005 0x00000053
+ 0x00030006 0x0000005f
+ 0x00030007 0x00000071>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ /* cpu thermal */
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <2000>;
+ thermal-sensors = <&tmu>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
@@ -288,6 +373,16 @@
#size-cells = <1>;
ranges = <0x30800000 0x30800000 0x400000>;
+ ecspi1: ecspi@30820000 {
+ compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
uart1: serial@30860000 {
compatible = "fsl,imx8mq-uart",
"fsl,imx6q-uart";
@@ -622,3 +717,35 @@
};
};
};
+
+
+
+&clk {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_SRC>,
+ <&clk IMX8MQ_CLK_USDHC1_DIV>,
+ <&clk IMX8MQ_CLK_USDHC2_SRC>,
+ <&clk IMX8MQ_CLK_USDHC2_DIV>,
+ <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
+ <&clk IMX8MQ_CLK_ENET_REF_SRC>,
+ <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
+
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_400M>,
+ <0>,
+ <&clk IMX8MQ_SYS1_PLL_400M>,
+ <0>,
+ <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS2_PLL_125M>,
+ <0>;
+
+ assigned-clock-rates = <400000000>,
+ <200000000>,
+ <400000000>,
+ <200000000>,
+ <266000000>,
+ <0>,
+ <125000000>,
+ <25000000>;
+};
+
diff --git a/arch/arm/dts/vf610-twr.dts b/arch/arm/dts/vf610-twr.dts
index 2456ade5f5..ac2774979e 100644
--- a/arch/arm/dts/vf610-twr.dts
+++ b/arch/arm/dts/vf610-twr.dts
@@ -8,6 +8,7 @@
*/
#include <arm/vf610-twr.dts>
+#include "vf610.dtsi"
#include "vf610-ddrmc.dtsi"
&usbdev0 {
diff --git a/arch/arm/dts/vf610-zii-cfu1-rev-a.dts b/arch/arm/dts/vf610-zii-cfu1-rev-a.dts
deleted file mode 100644
index 7e87a15c11..0000000000
--- a/arch/arm/dts/vf610-zii-cfu1-rev-a.dts
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include <arm/vf610-zii-dev.dtsi>
-
-#include "vf610-zii-dev.dtsi"
-
-/ {
- model = "ZII VF610 CFU1 Switch Management Board";
- compatible = "zii,vf610cfu1-a", "zii,vf610dev", "fsl,vf610";
-
- aliases {
- /delete-property/ serial1;
- /delete-property/ serial2;
- };
-
- gpio-leds {
- debug {
- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
- };
-
- fail {
- label = "zii_fail";
- gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
- default-state = "off";
- max-brightness = <1>;
- };
-
- status {
- label = "zii_status";
- gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- max-brightness = <1>;
- };
-
- status_a {
- label = "zii_status_a";
- gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- max-brightness = <1>;
- };
-
- status_b {
- label = "zii_status_b";
- gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- max-brightness = <1>;
- };
- };
-};
-
-&dspi1 {
- bus-num = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dspi1>;
- status = "okay";
-
- m25p128@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partition@0 {
- label = "m25p128-0";
- reg = <0x0 0x01000000>;
- };
- };
-};
-
-&esdhc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc0>;
- bus-width = <8>;
- status = "okay";
-};
-
-&fec0 {
- status = "disabled";
-};
-
-&i2c0 {
- clock-frequency = <400000>;
-
- pca9554@22 {
- compatible = "nxp,pca9554";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-/delete-node/ &i2c1;
-/delete-node/ &i2c2;
-/delete-node/ &uart1;
-/delete-node/ &uart2;
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- VF610_PAD_PTE2__GPIO_107 0x31c2 /* SOC_SW_RSTn */
- VF610_PAD_PTB28__GPIO_98 0x31c1 /* E6352_INTn */
-
- /* PTE27 is wired to signal SD on part CONN
- * SFF-F4 via net FIM_DS. An active high
- * on this indicates a received optical
- * signal
-
- * SPEED=0b11 HIGH, SRE=0b0, ODE=0b0, HYS=0b0
- * DSE=0b001 150Ohm, PUS=0b10 100k UP
- * PKE=0b0, PUE=0b0, OBE=0b0, IBE=0b1
- */
- VF610_PAD_PTE27__GPIO_132 0x3061
-
- /*
- * PTE13 is wired to signal T_DIS on part CONN
- * SFF-F4 via net FIM_TDIS. Setting this high
- * will disable optical output from the SFF-F4
-
- * SPEED=0b11 HIGH, SRE=0b0, ODE=0b0, HYS=0b0
- * DSE=0b001 150Ohm, PUS=0b00 100k DOWN
- * PKE=0b0, PUE=0b0, OBE=0b1, IBE=0b1
- * TODO: probably want IBE=0b0
- */
- VF610_PAD_PTE13__GPIO_118 0x3043
- >;
- };
-
- pinctrl_dspi1: dspi1grp {
- fsl,pins = <
- VF610_PAD_PTD5__DSPI1_CS0 0x1182
- VF610_PAD_PTC6__DSPI1_SIN 0x1181
- VF610_PAD_PTC7__DSPI1_SOUT 0x1182
- VF610_PAD_PTC8__DSPI1_SCK 0x1182
- >;
- };
-
- pinctrl_esdhc0: esdhc0grp {
- fsl,pins = <
- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
- >;
- };
-
- pinctrl_leds_debug: pinctrl-leds-debug {
- fsl,pins = <
- VF610_PAD_PTD3__GPIO_82 0x31c2
- VF610_PAD_PTE3__GPIO_108 0x31c2
- VF610_PAD_PTE4__GPIO_109 0x31c2
- VF610_PAD_PTE5__GPIO_110 0x31c2
- VF610_PAD_PTE6__GPIO_111 0x31c2
- >;
- };
-};
diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts
new file mode 100644
index 0000000000..80d3f54f78
--- /dev/null
+++ b/arch/arm/dts/vf610-zii-cfu1.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
+ */
+
+#include <arm/vf610-zii-cfu1.dts>
+
+#include "vf610-zii-dev.dtsi"
+
diff --git a/arch/arm/dts/vf610-zii-dev.dtsi b/arch/arm/dts/vf610-zii-dev.dtsi
index dc16280bc3..b6db262027 100644
--- a/arch/arm/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/dts/vf610-zii-dev.dtsi
@@ -42,6 +42,7 @@ n * copy, modify, merge, publish, distribute, sublicense, and/or
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include "vf610.dtsi"
#include "vf610-ddrmc.dtsi"
/ {
diff --git a/arch/arm/dts/vf610-zii-spu3-rev-a.dts b/arch/arm/dts/vf610-zii-spu3-rev-a.dts
deleted file mode 100644
index f362e7f0b9..0000000000
--- a/arch/arm/dts/vf610-zii-spu3-rev-a.dts
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include <arm/vf610-zii-dev.dtsi>
-
-#include "vf610-zii-dev.dtsi"
-
-/ {
- model = "ZII VF610 SPU3 Switch Management Board";
- compatible = "zii,vf610spu3-a", "zii,vf610dev", "fsl,vf610";
-
- aliases {
- /delete-property/ serial2;
- };
-
- gpio-leds {
- debug {
- gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&dspi1 {
- bus-num = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dspi1>;
- status = "okay";
-
- m25p128@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partition@0 {
- label = "m25p128-0";
- reg = <0x0 0x01000000>;
- };
- };
-};
-
-&esdhc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc0>;
- bus-width = <8>;
- status = "okay";
-};
-
-&fec0 {
- status = "disabled";
-};
-
-&i2c0 {
- /* Board Revision */
- gpio6: pca9505@22 {
- compatible = "nxp,pca9554";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-/delete-node/ &i2c1;
-/delete-node/ &i2c2;
-/delete-node/ &uart2;
-
-&iomuxc {
- pinctrl_dspi1: dspi1grp {
- fsl,pins = <
- VF610_PAD_PTD5__DSPI1_CS0 0x1182
- VF610_PAD_PTD4__DSPI1_CS1 0x1182
- VF610_PAD_PTC6__DSPI1_SIN 0x1181
- VF610_PAD_PTC7__DSPI1_SOUT 0x1182
- VF610_PAD_PTC8__DSPI1_SCK 0x1182
- >;
- };
-
- pinctrl_esdhc0: esdhc0grp {
- fsl,pins = <
- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
- >;
- };
-
- pinctrl_leds_debug: pinctrl-leds-debug {
- fsl,pins = <
- VF610_PAD_PTD3__GPIO_82 0x31c2
- >;
- };
-};
diff --git a/arch/arm/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/dts/vf610-zii-ssmb-spu3.dts
new file mode 100644
index 0000000000..e030109ce2
--- /dev/null
+++ b/arch/arm/dts/vf610-zii-ssmb-spu3.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <arm/vf610-zii-ssmb-spu3.dts>
+
+#include "vf610-zii-dev.dtsi"
diff --git a/arch/arm/dts/vf610.dtsi b/arch/arm/dts/vf610.dtsi
new file mode 100644
index 0000000000..3060031b8a
--- /dev/null
+++ b/arch/arm/dts/vf610.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Two aliases missing in upstream DT needed to make VFxxx's SD/MMC
+ * device naming scheme consistent with the rest of i.MX (which the
+ * following aliases from upstream.
+ */
+
+/ {
+ aliases {
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
+ };
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-22 18:47:11 +0000