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-rw-r--r--arch/arm/dts/Makefile6
-rw-r--r--arch/arm/dts/am335x-afi-gf.dts4
-rw-r--r--arch/arm/dts/am335x-baltos-minimal.dts4
-rw-r--r--arch/arm/dts/am335x-phytec-phycard-som.dtsi4
-rw-r--r--arch/arm/dts/am335x-phytec-phycore-som.dtsi4
-rw-r--r--arch/arm/dts/am335x-phytec-phyflex-som.dtsi4
-rw-r--r--arch/arm/dts/fsl-ls1046a-rdb.dts98
-rw-r--r--arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts240
-rw-r--r--arch/arm/dts/fsl-tqmls1046a.dtsi54
-rw-r--r--arch/arm/dts/imx6qdl-phytec-pfla02.dtsi17
-rw-r--r--arch/arm/dts/imx6qdl-zii-rdu2.dtsi126
-rw-r--r--arch/arm/dts/imx8mq-phytec-phycore-som.dts13
-rw-r--r--arch/arm/dts/imx8mq.dtsi135
-rw-r--r--arch/arm/dts/stm32mp157a-dk1.dts62
-rw-r--r--arch/arm/dts/stm32mp157c-dk2.dts14
-rw-r--r--arch/arm/dts/stm32mp157c.dtsi7
-rw-r--r--arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts459
-rw-r--r--arch/arm/dts/vf610-zii-scu4-aib.dts21
-rw-r--r--arch/arm/dts/vf610-zii-spb4.dts16
-rw-r--r--arch/arm/dts/vf610-zii-spb4.dtsi365
20 files changed, 1022 insertions, 631 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f989df6b0c..1c6129816d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -89,6 +89,7 @@ pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o \
imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \
imx6q-h100.dtb.o
+pbl-dtb-$(CONFIG_MACH_STM32MP157C_DK2) += stm32mp157c-dk2.dtb.o
pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
pbl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
@@ -123,7 +124,8 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
vf610-zii-dev-rev-c.dtb.o \
vf610-zii-cfu1.dtb.o \
vf610-zii-ssmb-spu3.dtb.o \
- vf610-zii-scu4-aib-rev-c.dtb.o
+ vf610-zii-scu4-aib.dtb.o \
+ vf610-zii-spb4.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
@@ -131,5 +133,7 @@ pbl-dtb-$(CONFIG_MACH_XILINX_ZCU104) += zynqmp-zcu104-revA.dtb.o
pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
pbl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
+pbl-dtb-$(CONFIG_MACH_LS1046ARDB) += fsl-ls1046a-rdb.dtb.o
+pbl-dtb-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/arm/dts/am335x-afi-gf.dts b/arch/arm/dts/am335x-afi-gf.dts
index d0860b8905..961fe2e241 100644
--- a/arch/arm/dts/am335x-afi-gf.dts
+++ b/arch/arm/dts/am335x-afi-gf.dts
@@ -367,10 +367,6 @@
status = "okay";
};
-&phy_sel {
- rmii-clock-ext;
-};
-
&am33xx_pinmux {
dcan0_pins: pinmux_dcan0_pins {
pinctrl-single,pins = <
diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts
index f939cf6406..137c177b2f 100644
--- a/arch/arm/dts/am335x-baltos-minimal.dts
+++ b/arch/arm/dts/am335x-baltos-minimal.dts
@@ -423,10 +423,6 @@
dual_emac_res_vlan = <2>;
};
-&phy_sel {
- rmii-clock-ext = <1>;
-};
-
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi
index 2320ca1807..1d45d60dc0 100644
--- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi
@@ -128,10 +128,6 @@
};
};
-&phy_sel {
- rmii-clock-ext;
-};
-
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rmii";
diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
index 0601f5ab7b..ae3f70acdd 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
@@ -250,10 +250,6 @@
};
};
-&phy_sel {
- rmii-clock-ext;
-};
-
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rmii";
diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
index 4d0a913988..0325c81346 100644
--- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi
@@ -207,10 +207,6 @@
};
};
-&phy_sel {
- rmii-clock-ext;
-};
-
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii";
diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
new file mode 100644
index 0000000000..e16948bc8a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/fsl-ls1046a-rdb.dts>
+
+/ {
+ chosen {
+ stdout-path = &duart0;
+
+ environment {
+ compatible = "barebox,environment";
+ device-path = &environment_sd;
+ };
+ };
+
+ aliases {
+ mmc0 = &esdhc;
+ };
+};
+
+&esdhc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ environment_sd: partition@200000 {
+ label = "barebox-environment";
+ reg = <0x200000 0x20000>;
+ };
+};
+
+&fman0 {
+ ethernet@e0000 {
+ status = "disabled";
+ };
+
+ ethernet@e2000 {
+ status = "disabled";
+ };
+
+ ethernet@e4000 {
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@e6000 {
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@e8000 {
+ };
+
+ ethernet@ea000 {
+ };
+
+ ethernet@f0000 {
+ };
+
+ ethernet@f2000 {
+ };
+
+ mdio@fc000 {
+ };
+
+ mdio@fd000 {
+ };
+
+ mdio@e1000 {
+ status = "disabled";
+ };
+
+ mdio@e3000 {
+ status = "disabled";
+ };
+
+ mdio@e5000 {
+ status = "disabled";
+ };
+
+ mdio@e7000 {
+ status = "disabled";
+ };
+
+ mdio@e9000 {
+ status = "disabled";
+ };
+
+ mdio@eb000 {
+ status = "disabled";
+ };
+
+ mdio@f1000 {
+ status = "disabled";
+ };
+
+ mdio@f3000 {
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
new file mode 100644
index 0000000000..f21479eef8
--- /dev/null
+++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for TQMLS1046A SoM on MBLS10xxA from TQ
+ *
+ * Copyright 2018 TQ-Systems GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "fsl-tqmls1046a.dtsi"
+
+/ {
+ model = "TQ TQMLS1046A SoM on MBLS10xxA board";
+ compatible = "tqc,tqmls1046a", "fsl,ls1046a";
+
+ aliases {
+ serial0 = &duart0;
+ serial1 = &duart1;
+ mmc0 = &esdhc;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ gpio-keys,name = "gpio-keys";
+ poll-interval = <100>;
+ autorepeat;
+
+ button0 {
+ label = "button0";
+ gpios = <&gpioexp3 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F1>;
+ };
+
+ button1 {
+ label = "button1";
+ gpios = <&gpioexp3 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F2>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user {
+ gpios = <&gpioexp3 13 GPIO_ACTIVE_LOW>;
+ label = "led:user";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+};
+
+
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9544";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+
+ gpioexp1: pca9555@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioexp2: pca9555@21 {
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioexp3: pca9555@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+ };
+};
+
+&usb1 {
+ dr_mode = "otg";
+};
+
+#include <arm64/freescale/fsl-ls1046-post.dtsi>
+#include <dt-bindings/net/ti-dp83867.h>
+
+&fman0 {
+ status = "okay";
+
+ ethernet@e0000 {
+ status = "disabled";
+ };
+
+ ethernet@e2000 {
+ phy-handle = <&qsgmii1_phy2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e4000 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii";
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@e6000 {
+ phy-handle = <&rgmii_phy2>;
+ phy-connection-type = "rgmii";
+ phy-mode = "rgmii-id";
+ };
+
+ ethernet@e8000 {
+ status = "disabled";
+ };
+
+ ethernet@ea000 {
+ phy-handle = <&qsgmii2_phy2>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f0000 {
+ phy-handle = <&qsgmii1_phy1>;
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@f2000 {
+ phy-handle = <&qsgmii2_phy1>;
+ phy-connection-type = "sgmii";
+ };
+
+ mdio@e1000 {
+ status = "disabled";
+ };
+
+ mdio@e3000 {
+ status = "disabled";
+ };
+
+ mdio@e5000 {
+ status = "disabled";
+ };
+
+ mdio@e7000 {
+ status = "disabled";
+ };
+
+ mdio@e9000 {
+ status = "disabled";
+ };
+
+ mdio@eb000 {
+ status = "disabled";
+ };
+
+ mdio@f1000 {
+ status = "disabled";
+ };
+
+ mdio@f3000 {
+ status = "disabled";
+ };
+
+ mdio@fc000 {
+ rgmii_phy1: ethernet-phy@0e {
+ reg = <0x0e>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ };
+
+ qsgmii1_phy1: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ qsgmii1_phy2: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+ };
+
+ mdio@fd000 {
+ rgmii_phy2: ethernet-phy@0c {
+ reg = <0x0c>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ };
+
+ qsgmii2_phy1: ethernet-phy@00 {
+ reg = <0x00>;
+ };
+
+ qsgmii2_phy2: ethernet-phy@01 {
+ reg = <0x01>;
+ };
+ };
+};
diff --git a/arch/arm/dts/fsl-tqmls1046a.dtsi b/arch/arm/dts/fsl-tqmls1046a.dtsi
new file mode 100644
index 0000000000..4717e66857
--- /dev/null
+++ b/arch/arm/dts/fsl-tqmls1046a.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for LS1046A based SoM of TQ
+ *
+ * Copyright 2018 TQ-Systems GmbH
+ */
+
+#include <arm64/freescale/fsl-ls1046a.dtsi>
+
+&i2c0 {
+ status = "okay";
+
+ temp-sensor@18 {
+ compatible = "jc42";
+ reg = <0x18>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c256";
+ reg = <0x57>;
+ };
+};
+
+&qspi {
+ num-cs = <2>;
+ bus-num = <0>;
+ status = "okay";
+
+ qflash0: mx66u51235f@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <108000000>;
+ reg = <0>;
+ };
+
+ qflash1: mx66u51235f@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <108000000>;
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ };
+};
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index aba86a3ec1..f0bba2e098 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -86,23 +86,6 @@
};
};
-&fec {
- phy-handle = <&ethphy>;
- phy-reset-duration = <10>; /* in msecs */
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@3 {
- reg = <3>;
-
- txc-skew-ps = <1680>;
- rxc-skew-ps = <1860>;
- };
- };
-};
-
&gpmi {
partitions {
compatible = "fixed-partitions";
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index fea219f1e1..bfc75ba606 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -49,6 +49,11 @@
};
};
+ device-info {
+ nvmem-cells = <&lru_part_number>;
+ nvmem-cell-names = "lru-part-number";
+ };
+
aliases {
ethernet0 = &fec;
ethernet1 = &i210;
@@ -59,8 +64,96 @@
*/
switch-eeprom = &switch;
};
-};
+ panel {
+ compatible = "simple-panel";
+ /* Timings for all supported panels, the correct one is enabled
+ * after the board data has been retrieved from the environment
+ * controller
+ */
+
+ display-timings {
+ innolux-g121i1-l01 {
+ compatible = "innolux,g121i1-l01";
+
+ hback-porch = <79>;
+ hfront-porch = <80>;
+ hactive = <1280>;
+ hsync-len = <1>;
+ vback-porch = <11>;
+ vfront-porch = <11>;
+ vactive = <800>;
+ vsync-len = <1>;
+ clock-frequency = <71000000>;
+ };
+ nec-nl12880bc20-05 {
+ compatible = "nec,nl12880bc20-05";
+
+ hback-porch = <100>;
+ hfront-porch = <30>;
+ hactive = <1280>;
+ hsync-len = <30>;
+ vback-porch = <11>;
+ vfront-porch = <5>;
+ vactive = <800>;
+ vsync-len = <7>;
+ clock-frequency = <71000000>;
+ };
+ auo-g133han01 {
+ compatible = "auo,g133han01";
+
+ hback-porch = <88>;
+ hfront-porch = <58>;
+ hactive = <1920>;
+ hsync-len = <42>;
+ vback-porch = <14>;
+ vfront-porch = <8>;
+ vactive = <1080>;
+ vsync-len = <14>;
+ clock-frequency = <141200000>;
+ };
+ auo-g185han01 {
+ compatible = "auo,g185han01";
+
+ hback-porch = <44>;
+ hfront-porch = <60>;
+ hactive = <1920>;
+ hsync-len = <24>;
+ vback-porch = <5>;
+ vfront-porch = <10>;
+ vactive = <1080>;
+ vsync-len = <5>;
+ clock-frequency = <144000000>;
+ };
+ nlt-nl192108ac18-02d {
+ compatible = "nlt,nl192108ac18-02d";
+
+ hback-porch = <120>;
+ hfront-porch = <100>;
+ hactive = <1920>;
+ hsync-len = <60>;
+ vback-porch = <10>;
+ vfront-porch = <30>;
+ vactive = <1080>;
+ vsync-len = <5>;
+ clock-frequency = <148350000>;
+ };
+ auo-p320hvn03 {
+ compatible = "auo,p320hvn03";
+
+ hback-porch = <50>;
+ hfront-porch = <50>;
+ hactive = <1920>;
+ hsync-len = <40>;
+ vback-porch = <17>;
+ vfront-porch = <17>;
+ vactive = <1080>;
+ vsync-len = <11>;
+ clock-frequency = <148500000>;
+ };
+ };
+ };
+};
&uart4 {
rave-sp {
@@ -73,6 +166,11 @@
};
eeprom@a4 {
+ lru_part_number: lru-part-number@21 {
+ reg = <0x21 15>;
+ read-only;
+ };
+
boot_source: boot-source@83 {
reg = <0x83 1>;
};
@@ -110,12 +208,38 @@
nvmem-cell-names = "mac-address";
};
+&i2c1 {
+ edp-bridge@68 {
+ pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ tc358767_in: endpoint {
+ remote-endpoint = <&disp0_out>;
+ };
+ };
+ };
+ };
+};
+
&i2c2 {
temp-sense@48 {
barebox,sensor-name = "Temp Sensor 1";
};
};
+&ipu1_di0_disp0 {
+ remote-endpoint = <&tc358767_in>;
+};
+
+&ldb {
+ lvds-channel@0 {
+ fsl,data-width = <24>;
+ };
+};
+
&i210 {
nvmem-cells = <&mac_address_1>;
nvmem-cell-names = "mac-address";
diff --git a/arch/arm/dts/imx8mq-phytec-phycore-som.dts b/arch/arm/dts/imx8mq-phytec-phycore-som.dts
index de8ed1873f..736c007f49 100644
--- a/arch/arm/dts/imx8mq-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx8mq-phytec-phycore-som.dts
@@ -205,6 +205,13 @@
};
};
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@@ -325,4 +332,10 @@
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index d6a4c715bd..d1d8bdaa0e 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -16,7 +16,6 @@
gpio4 = &gpio5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
- spi0 = &ecspi1;
};
thermal-zones {
@@ -113,136 +112,6 @@
reg = <0x30390000 0x10000>;
#reset-cells = <1>;
};
-
- gpc: gpc@303a0000 {
- compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc";
- reg = <0x303a0000 0x10000>;
- #power-domain-cells = <1>;
-
- interrupt-controller;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
-
- pgc {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /*
- * As per comment in ATF source code:
- *
- * PCIE1 and PCIE2 share the
- * same reset signal, if we power
- * down PCIE2, PCIE1 will be held
- * in reset too.
- *
- * So instead of creating two
- * separate power domains for
- * PCIE1 and PCIE2. We create
- * a link between 1 and 10 and
- * use what was supposed to be
- * domain 1 as a shared PCIE
- * power domain powering both
- * PCIE1 and PCIE2 at the same
- * time
- */
- pgc_pcie_phy: gpc_power_domain@1 {
- #power-domain-cells = <0>;
- reg = <1>;
- power-domains = <&pgc_pcie2_phy>;
- };
-
- pgc_otg1: power-domain@2 {
- #power-domain-cells = <0>;
- reg = <2>;
- };
-
- pgc_otg2: power-domain@3 {
- #power-domain-cells = <0>;
- reg = <3>;
- };
-
- pgc_pcie2_phy: gpc_power_domain@10 {
- #power-domain-cells = <0>;
- reg = <10>;
- };
- };
- };
- };
-
- bus@30800000 {
- ecspi1: ecspi@30820000 {
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
- <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
- };
-
-
- usb_dwc3_0: usb@38100000 {
- compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
- reg = <0x38100000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_USB_BUS>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>,
- <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
- clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
- <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <500000000>, <100000000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy0>, <&usb3_phy0>;
- phy-names = "usb2-phy", "usb3-phy";
- power-domains = <&pgc_otg1>;
- status = "disabled";
- };
-
- usb3_phy0: phy@381f0040 {
- compatible = "fsl,imx8mq-usb-phy";
- reg = <0x381f0040 0x40>;
- clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
- clock-names = "phy";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb_dwc3_1: usb@38200000 {
- compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
- reg = <0x38200000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_USB_BUS>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>,
- <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
- clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
- <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <500000000>, <100000000>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy1>, <&usb3_phy1>;
- phy-names = "usb2-phy", "usb3-phy";
- power-domains = <&pgc_otg2>;
- status = "disabled";
- };
-
- usb3_phy1: phy@382f0040 {
- compatible = "fsl,imx8mq-usb-phy";
- reg = <0x382f0040 0x40>;
- clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
- clock-names = "phy";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <0>;
- status = "disabled";
};
pcie0: pcie@33800000 {
@@ -266,7 +135,7 @@
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
- power-domains = <&pgc_pcie_phy>;
+ power-domains = <&pgc_pcie1>;
resets = <&src IMX8MQ_RESET_PCIEPHY>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
@@ -295,7 +164,7 @@
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
fsl,max-link-speed = <2>;
- power-domains = <&pgc_pcie_phy>;
+ power-domains = <&pgc_pcie1>;
resets = <&src IMX8MQ_RESET_PCIEPHY2>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
new file mode 100644
index 0000000000..741284a444
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include <arm/stm32mp157c.dtsi>
+#include <arm/stm32mp157-pinctrl.dtsi>
+
+/ {
+ model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
+ compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = &ethernet0;
+ serial0 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sram: sram@10050000 {
+ compatible = "mmio-sram";
+ reg = <0x10050000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10050000 0x10000>;
+
+ dma_pool: dma_pool@0 {
+ reg = <0x0 0x10000>;
+ pool;
+ };
+ };
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
new file mode 100644
index 0000000000..7565cabc3d
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157a-dk1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
+ compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
+};
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
new file mode 100644
index 0000000000..fa0d00ff02
--- /dev/null
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -0,0 +1,7 @@
+
+/ {
+ clocks {
+ /* Needed to let barebox find the clock nodes */
+ compatible = "simple-bus";
+ };
+};
diff --git a/arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts b/arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts
deleted file mode 100644
index 12c2568bcc..0000000000
--- a/arch/arm/dts/vf610-zii-scu4-aib-rev-c.dts
+++ /dev/null
@@ -1,459 +0,0 @@
-/*
- * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
- *
- * Based on an original 'vf610-twr.dts' which is Copyright 2015,
- * Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include <arm/vf610-zii-dev.dtsi>
-
-#include "vf610-zii-dev.dtsi"
-
-/ {
- model = "ZII VF610 SCU4 AIB, Rev C";
- compatible = "zii,vf610scu4-aib-c", "zii,vf610dev", "fsl,vf610";
-
- chosen {
- bootargs = "console=ttyLP0,115200n8";
- };
-
- gpio-leds {
- debug {
- gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- mdio-mux {
- compatible = "mdio-mux-gpio";
- pinctrl-0 = <&pinctrl_mdio_mux>;
- pinctrl-names = "default";
- gpios = <&gpio4 4 GPIO_ACTIVE_HIGH
- &gpio4 5 GPIO_ACTIVE_HIGH
- &gpio3 30 GPIO_ACTIVE_HIGH
- &gpio3 31 GPIO_ACTIVE_HIGH>;
- mdio-parent-bus = <&mdio1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio_mux_1: mdio@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio_mux_2: mdio@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio_mux_4: mdio@4 {
- reg = <4>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio_mux_8: mdio@8 {
- reg = <8>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- spi2 {
- compatible = "spi-gpio";
- pinctrl-0 = <&pinctrl_dspi2>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&gpio2 3 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
- num-chipselects = <1>;
-
- at93c46d@0 {
- compatible = "atmel,at93c46d";
- #address-cells = <0>;
- #size-cells = <0>;
- reg = <0>;
- spi-max-frequency = <500000>;
- spi-cs-high;
- data-size = <16>;
- select-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&dspi0 {
- pinctrl-0 = <&pinctrl_dspi0>, <&pinctrl_dspi0_cs_4_5>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&dspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dspi1>;
- status = "okay";
-
- m25p128@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p128", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partition@0 {
- label = "m25p128-0";
- reg = <0x0 0x01000000>;
- };
- };
-
- m25p128@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p128", "jedec,spi-nor";
- reg = <1>;
- spi-max-frequency = <50000000>;
-
- partition@0 {
- label = "m25p128-1";
- reg = <0x0 0x01000000>;
- };
- };
-};
-
-&esdhc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_esdhc0>;
- bus-width = <8>;
- status = "okay";
-};
-
-&fec0 {
- status = "disabled";
-};
-
-&i2c0 {
- /* Reset Signals */
- gpio5: pca9505@20 {
- compatible = "nxp,pca9554";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- /* Board Revision */
- gpio6: pca9505@22 {
- compatible = "nxp,pca9554";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&i2c1 {
- /* Wireless 2 */
- gpio8: pca9554@18 {
- compatible = "nxp,pca9557";
- reg = <0x18>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- /* Wireless 1 */
- gpio7: pca9554@24 {
- compatible = "nxp,pca9554";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- /* AIB voltage monitor */
- adt7411@4a {
- compatible = "adi,adt7411";
- reg = <0x4a>;
- };
-};
-
-&i2c2 {
- /* FIB voltage monitor */
- adt7411@4a {
- compatible = "adi,adt7411";
- reg = <0x4a>;
- };
-
- lm75_swb {
- compatible = "national,lm75";
- reg = <0x4e>;
- };
-
- lm75_swa {
- compatible = "national,lm75";
- reg = <0x4f>;
- };
-
- /* FIB Nameplate */
- at24c08@57 {
- compatible = "atmel,24c08";
- reg = <0x57>;
- };
-
- tca9548@70 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x70>;
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- sff0: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- sff1: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- sff2: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
-
- sff3: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@5 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <5>;
-
- sff4: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
- };
-
-
- tca9548@71 {
- compatible = "nxp,pca9548";
- reg = <0x71>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- sff5: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- sff6: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- sff7: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
-
- };
-
- i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
-
- sff8: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
-
- i2c@5 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <5>;
-
- sff9: at24c04@50 {
- compatible = "atmel,24c04";
- reg = <0x50>;
- };
- };
- };
-};
-
-&uart1 {
- linux,rs485-enabled-at-boot-time;
- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_rts>;
-};
-
-&uart2 {
- linux,rs485-enabled-at-boot-time;
- pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart2_rts>;
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpo_public>;
-
-
- pinctrl_gpo_public: gpopubgrp {
- fsl,pins = <
- VF610_PAD_PTE2__GPIO_107 0x2062
- VF610_PAD_PTE3__GPIO_108 0x2062
- VF610_PAD_PTE4__GPIO_109 0x2062
- VF610_PAD_PTE5__GPIO_110 0x2062
- VF610_PAD_PTE6__GPIO_111 0x2062
- >;
- };
-
- pinctrl_dspi0_cs_4_5: dspi0grp-cs-4-5 {
- fsl,pins = <
- VF610_PAD_PTB13__DSPI0_CS4 0x1182
- VF610_PAD_PTB12__DSPI0_CS5 0x1182
- >;
- };
-
- pinctrl_dspi1: dspi1grp {
- fsl,pins = <
- VF610_PAD_PTD5__DSPI1_CS0 0x1182
- VF610_PAD_PTD4__DSPI1_CS1 0x1182
- VF610_PAD_PTC6__DSPI1_SIN 0x1181
- VF610_PAD_PTC7__DSPI1_SOUT 0x1182
- VF610_PAD_PTC8__DSPI1_SCK 0x1182
- >;
- };
-
- pinctrl_esdhc0: esdhc0grp {
- fsl,pins = <
- VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
- VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
- VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
- VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
- VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
- VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
- VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
- VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
- VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
- VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- VF610_PAD_PTA30__I2C3_SCL 0x37ff
- VF610_PAD_PTA31__I2C3_SDA 0x37ff
- >;
- };
-
- pinctrl_leds_debug: pinctrl-leds-debug {
- fsl,pins = <
- VF610_PAD_PTB26__GPIO_96 0x31c2
- >;
- };
-
- pinctrl_uart1_rts: uart1grp-rts {
- fsl,pins = <
- VF610_PAD_PTB25__UART1_RTS 0x2062
- >;
- };
-
- pinctrl_uart2_rts: uart2grp-rts {
- fsl,pins = <
- VF610_PAD_PTD2__UART2_RTS 0x2062
- >;
- };
-
- pinctrl_mdio_mux: pinctrl-mdio-mux {
- fsl,pins = <
- VF610_PAD_PTE27__GPIO_132 0x31c2
- VF610_PAD_PTE28__GPIO_133 0x31c2
- VF610_PAD_PTE21__GPIO_126 0x31c2
- VF610_PAD_PTE22__GPIO_127 0x31c2
- >;
- };
-};
diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts
new file mode 100644
index 0000000000..abe9e14fd7
--- /dev/null
+++ b/arch/arm/dts/vf610-zii-scu4-aib.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright (C) 2016-2018 Zodiac Inflight Innovations
+
+#include <arm/vf610-zii-scu4-aib.dts>
+
+#include "vf610-zii-dev.dtsi"
+
+/ {
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shares DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch0-eeprom = &switch0;
+ switch1-eeprom = &switch1;
+ switch2-eeprom = &switch2;
+ switch3-eeprom = &switch3;
+ };
+};
diff --git a/arch/arm/dts/vf610-zii-spb4.dts b/arch/arm/dts/vf610-zii-spb4.dts
new file mode 100644
index 0000000000..e7d35d0e69
--- /dev/null
+++ b/arch/arm/dts/vf610-zii-spb4.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "vf610-zii-spb4.dtsi"
+
+#include "vf610-zii-dev.dtsi"
+
+/ {
+ aliases {
+ /*
+ * NVMEM device corresponding to EEPROM attached to
+ * the switch shared DT node with it, so we use that
+ * fact to create a desirable naming
+ */
+ switch-eeprom = &switch0;
+ };
+};
diff --git a/arch/arm/dts/vf610-zii-spb4.dtsi b/arch/arm/dts/vf610-zii-spb4.dtsi
new file mode 100644
index 0000000000..f618ca45ee
--- /dev/null
+++ b/arch/arm/dts/vf610-zii-spb4.dtsi
@@ -0,0 +1,365 @@
+/*
+ * This is a copy of DTS file from Linux. Remove it once the same file
+ * is availible via dts/src/arm
+ */
+
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/*
+ * Device tree file for ZII's SPB4 board
+ *
+ * SPB - Seat Power Box
+ *
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+#include <arm/vf610.dtsi>
+
+/ {
+ model = "ZII VF610 SPB4 Board";
+ compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pinctrl_leds_debug>;
+ pinctrl-names = "default";
+
+ led-debug {
+ label = "zii:green:debug1";
+ gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ max-brightness = <1>;
+ };
+ };
+
+ reg_vcc_3v3_mcu: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_mcu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc0 {
+ vref-supply = <&reg_vcc_3v3_mcu>;
+ status = "okay";
+};
+
+&adc1 {
+ vref-supply = <&reg_vcc_3v3_mcu>;
+ status = "okay";
+};
+
+&dspi1 {
+ bus-num = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dspi1>;
+ status = "okay";
+
+ m25p128@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&edma0 {
+ status = "okay";
+};
+
+&edma1 {
+ status = "okay";
+};
+
+&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc0>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ keep-power-in-suspend;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ bus-width = <4>;
+ no-sdio;
+ status = "okay";
+};
+
+&fec1 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ status = "okay";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+
+ mdio1: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ switch0: switch0@0 {
+ compatible = "marvell,mv88e6190";
+ pinctrl-0 = <&pinctrl_gpio_switch0>;
+ pinctrl-names = "default";
+ reg = <0>;
+ eeprom-length = <65536>;
+ reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&fec1>;
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "eth_cu_1000_1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "eth_cu_1000_2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "eth_cu_1000_3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "eth_cu_1000_4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "eth_cu_1000_5";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "eth_cu_1000_6";
+ };
+ };
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ status = "okay";
+
+ gpio6: pca9505@22 {
+ compatible = "nxp,pca9554";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ at24c04@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ label = "nameplate";
+ };
+
+ at24c04@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+};
+
+&snvsrtc {
+ status = "disabled";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+
+ rave-sp {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+
+ eeprom@a3 {
+ compatible = "zii,rave-sp-eeprom";
+ reg = <0xa3 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ zii,eeprom-name = "main-eeprom";
+ };
+ };
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&wdoga5 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_dspi1: dspi1grp {
+ fsl,pins = <
+ VF610_PAD_PTD5__DSPI1_CS0 0x1182
+ VF610_PAD_PTD4__DSPI1_CS1 0x1182
+ VF610_PAD_PTC6__DSPI1_SIN 0x1181
+ VF610_PAD_PTC7__DSPI1_SOUT 0x1182
+ VF610_PAD_PTC8__DSPI1_SCK 0x1182
+ >;
+ };
+
+ pinctrl_esdhc0: esdhc0grp {
+ fsl,pins = <
+ VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
+ VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
+ VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
+ VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
+ VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
+ VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
+ VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
+ VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
+ VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
+ VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
+ VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
+ VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
+ VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
+ VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
+ VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ VF610_PAD_PTA6__RMII_CLKIN 0x30d1
+ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
+ VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
+ VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
+ VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
+ VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
+ VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
+ VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
+ VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
+ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
+ >;
+ };
+
+ pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
+ fsl,pins = <
+ VF610_PAD_PTE2__GPIO_107 0x31c2
+ VF610_PAD_PTB28__GPIO_98 0x219d
+ >;
+ };
+
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ VF610_PAD_PTB14__I2C0_SCL 0x37ff
+ VF610_PAD_PTB15__I2C0_SDA 0x37ff
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ VF610_PAD_PTB16__I2C1_SCL 0x37ff
+ VF610_PAD_PTB17__I2C1_SDA 0x37ff
+ >;
+ };
+
+ pinctrl_leds_debug: pinctrl-leds-debug {
+ fsl,pins = <
+ VF610_PAD_PTD3__GPIO_82 0x31c2
+ >;
+ };
+
+ pinctrl_uart0: uart0grp {
+ fsl,pins = <
+ VF610_PAD_PTB10__UART0_TX 0x21a2
+ VF610_PAD_PTB11__UART0_RX 0x21a1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ VF610_PAD_PTB23__UART1_TX 0x21a2
+ VF610_PAD_PTB24__UART1_RX 0x21a1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ VF610_PAD_PTD0__UART2_TX 0x21a2
+ VF610_PAD_PTD1__UART2_RX 0x21a1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ VF610_PAD_PTA30__UART3_TX 0x21a2
+ VF610_PAD_PTA31__UART3_RX 0x21a1
+ >;
+ };
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 19:26:15 +0000