diff options
Diffstat (limited to 'arch/arm/dts')
24 files changed, 549 insertions, 186 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 010408bd59..957b32945c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -63,10 +63,13 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ imx6qp-phytec-phycore-som-nand.dtb.o \ imx6dl-phytec-phycore-som-nand.dtb.o \ + imx6dl-phytec-phycore-som-lc-nand.dtb.o \ imx6dl-phytec-phycore-som-emmc.dtb.o \ - imx6ul-phytec-phycore-som.dtb.o \ - imx6ull-phytec-phycore-som-lc.dtb.o \ - imx6ull-phytec-phycore-som.dtb.o + imx6dl-phytec-phycore-som-lc-emmc.dtb.o \ + imx6ul-phytec-phycore-som-nand.dtb.o \ + imx6ull-phytec-phycore-som-lc-nand.dtb.o \ + imx6ull-phytec-phycore-som-nand.dtb.o \ + imx6ull-phytec-phycore-som-emmc.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o diff --git a/arch/arm/dts/am335x-phytec-state.dtsi b/arch/arm/dts/am335x-phytec-state.dtsi index 1f61cf5a2e..af4da4ea64 100644 --- a/arch/arm/dts/am335x-phytec-state.dtsi +++ b/arch/arm/dts/am335x-phytec-state.dtsi @@ -23,6 +23,7 @@ compatible = "barebox,state"; backend-type = "raw"; backend = <&backend_state_mac_eeprom>; + backend-storage-type = "direct"; backend-stridesize = <40>; keep-previous-content; @@ -44,6 +45,7 @@ compatible = "barebox,state"; backend-type = "raw"; backend = <&backend_state_update_eeprom>; + backend-storage-type = "direct"; backend-stridesize = <54>; keep-previous-content; diff --git a/arch/arm/dts/am33xx-clocks-strip.dtsi b/arch/arm/dts/am33xx-clocks-strip.dtsi index 706e1c9712..e832616765 100644 --- a/arch/arm/dts/am33xx-clocks-strip.dtsi +++ b/arch/arm/dts/am33xx-clocks-strip.dtsi @@ -8,8 +8,6 @@ */ /delete-node/ &adc_tsc_fck; -/delete-node/ &dcan0_fck; -/delete-node/ &dcan1_fck; /delete-node/ &mcasp0_fck; /delete-node/ &mcasp1_fck; /delete-node/ &smartreflex0_fck; diff --git a/arch/arm/dts/bcm2837-rpi-cm3.dts b/arch/arm/dts/bcm2837-rpi-cm3.dts index cfbffe175f..01c1f9a677 100644 --- a/arch/arm/dts/bcm2837-rpi-cm3.dts +++ b/arch/arm/dts/bcm2837-rpi-cm3.dts @@ -9,10 +9,3 @@ reg = <0x0 0x0>; }; }; - -&sdhci { - pinctrl-0 = <&emmc_gpio48>; - no-sd; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts index e602b77e99..21cbb5f944 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts @@ -15,6 +15,7 @@ #include <arm/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-state.dtsi" / { model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC"; @@ -30,7 +31,7 @@ }; ðphy { - max-speed = <100>; + max-speed = <1000>; }; &fec { diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts new file mode 100644 index 0000000000..b8efb95ee0 --- /dev/null +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-emmc.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH, + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/dts-v1/; + +#include <arm/imx6dl.dtsi> +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-state.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 DualLite/SOLO with eMMC low-cost"; + compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl"; +}; + +&ecspi1 { + status = "okay"; +}; + +&eeprom { + status = "okay"; +}; + +ðphy { + max-speed = <100>; +}; + +&fec { + status = "okay"; +}; + +&flash { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc4 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts new file mode 100644 index 0000000000..4d38d1698a --- /dev/null +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-lc-nand.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH, + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/dts-v1/; + +#include <arm/imx6dl.dtsi> +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-state.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 Duallite/SOLO with NAND low-cost"; + compatible = "phytec,imx6dl-pcm058-nand", "fsl,imx6dl"; +}; + +&eeprom { + status = "okay"; +}; + +ðphy { + max-speed = <100>; +}; + +&fec { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts index 77f143438b..3ad3723d28 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -14,6 +14,7 @@ #include <arm/imx6dl.dtsi> #include "imx6dl.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-state.dtsi" / { model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND"; @@ -25,7 +26,7 @@ }; ðphy { - max-speed = <100>; + max-speed = <1000>; }; &fec { diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts index 94a70389f0..7a86d5b94d 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -14,6 +14,7 @@ #include <arm/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-state.dtsi" / { model = "Phytec phyCORE-i.MX6 Quad with eMMC"; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts index 6d82ec34d6..96d1de224c 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -14,6 +14,7 @@ #include <arm/imx6q.dtsi> #include "imx6q.dtsi" #include "imx6qdl-phytec-phycore-som.dtsi" +#include "imx6qdl-phytec-state.dtsi" / { model = "Phytec phyCORE-i.MX6 Quad with NAND"; diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index 8fde27bd0c..1d39368165 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -110,6 +110,7 @@ phy-handle = <ðphy>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; /* in msecs */ status = "disabled"; mdio { diff --git a/arch/arm/dts/imx6qdl-phytec-state.dtsi b/arch/arm/dts/imx6qdl-phytec-state.dtsi new file mode 100644 index 0000000000..1522b92be1 --- /dev/null +++ b/arch/arm/dts/imx6qdl-phytec-state.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH, + * Author: Daniel Schultz <d.schultz@phytec.de> + */ + +/ { + aliases { + state = &state; + }; + + state: imx6qdl_phytec_boot_state { + magic = <0x883b86a6>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&backend_update_eeprom>; + backend-storage-type = "direct"; + backend-stridesize = <54>; + + #address-cells = <1>; + #size-cells = <1>; + bootstate { + #address-cells = <1>; + #size-cells = <1>; + last_chosen { + reg = <0x0 0x4>; + type = "uint32"; + }; + system0 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x8 0x4>; + type = "uint32"; + default = <21>; + }; + ok { + reg = <0xc 0x4>; + type = "uint32"; + default = <0>; + }; + }; + system1 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x10 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x14 0x4>; + type = "uint32"; + default = <20>; + }; + ok { + reg = <0x18 0x4>; + type = "uint32"; + default = <0>; + }; + }; + }; + }; +}; + +&eeprom { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + backend_update_eeprom: state@0 { + reg = <0x0 0x100>; + label = "update-eeprom"; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts new file mode 100644 index 0000000000..67478e26dc --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-phycore-som-nand.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Christian Hemp <c.hemp@phytec.de> + */ + +/dts-v1/; + +#include <arm/imx6ul.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 Ultra Lite SOM with NAND"; + compatible = "phytec,imx6ul-pcl063-nand", "fsl,imx6ul"; +}; + +&fec1 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&state { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts deleted file mode 100644 index 6d1876702d..0000000000 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2016 PHYTEC Messtechnik GmbH - * Author: Christian Hemp <c.hemp@phytec.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include <arm/imx6ul.dtsi> -#include "imx6ul-phytec-phycore-som.dtsi" - -/ { - model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; - compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul"; -}; - -&fec1 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi index 964f91950d..c7c657bcd4 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi @@ -25,6 +25,12 @@ device-path = &usdhc1, "partname:barebox-environment"; status = "disabled"; }; + + environment-sd2 { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; }; }; @@ -79,7 +85,7 @@ clock-frequency = <100000>; status = "disabled"; - eeprom@52 { + eeprom: eeprom@52 { compatible = "cat,24c32"; reg = <0x52>; }; @@ -125,6 +131,27 @@ }; }; +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + non-removable; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + &iomuxc { pinctrl-names = "default"; @@ -132,16 +159,16 @@ pinctrl_enet1: enet1grp { fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 >; }; @@ -196,6 +223,21 @@ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ >; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; }; }; diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi b/arch/arm/dts/imx6ul-phytec-state.dtsi new file mode 100644 index 0000000000..78a32ed96b --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-state.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH, + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/ { + aliases { + state = &state; + }; + + state: imx6ul_phytec_boot_state { + magic = <0x883b86a6>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&backend_update_eeprom>; + backend-storage-type = "direct"; + backend-stridesize = <54>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + bootstate { + #address-cells = <1>; + #size-cells = <1>; + last_chosen { + reg = <0x0 0x4>; + type = "uint32"; + }; + system0 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x8 0x4>; + type = "uint32"; + default = <21>; + }; + ok { + reg = <0xc 0x4>; + type = "uint32"; + default = <0>; + }; + }; + system1 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x10 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x14 0x4>; + type = "uint32"; + default = <20>; + }; + ok { + reg = <0x18 0x4>; + type = "uint32"; + default = <0>; + }; + }; + }; + }; +}; + +&eeprom { + partitions { + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + backend_update_eeprom: state@0 { + reg = <0x0 0x100>; + label = "update-eeprom"; + }; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts new file mode 100644 index 0000000000..aa162cc42d --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-emmc.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/dts-v1/; + +#include <arm/imx6ull.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 ULL SOM with eMMC"; + compatible = "phytec,imx6ul-pcl063-emmc", "fsl,imx6ull"; +}; + +&fec1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts index 94a7830756..e6c588b449 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc-nand.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Copyright (C) 2019 PHYTEC Messtechnik GmbH * Author: Stefan Riedmueller <s.riedmueller@phytec.de> */ @@ -10,8 +10,8 @@ #include "imx6ul-phytec-phycore-som.dtsi" / { - model = "Phytec phyCORE-i.MX6 ULL SOM low-cost"; - compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull"; + model = "PHYTEC phyCORE-i.MX6 ULL SOM low-cost with NAND"; + compatible = "phytec,imx6ul-pcl063-nand", "fsl,imx6ull"; }; &fec1 { diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts new file mode 100644 index 0000000000..a5fa3e051c --- /dev/null +++ b/arch/arm/dts/imx6ull-phytec-phycore-som-nand.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/dts-v1/; + +#include <arm/imx6ull.dtsi> +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" + +/ { + model = "PHYTEC phyCORE-i.MX6 ULL SOM with NAND"; + compatible = "phytec,imx6ul-pcl063-nand", "fsl,imx6ull"; +}; + +&fec1 { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&state { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts deleted file mode 100644 index 4d73010131..0000000000 --- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2017 PHYTEC Messtechnik GmbH - * Author: Stefan Riedmueller <s.riedmueller@phytec.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; - -#include <arm/imx6ull.dtsi> -#include "imx6ul-phytec-phycore-som.dtsi" - -/ { - model = "Phytec phyCORE-i.MX6 ULL SOM"; - compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull"; -}; - -&fec1 { - status = "okay"; -}; - -&gpmi { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; -}; - -&usbotg1 { - status = "okay"; -}; - -&usbotg2 { - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index 741284a444..f2cafae66b 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -4,59 +4,5 @@ * Author: Alexandre Torgue <alexandre.torgue@st.com>. */ -/dts-v1/; - -#include "stm32mp157c.dtsi" -#include <arm/stm32mp157c.dtsi> -#include <arm/stm32mp157-pinctrl.dtsi> - -/ { - model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; - compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - serial0 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sram: sram@10050000 { - compatible = "mmio-sram"; - reg = <0x10050000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10050000 0x10000>; - - dma_pool: dma_pool@0 { - reg = <0x0 0x10000>; - pool; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - status = "okay"; -}; +#include <arm/stm32mp157a-dk1.dts> +#include "stm32mp157a-dk1.dtsi" diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp157a-dk1.dtsi new file mode 100644 index 0000000000..cd3d614d46 --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dk1.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@st.com>. + */ + +#include "stm32mp157c.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + led { + red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; + }; + + blue { + default-state = "on"; + }; + }; + + sram: sram@10050000 { + compatible = "mmio-sram"; + reg = <0x10050000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10050000 0x10000>; + + dma_pool: dma_pool@0 { + reg = <0x0 0x10000>; + pool; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 7565cabc3d..6e73162ea4 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -4,11 +4,5 @@ * Author: Alexandre Torgue <alexandre.torgue@st.com>. */ -/dts-v1/; - -#include "stm32mp157a-dk1.dts" - -/ { - model = "STMicroelectronics STM32MP157C-DK2 Discovery Board"; - compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; -}; +#include <arm/stm32mp157c-dk2.dts> +#include "stm32mp157a-dk1.dtsi" diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index fa0d00ff02..b97622c8d4 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -4,4 +4,19 @@ /* Needed to let barebox find the clock nodes */ compatible = "simple-bus"; }; + + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio11 = &gpioz; + }; }; |