diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91_pmc.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index bbbd497afa..4d60becefb 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -50,14 +50,19 @@ #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ +#define AT91_PMC_OSCOUNT_(x) ((x) << 8) +#define AT91_PMC_KEY_MASK (0xff << 16) /* MOR Writing Key */ +#define AT91_PMC_KEY (0x37 << 16) #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Frequency Measure Ready */ +#define AT91_PMC_RCMEAS (1 << 20) /* RC Oscillator Frequency Measure (write-only) */ +#define AT91_PMC_CCSS (1 << 24) /* Counter Clock Source Selection */ +#define AT91_PMC_CCSS_RC_OSC (0 << 24) /* MAINF counter clock is the RC oscillator. */ +#define AT91_PMC_CCSS_XTAL_OSC (1 << 24) /* MAINF counter clock is the crystal oscillator. */ #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ #define AT91_PMC_DIV (0xff << 0) /* Divider */ @@ -133,6 +138,7 @@ #define AT91_PMC_CSSMCK_MCK (1 << 8) #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ +#define AT91_PMC_MOSCXTS (1 << 0) /* Oscillator Startup Time */ #define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ #define AT91_PMC_SR 0x68 /* Status Register */ #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ @@ -148,6 +154,17 @@ #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ +#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ +#define AT91_PMC_ICPPLLA (0xf << 0) +#define AT91_PMC_ICPPLLA_0 (0 << 0) +#define AT91_PMC_ICPPLLA_1 (1 << 0) +#define AT91_PMC_REALLOCK (0x1 << 7) +#define AT91_PMC_IPLLA (0xf << 8) +#define AT91_PMC_IPLLA_0 (0 << 8) +#define AT91_PMC_IPLLA_1 (1 << 8) +#define AT91_PMC_IPLLA_2 (2 << 8) +#define AT91_PMC_IPLLA_3 (3 << 8) + #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ @@ -163,6 +180,7 @@ #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ +#define AT91_PMC_PCR_DIV_MASK (0x3 << 16) #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */ #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ #define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ |