diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam926x_board_init.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam926x_board_init.h | 83 |
1 files changed, 55 insertions, 28 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h index 70ae903374..9ab0eef728 100644 --- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h +++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h @@ -18,13 +18,14 @@ #include <mach/at91_wdt.h> #include <mach/hardware.h> #include <mach/gpio.h> +#include <mach/at91sam926x.h> struct at91sam926x_board_cfg { /* SoC specific */ void __iomem *pio; void __iomem *sdramc; u32 ebi_pio_is_peripha; - u32 matrix_csa; + void __iomem *matrix_csa; /* board specific */ u32 wdt_mr; @@ -50,7 +51,7 @@ struct at91sam926x_board_cfg { static void __always_inline access_sdram(void) { - writel(0x00000000, AT91_SDRAM_BASE); + writel(0x00000000, AT91_CHIPSELECT_1); } static void __always_inline pmc_check_mckrdy(void) @@ -58,7 +59,7 @@ static void __always_inline pmc_check_mckrdy(void) u32 r; do { - r = at91_pmc_read(AT91_PMC_SR); + r = readl(AT91SAM926X_BASE_PMC + AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); } @@ -82,49 +83,51 @@ static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg return; /* SDRAMC_MR : Normal Mode */ - __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL); + __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); /* SDRAMC_TR - Refresh Timer register */ - __raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr1); + __raw_writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR); /* SDRAMC_CR - Configuration register*/ - __raw_writel(AT91_SDRAMC_CR, cfg->sdramc + cfg->sdrc_cr); + __raw_writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR); /* Memory Device Type */ - __raw_writel(AT91_SDRAMC_MDR, cfg->sdramc + cfg->sdrc_mdr); + __raw_writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR); /* SDRAMC_MR : Precharge All */ - __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_PRECHARGE); + __raw_writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR); access_sdram(); /* SDRAMC_MR : refresh */ - __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_REFRESH); + __raw_writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR); /* access SDRAM 8 times */ for (i = 0; i < 8; i++) access_sdram(); /* SDRAMC_MR : Load Mode Register */ - __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_LMR); + __raw_writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR); access_sdram(); /* SDRAMC_MR : Normal Mode */ - __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL); + __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); access_sdram(); /* SDRAMC_TR : Refresh Timer Counter */ - __raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr2); + __raw_writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR); access_sdram(); } -static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg *cfg) +static void __always_inline at91sam926x_board_init(void __iomem *smcbase, + struct at91sam926x_board_cfg *cfg) { u32 r; + void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC); if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT)) return; - __raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR); + __raw_writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR); /* configure PIOx as EBI0 D[16-31] */ at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr); @@ -132,44 +135,44 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg if (cfg->ebi_pio_is_peripha) at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr); - at91_sys_write(cfg->matrix_csa, cfg->ebi_csa); + writel(cfg->ebi_csa, cfg->matrix_csa); /* flash */ - at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode); - at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle); - at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse); - at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup); + writel(cfg->smc_mode, smcbase + cfg->smc_cs * 0x10 + AT91_SAM9_SMC_MODE); + writel(cfg->smc_cycle, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_CYCLE); + writel(cfg->smc_pulse, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_PULSE); + writel(cfg->smc_setup, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_SETUP); /* PMC Check if the PLL is already initialized */ - r = at91_pmc_read(AT91_PMC_MCKR); + r = readl(pmc + AT91_PMC_MCKR); if ((r & AT91_PMC_CSS) && !running_in_sram()) return; /* Enable the Main Oscillator */ - at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor); + writel(cfg->pmc_mor, pmc + AT91_CKGR_MOR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* PLLAR: x MHz for PCK */ - at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar); + writel(cfg->pmc_pllar, pmc + AT91_CKGR_PLLAR); do { - r = at91_pmc_read(AT91_PMC_SR); + r = readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* PCK/x = MCK Master Clock from SLOW */ - at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1); + writel(cfg->pmc_mckr1, pmc + AT91_PMC_MCKR); pmc_check_mckrdy(); /* PCK/x = MCK Master Clock from PLLA */ - at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2); + writel(cfg->pmc_mckr2, pmc + AT91_PMC_MCKR); pmc_check_mckrdy(); /* Init SDRAM */ at91sam926x_sdramc_init(cfg); /* User reset enable*/ - at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr); + writel(cfg->rstc_rmr, AT91SAM926X_BASE_RSTC + AT91_RSTC_MR); /* * When boot from external boot @@ -177,7 +180,31 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg * so enable all of them * We will shutdown what we don't need later */ - at91_pmc_write(AT91_PMC_PCER, 0xffffffff); + writel(0xffffffff, pmc + AT91_PMC_PCER); } +#if defined CONFIG_ARCH_AT91SAM9260 +#include <mach/at91sam9260.h> +static void __always_inline at91sam9260_board_init(struct at91sam926x_board_cfg *cfg) +{ + at91sam926x_board_init(IOMEM(AT91SAM9260_BASE_SMC), cfg); +} +#endif + +#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10 +#include <mach/at91sam9261.h> +static void __always_inline at91sam9261_board_init(struct at91sam926x_board_cfg *cfg) +{ + at91sam926x_board_init(IOMEM(AT91SAM9261_BASE_SMC), cfg); +} +#endif + +#if defined CONFIG_ARCH_AT91SAM9263 +#include <mach/at91sam9263.h> +static void __always_inline at91sam9263_board_init(struct at91sam926x_board_cfg *cfg) +{ + at91sam926x_board_init(IOMEM(AT91SAM9263_BASE_SMC0), cfg); +} +#endif + #endif /* __AT91SAM926X_BOARD_INIT_H__ */ |