diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9n12.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9n12.h | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h index 249bde466b..dd9c0fc4e0 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h @@ -18,8 +18,6 @@ /* * Peripheral identifiers/interrupts. */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller Interrupt */ #define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ #define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ /* Reserved 4 */ @@ -79,7 +77,6 @@ #define AT91SAM9N12_BASE_UART1 0xf8044000 #define AT91SAM9N12_BASE_TRNG 0xf8048000 #define AT91SAM9N12_BASE_ADC 0xf804c000 -#define AT91_BASE_SYS 0xffffc000 /* * System Peripherals @@ -106,32 +103,6 @@ #define AT91SAM9N12_BASE_RTC 0xfffffeb0 /* - * System Peripherals (offset from AT91_BASE_SYS) - */ -#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS) -#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS) -#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS) -#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS) - -#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT -#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC -#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA -#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB -#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC -#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD - -#define AT91_USART0 AT91SAM9X5_BASE_US0 -#define AT91_USART1 AT91SAM9X5_BASE_US1 -#define AT91_USART2 AT91SAM9X5_BASE_US2 -#define AT91_USART3 AT91SAM9X5_BASE_US3 -#define AT91_NB_USART 5 - -#define AT91_PMC 0xfffffc00 - -/* * Internal Memory. */ #define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ @@ -143,42 +114,4 @@ #define AT91SAM9N12_SMD_BASE 0x00400000 /* SMD Controller */ #define AT91SAM9N12_OHCI_BASE 0x00500000 /* USB Host controller (OHCI) */ -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_1 - -#define CONSISTENT_DMA_SIZE (14 * SZ_1M) - -/* - * DMA0 peripheral identifiers - * for hardware handshaking interface - */ -#define AT_DMA_ID_MCI 0 -#define AT_DMA_ID_SPI0_TX 1 -#define AT_DMA_ID_SPI0_RX 2 -#define AT_DMA_ID_SPI1_TX 3 -#define AT_DMA_ID_SPI1_RX 4 -#define AT_DMA_ID_USART0_TX 5 -#define AT_DMA_ID_USART0_RX 6 -#define AT_DMA_ID_USART1_TX 7 -#define AT_DMA_ID_USART1_RX 8 -#define AT_DMA_ID_USART2_TX 9 -#define AT_DMA_ID_USART2_RX 10 -#define AT_DMA_ID_USART3_TX 11 -#define AT_DMA_ID_USART3_RX 12 -#define AT_DMA_ID_TWI0_TX 13 -#define AT_DMA_ID_TWI0_RX 14 -#define AT_DMA_ID_TWI1_TX 15 -#define AT_DMA_ID_TWI1_RX 16 -#define AT_DMA_ID_UART0_TX 17 -#define AT_DMA_ID_UART0_RX 18 -#define AT_DMA_ID_UART1_TX 19 -#define AT_DMA_ID_UART1_RX 20 -#define AT_DMA_ID_SSC_TX 21 -#define AT_DMA_ID_SSC_RX 22 -#define AT_DMA_ID_ADC_RX 23 -#define AT_DMA_ID_DBGU_TX 24 -#define AT_DMA_ID_DBGU_RX 25 -#define AT_DMA_ID_AES_TX 26 -#define AT_DMA_ID_AES_RX 27 -#define AT_DMA_ID_SHA_RX 28 - #endif |