diff options
Diffstat (limited to 'arch/arm/mach-at91')
88 files changed, 2338 insertions, 6119 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 5ad1f62c8d..0e89916c9c 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + if ARCH_AT91 config HAVE_AT91_UTMI @@ -6,9 +8,6 @@ config HAVE_AT91_UTMI config HAVE_AT91_USB_CLK bool -config HAVE_AT91_PIO4 - bool - config COMMON_CLK_AT91 bool select COMMON_CLK @@ -21,6 +20,10 @@ config MACH_AT91SAM9263EK_DT Enabled for at91sam9263ek - evaluation kit. But only if we need the device tree (bootstrap do not use DT) +config HAVE_AT91_LEGACY_CLK + def_bool !COMMON_CLK_OF_PROVIDER + select HAVE_LEGACY_CLK + config HAVE_AT91_SMD bool @@ -34,6 +37,24 @@ config HAVE_AT91_GENERATED_CLK config HAVE_AT91_BOOTSTRAP bool +config HAVE_AT91_AUDIO_PLL + bool + +config HAVE_AT91_I2S_MUX_CLK + bool + +config HAVE_AT91_SAM9X60_PLL + bool + +config HAVE_AT91_SDRAMC + bool + +config HAVE_AT91_DDRAMC + bool + +config AT91_MCI_PBL + def_bool MCI_ATMEL_PBL || MCI_ATMEL_SDHCI_PBL + # Select if board uses the common at91sam926x_board_init config AT91SAM926X_BOARD_INIT bool @@ -41,20 +62,32 @@ config AT91SAM926X_BOARD_INIT config AT91SAM9_SMC bool +config HAVE_AT91SAM9_RST + bool + config SOC_AT91SAM9 bool select CPU_ARM926T select AT91SAM9_SMC select CLOCKSOURCE_ATMEL_PIT select PINCTRL + select HAVE_AT91SAM9_RST select HAVE_AT91_SMD select HAVE_AT91_USB_CLK select HAVE_AT91_UTMI select PINCTRL_AT91 +config SOC_SAM_V7 + select CPU_V7 + bool + config SOC_SAMA5 bool - select CPU_V7 + select HAVE_AT91SAM9_RST + select SOC_SAM_V7 + +config SOC_SAMA5_MULTI + def_bool SOC_SAMA5 && AT91_MULTI_BOARDS config SOC_SAMA5D2 bool @@ -65,9 +98,12 @@ config SOC_SAMA5D2 select HAVE_AT91_UTMI select HAVE_AT91_USB_CLK select HAVE_AT91_GENERATED_CLK + select PINCTRL + select HAVE_AT91_AUDIO_PLL + select HAVE_AT91_I2S_MUX_CLK select PINCTRL_AT91PIO4 select HAS_MACB - select HAVE_MACH_ARM_HEAD + select HAVE_AT91_DDRAMC config SOC_SAMA5D3 bool @@ -79,7 +115,7 @@ config SOC_SAMA5D3 select HAVE_AT91_UTMI select PINCTRL_AT91 select HAS_MACB - select HAVE_MACH_ARM_HEAD + select HAVE_AT91_DDRAMC config SOC_SAMA5D4 bool @@ -92,7 +128,24 @@ config SOC_SAMA5D4 select HAVE_AT91_UTMI select PINCTRL_AT91 select HAS_MACB - select HAVE_MACH_ARM_HEAD + select HAVE_AT91_DDRAMC + +config SOC_SAM9X60 + bool + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select PINCTRL_AT91 + +config SOC_SAMA7G5 + bool + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select HAVE_AT91_UTMI + select SOC_SAM_V7 + help + Select this if you are using one of Microchip's SAMA7G5 family SoC. config ARCH_TEXT_BASE hex @@ -117,7 +170,6 @@ config SOC_AT91RM9200 bool select CPU_ARM920T select HAS_AT91_ETHER - select HAVE_AT91_DBGU0 select HAVE_AT91_USB_CLK select PINCTRL_AT91 @@ -126,7 +178,6 @@ config SOC_AT91SAM9260 select SOC_AT91SAM9 select HAS_MACB select PINCTRL_AT91 - select HAVE_MACH_ARM_HEAD help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE or AT91SAM9G20 SoC. @@ -136,7 +187,6 @@ config SOC_AT91SAM9261 select SOC_AT91SAM9 select PINCTRL_AT91 select HAVE_AT91_LOAD_BAREBOX_SRAM - select HAVE_MACH_ARM_HEAD help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. @@ -145,7 +195,6 @@ config SOC_AT91SAM9263 select SOC_AT91SAM9 select HAS_MACB select HAVE_AT91_LOAD_BAREBOX_SRAM - select HAVE_MACH_ARM_HEAD select PINCTRL_AT91 config SOC_AT91SAM9G45 @@ -153,7 +202,6 @@ config SOC_AT91SAM9G45 select SOC_AT91SAM9 select HAS_MACB select PINCTRL_AT91 - select HAVE_MACH_ARM_HEAD help Select this if you are using one of Atmel's AT91SAM9G45 family SoC. This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. @@ -176,7 +224,6 @@ config SOC_AT91SAM9N12 bool select SOC_AT91SAM9 select PINCTRL_AT91 - select HAVE_MACH_ARM_HEAD help Select this if you are using Atmel's AT91SAM9N12 SoC. @@ -506,11 +553,6 @@ config MACH_SAMA5D3XEK help Select this if you are using Atmel's SAMA5D3X-EK Evaluation Kit. -config MACH_SAMA5D3_XPLAINED - bool "Atmel SAMA5D3_XPLAINED Evaluation Kit" - help - Select this if you are using Atmel's SAMA5D3_XPLAINED Evaluation Kit. - endchoice endif @@ -542,11 +584,29 @@ endif config AT91_MULTI_BOARDS bool "Allow multiple boards to be selected" - select HAVE_PBL_MULTI_IMAGES select ARM_USE_COMPRESSED_DTB if AT91_MULTI_BOARDS +config MACH_CALAO + bool "CALAO DT-enabled boards (TNY/USB-A9260/A9G20)" + select SOC_AT91SAM9260 + select OFDEVICE + select COMMON_CLK_OF_PROVIDER + select HAVE_AT91_SDRAMC + help + Select this if you are using a device tree enabled board + from Calao Systems: TNY-A9260, TNY-A9G20, USB-A9260 or USB-A9G20. + +config MACH_SKOV_ARM9CPU + bool "SKOV ARM9 CPU" + select SOC_AT91SAM9263 + select OFDEVICE + select COMMON_CLK_OF_PROVIDER + select MCI_ATMEL_PBL + help + Say y here if you are using SKOV's ARM9 CPU board + config MACH_AT91SAM9263EK bool "Atmel AT91SAM9263-EK" select SOC_AT91SAM9263 @@ -569,18 +629,56 @@ config MACH_MICROCHIP_KSZ9477_EVB bool "Microchip EVB-KSZ9477 Evaluation Kit" select SOC_SAMA5D3 select OFDEVICE + select MCI_ATMEL_PBL select COMMON_CLK_OF_PROVIDER help Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit. +config MACH_MICROCHIP_SAMA5D3_EDS + bool "Microchip SAMA5D3 Ethernet Development System" + select SOC_SAMA5D3 + select OFDEVICE + select MCI_ATMEL_PBL + select COMMON_CLK_OF_PROVIDER + help + Select this if you are using Microchip's SAMA5D3 Ethernet Development + System. + +config MACH_SAMA5D3_XPLAINED + bool "Atmel SAMA5D3_XPLAINED Evaluation Kit" + select SOC_SAMA5D3 + select OFDEVICE + select MCI_ATMEL_PBL + select COMMON_CLK_OF_PROVIDER + help + Select this if you are using Atmel's SAMA5D3_XPLAINED Evaluation Kit. + config MACH_SAMA5D27_SOM1 bool "Microchip SAMA5D27 SoM-1 Evaluation Kit" select SOC_SAMA5D2 select OFDEVICE + select MCI_ATMEL_SDHCI_PBL select COMMON_CLK_OF_PROVIDER + select FS_FAT_WRITE if MCI_ATMEL_SDHCI && FS_FAT && ENV_HANDLING help Select this if you are using Microchip's sama5d27 SoM evaluation kit +config MACH_SAMA5D27_GIANTBOARD + bool "Groboards SAMA5D27 Giant Board" + select SOC_SAMA5D2 + select OFDEVICE + select COMMON_CLK_OF_PROVIDER + help + Select this if you are using the Groboards sama5d27 Giantboard + +config MACH_SAMA5D4_WIFX + bool "Wifx L1 LoRaWAN base station" + select SOC_SAMA5D4 + select OFDEVICE + select COMMON_CLK_OF_PROVIDER + help + Select this if you are using the SAMA5D4-based Wifx L1. + endif comment "AT91 Board Options" @@ -606,12 +704,6 @@ config AT91_HAVE_2MMC with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and onwards. -config AT91_HAVE_SRAM_128M - bool "Have 128 of ram" - depends on MACH_USB_A9G20 || MACH_USB_A9263 || MACH_QIL_A9260 || MACH_QIL_A9G20 - help - Select this if you board have 128 MiB of Ram (as USB_A9G20 C11) - choice prompt "LCD type" depends on MACH_AT91SAM9M10G45EK diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 66d0b700f6..7d7f27749f 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,30 +1,42 @@ -obj-y += setup.o -lwl-y += at91_pmc_ll.o +# SPDX-License-Identifier: GPL-2.0-only -ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),) -obj-y += clock.o -endif +obj-y += setup.o aic.o +lwl-y += at91_pmc_ll.o ddramc_ll.o at91sam9_sdramc_ll.o matrix.o +lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o + +obj-$(CONFIG_HAVE_AT91_LEGACY_CLK) += clock.o obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o +obj-$(CONFIG_BOOTM) += bootm-barebox.o obj-y += at91sam9_reset.o obj-y += at91sam9g45_reset.o +obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o +obj-pbl-$(CONFIG_HAVE_AT91_SDRAMC) += sdramc.o +pbl-$(CONFIG_AT91_MCI_PBL) += xload-mmc.o +pbl-$(CONFIG_AT91_MCI_PBL) += at91sam9_xload_mmc.o obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o +obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o # CPU-specific support obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o obj-$(CONFIG_SOC_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o obj-$(CONFIG_SOC_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o -ifeq ($(CONFIG_OFDEVICE),) +ifeq ($(CONFIG_AT91_MULTI_BOARDS),) +obj-$(CONFIG_SOC_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o sama5d3_devices.o +obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o sama5d4_devices.o endif +lwl-$(CONFIG_SOC_AT91SAM9263) += sam9263_ll.o +lwl-$(CONFIG_SOC_SAMA5D2) += sama5d2_ll.o +obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o +lwl-$(CONFIG_SOC_SAMA5D3) += sama5d3_ll.o obj-$(CONFIG_SOC_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o -obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o sama5d4_devices.o +obj-$(CONFIG_SOC_SAMA5_MULTI) += sama5_bootsource.o diff --git a/arch/arm/mach-at91/aic.c b/arch/arm/mach-at91/aic.c new file mode 100644 index 0000000000..b57fe57361 --- /dev/null +++ b/arch/arm/mach-at91/aic.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2015, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ + +#include <mach/at91/aic.h> +#include <io.h> + +#define SFR_AICREDIR 0x54 +#define SFR_SN1 0x50 /* Serial Number 1 Register */ + +void at91_aic_redir(void __iomem *sfr, u32 key) +{ + u32 key32; + + if (readl(sfr + SFR_AICREDIR) & 0x01) + return; + + key32 = readl(sfr + SFR_SN1) ^ key; + writel(key32 | 0x01, sfr + SFR_AICREDIR); + /* bits[31:1] = key */ + /* bit[0] = 1 => all interrupts redirected to AIC */ + /* bit[0] = 0 => secure interrupts directed to SAIC, + others to AIC (default) */ +} diff --git a/arch/arm/mach-at91/at91_pmc_ll.c b/arch/arm/mach-at91/at91_pmc_ll.c index 4d39f57909..0101623c8e 100644 --- a/arch/arm/mach-at91/at91_pmc_ll.c +++ b/arch/arm/mach-at91/at91_pmc_ll.c @@ -1,17 +1,51 @@ // SPDX-License-Identifier: BSD-1-Clause /* * Copyright (c) 2006, Atmel Corporation + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries * - * Atmel's name may not be used to endorse or promote products + * Atmel/Microchip's name may not be used to endorse or promote products * derived from this software without specific prior written permission. */ +#define pr_fmt(fmt) "at91pmc: " fmt + #include <common.h> -#include <mach/at91_pmc_ll.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91_pmc_ll.h> +#include <mach/at91/early_udelay.h> + +#define SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ +#define AT91_UTMICKTRIM_FREQ 0x03 + +#define PMC_GCSR0 0xC0 /* PMCv2 Generic Clock Status Register 0 */ +#define PMC_GCSR1 0xC4 /* PMCv2 Generic Clock Status Register 1 */ #define at91_pmc_write(off, val) writel(val, pmc_base + off) #define at91_pmc_read(off) readl(pmc_base + off) +#define MHZ (1000 * 1000UL) + +static unsigned long at91_pmc_get_main_xtal(void __iomem *pmc_base) +{ + u32 tmp; + + /* Enable a measurement of the Main Crystal Oscillator */ + tmp = at91_pmc_read(AT91_CKGR_MCFR); + tmp |= AT91_PMC_CCSS_XTAL_OSC; + tmp |= AT91_PMC_RCMEAS; + at91_pmc_write(AT91_CKGR_MCFR, tmp); + + do { + tmp = at91_pmc_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + + /* read once more like the datasheet says */ + tmp = at91_pmc_read(AT91_CKGR_MCFR) & AT91_PMC_MAINF; + + return tmp * (AT91_SLOW_CLOCK / 16); +} + void at91_pmc_init(void __iomem *pmc_base, unsigned int flags) { u32 tmp; @@ -46,22 +80,16 @@ void at91_pmc_init(void __iomem *pmc_base, unsigned int flags) while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS)) ; - if (flags & AT91_PMC_LL_FLAG_MEASURE_XTAL) { - /* Enable a measurement of the Main Crystal Oscillator */ - tmp = at91_pmc_read(AT91_CKGR_MCFR); - tmp |= AT91_PMC_CCSS_XTAL_OSC; - tmp |= AT91_PMC_RCMEAS; - at91_pmc_write(AT91_CKGR_MCFR, tmp); - - while (!(at91_pmc_read(AT91_CKGR_MCFR) & AT91_PMC_MAINRDY)) - ; - } + if (flags & AT91_PMC_LL_FLAG_MEASURE_XTAL) + (void)at91_pmc_get_main_xtal(pmc_base); /* Switch from internal 12MHz RC to the Main Crystal Oscillator */ tmp = at91_pmc_read(AT91_CKGR_MOR); tmp &= ~AT91_PMC_OSCBYPASS; tmp &= ~AT91_PMC_KEY_MASK; tmp |= AT91_PMC_KEY; + if (flags & AT91_PMC_LL_FLAG_MCK_BYPASS) + tmp |= AT91_PMC_OSCBYPASS; at91_pmc_write(AT91_CKGR_MOR, tmp); tmp = at91_pmc_read(AT91_CKGR_MOR); @@ -129,6 +157,17 @@ void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, ; } +void at91_pmc_cfg_pllb(void __iomem *pmc_base, u32 pmc_pllbr, + unsigned int __always_unused flags) +{ + /* Always disable PLL before configuring it */ + at91_pmc_write(AT91_CKGR_PLLBR, 0); + at91_pmc_write(AT91_CKGR_PLLBR, pmc_pllbr); + + while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB)) + ; +} + void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags) { u32 tmp; @@ -184,3 +223,124 @@ void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags) while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY)) ; } + +static void pmc_configure_utmi_ref_clk(void __iomem *pmc_base, + void __iomem *sfr_base, + unsigned long main_xtal) +{ + unsigned int utmi_ref_clk_freq = 0, tmp; + + /* + * If mainck rate is different from 12 MHz, we have to configure + * the FREQ field of the SFR_UTMICKTRIM register to generate properly + * the utmi clock. + */ + if (main_xtal < (16 + 4) * MHZ) + utmi_ref_clk_freq++; + if (main_xtal < (24 + 10) * MHZ) + utmi_ref_clk_freq++; + if (main_xtal < (48 + 10) * MHZ) + utmi_ref_clk_freq++; + + /* + * Not supported on SAMA5D2 but it's not an issue since MAINCK + * maximum value is 24 MHz. + */ + tmp = readl(sfr_base + SFR_UTMICKTRIM); + tmp &= ~AT91_UTMICKTRIM_FREQ; + tmp |= utmi_ref_clk_freq; + writel(tmp, sfr_base + SFR_UTMICKTRIM); +} + +static void pmc_uckr_clk(void __iomem *pmc_base, + void __iomem *sfr_base, + unsigned long main_xtal) +{ + unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR); + unsigned int sr; + + if (main_xtal) { + pmc_configure_utmi_ref_clk(pmc_base, sfr_base, + main_xtal); + uckr |= (AT91_PMC_UPLLCOUNT_DEFAULT | + AT91_PMC_UPLLEN | AT91_PMC_BIASEN); + sr = AT91_PMC_LOCKU; + } else { + uckr &= ~(AT91_PMC_UPLLEN | AT91_PMC_BIASEN); + sr = 0; + } + + at91_pmc_write(AT91_CKGR_UCKR, uckr); + + do { + early_udelay(1); + } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != sr); +} + +static inline unsigned gck_status(unsigned periph_id, + unsigned flags) +{ + if (flags & AT91_PMC_LL_FLAG_GCSR) + return periph_id < 32 ? PMC_GCSR0 : PMC_GCSR1; + + return AT91_PMC_SR; +} + +static inline unsigned gck_ready(unsigned status, + unsigned periph_id, + unsigned flags) +{ + unsigned mask; + + if (flags & AT91_PMC_LL_FLAG_GCSR) + mask = 1 << (periph_id & 0x1f); + else + mask = AT91_PMC_GCKRDY; + + return status & mask; +} + +int at91_pmc_enable_generic_clock(void __iomem *pmc_base, + void __iomem *sfr_base, + unsigned int periph_id, + unsigned int clk_source, unsigned int div, + unsigned int flags) +{ + unsigned long main_xtal; + unsigned int regval, status; + unsigned int timeout = 1000; + + if (periph_id > 0x7f) + return -EINVAL; + + if (div > 0xff) + return -EINVAL; + + main_xtal = at91_pmc_get_main_xtal(pmc_base); + + if ((flags & AT91_PMC_LL_FLAG_PMC_UTMI) && + !(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU)) + pmc_uckr_clk(pmc_base, sfr_base, main_xtal); + + at91_pmc_write(AT91_PMC_PCR, periph_id); + regval = at91_pmc_read(AT91_PMC_PCR); + regval &= ~AT91_PMC_GCKCSS; + regval &= ~AT91_PMC_GCKDIV; + + regval |= clk_source; + regval |= AT91_PMC_PCR_CMD | AT91_PMC_GCKDIV_(div) | AT91_PMC_GCK_EN; + + at91_pmc_write(AT91_PMC_PCR, regval); + + for (timeout = 1000; timeout; timeout--) { + early_udelay(1); + + status = at91_pmc_read(gck_status(periph_id, flags)); + if (gck_ready(status, periph_id, flags)) + return 0; + } + + pr_warn("Timeout waiting for GCK ready!\n"); + + return 0; +} diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index ba680eb81f..a45bf7cdd3 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -1,8 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> #include "clock.h" #include "generic.h" diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index f370160580..8717aefc77 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -1,23 +1,17 @@ -/* - * arch/arm/mach-at91/at91rm9200_devices.c - * - * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> - * Copyright (C) 2005 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2005 Thibaut VARENE <varenet@parisc-linux.org> +// SPDX-FileCopyrightText: 2005 David Brownell + +/* arch/arm/mach-at91/at91rm9200_devices.c */ + #include <common.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/at91rm9200.h> -#include <mach/board.h> -#include <mach/iomux.h> -#include <mach/at91rm9200_mc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91rm9200.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> +#include <mach/at91/at91rm9200_mc.h> #include <i2c/i2c-gpio.h> #include <linux/sizes.h> diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 63975071f1..c8394d3d74 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -1,36 +1,13 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2002 Sysgo Real-Time Solutions GmbH (http://www.elinos.com, Marius Groeger <mgroeger@sysgo.de>, Alex Zuepke <azu@sysgo.de>) +// SPDX-FileCopyrightText: 2002 Gary Jennejohn <gj@denx.de>, DENX Software Engineering #include <common.h> #include <init.h> #include <clock.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91rm9200_st.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91rm9200_st.h> #include <io.h> static void __iomem *st = IOMEM(AT91RM9200_BASE_ST); @@ -58,6 +35,7 @@ static struct clocksource cs = { .mask = CLOCKSOURCE_MASK(20), .read = at91rm9200_clocksource_read, .shift = 10, + .priority = 80, }; static int clocksource_init (void) @@ -91,7 +69,7 @@ static void __noreturn at91rm9200_restart_soc(struct restart_handler *rst) static int restart_register_feature(void) { - restart_handler_register_fn(at91rm9200_restart_soc); + restart_handler_register_fn("soc-wdt", at91rm9200_restart_soc); return 0; } diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 56327a2c47..623c01605f 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -1,11 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include "generic.h" #include "clock.h" @@ -243,7 +245,7 @@ static void at91sam9260_initialize(void) at91_add_pit(AT91SAM9260_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9260_restart); + restart_handler_register_fn("soc", at91sam9260_restart); } static int at91sam9260_setup(void) diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index eafcfeacf7..435535a917 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -1,27 +1,21 @@ -/* - * arch/arm/mach-at91/at91sam9260_devices.c - * - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2006 Atmel + +/* arch/arm/mach-at91/at91sam9260_devices.c */ + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/board.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9260_matrix.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91_rtt.h> -#include <mach/iomux.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9260_matrix.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91_rtt.h> +#include <mach/at91/iomux.h> +#include <mach/at91/cpu.h> #include <i2c/i2c-gpio.h> #include "generic.h" @@ -348,7 +342,7 @@ resource_size_t __init at91_configure_usart5(unsigned pins) /* Consider only one slot : slot 0 */ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) { - struct device_d *dev; + struct device *dev; if (!data) return; diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 4abc556354..df35b7239c 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -1,11 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include "generic.h" #include "clock.h" @@ -235,7 +237,7 @@ static void at91sam9261_initialize(void) at91_add_pit(AT91SAM9261_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9261_restart); + restart_handler_register_fn("soc", at91sam9261_restart); } static int at91sam9261_setup(void) diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index fcf719a09a..20446a7077 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -1,27 +1,21 @@ -/* - * arch/arm/mach-at91/at91sam9261_devices.c - * - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2006 Atmel + +/* arch/arm/mach-at91/at91sam9261_devices.c */ + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9261_matrix.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91_rtt.h> -#include <mach/board.h> -#include <mach/iomux.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9261_matrix.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91_rtt.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> +#include <mach/at91/cpu.h> #include <i2c/i2c-gpio.h> #include "generic.h" @@ -315,7 +309,7 @@ resource_size_t __init at91_configure_usart2(unsigned pins) /* Consider only one slot : slot 0 */ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) { - struct device_d *dev; + struct device *dev; if (!data) return; diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 690f8e06bb..2241e568d4 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -1,11 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include "clock.h" #include "generic.h" @@ -256,7 +258,7 @@ static void at91sam9263_initialize(void) at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200); at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200); - restart_handler_register_fn(at91sam9263_restart); + restart_handler_register_fn("soc", at91sam9263_restart); } static int at91sam9263_setup(void) diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index c7e4962a93..1813eee746 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -1,26 +1,20 @@ -/* - * arch/arm/mach-at91/at91sam9263_devices.c - * - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2006 Atmel + +/* arch/arm/mach-at91/at91sam9263_devices.c */ + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9263_matrix.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91_rtt.h> -#include <mach/board.h> -#include <mach/iomux.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9263_matrix.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91_rtt.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> #include <i2c/i2c-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S index 65e22f4fe7..37d0c8fc5d 100644 --- a/arch/arm/mach-at91/at91sam9_reset.S +++ b/arch/arm/mach-at91/at91sam9_reset.S @@ -1,22 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-FileCopyrightText: 2010 BitBox Ltd */ + /* * reset AT91SAM9G20 as per errata * - * (C) BitBox Ltd 2010 - * * unless the SDRAM is cleanly shutdown before we hit the * reset register it can be left driving the data bus and * killing the chance of a subsequent boot from NAND - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #include <linux/linkage.h> -#include <mach/hardware.h> -#include <mach/at91sam9_sdramc.h> -#include <mach/at91_rstc.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/at91_rstc.h> .arm diff --git a/arch/arm/mach-at91/at91sam9_rst.c b/arch/arm/mach-at91/at91sam9_rst.c new file mode 100644 index 0000000000..d2c008e343 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_rst.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pengutronix, Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +#include <common.h> +#include <init.h> +#include <io.h> +#include <restart.h> +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91sam9260.h> +#include <reset_source.h> + +struct at91sam9x_rst { + struct restart_handler restart; + void __iomem *base; +}; + +static int reasons[] = { + RESET_POR, /* GENERAL Both VDDCORE and VDDBU rising */ + RESET_WKE, /* WAKEUP VDDCORE rising */ + RESET_WDG, /* WATCHDOG Watchdog fault occurred */ + RESET_RST, /* SOFTWARE Reset required by the software */ + RESET_EXT, /* USER NRST pin detected low */ +}; + +static void at91sam9x_set_reset_reason(struct device *dev, + void __iomem *base) +{ + enum reset_src_type type = RESET_UKWN; + u32 sr, rsttyp; + + sr = readl(base + AT91_RSTC_SR); + rsttyp = FIELD_GET(AT91_RSTC_RSTTYP, sr); + + if (rsttyp < ARRAY_SIZE(reasons)) + type = reasons[rsttyp]; + + dev_info(dev, "reset reason %s (RSTC_SR: 0x%05x)\n", + reset_source_to_string(type), sr); + + reset_source_set(type); +} + +static void __noreturn at91sam9x_restart_soc(struct restart_handler *rst) +{ + struct at91sam9x_rst *priv = container_of(rst, struct at91sam9x_rst, restart); + + writel(AT91_RSTC_PROCRST + | AT91_RSTC_PERRST + | AT91_RSTC_EXTRST + | AT91_RSTC_KEY, + priv->base + AT91_RSTC_CR); + + hang(); +} + +void __noreturn at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr); + +static void __noreturn at91sam9260_restart_soc(struct restart_handler *rst) +{ + struct at91sam9x_rst *priv = container_of(rst, struct at91sam9x_rst, restart); + + at91sam9_reset(IOMEM(AT91SAM9260_BASE_SDRAMC), + IOMEM(priv->base + AT91_RSTC_CR)); +} + +static int at91sam9x_rst_probe(struct device *dev) +{ + struct at91sam9x_rst *priv; + struct resource *iores; + struct clk *clk; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) { + dev_err(dev, "could not get reset memory region\n"); + return PTR_ERR(iores); + } + + priv = xzalloc(sizeof(*priv)); + priv->base = IOMEM(iores->start); + + clk = clk_get(dev, NULL); + if (IS_ERR(clk)) { + release_region(iores); + free(priv); + return PTR_ERR(clk); + } + + clk_enable(clk); + + at91sam9x_set_reset_reason(dev, priv->base); + + priv->restart.name = "at91sam9x-rst"; + priv->restart.restart = device_get_match_data(dev); + + return restart_handler_register(&priv->restart); +} + +static const __maybe_unused struct of_device_id at91sam9x_rst_dt_ids[] = { + { .compatible = "atmel,at91sam9260-rstc", at91sam9260_restart_soc }, + { .compatible = "atmel,at91sam9g45-rstc", at91sam9x_restart_soc }, + { .compatible = "atmel,sama5d3-rstc", at91sam9x_restart_soc }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, at91sam9x_rst_dt_ids); + +static struct driver at91sam9x_rst_driver = { + .name = "at91sam9x-rst", + .of_compatible = DRV_OF_COMPAT(at91sam9x_rst_dt_ids), + .probe = at91sam9x_rst_probe, +}; +device_platform_driver(at91sam9x_rst_driver); diff --git a/arch/arm/mach-at91/at91sam9_sdramc_ll.c b/arch/arm/mach-at91/at91sam9_sdramc_ll.c new file mode 100644 index 0000000000..5305c94248 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_sdramc_ll.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2006, Atmel Corporation + */ + +#include <mach/at91/at91sam9_sdramc.h> +#include <mach/at91/early_udelay.h> + +static inline void sdramc_wr(const struct at91sam9_sdramc_config *config, + unsigned int offset, + const unsigned int value) +{ + writel(value, config->sdramc + offset); +} + +int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config, + unsigned int sdram_address) +{ + unsigned int i; + + /* Step#1 SDRAM feature must be in the configuration register */ + sdramc_wr(config, AT91_SDRAMC_CR, config->cr); + + /* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */ + + /* Step#3 The SDRAM memory type must be set in the Memory Device Register */ + sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr); + + /* Step#4 The minimum pause of 200 us is provided to precede any single toggle */ + early_udelay(200); + + /* Step#5 A NOP command is issued to the SDRAM devices */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP); + writel(0x00000000, sdram_address); + + /* Step#6 An All Banks Precharge command is issued to the SDRAM devices */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE); + writel(0x00000000, sdram_address); + + /* Pause cycles */ + early_udelay(2000); + + /* Step#7 Eight auto-refresh cycles are provided */ + for (i = 0; i < 8; i++) { + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH); + writel(0x00000001 + i, sdram_address + 4 + 4 * i); + } + + /* Pause cycles */ + early_udelay(200); + + /* Step#8 A Mode Register set (MRS) cycle is issued to program (TCSR, PASR, DS) */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR); + writel(0xcafedede, sdram_address + 0x24); + + /* Pause cycles */ + early_udelay(200); + + /* Step#9 For mobile SDRAM initialization, an Extended Mode Register set ... */ + + /* Step#10 The application must go into Normal Mode, setting Mode to 0 + * and perform a write access at any location in the SDRAM. + */ + sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); // Set mode + writel(0x00000000, sdram_address); // Perform mode + + /* Step#11 Write the refresh rate into the count field in the Refresh Register. */ + sdramc_wr(config, AT91_SDRAMC_TR, config->tr); + + return 0; +} diff --git a/arch/arm/mach-at91/at91sam9_xload_mmc.c b/arch/arm/mach-at91/at91sam9_xload_mmc.c new file mode 100644 index 0000000000..26f268ae91 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9_xload_mmc.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2022 Sam Ravnborg */ + +#include <debug_ll.h> +#include <common.h> +#include <pbl/bio.h> + +#include <linux/sizes.h> +#include <asm/cache.h> + +#include <mach/at91/at91_pmc_ll.h> +#include <mach/at91/at91sam9263.h> +#include <mach/at91/at91sam926x.h> +#include <mach/at91/hardware.h> +#include <mach/at91/iomux.h> +#include <mach/at91/xload.h> +#include <mach/at91/gpio.h> + +typedef void (*func)(int zero, int arch, void *params); + +/* + * Load barebox.bin and start executing the first byte in the barebox image. + * barebox.bin is loaded to AT91_CHIPSELECT_1. + * + * To be able to load barebox.bin do a minimal init of the pheriferals + * used by MCI. + * This functions runs in PBL code and uses the PBL variant of the + * atmel_mci driver. + */ +void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock, + bool slot_b) +{ + void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOA); + void *buf = (void *)AT91_CHIPSELECT_1; + void __iomem *base; + struct pbl_bio bio; + int ret; + + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_PIOA); + + if (mmc_id == 0) { + base = IOMEM(AT91SAM9263_BASE_MCI0); + + /* CLK */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA12), AT91_MUX_PERIPH_A, 0); + + if (!slot_b) { + /* CMD */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA1), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + + /* DAT0 to DAT3 */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA0), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA3), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA4), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA5), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + } else { + /* CMD */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA16), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + + /* DAT0 to DAT3 */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA17), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA18), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA19), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA20), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + } + + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI0); + } else { + base = IOMEM(AT91SAM9263_BASE_MCI1); + + /* CLK */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA6), AT91_MUX_PERIPH_A, 0); + + if (!slot_b) { + /* CMD */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA7), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + + /* DAT0 to DAT3 */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA8), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA9), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA10), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA11), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + } else { + /* CMD */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA21), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + + /* DAT0 to DAT3 */ + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA22), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA23), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA24), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA25), AT91_MUX_PERIPH_A, GPIO_PULL_UP); + } + + at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI1); + } + + ret = at91_mci_bio_init(&bio, base, clock, (int)slot_b); + if (ret) { + pr_err("atmci_start_image: bio init faild: %d\n", ret); + goto out_panic; + } + + /* at91sam9x do not support high capacity */ + at91_mci_bio_set_highcapacity(false); + + ret = pbl_fat_load(&bio, "barebox.bin", buf, SZ_16M); + if (ret < 0) { + pr_err("pbl_fat_load: error %d\n", ret); + goto out_panic; + } + + sync_caches_for_execution(); + + ((func)buf)(0, 0, NULL); + +out_panic: + panic("FAT chainloading failed\n"); +} diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 569aa274fc..0d8d399fc5 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -1,12 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/cpu.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/cpu.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include "generic.h" #include "clock.h" @@ -270,7 +272,7 @@ static void at91sam9g45_initialize(void) at91_add_pit(AT91SAM9G45_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9g45_restart); + restart_handler_register_fn("soc", at91sam9g45_restart); } static int at91sam9g45_setup(void) diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 43d8d5fbd6..e74ba8e917 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -1,26 +1,20 @@ -/* - * arch/arm/mach-at91/at91sam9263_devices.c - * - * Copyright (C) 2006 Atmel - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2006 Atmel + +/* arch/arm/mach-at91/at91sam9263_devices.c */ + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9g45_matrix.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/at91_rtt.h> -#include <mach/board.h> -#include <mach/iomux.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9g45_matrix.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/at91_rtt.h> +#include <mach/at91/board.h> +#include <mach/at91/iomux.h> #include <i2c/i2c-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S index 6a58de618c..4189c4bfd7 100644 --- a/arch/arm/mach-at91/at91sam9g45_reset.S +++ b/arch/arm/mach-at91/at91sam9g45_reset.S @@ -11,22 +11,21 @@ */ #include <linux/linkage.h> -#include <mach/hardware.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/at91_rstc.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/at91_rstc.h> .arm .globl at91sam9g45_reset at91sam9g45_reset: mov r2, #1 - mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN + mov r3, #AT91_DDRC2_LPCB_POWERDOWN ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST .balign 32 @ align to cache line - str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access - str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 + str r2, [r0, #AT91_HDDRSDRC2_RTR] @ disable DDR0 access + str r3, [r0, #AT91_HDDRSDRC2_LPR] @ power down DDR0 str r4, [r1] @ reset processor b . diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 365bded56e..e6f4495fc1 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -1,12 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/cpu.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/cpu.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include "generic.h" #include "clock.h" @@ -226,7 +228,7 @@ static void at91sam9n12_initialize(void) at91_add_pit(AT91SAM9N12_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200); - restart_handler_register_fn(at91sam9n12_restart); + restart_handler_register_fn("soc", at91sam9n12_restart); } static int at91sam9n12_setup(void) diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c index 43cbb79af4..626b267954 100644 --- a/arch/arm/mach-at91/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/at91sam9n12_devices.c @@ -1,26 +1,20 @@ -/* - * On-Chip devices setup code for the AT91SAM9x5 family - * - * Copyright (C) 2010 Atmel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Atmel Corporation + +/* On-Chip devices setup code for the AT91SAM9x5 family */ + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/board.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9n12_matrix.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/iomux.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9n12_matrix.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/cpu.h> #include <i2c/i2c-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 40ba9ed56e..0b0fbc6ff3 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -1,9 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <init.h> #include <restart.h> -#include <mach/at91sam9x5.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/at91sam9x5.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> static void at91sam9x5_restart(struct restart_handler *rst) { @@ -11,10 +13,17 @@ static void at91sam9x5_restart(struct restart_handler *rst) IOMEM(AT91SAM9X5_BASE_RSTC + AT91_RSTC_CR)); } +static struct restart_handler restart; + static int at91sam9x5_initialize(void) { - restart_handler_register_fn(at91sam9x5_restart); + if (IS_ENABLED(CONFIG_OFDEVICE) && !of_machine_is_compatible("atmel,at91sam9x5")) + return 0; + + restart.name = "soc"; + restart.priority = 110; + restart.restart = at91sam9x5_restart; - return 0; + return restart_handler_register(&restart); } coredevice_initcall(at91sam9x5_initialize); diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c index ab506a1f42..c5dea4e3d7 100644 --- a/arch/arm/mach-at91/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/at91sam9x5_devices.c @@ -1,25 +1,19 @@ -/* - * On-Chip devices setup code for the AT91SAM9x5 family - * - * Copyright (C) 2010 Atmel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Atmel Corporation + +/* On-Chip devices setup code for the AT91SAM9x5 family */ + #include <common.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/board.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9x5_matrix.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/iomux.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9x5_matrix.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/cpu.h> #include <i2c/i2c-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c index 4fd1998ad0..9a5c0e3e4e 100644 --- a/arch/arm/mach-at91/boot_test_cmd.c +++ b/arch/arm/mach-at91/boot_test_cmd.c @@ -24,7 +24,6 @@ static int do_at91_boot_test(int argc, char *argv[]) int ret = 1; char *sram = "/dev/sram0"; u32 read_size, write_size; - u32 tmp = 0; while ((opt = getopt(argc, argv, "j:s:")) > 0) { switch (opt) { @@ -58,13 +57,13 @@ static int do_at91_boot_test(int argc, char *argv[]) fd = open(sram, O_WRONLY); if (fd < 0) { - printf("could not open %s: %s\n", sram, errno_str()); + printf("could not open %s: %m\n", sram); ret = fd; goto err; } while (write_size) { - tmp = write(fd, buf, write_size); + int tmp = write(fd, buf, write_size); if (tmp < 0) { perror("write"); goto err_open; diff --git a/arch/arm/mach-at91/bootm-barebox.c b/arch/arm/mach-at91/bootm-barebox.c new file mode 100644 index 0000000000..5540b8fad3 --- /dev/null +++ b/arch/arm/mach-at91/bootm-barebox.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "at91-bootm-barebox: " fmt + +#include <bootm.h> +#include <common.h> +#include <init.h> +#include <memory.h> +#include <mach/at91/sama5_bootsource.h> + +unsigned long at91_bootsource; +EXPORT_SYMBOL(at91_bootsource); + +static int do_bootm_at91_barebox_image(struct image_data *data) +{ + resource_size_t start, end; + int ret; + + ret = memory_bank_first_find_space(&start, &end); + if (ret) + return ret; + + ret = bootm_load_os(data, start); + if (ret) + return ret; + + if (data->verbose) + printf("Loaded barebox image to 0x%08zx\n", start); + + shutdown_barebox(); + + sama5_boot_xload((void *)start, at91_bootsource); + + return -EIO; +} + +static struct image_handler image_handler_at91_barebox_image = { + .name = "AT91 barebox image", + .bootm = do_bootm_at91_barebox_image, + .filetype = filetype_arm_barebox, +}; + +static int at91_register_barebox_image_handler(void) +{ + if (!of_machine_is_compatible("atmel,sama5")) + return 0; + + return register_image_handler(&image_handler_at91_barebox_image); +} +late_initcall(at91_register_barebox_image_handler); diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c index 5d21b2d021..fbf5fa78a1 100644 --- a/arch/arm/mach-at91/bootstrap.c +++ b/arch/arm/mach-at91/bootstrap.c @@ -6,7 +6,7 @@ #include <common.h> #include <bootstrap.h> -#include <mach/bootstrap.h> +#include <mach/at91/bootstrap.h> #include <linux/sizes.h> #include <malloc.h> #include <restart.h> @@ -78,7 +78,7 @@ static void at91bootstrap_boot_nand(bool is_barebox) kernel_entry_func func = NULL; printf("Boot %s from nand\n", name); - func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M); + func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M, NULL); bootstrap_boot(func, is_barebox); bootstrap_err("... failed\n"); free(func); @@ -89,7 +89,7 @@ static void at91bootstrap_boot_mmc(void) kernel_entry_func func = NULL; printf("Boot from mmc\n"); - func = bootstrap_read_disk("disk0.0", NULL); + func = bootstrap_read_disk("disk0.0", NULL, NULL); bootstrap_boot(func, false); bootstrap_err("... failed\n"); free(func); diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 9a58b243d8..a3071189bb 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -1,14 +1,8 @@ -/* - * linux/arch/arm/mach-at91/clock.c - * - * Copyright (C) 2005 David Brownell - * Copyright (C) 2005 Ivan Kokshaysky - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2005 David Brownell +// SPDX-FileCopyrightText: 2005 Ivan Kokshaysky + +/* linux/arch/arm/mach-at91/clock.c */ #include <common.h> #include <command.h> @@ -19,10 +13,10 @@ #include <linux/clk.h> #include <init.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/cpu.h> -#include <mach/board.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/cpu.h> +#include <mach/at91/board.h> #include "clock.h" #include "generic.h" diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index 97a08fd83f..30297a20a0 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h @@ -1,10 +1,6 @@ -/* - * linux/arch/arm/mach-at91/clock.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* linux/arch/arm/mach-at91/clock.h */ #include <linux/clkdev.h> diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c new file mode 100644 index 0000000000..4d0637b487 --- /dev/null +++ b/arch/arm/mach-at91/ddramc.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +#include <common.h> +#include <init.h> +#include <mach/at91/ddramc.h> +#include <mach/at91/hardware.h> +#include <asm/barebox-arm.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/sama5_bootsource.h> +#include <asm/memory.h> +#include <pbl.h> +#include <io.h> + +static unsigned sama5_ramsize(void __iomem *base) +{ + return at91_get_ddram_size(base, true); +} + +void __noreturn sama5d2_barebox_entry(unsigned int r4, void *boarddata) +{ + __sama5d2_stashed_bootrom_r4 = r4; + barebox_arm_entry(SAMA5_DDRCS, sama5_ramsize(SAMA5D2_BASE_MPDDRC), + boarddata); +} + +void __noreturn sama5d3_barebox_entry(unsigned int r4, void *boarddata) +{ + __sama5d3_stashed_bootrom_r4 = r4; + + barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), + boarddata); +} +void __noreturn sama5d4_barebox_entry(unsigned int r4, void *boarddata) +{ + __sama5d4_stashed_bootrom_r4 = r4; + + barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(), + boarddata); +} + +static int sama5_ddr_probe(struct device *dev) +{ + struct resource *iores; + void __iomem *base; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); + + return arm_add_mem_device("ram0", SAMA5_DDRCS, sama5_ramsize(base)); +} + +static struct of_device_id sama5_ddr_dt_ids[] = { + { .compatible = "atmel,sama5d3-ddramc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sama5_ddr_dt_ids); + +static struct driver sama5_ddr_driver = { + .name = "sama5-ddramc", + .probe = sama5_ddr_probe, + .of_compatible = sama5_ddr_dt_ids, +}; + +mem_platform_driver(sama5_ddr_driver); diff --git a/arch/arm/mach-at91/ddramc_ll.c b/arch/arm/mach-at91/ddramc_ll.c new file mode 100644 index 0000000000..001d3d7a22 --- /dev/null +++ b/arch/arm/mach-at91/ddramc_ll.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2007, Stelian Pop <stelian.pop@leadtechdesign.com> + * Copyright (c) 2007 Lead Tech Design <www.leadtechdesign.com> + */ + +#include <linux/kconfig.h> +#include <asm/system.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/ddramc.h> +#include <mach/at91/early_udelay.h> + +void at91_ddram_initialize(void __iomem *base_address, + void __iomem *ram_address, + const struct at91_ddramc_register *ddramc_config) +{ + unsigned long ba_offset; + unsigned long cr = 0; + + /* compute BA[] offset according to CR configuration */ + ba_offset = (ddramc_config->cr & AT91_DDRC2_NC) + 9; + if ((ddramc_config->cr & AT91_DDRC2_DECOD) == AT91_DDRC2_DECOD_SEQUENTIAL) + ba_offset += ((ddramc_config->cr & AT91_DDRC2_NR) >> 2) + 11; + + ba_offset += (ddramc_config->mdr & AT91_DDRC2_DBW) ? 1 : 2; + + /* + * Step 1: Program the memory device type into the Memory Device Register + */ + writel(ddramc_config->mdr, base_address + AT91_HDDRSDRC2_MDR); + + /* + * Step 2: Program the feature of DDR2-SDRAM device into + * the Timing Register, and into the Configuration Register + */ + writel(ddramc_config->cr, base_address + AT91_HDDRSDRC2_CR); + + writel(ddramc_config->t0pr, base_address + AT91_HDDRSDRC2_T0PR); + writel(ddramc_config->t1pr, base_address + AT91_HDDRSDRC2_T1PR); + writel(ddramc_config->t2pr, base_address + AT91_HDDRSDRC2_T2PR); + + /* + * Step 3: An NOP command is issued to the DDR2-SDRAM + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + /* Now, clocks which drive the DDR2-SDRAM device are enabled */ + + /* A minimum pause wait 200 us is provided to precede any signal toggle. + (6 core cycles per iteration, core is at 396MHz: min 13340 loops) */ + early_udelay(200); + + /* + * Step 4: An NOP command is issued to the DDR2-SDRAM + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + /* Now, CKE is driven high */ + /* wait 400 ns min */ + early_udelay(1); + + /* + * Step 5: An all banks precharge command is issued to the DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_PRCGALL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high + * temperature operations. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x2 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 7: An Extended Mode Register set(EMRS3) cycle is issued + * to set the Extended Mode Register to "0". + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x3 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL, + * and to program D.I.C(Output Driver Impedance Control) + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x1 << ba_offset)); + + /* An additional 200 cycles of clock are required for locking DLL */ + early_udelay(1); + + /* + * Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset) + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr | AT91_DDRC2_ENABLE_RESET_DLL, base_address + AT91_HDDRSDRC2_CR); + + /* + * Step 10: A Mode Register set(MRS) cycle is issied to reset DLL. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1:0] bits are set to 0. + */ + writel(AT91_DDRC2_MODE_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x0 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 11: An all banks precharge command is issued to the DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_PRCGALL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait 400 ns min (not needed on certain DDR2 devices) */ + early_udelay(1); + + /* + * Step 12: Two auto-refresh (CBR) cycles are provided. + * Program the auto refresh command (CBR) into the Mode Register. + */ + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait TRFC cycles min (135 ns min) extended to 400 ns */ + early_udelay(1); + + /* Set 2nd CBR */ + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* wait TRFC cycles min (135 ns min) extended to 400 ns */ + early_udelay(1); + + /* + * Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr & ~AT91_DDRC2_ENABLE_RESET_DLL, base_address + AT91_HDDRSDRC2_CR); + + /* + * Step 14: A Mode Register set (MRS) cycle is issued to program + * the parameters of the DDR2-SDRAM devices, in particular CAS latency, + * burst length and to disable DDL reset. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1:0] bits are set to 0. + */ + writel(AT91_DDRC2_MODE_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x0 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 15: Program OCD field into the Configuration Register + * to high (OCD calibration default). + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr | AT91_DDRC2_OCD_DEFAULT, base_address + AT91_HDDRSDRC2_CR); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x1 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 17: Program OCD field into the Configuration Register + * to low (OCD calibration mode exit). + */ + cr = readl(base_address + AT91_HDDRSDRC2_CR); + writel(cr & ~AT91_DDRC2_OCD_DEFAULT, base_address + AT91_HDDRSDRC2_CR); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. + * Perform a write access to DDR2-SDRAM to acknowledge this command. + * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x1 << ba_offset)); + + /* wait 2 cycles min (of tCK) = 15 ns min */ + early_udelay(1); + + /* + * Step 19: A Nornal mode command is provided. + */ + writel(AT91_DDRC2_MODE_NORMAL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 20: Perform a write access to any DDR2-SDRAM address + */ + writel(0, ram_address); + + /* + * Step 21: Write the refresh rate into the count field in the Refresh Timer register. + */ + writel(ddramc_config->rtr, base_address + AT91_HDDRSDRC2_RTR); + + /* + * Now we are ready to work on the DDRSDR + * wait for end of calibration + */ + early_udelay(10); +} + +/* This initialization sequence is sama5d3 and sama5d4 LP-DDR2 specific */ + +void at91_lpddr2_sdram_initialize(void __iomem *base_address, + void __iomem *ram_address, + const struct at91_ddramc_register *ddramc_config) +{ + unsigned long reg; + + writel(ddramc_config->lpddr2_lpr, base_address + AT91_MPDDRC_LPDDR2_LPR); + + writel(ddramc_config->tim_calr, base_address + AT91_MPDDRC_LPDDR2_TIM_CAL); + + /* + * Step 1: Program the memory device type. + */ + writel(ddramc_config->mdr, base_address + AT91_HDDRSDRC2_MDR); + + /* + * Step 2: Program the feature of the low-power DDR2-SDRAM device. + */ + writel(ddramc_config->cr, base_address + AT91_HDDRSDRC2_CR); + + writel(ddramc_config->t0pr, base_address + AT91_HDDRSDRC2_T0PR); + writel(ddramc_config->t1pr, base_address + AT91_HDDRSDRC2_T1PR); + writel(ddramc_config->t2pr, base_address + AT91_HDDRSDRC2_T2PR); + + /* + * Step 3: A NOP command is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + + /* + * Step 3bis: Add memory barrier then Perform a write access to + * any low-power DDR2-SDRAM address to acknowledge the command. + */ + dmb(); + writel(0, ram_address); + + /* + * Step 4: A pause of at least 100 ns must be observed before + * a single toggle. + */ + early_udelay(1); + + /* + * Step 5: A NOP command is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 6: A pause of at least 200 us must be observed before a Reset + * Command. + */ + early_udelay(200); + + /* + * Step 7: A Reset command is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(63) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 8: A pause of at least tINIT5 must be observed before issuing + * any commands. + */ + early_udelay(1); + + /* + * Step 9: A Calibration command is issued to the low-power DDR2-SDRAM. + */ + reg = readl(base_address + AT91_HDDRSDRC2_CR); + reg &= ~AT91_DDRC2_ZQ; + reg |= AT91_DDRC2_ZQ_RESET; + writel(reg, base_address + AT91_HDDRSDRC2_CR); + + writel(AT91_DDRC2_MRS(10) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 9bis: The ZQ Calibration command is now issued. + * Program the type of calibration in the MPDDRC_CR: set the + * ZQ field to the SHORT value. + */ + reg = readl(base_address + AT91_HDDRSDRC2_CR); + reg &= ~AT91_DDRC2_ZQ; + reg |= AT91_DDRC2_ZQ_SHORT; + writel(reg, base_address + AT91_HDDRSDRC2_CR); + + /* + * Step 10: A Mode Register Write command with 1 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(1) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 11: A Mode Register Write command with 2 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(2) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 12: A Mode Register Write command with 3 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(3) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 13: A Mode Register Write command with 16 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + writel(AT91_DDRC2_MRS(16) | AT91_DDRC2_MODE_LPDDR2_CMD, + base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 14: A Normal Mode command is provided. + */ + writel(AT91_DDRC2_MODE_NORMAL_CMD, base_address + AT91_HDDRSDRC2_MR); + dmb(); + writel(0, ram_address); + + /* + * Step 15: close the input buffers: error in documentation: no need. + */ + + /* + * Step 16: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register. + */ + writel(ddramc_config->rtr, base_address + AT91_HDDRSDRC2_RTR); + + /* + * Now configure the CAL MR4 register. + */ + writel(ddramc_config->cal_mr4r, base_address + AT91_MPDDRC_LPDDR2_CAL_MR4); +} + +void at91_lpddr1_sdram_initialize(void __iomem *base_address, + void __iomem *ram_address, + const struct at91_ddramc_register *ddramc_config) +{ + unsigned long ba_offset; + + /* Compute BA[] offset according to CR configuration */ + ba_offset = (ddramc_config->cr & AT91_DDRC2_NC) + 8; + if (!(ddramc_config->cr & AT91_DDRC2_DECOD_INTERLEAVED)) + ba_offset += ((ddramc_config->cr & AT91_DDRC2_NR) >> 2) + 11; + + ba_offset += (ddramc_config->mdr & AT91_DDRC2_DBW) ? 1 : 2; + + /* + * Step 1: Program the memory device type in the MPDDRC Memory Device Register + */ + writel(ddramc_config->mdr, base_address + AT91_HDDRSDRC2_MDR); + + /* + * Step 2: Program the features of the low-power DDR1-SDRAM device + * in the MPDDRC Configuration Register and in the MPDDRC Timing + * Parameter 0 Register/MPDDRC Timing Parameter 1 Register. + */ + writel(ddramc_config->cr, base_address + AT91_HDDRSDRC2_CR); + + writel(ddramc_config->t0pr, base_address + AT91_HDDRSDRC2_T0PR); + writel(ddramc_config->t1pr, base_address + AT91_HDDRSDRC2_T1PR); + writel(ddramc_config->t2pr, base_address + AT91_HDDRSDRC2_T2PR); + + /* + * Step 3: Program Temperature Compensated Self-refresh (TCR), + * Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters + * in the MPDDRC Low-power Register. + */ + writel(ddramc_config->lpr, base_address + AT91_HDDRSDRC2_LPR); + + /* + * Step 4: A NOP command is issued to the low-power DDR1-SDRAM. + * Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). + * The clocks which drive the low-power DDR1-SDRAM device + * are now enabled. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 5: A pause of at least 200 us must be observed before + * a signal toggle. + */ + early_udelay(200); + + /* + * Step 6: A NOP command is issued to the low-power DDR1-SDRAM. + * Program the NOP command in the MPDDRC_MR. calibration request is + * now made to the I/O pad. + */ + writel(AT91_DDRC2_MODE_NOP_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 7: An All Banks Precharge command is issued + * to the low-power DDR1-SDRAM. + * Program All Banks Precharge command in the MPDDRC_MR. + */ + writel(AT91_DDRC2_MODE_PRCGALL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 8: Two auto-refresh (CBR) cycles are provided. + * Program the Auto Refresh command (CBR) in the MPDDRC_MR. + * The application must write a four to the MODE field + * in the MPDDRC_MR. Perform a write access to any low-power + * DDR1-SDRAM location twice to acknowledge these commands. + */ + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + writel(AT91_DDRC2_MODE_RFSH_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 9: An Extended Mode Register Set (EMRS) cycle is issued to + * program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS). + * The application must write a five to the MODE field in the MPDDRC_MR + * and perform a write access to the SDRAM to acknowledge this command. + * The write address must be chosen so that signal BA[1] is set to 1 + * and BA[0] is set to 0. + */ + writel(AT91_DDRC2_MODE_EXT_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x2 << ba_offset)); + + /* + * Step 10: A Mode Register Set (MRS) cycle is issued to program + * parameters of the low-power DDR1-SDRAM devices, in particular + * CAS latency. + * The application must write a three to the MODE field in the MPDDRC_MR + * and perform a write access to the SDRAM to acknowledge this command. + * The write address must be chosen so that signals BA[1:0] are set to 0. + */ + writel(AT91_DDRC2_MODE_LMR_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address + (0x0 << ba_offset)); + + /* + * Step 11: The application must enter Normal mode, write a zero + * to the MODE field in the MPDDRC_MR and perform a write access + * at any location in the SDRAM to acknowledge this command. + */ + writel(AT91_DDRC2_MODE_NORMAL_CMD, base_address + AT91_HDDRSDRC2_MR); + writel(0, ram_address); + + /* + * Step 12: Perform a write access to any low-power DDR1-SDRAM address. + */ + writel(0, ram_address); + + /* + * Step 14: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register (MPDDRC_RTR): + */ + writel(ddramc_config->rtr, base_address + AT91_HDDRSDRC2_RTR); +} diff --git a/arch/arm/mach-at91/early_udelay.c b/arch/arm/mach-at91/early_udelay.c new file mode 100644 index 0000000000..c1a22d901a --- /dev/null +++ b/arch/arm/mach-at91/early_udelay.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2012, Atmel Corporation + */ + +#include <mach/at91/hardware.h> +#include <asm/io.h> +#include <mach/at91/at91_pmc_ll.h> +#include <mach/at91/at91_pit.h> +#include <mach/at91/early_udelay.h> + +static unsigned int master_clock; +static void __iomem *pmc, *pit; +static bool has_h32mxdiv; + +/* Because the below statement is used in the function: + * ((MASTER_CLOCK >> 10) * usec) is used, + * to our 32-bit system. the argu "usec" maximum value is: + * supposed "MASTER_CLOCK" is 132M. + * 132000000 / 1024 = 128906 + * (0xffffffff) / 128906 = 33318. + * So the maximum delay time is 33318 us. + */ +/* requires PIT to be initialized, but not the clocksource framework */ +void early_udelay(unsigned int usec) +{ + unsigned int delay; + unsigned int current; + unsigned int base = readl(pit + AT91_PIT_PIIR); + + if (has_h32mxdiv) + master_clock /= 2; + + delay = ((master_clock >> 10) * usec) >> 14; + + do { + current = readl(pit + AT91_PIT_PIIR); + current -= base; + } while (current < delay); +} + +void early_udelay_init(void __iomem *pmc_base, + void __iomem *pit_base, + unsigned int clock, + unsigned int master_clock_rate, + unsigned int flags) +{ + master_clock = master_clock_rate; + pmc = pmc_base; + pit = pit_base; + has_h32mxdiv = at91_pmc_check_mck_h32mxdiv(pmc, flags); + + writel(AT91_PIT_PIV | AT91_PIT_PITEN, pit + AT91_PIT_MR); + + at91_pmc_enable_periph_clock(pmc_base, clock); +} diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index d125e5ffd0..4ea9779d34 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -1,12 +1,7 @@ -/* - * linux/arch/arm/mach-at91/generic.h - * - * Copyright (C) 2005 David Brownell - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-FileCopyrightText: 2005 David Brownell */ + +/* linux/arch/arm/mach-at91/generic.h */ /* function called by setup to perform late init */ extern void (*at91_boot_soc)(void); @@ -18,25 +13,25 @@ static inline int __init at91_clock_init(void) { return 0; } extern int __init at91_clock_init(void); #endif -static inline struct device_d *at91_add_rm9200_gpio(int id, resource_size_t start) +static inline struct device *at91_add_rm9200_gpio(int id, resource_size_t start) { return add_generic_device("at91rm9200-gpio", id, NULL, start, 512, IORESOURCE_MEM, NULL); } -static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t start) +static inline struct device *at91_add_sam9x5_gpio(int id, resource_size_t start) { return add_generic_device("at91sam9x5-gpio", id, NULL, start, 512, IORESOURCE_MEM, NULL); } -static inline struct device_d *at91_add_pit(resource_size_t start) +static inline struct device *at91_add_pit(resource_size_t start) { return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16, IORESOURCE_MEM, NULL); } -static inline struct device_d *at91_add_sam9_smc(int id, resource_size_t start, +static inline struct device *at91_add_sam9_smc(int id, resource_size_t start, resource_size_t size) { return add_generic_device("at91sam9-smc", id, NULL, start, size, diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h deleted file mode 100644 index 0ba9cdae10..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_dbgu.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Debug Unit (DBGU) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E and SAMA5D3 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_DBGU_H -#define AT91_DBGU_H - -#define AT91_DBGU_CR (0x00) /* Control Register */ -#define AT91_DBGU_RSTRX (1 << 2) /* Reset Receiver */ -#define AT91_DBGU_RSTTX (1 << 3) /* Reset Transmitter */ -#define AT91_DBGU_RXEN (1 << 4) /* Receiver Enable */ -#define AT91_DBGU_RXDIS (1 << 5) /* Receiver Disable */ -#define AT91_DBGU_TXEN (1 << 6) /* Transmitter Enable */ -#define AT91_DBGU_TXDIS (1 << 7) /* Transmitter Disable */ -#define AT91_DBGU_RSTSTA (1 << 8) /* Reset Status Bits */ -#define AT91_DBGU_MR (0x04) /* Mode Register */ -#define AT91_DBGU_NBSTOP_1BIT (0 << 12) /* 1 stop bit */ -#define AT91_DBGU_NBSTOP_1_5BIT (1 << 12) /* 1.5 stop bits */ -#define AT91_DBGU_NBSTOP_2BIT (2 << 12) /* 2 stop bits */ - -#define AT91_DBGU_CHRL_5BIT (0 << 6) /* 5 bit character length */ -#define AT91_DBGU_CHRL_6BIT (1 << 6) /* 6 bit character length */ -#define AT91_DBGU_CHRL_7BIT (2 << 6) /* 7 bit character length */ -#define AT91_DBGU_CHRL_8BIT (3 << 6) /* 8 bit character length */ - -#define AT91_DBGU_PAR_EVEN (0 << 9) /* Even Parity */ -#define AT91_DBGU_PAR_ODD (1 << 9) /* Odd Parity */ -#define AT91_DBGU_PAR_SPACE (2 << 9) /* Space: Force Parity to 0 */ -#define AT91_DBGU_PAR_MARK (3 << 9) /* Mark: Force Parity to 1 */ -#define AT91_DBGU_PAR_NONE (4 << 9) /* No Parity */ - -#define AT91_DBGU_CHMODE_NORMAL (0 << 14) /* Normal mode */ -#define AT91_DBGU_CHMODE_AUTO (1 << 14) /* Automatic Echo */ -#define AT91_DBGU_CHMODE_LOCAL (2 << 14) /* Local Loopback */ -#define AT91_DBGU_CHMODE_REMOTE (3 << 14) /* Remote Loopback */ -#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ -#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ -#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ -#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */ -#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */ -#define AT91_DBGU_SR (0x14) /* Status Register */ -#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */ -#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */ -#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */ - -#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */ -#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */ -#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ -#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ - - -/* - * Some AT91 parts that don't have full DEBUG units still support the ID - * and extensions register. - */ -#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ -#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ -#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ -#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ -#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ -#define AT91_CIDR_SRAMSIZ_1K (1 << 16) -#define AT91_CIDR_SRAMSIZ_2K (2 << 16) -#define AT91_CIDR_SRAMSIZ_112K (4 << 16) -#define AT91_CIDR_SRAMSIZ_4K (5 << 16) -#define AT91_CIDR_SRAMSIZ_80K (6 << 16) -#define AT91_CIDR_SRAMSIZ_160K (7 << 16) -#define AT91_CIDR_SRAMSIZ_8K (8 << 16) -#define AT91_CIDR_SRAMSIZ_16K (9 << 16) -#define AT91_CIDR_SRAMSIZ_32K (10 << 16) -#define AT91_CIDR_SRAMSIZ_64K (11 << 16) -#define AT91_CIDR_SRAMSIZ_128K (12 << 16) -#define AT91_CIDR_SRAMSIZ_256K (13 << 16) -#define AT91_CIDR_SRAMSIZ_96K (14 << 16) -#define AT91_CIDR_SRAMSIZ_512K (15 << 16) -#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ -#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ -#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ - -#ifndef __ASSEMBLY__ - -#include <asm/io.h> -static inline void at91_dbgu_setup_ll(void __iomem *dbgu_base, - unsigned mck, - unsigned baudrate) -{ - if (IS_ENABLED(CONFIG_DEBUG_LL)) { - u32 brgr = mck / (baudrate * 16); - - if ((mck / (baudrate * 16)) % 10 >= 5) - brgr++; - - writel(~0, dbgu_base + AT91_DBGU_IDR); - - writel(AT91_DBGU_RSTRX - | AT91_DBGU_RSTTX - | AT91_DBGU_RXDIS - | AT91_DBGU_TXDIS, - dbgu_base + AT91_DBGU_CR); - - writel(brgr, dbgu_base + AT91_DBGU_BRGR); - - writel(AT91_DBGU_PAR_NONE - | AT91_DBGU_CHMODE_NORMAL - | AT91_DBGU_CHRL_8BIT - | AT91_DBGU_NBSTOP_1BIT, - dbgu_base + AT91_DBGU_MR); - - writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR); - } -} - -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h deleted file mode 100644 index 0f129c9975..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * Copyright (C) 2015 Atmel, - * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> - * - * Parallel I/O Controller (PIO) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIO_H -#define AT91_PIO_H - -#include <linux/bitops.h> - -#define PIO_PER 0x00 /* Enable Register */ -#define PIO_PDR 0x04 /* Disable Register */ -#define PIO_PSR 0x08 /* Status Register */ -#define PIO_OER 0x10 /* Output Enable Register */ -#define PIO_ODR 0x14 /* Output Disable Register */ -#define PIO_OSR 0x18 /* Output Status Register */ -#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ -#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ -#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ -#define PIO_SODR 0x30 /* Set Output Data Register */ -#define PIO_CODR 0x34 /* Clear Output Data Register */ -#define PIO_ODSR 0x38 /* Output Data Status Register */ -#define PIO_PDSR 0x3c /* Pin Data Status Register */ -#define PIO_IER 0x40 /* Interrupt Enable Register */ -#define PIO_IDR 0x44 /* Interrupt Disable Register */ -#define PIO_IMR 0x48 /* Interrupt Mask Register */ -#define PIO_ISR 0x4c /* Interrupt Status Register */ -#define PIO_MDER 0x50 /* Multi-driver Enable Register */ -#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ -#define PIO_MDSR 0x58 /* Multi-driver Status Register */ -#define PIO_PUDR 0x60 /* Pull-up Disable Register */ -#define PIO_PUER 0x64 /* Pull-up Enable Register */ -#define PIO_PUSR 0x68 /* Pull-up Status Register */ -#define PIO_ASR 0x70 /* Peripheral A Select Register */ -#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */ -#define PIO_BSR 0x74 /* Peripheral B Select Register */ -#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */ -#define PIO_ABSR 0x78 /* AB Status Register */ -#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */ -#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */ -#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */ -#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */ -#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ -#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */ -#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */ -#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */ -#define PIO_OWER 0xa0 /* Output Write Enable Register */ -#define PIO_OWDR 0xa4 /* Output Write Disable Register */ -#define PIO_OWSR 0xa8 /* Output Write Status Register */ -#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */ -#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */ -#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */ -#define PIO_ESR 0xc0 /* Edge Select Register */ -#define PIO_LSR 0xc4 /* Level Select Register */ -#define PIO_ELSR 0xc8 /* Edge/Level Status Register */ -#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */ -#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */ -#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */ -#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */ - -#define ABCDSR_PERIPH_A 0x0 -#define ABCDSR_PERIPH_B 0x1 -#define ABCDSR_PERIPH_C 0x2 -#define ABCDSR_PERIPH_D 0x3 - -#define PIO4_MSKR 0x0000 /* Mask Register */ -#define PIO4_CFGR 0x0004 /* Configuration Register */ -#define PIO4_CFGR_FUNC_MASK GENMASK(2, 0) -#define PIO4_DIR_MASK BIT(8) -#define PIO4_PUEN_MASK BIT(9) -#define PIO4_PDEN_MASK BIT(10) -#define PIO4_IFEN_MASK BIT(12) -#define PIO4_IFSCEN_MASK BIT(13) -#define PIO4_OPD_MASK BIT(14) -#define PIO4_SCHMITT_MASK BIT(15) -#define PIO4_DRVSTR_MASK GENMASK(17, 16) -#define PIO4_DRVSTR_OFFSET 16 -#define PIO4_CFGR_EVTSEL_MASK GENMASK(26, 24) -#define PIO4_CFGR_EVTSEL_FALLING (0 << 24) -#define PIO4_CFGR_EVTSEL_RISING (1 << 24) -#define PIO4_CFGR_EVTSEL_BOTH (2 << 24) -#define PIO4_CFGR_EVTSEL_LOW (3 << 24) -#define PIO4_CFGR_EVTSEL_HIGH (4 << 24) -#define PIO4_PDSR 0x0008 /* Data Status Register */ -#define PIO4_LOCKSR 0x000C /* Lock Status Register */ -#define PIO4_SODR 0x0010 /* Set Output Data Register */ -#define PIO4_CODR 0x0014 /* Clear Output Data Register */ -#define PIO4_ODSR 0x0018 /* Output Data Status Register */ -#define PIO4_IER 0x0020 /* Interrupt Enable Register */ -#define PIO4_IDR 0x0024 /* Interrupt Disable Register */ -#define PIO4_IMR 0x0028 /* Interrupt Mask Register */ -#define PIO4_ISR 0x002C /* Interrupt Status Register */ -#define PIO4_IOFR 0x003C /* I/O Freeze Configuration Register */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h deleted file mode 100644 index 8581efacb9..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pit.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Periodic Interval Timer (PIT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PIT_H -#define AT91_PIT_H - -#define AT91_PIT_MR 0x00 /* Mode Register */ -#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ -#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ -#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ - -#define AT91_PIT_SR 0x04 /* Status Register */ -#define AT91_PIT_PITS (1 << 0) /* Timer Status */ - -#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ -#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ -#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ -#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h deleted file mode 100644 index 4d60becefb..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ -#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ - -#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ - -#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ -#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#define AT91_PMC_OSCOUNT_(x) ((x) << 8) -#define AT91_PMC_KEY_MASK (0xff << 16) /* MOR Writing Key */ -#define AT91_PMC_KEY (0x37 << 16) -#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ - -#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Frequency Measure Ready */ -#define AT91_PMC_RCMEAS (1 << 20) /* RC Oscillator Frequency Measure (write-only) */ -#define AT91_PMC_CCSS (1 << 24) /* Counter Clock Source Selection */ -#define AT91_PMC_CCSS_RC_OSC (0 << 24) /* MAINF counter clock is the RC oscillator. */ -#define AT91_PMC_CCSS_XTAL_OSC (1 << 24) /* MAINF counter clock is the crystal oscillator. */ -#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ -#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ -#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ - -#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ -#define PMC_PRES_OFFSET 2 -#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) -#define PMC_ALT_PRES_OFFSET 4 -#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ -#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) -#define AT91_PMC_H32MXDIV (1 << 24) /* AHB 32-bit Matrix Divisor [some SAMA5 only] */ - -#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ - -#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ -#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ -#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ -#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) - -#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ -#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) - -#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ -#define AT91_PMC_MOSCXTS (1 << 0) /* Oscillator Startup Time */ -#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ -#define AT91_PMC_SR 0x68 /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ -#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ -#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ -#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ -#define AT91_PMC_ICPPLLA (0xf << 0) -#define AT91_PMC_ICPPLLA_0 (0 << 0) -#define AT91_PMC_ICPPLLA_1 (1 << 0) -#define AT91_PMC_REALLOCK (0x1 << 7) -#define AT91_PMC_IPLLA (0xf << 8) -#define AT91_PMC_IPLLA_0 (0 << 8) -#define AT91_PMC_IPLLA_1 (1 << 8) -#define AT91_PMC_IPLLA_2 (2 << 8) -#define AT91_PMC_IPLLA_3 (3 << 8) - - -#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ -#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ -#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ -#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ - -#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ -#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ -#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ - -#define AT91_PMC_VER 0xfc /* PMC Module Version [AT91CAP9 only] */ - -#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ -#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ -#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ -#define AT91_PMC_PCR_DIV_MASK (0x3 << 16) -#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */ -#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ -#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ -#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ -#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ -#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ - -#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 */ -#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Disable Register 1 */ -#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Status Register 1 */ -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h b/arch/arm/mach-at91/include/mach/at91_pmc_ll.h deleted file mode 100644 index eda40e8e12..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc_ll.h +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: BSD-1-Clause -/* - * Copyright (c) 2006, Atmel Corporation - */ - -#ifndef AT91_PMC_LL_H -#define AT91_PMC_LL_H - -#include <errno.h> -#include <asm/io.h> -#include <mach/at91_pmc.h> - -#define AT91_PMC_LL_FLAG_SAM9X5_PMC (1 << 0) -#define AT91_PMC_LL_FLAG_MEASURE_XTAL (1 << 1) -#define AT91_PMC_LL_FLAG_DISABLE_RC (1 << 2) - -#define AT91_PMC_LL_AT91RM9200 (0) -#define AT91_PMC_LL_AT91SAM9260 (0) -#define AT91_PMC_LL_AT91SAM9261 (0) -#define AT91_PMC_LL_AT91SAM9263 (0) -#define AT91_PMC_LL_AT91SAM9G45 (0) -#define AT91_PMC_LL_AT91SAM9X5 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC) -#define AT91_PMC_LL_AT91SAM9N12 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC) -#define AT91_PMC_LL_SAMA5D2 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_MEASURE_XTAL) -#define AT91_PMC_LL_SAMA5D3 (AT91_PMC_LL_FLAG_SAM9X5_PMC | \ - AT91_PMC_LL_FLAG_DISABLE_RC) -#define AT91_PMC_LL_SAMA5D4 (AT91_PMC_LL_FLAG_SAM9X5_PMC) - -void at91_pmc_init(void __iomem *pmc_base, unsigned int flags); -void at91_pmc_cfg_mck(void __iomem *pmc_base, u32 pmc_mckr, unsigned int flags); -void at91_pmc_cfg_plla(void __iomem *pmc_base, u32 pmc_pllar, unsigned int flags); - -static inline void at91_pmc_init_pll(void __iomem *pmc_base, u32 pmc_pllicpr) -{ - writel(pmc_pllicpr, pmc_base + AT91_PMC_PLLICPR); -} - -static inline void at91_pmc_enable_system_clock(void __iomem *pmc_base, - unsigned clock_id) -{ - writel(clock_id, pmc_base + AT91_PMC_SCER); -} - -static inline int at91_pmc_enable_periph_clock(void __iomem *pmc_base, - unsigned periph_id) -{ - u32 mask = 0x01 << (periph_id % 32); - - if ((periph_id / 32) == 1) - writel(mask, pmc_base + AT91_PMC_PCER1); - else if ((periph_id / 32) == 0) - writel(mask, pmc_base + AT91_PMC_PCER); - else - return -EINVAL; - - return 0; -} - -static inline int at91_pmc_sam9x5_enable_periph_clock(void __iomem *pmc_base, - unsigned periph_id) -{ - u32 pcr = periph_id; - - if (periph_id >= 0x80) /* 7 bits only */ - return -EINVAL; - - writel(pcr, pmc_base + AT91_PMC_PCR); - pcr |= readl(pmc_base + AT91_PMC_PCR) & AT91_PMC_PCR_DIV_MASK; - pcr |= AT91_PMC_PCR_CMD | AT91_PMC_PCR_EN; - writel(pcr, pmc_base + AT91_PMC_PCR); - - return 0; -} - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h deleted file mode 100644 index d67bed5213..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_rstc.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Reset Controller (RSTC) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RSTC_H -#define AT91_RSTC_H - -#define AT91_RSTC_CR (0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ -#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_RSTC_SR (0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h deleted file mode 100644 index ad29df1918..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_rtt.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_rtt.h - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Real-time Timer (RTT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_RTT_H -#define AT91_RTT_H - -#include <io.h> - -#define AT91_RTT_MR 0x00 /* Real-time Mode Register */ -#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ -#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ -#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ -#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ - -#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ -#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ - -#define AT91_RTT_VR 0x08 /* Real-time Value Register */ -#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ - -#define AT91_RTT_SR 0x0c /* Real-time Status Register */ -#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ -#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ - - -/* - * As the RTT is powered by the backup power so if the interrupt - * is still on when the kernel start, the kernel will end up with - * dead lock interrupt that it can not clear. Because the interrupt line is - * shared with the basic timer (PIT) on AT91_ID_SYS. - */ -static inline void at91_rtt_irq_fixup(void *base) -{ - void __iomem *reg = base + AT91_RTT_MR; - u32 mr = readl(reg); - - writel(mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN), reg); -} -#endif diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h deleted file mode 100644 index 36d37b9d2d..0000000000 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Watchdog Timer (WDT) - System peripherals regsters. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_WDT_H -#define AT91_WDT_H - -#define AT91_WDT_CR 0x00 /* Watchdog Control Register */ -#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ -#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ - -#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ -#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ -#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ -#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ -#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ -#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ -#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ -#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ -#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ - -#define AT91_WDT_SR 0x08 /* Watchdog Status Register */ -#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ -#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h deleted file mode 100644 index 01f5d23e0c..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91rm9200.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_H -#define AT91RM9200_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91RM9200_ID_US0 6 /* USART 0 */ -#define AT91RM9200_ID_US1 7 /* USART 1 */ -#define AT91RM9200_ID_US2 8 /* USART 2 */ -#define AT91RM9200_ID_US3 9 /* USART 3 */ -#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91RM9200_ID_UDP 11 /* USB Device Port */ -#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ -#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ -#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ -#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ -#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ -#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ -#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ -#define AT91RM9200_ID_UHP 23 /* USB Host port */ -#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ -#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ -#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ -#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ -#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ -#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ - - -/* - * Peripheral physical base addresses. - */ -#define AT91RM9200_BASE_TCB0 0xfffa0000 -#define AT91RM9200_BASE_TC0 0xfffa0000 -#define AT91RM9200_BASE_TC1 0xfffa0040 -#define AT91RM9200_BASE_TC2 0xfffa0080 -#define AT91RM9200_BASE_TCB1 0xfffa4000 -#define AT91RM9200_BASE_TC3 0xfffa4000 -#define AT91RM9200_BASE_TC4 0xfffa4040 -#define AT91RM9200_BASE_TC5 0xfffa4080 -#define AT91RM9200_BASE_UDP 0xfffb0000 -#define AT91RM9200_BASE_MCI 0xfffb4000 -#define AT91RM9200_BASE_TWI 0xfffb8000 -#define AT91RM9200_BASE_EMAC 0xfffbc000 -#define AT91RM9200_BASE_US0 0xfffc0000 -#define AT91RM9200_BASE_US1 0xfffc4000 -#define AT91RM9200_BASE_US2 0xfffc8000 -#define AT91RM9200_BASE_US3 0xfffcc000 -#define AT91RM9200_BASE_SSC0 0xfffd0000 -#define AT91RM9200_BASE_SSC1 0xfffd4000 -#define AT91RM9200_BASE_SSC2 0xfffd8000 -#define AT91RM9200_BASE_SPI 0xfffe0000 - -/* - * System Peripherals - */ -#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ -#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ -#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ -#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ -#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ -#define AT91RM9200_BASE_PMC 0xfffffc00 -#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */ -#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ -#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */ - -/* - * Internal Memory. - */ -#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ - -#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ - -#define AT91_VA_BASE_EMAC AT91RM9200_BASE_EMAC - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h deleted file mode 100644 index 74244520e6..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * [origin: arch/arm/mach-at91/include/mach/at91rm9200_emac.h] - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Ethernet MAC registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_EMAC_H -#define AT91RM9200_EMAC_H - -#define AT91_EMAC_CTL 0x00 /* Control Register */ -#define AT91_EMAC_LB (1 << 0) /* Loopback */ -#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ -#define AT91_EMAC_RE (1 << 2) /* Receive Enable */ -#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ -#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ -#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ -#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ -#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ -#define AT91_EMAC_BP (1 << 8) /* Back Pressure */ - -#define AT91_EMAC_CFG 0x04 /* Configuration Register */ -#define AT91_EMAC_SPD (1 << 0) /* Speed */ -#define AT91_EMAC_FD (1 << 1) /* Full Duplex */ -#define AT91_EMAC_BR (1 << 2) /* Bit Rate */ -#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ -#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ -#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ -#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ -#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ -#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ -#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ -#define AT91_EMAC_CLK_DIV8 (0 << 10) -#define AT91_EMAC_CLK_DIV16 (1 << 10) -#define AT91_EMAC_CLK_DIV32 (2 << 10) -#define AT91_EMAC_CLK_DIV64 (3 << 10) -#define AT91_EMAC_RTY (1 << 12) /* Retry Test */ -#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ - -#define AT91_EMAC_SR 0x08 /* Status Register */ -#define AT91_EMAC_SR_LINK (1 << 0) /* Link */ -#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ -#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ - -#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ - -#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ -#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ -#define AT91_EMAC_NCRC (1 << 15) /* No CRC */ - -#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ -#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ -#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ -#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ -#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ -#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ -#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ - -#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ - -#define AT91_EMAC_RSR 0x20 /* Receive Status Register */ -#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ -#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ -#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ - -#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ -#define AT91_EMAC_DONE (1 << 0) /* Management Done */ -#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ -#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ -#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ -#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ -#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ -#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ -#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ -#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ -#define AT91_EMAC_LINK (1 << 9) /* Link */ -#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ -#define AT91_EMAC_ABT (1 << 11) /* Abort */ - -#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ -#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ -#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ - -#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ -#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ -#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ -#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ -#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ -#define AT91_EMAC_RW_W (1 << 28) -#define AT91_EMAC_RW_R (2 << 28) -#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ - -/* - * Statistics Registers. - */ -#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ -#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ -#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ -#define AT91_EMAC_OK 0x4c /* Frames Received OK */ -#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ -#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ -#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ -#define AT91_EMAC_LCOL 0x5c /* Late Collision */ -#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ -#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ -#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ -#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ -#define AT91_EMAC_ROV 0x70 /* Receive Overrun */ -#define AT91_EMAC_CDE 0x74 /* Code Error */ -#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ -#define AT91_EMAC_RJB 0x7c /* Receive Jabber */ -#define AT91_EMAC_USF 0x80 /* Undersize Frame */ -#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ - -/* - * Address Registers. - */ -#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ -#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ -#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ -#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ -#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ -#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ -#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ -#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ -#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ -#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h deleted file mode 100644 index 03e1b87f5f..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91rm9200_mc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_MC_H -#define AT91RM9200_MC_H - -/* Memory Controller */ -#define AT91RM9200_MC_RCR (0x00) /* MC Remap Control Register */ -#define AT91RM9200_MC_RCB (1 << 0) /* Remap Command Bit */ - -#define AT91RM9200_MC_ASR (0x04) /* MC Abort Status Register */ -#define AT91RM9200_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ -#define AT91RM9200_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ -#define AT91RM9200_MC_ABTSZ (3 << 8) /* Abort Size Status */ -#define AT91RM9200_MC_ABTSZ_BYTE (0 << 8) -#define AT91RM9200_MC_ABTSZ_HALFWORD (1 << 8) -#define AT91RM9200_MC_ABTSZ_WORD (2 << 8) -#define AT91RM9200_MC_ABTTYP (3 << 10) /* Abort Type Status */ -#define AT91RM9200_MC_ABTTYP_DATAREAD (0 << 10) -#define AT91RM9200_MC_ABTTYP_DATAWRITE (1 << 10) -#define AT91RM9200_MC_ABTTYP_FETCH (2 << 10) -#define AT91RM9200_MC_MST0 (1 << 16) /* ARM920T Abort Source */ -#define AT91RM9200_MC_MST1 (1 << 17) /* PDC Abort Source */ -#define AT91RM9200_MC_MST2 (1 << 18) /* UHP Abort Source */ -#define AT91RM9200_MC_MST3 (1 << 19) /* EMAC Abort Source */ -#define AT91RM9200_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ -#define AT91RM9200_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ -#define AT91RM9200_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ -#define AT91RM9200_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ - -#define AT91RM9200_MC_AASR (0x08) /* MC Abort Address Status Register */ - -#define AT91RM9200_MC_MPR (0x0c) /* MC Master Priority Register */ -#define AT91RM9200_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ -#define AT91RM9200_MPR_MSTP1 (7 << 4) /* PDC Priority */ -#define AT91RM9200_MPR_MSTP2 (7 << 8) /* UHP Priority */ -#define AT91RM9200_MPR_MSTP3 (7 << 12) /* EMAC Priority */ - -/* External Bus Interface (EBI) registers */ -#define AT91RM9200_EBI_CSA (0x60) /* Chip Select Assignment Register */ -#define AT91RM9200_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ -#define AT91RM9200_EBI_CS0A_SMC (0 << 0) -#define AT91RM9200_EBI_CS0A_BFC (1 << 0) -#define AT91RM9200_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91RM9200_EBI_CS1A_SMC (0 << 1) -#define AT91RM9200_EBI_CS1A_SDRAMC (1 << 1) -#define AT91RM9200_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ -#define AT91RM9200_EBI_CS3A_SMC (0 << 3) -#define AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91RM9200_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ -#define AT91RM9200_EBI_CS4A_SMC (0 << 4) -#define AT91RM9200_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) -#define AT91RM9200_EBI_CFGR (0x64) /* Configuration Register */ -#define AT91RM9200_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ - -/* Static Memory Controller (SMC) registers */ -#define AT91RM9200_SMC_CSR(n) (0x70 + ((n) * 4))/* SMC Chip Select Register */ -#define AT91RM9200_SMC_NWS (0x7f << 0) /* Number of Wait States */ -#define AT91RM9200_SMC_NWS_(x) ((x) << 0) -#define AT91RM9200_SMC_WSEN (1 << 7) /* Wait State Enable */ -#define AT91RM9200_SMC_TDF (0xf << 8) /* Data Float Time */ -#define AT91RM9200_SMC_TDF_(x) ((x) << 8) -#define AT91RM9200_SMC_BAT (1 << 12) /* Byte Access Type */ -#define AT91RM9200_SMC_DBW (3 << 13) /* Data Bus Width */ -#define AT91RM9200_SMC_DBW_16 (1 << 13) -#define AT91RM9200_SMC_DBW_8 (2 << 13) -#define AT91RM9200_SMC_DPR (1 << 15) /* Data Read Protocol */ -#define AT91RM9200_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ -#define AT91RM9200_SMC_ACSS_STD (0 << 16) -#define AT91RM9200_SMC_ACSS_1 (1 << 16) -#define AT91RM9200_SMC_ACSS_2 (2 << 16) -#define AT91RM9200_SMC_ACSS_3 (3 << 16) -#define AT91RM9200_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ -#define AT91RM9200_SMC_RWSETUP_(x) ((x) << 24) -#define AT91RM9200_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ -#define AT91RM9200_SMC_RWHOLD_(x) ((x) << 28) - -/* SDRAM Controller registers */ -#define AT91RM9200_SDRAMC_MR (0x90) /* Mode Register */ -#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0) -#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0) -#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0) -#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0) -#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0) -#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */ -#define AT91RM9200_SDRAMC_DBW_32 (0 << 4) -#define AT91RM9200_SDRAMC_DBW_16 (1 << 4) - -#define AT91RM9200_SDRAMC_TR (0x94) /* Refresh Timer Register */ -#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ - -#define AT91RM9200_SDRAMC_CR (0x98) /* Configuration Register */ -#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91RM9200_SDRAMC_NC_8 (0 << 0) -#define AT91RM9200_SDRAMC_NC_9 (1 << 0) -#define AT91RM9200_SDRAMC_NC_10 (2 << 0) -#define AT91RM9200_SDRAMC_NC_11 (3 << 0) -#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91RM9200_SDRAMC_NR_11 (0 << 2) -#define AT91RM9200_SDRAMC_NR_12 (1 << 2) -#define AT91RM9200_SDRAMC_NR_13 (2 << 2) -#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91RM9200_SDRAMC_NB_2 (0 << 4) -#define AT91RM9200_SDRAMC_NB_4 (1 << 4) -#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91RM9200_SDRAMC_CAS_2 (2 << 5) -#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ -#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ -#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ -#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ -#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ -#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ - -#define AT91RM9200_SDRAMC_SRR (0x9c) /* Self Refresh Register */ -#define AT91RM9200_SDRAMC_LPR (0xa0) /* Low Power Register */ -#define AT91RM9200_SDRAMC_IER (0xa4) /* Interrupt Enable Register */ -#define AT91RM9200_SDRAMC_IDR (0xa8) /* Interrupt Disable Register */ -#define AT91RM9200_SDRAMC_IMR (0xac) /* Interrupt Mask Register */ -#define AT91RM9200_SDRAMC_ISR (0xb0) /* Interrupt Status Register */ - -/* Burst Flash Controller register */ -#define AT91RM9200_BFC_MR (0xc0) /* Mode Register */ -#define AT91RM9200_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ -#define AT91RM9200_BFC_BFCOM_DISABLED (0 << 0) -#define AT91RM9200_BFC_BFCOM_ASYNC (1 << 0) -#define AT91RM9200_BFC_BFCOM_BURST (2 << 0) -#define AT91RM9200_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ -#define AT91RM9200_BFC_BFCC_MCK (1 << 2) -#define AT91RM9200_BFC_BFCC_DIV2 (2 << 2) -#define AT91RM9200_BFC_BFCC_DIV4 (3 << 2) -#define AT91RM9200_BFC_AVL (0xf << 4) /* Address Valid Latency */ -#define AT91RM9200_BFC_PAGES (7 << 8) /* Page Size */ -#define AT91RM9200_BFC_PAGES_NO_PAGE (0 << 8) -#define AT91RM9200_BFC_PAGES_16 (1 << 8) -#define AT91RM9200_BFC_PAGES_32 (2 << 8) -#define AT91RM9200_BFC_PAGES_64 (3 << 8) -#define AT91RM9200_BFC_PAGES_128 (4 << 8) -#define AT91RM9200_BFC_PAGES_256 (5 << 8) -#define AT91RM9200_BFC_PAGES_512 (6 << 8) -#define AT91RM9200_BFC_PAGES_1024 (7 << 8) -#define AT91RM9200_BFC_OEL (3 << 12) /* Output Enable Latency */ -#define AT91RM9200_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ -#define AT91RM9200_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ -#define AT91RM9200_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ -#define AT91RM9200_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ - -#ifndef __ASSEMBLY__ -#include <io.h> -#include <mach/at91rm9200.h> -static inline u32 at91rm9200_get_sdram_size(void) -{ - u32 cr, mr; - u32 size; - - cr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_CR); - mr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_MR); - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (cr & AT91RM9200_SDRAMC_NC) + 8; - /* ROW */ - size += ((cr & AT91RM9200_SDRAMC_NR) >> 2) + 11; - /* BANK */ - size = ((cr & AT91RM9200_SDRAMC_NB) ? 4 : 2) << size; - /* bandwidth */ - if (!(mr & AT91RM9200_SDRAMC_DBW)) - size <<= 1; - - return size; -} -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_st.h b/arch/arm/mach-at91/include/mach/at91rm9200_st.h deleted file mode 100644 index bd676a7081..0000000000 --- a/arch/arm/mach-at91/include/mach/at91rm9200_st.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_st.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * System Timer (ST) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91RM9200_ST_H -#define AT91RM9200_ST_H - -#define AT91RM9200_ST_CR (0x00) /* Control Register */ -#define AT91RM9200_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ - -#define AT91RM9200_ST_PIMR (0x04) /* Period Interval Mode Register */ -#define AT91RM9200_ST_PIV (0xffff << 0) /* Period Interval Value */ - -#define AT91RM9200_ST_WDMR (0x08) /* Watchdog Mode Register */ -#define AT91RM9200_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ -#define AT91RM9200_ST_RSTEN (1 << 16) /* Reset Enable */ -#define AT91RM9200_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ - -#define AT91RM9200_ST_RTMR (0x0c) /* Real-time Mode Register */ -#define AT91RM9200_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ - -#define AT91RM9200_ST_SR (0x10) /* Status Register */ -#define AT91RM9200_ST_PITS (1 << 0) /* Period Interval Timer Status */ -#define AT91RM9200_ST_WDOVF (1 << 1) /* Watchdog Overflow */ -#define AT91RM9200_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ -#define AT91RM9200_ST_ALMS (1 << 3) /* Alarm Status */ - -#define AT91RM9200_ST_IER (0x14) /* Interrupt Enable Register */ -#define AT91RM9200_ST_IDR (0x18) /* Interrupt Disable Register */ -#define AT91RM9200_ST_IMR (0x1c) /* Interrupt Mask Register */ - -#define AT91RM9200_ST_RTAR (0x20) /* Real-time Alarm Register */ -#define AT91RM9200_ST_ALMV (0xfffff << 0) /* Alarm Value */ - -#define AT91RM9200_ST_CRTR (0x24) /* Current Real-time Register */ -#define AT91RM9200_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h deleted file mode 100644 index 708e661b4d..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] - * - * (C) 2006 Andrew Victor - * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_H -#define AT91SAM9260_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 - -/* - * System Peripherals - */ -#define AT91SAM9260_BASE_ECC 0xffffe800 -#define AT91SAM9260_BASE_SDRAMC 0xffffea00 -#define AT91SAM9260_BASE_SMC 0xffffec00 -#define AT91SAM9260_BASE_MATRIX 0xffffee00 -#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9260_BASE_PIOA 0xfffff400 -#define AT91SAM9260_BASE_PIOB 0xfffff600 -#define AT91SAM9260_BASE_PIOC 0xfffff800 -#define AT91SAM9260_BASE_RSTC 0xfffffd00 -#define AT91SAM9260_BASE_SHDWC 0xfffffd10 -#define AT91SAM9260_BASE_RTT 0xfffffd20 -#define AT91SAM9260_BASE_PIT 0xfffffd30 -#define AT91SAM9260_BASE_WDT 0xfffffd40 -#define AT91SAM9260_BASE_GPBR 0xfffffd50 - -/* - * Internal Memory. - */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ -#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */ -#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */ - -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ - -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ - -#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ -#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ -#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */ -#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h deleted file mode 100644 index 792afa39b7..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9260 datasheet revision B. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9260_MATRIX_H -#define AT91SAM9260_MATRIX_H - -#define AT91SAM9260_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9260_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9260_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9260_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9260_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9260_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9260_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9260_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9260_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9260_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9260_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9260_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91SAM9260_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9260_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9260_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9260_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9260_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9260_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9260_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91SAM9260_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91SAM9260_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91SAM9260_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91SAM9260_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9260_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9260_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9260_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9260_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9260_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9260_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9260_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9260_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9260_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9260_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91SAM9260_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9260_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9260_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91SAM9260_MATRIX_EBICSA (0x11C) /* EBI Chip Select Assignment Register */ -#define AT91SAM9260_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9260_MATRIX_CS1A_SMC (0 << 1) -#define AT91SAM9260_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91SAM9260_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9260_MATRIX_CS3A_SMC (0 << 3) -#define AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9260_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9260_MATRIX_CS4A_SMC (0 << 4) -#define AT91SAM9260_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91SAM9260_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9260_MATRIX_CS5A_SMC (0 << 5) -#define AT91SAM9260_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91SAM9260_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9260_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9260_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9260_MATRIX_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h deleted file mode 100644 index df948d3e72..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] - * - * Copyright (C) SAN People - * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_H -#define AT91SAM9261_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 - - -/* - * System Peripherals - */ -#define AT91SAM9261_BASE_SMC 0xffffec00 -#define AT91SAM9261_BASE_MATRIX 0xffffee00 -#define AT91SAM9261_BASE_SDRAMC 0xffffea00 -#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 -#define AT91SAM9261_BASE_PIOA 0xfffff400 -#define AT91SAM9261_BASE_PIOB 0xfffff600 -#define AT91SAM9261_BASE_PIOC 0xfffff800 -#define AT91SAM9261_BASE_RSTC 0xfffffd00 -#define AT91SAM9261_BASE_SHDWC 0xfffffd10 -#define AT91SAM9261_BASE_RTT 0xfffffd20 -#define AT91SAM9261_BASE_PIT 0xfffffd30 -#define AT91SAM9261_BASE_WDT 0xfffffd40 -#define AT91SAM9261_BASE_GPBR 0xfffffd50 - -/* - * Internal Memory. - */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ -#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h deleted file mode 100644 index 63e92ccd22..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] - * - * Copyright (C) 2007 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9261_MATRIX_H -#define AT91SAM9261_MATRIX_H - -#define AT91SAM9261_MATRIX_MCFG (0x00) /* Master Configuration Register */ -#define AT91SAM9261_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9261_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ - -#define AT91SAM9261_MATRIX_SCFG0 (0x04) /* Slave Configuration Register 0 */ -#define AT91SAM9261_MATRIX_SCFG1 (0x08) /* Slave Configuration Register 1 */ -#define AT91SAM9261_MATRIX_SCFG2 (0x0C) /* Slave Configuration Register 2 */ -#define AT91SAM9261_MATRIX_SCFG3 (0x10) /* Slave Configuration Register 3 */ -#define AT91SAM9261_MATRIX_SCFG4 (0x14) /* Slave Configuration Register 4 */ -#define AT91SAM9261_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9261_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9261_MATRIX_TCR (0x24) /* TCM Configuration Register */ -#define AT91SAM9261_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91SAM9261_MATRIX_ITCM_0 (0 << 0) -#define AT91SAM9261_MATRIX_ITCM_16 (5 << 0) -#define AT91SAM9261_MATRIX_ITCM_32 (6 << 0) -#define AT91SAM9261_MATRIX_ITCM_64 (7 << 0) -#define AT91SAM9261_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91SAM9261_MATRIX_DTCM_0 (0 << 4) -#define AT91SAM9261_MATRIX_DTCM_16 (5 << 4) -#define AT91SAM9261_MATRIX_DTCM_32 (6 << 4) -#define AT91SAM9261_MATRIX_DTCM_64 (7 << 4) - -#define AT91SAM9261_MATRIX_EBICSA (0x30) /* EBI Chip Select Assignment Register */ -#define AT91SAM9261_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9261_MATRIX_CS1A_SMC (0 << 1) -#define AT91SAM9261_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91SAM9261_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9261_MATRIX_CS3A_SMC (0 << 3) -#define AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9261_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9261_MATRIX_CS4A_SMC (0 << 4) -#define AT91SAM9261_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91SAM9261_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9261_MATRIX_CS5A_SMC (0 << 5) -#define AT91SAM9261_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91SAM9261_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ - -#define AT91SAM9261_MATRIX_USBPUCR (0x34) /* USB Pad Pull-Up Control Register */ -#define AT91SAM9261_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h deleted file mode 100644 index a357ea83fe..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] - * - * (C) 2007 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_H -#define AT91SAM9263_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 - - -/* - * System Peripherals - */ -#define AT91SAM9263_BASE_ECC0 0xffffe000 -#define AT91SAM9263_BASE_SDRAMC0 0xffffe200 -#define AT91SAM9263_BASE_SMC0 0xffffe400 -#define AT91SAM9263_BASE_ECC1 0xffffe600 -#define AT91SAM9263_BASE_SDRAMC1 0xffffe800 -#define AT91SAM9263_BASE_SMC1 0xffffea00 -#define AT91SAM9263_BASE_MATRIX 0xffffec00 -#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9263_BASE_PIOA 0xfffff200 -#define AT91SAM9263_BASE_PIOB 0xfffff400 -#define AT91SAM9263_BASE_PIOC 0xfffff600 -#define AT91SAM9263_BASE_PIOD 0xfffff800 -#define AT91SAM9263_BASE_PIOE 0xfffffa00 -#define AT91SAM9263_BASE_RSTC 0xfffffd00 -#define AT91SAM9263_BASE_SHDWC 0xfffffd10 -#define AT91SAM9263_BASE_RTT0 0xfffffd20 -#define AT91SAM9263_BASE_PIT 0xfffffd30 -#define AT91SAM9263_BASE_WDT 0xfffffd40 -#define AT91SAM9263_BASE_RTT1 0xfffffd50 -#define AT91SAM9263_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ - -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ - -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ - -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h deleted file mode 100644 index 0082666cd3..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] - * - * Copyright (C) 2006 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9263 datasheet revision B (Preliminary). - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9263_MATRIX_H -#define AT91SAM9263_MATRIX_H - -#define AT91SAM9263_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9263_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9263_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9263_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9263_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9263_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9263_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */ -#define AT91SAM9263_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */ -#define AT91SAM9263_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */ -#define AT91SAM9263_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9263_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9263_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9263_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9263_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */ -#define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */ -#define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */ -#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91SAM9263_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9263_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */ -#define AT91SAM9263_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9263_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */ -#define AT91SAM9263_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9263_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */ -#define AT91SAM9263_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9263_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */ -#define AT91SAM9263_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9263_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */ -#define AT91SAM9263_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */ -#define AT91SAM9263_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */ -#define AT91SAM9263_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */ -#define AT91SAM9263_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */ -#define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */ -#define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */ -#define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ - -#define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9263_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9263_MATRIX_RCB2 (1 << 2) -#define AT91SAM9263_MATRIX_RCB3 (1 << 3) -#define AT91SAM9263_MATRIX_RCB4 (1 << 4) -#define AT91SAM9263_MATRIX_RCB5 (1 << 5) -#define AT91SAM9263_MATRIX_RCB6 (1 << 6) -#define AT91SAM9263_MATRIX_RCB7 (1 << 7) -#define AT91SAM9263_MATRIX_RCB8 (1 << 8) - -#define AT91SAM9263_MATRIX_TCMR (0x114) /* TCM Configuration Register */ -#define AT91SAM9263_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91SAM9263_MATRIX_ITCM_0 (0 << 0) -#define AT91SAM9263_MATRIX_ITCM_16 (5 << 0) -#define AT91SAM9263_MATRIX_ITCM_32 (6 << 0) -#define AT91SAM9263_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91SAM9263_MATRIX_DTCM_0 (0 << 4) -#define AT91SAM9263_MATRIX_DTCM_16 (5 << 4) -#define AT91SAM9263_MATRIX_DTCM_32 (6 << 4) - -#define AT91SAM9263_MATRIX_EBI0CSA (0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91SAM9263_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91SAM9263_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9263_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91SAM9263_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91SAM9263_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) - -#define AT91SAM9263_MATRIX_EBI1CSA (0x124) /* EBI1 Chip Select Assignment Register */ -#define AT91SAM9263_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9263_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91SAM9263_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91SAM9263_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9263_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h deleted file mode 100644 index ab5cf515ef..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam926x.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __MACH_AT91SAM926X_H -#define __MACH_AT91SAM926X_H - -#define AT91SAM926X_BASE_PMC 0xfffffc00 -#define AT91SAM926X_BASE_RSTC 0xfffffd00 -#define AT91SAM926X_BASE_WDT 0xfffffd40 - -#endif /* __MACH_AT91SAM926X_H */ diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h deleted file mode 100644 index 3dab64b71a..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h +++ /dev/null @@ -1,204 +0,0 @@ -#ifndef __AT91SAM926X_BOARD_INIT_H__ -#define __AT91SAM926X_BOARD_INIT_H__ -/* - * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) - * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 - */ - -#include <common.h> -#include <init.h> - -#include <mach/at91sam9_sdramc.h> -#include <mach/at91sam9_smc.h> -#include <mach/at91_rstc.h> -#include <mach/at91_pio.h> -#include <mach/at91_pmc.h> -#include <mach/at91_wdt.h> -#include <mach/hardware.h> -#include <mach/gpio.h> -#include <mach/at91sam926x.h> - -struct at91sam926x_board_cfg { - /* SoC specific */ - void __iomem *pio; - void __iomem *sdramc; - u32 ebi_pio_is_peripha; - void __iomem *matrix_csa; - - /* board specific */ - u32 wdt_mr; - u32 ebi_pio_pdr; - u32 ebi_pio_ppudr; - u32 ebi_csa; - u32 smc_cs; - u32 smc_mode; - u32 smc_cycle; - u32 smc_pulse; - u32 smc_setup; - u32 pmc_mor; - u32 pmc_pllar; - u32 pmc_mckr1; - u32 pmc_mckr2; - u32 sdrc_cr; - u32 sdrc_tr1; - u32 sdrc_mdr; - u32 sdrc_tr2; - u32 rstc_rmr; -}; - - -static void __always_inline access_sdram(void) -{ - writel(0x00000000, AT91_CHIPSELECT_1); -} - -static void __always_inline pmc_check_mckrdy(void) -{ - u32 r; - - do { - r = readl(AT91SAM926X_BASE_PMC + AT91_PMC_SR); - } while (!(r & AT91_PMC_MCKRDY)); -} - -static int __always_inline running_in_sram(void) -{ - u32 addr = get_pc(); - - addr >>= 28; - return addr == 0; -} - -static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg *cfg) -{ - u32 r; - int i; - int in_sram = running_in_sram(); - - /* SDRAMC Check if Refresh Timer Counter is already initialized */ - r = readl(cfg->sdramc + AT91_SDRAMC_TR); - if (r && !in_sram) - return; - - /* SDRAMC_MR : Normal Mode */ - writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); - - /* SDRAMC_TR - Refresh Timer register */ - writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR); - - /* SDRAMC_CR - Configuration register*/ - writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR); - - /* Memory Device Type */ - writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR); - - /* SDRAMC_MR : Precharge All */ - writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR); - access_sdram(); - - /* SDRAMC_MR : refresh */ - writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR); - - /* access SDRAM 8 times */ - for (i = 0; i < 8; i++) - access_sdram(); - - /* SDRAMC_MR : Load Mode Register */ - writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR); - access_sdram(); - - /* SDRAMC_MR : Normal Mode */ - writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); - access_sdram(); - - /* SDRAMC_TR : Refresh Timer Counter */ - writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR); - access_sdram(); -} - -static void __always_inline at91sam926x_board_init(void __iomem *smcbase, - struct at91sam926x_board_cfg *cfg) -{ - u32 r; - void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC); - - if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT)) - return; - - writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR); - - /* configure PIOx as EBI0 D[16-31] */ - at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr); - at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true); - if (cfg->ebi_pio_is_peripha) - at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr); - - writel(cfg->ebi_csa, cfg->matrix_csa); - - /* flash */ - writel(cfg->smc_mode, smcbase + cfg->smc_cs * 0x10 + AT91_SAM9_SMC_MODE); - writel(cfg->smc_cycle, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_CYCLE); - writel(cfg->smc_pulse, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_PULSE); - writel(cfg->smc_setup, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_SETUP); - - /* PMC Check if the PLL is already initialized */ - r = readl(pmc + AT91_PMC_MCKR); - if ((r & AT91_PMC_CSS) && !running_in_sram()) - return; - - /* Enable the Main Oscillator */ - writel(cfg->pmc_mor, pmc + AT91_CKGR_MOR); - do { - r = readl(pmc + AT91_PMC_SR); - } while (!(r & AT91_PMC_MOSCS)); - - /* PLLAR: x MHz for PCK */ - writel(cfg->pmc_pllar, pmc + AT91_CKGR_PLLAR); - do { - r = readl(pmc + AT91_PMC_SR); - } while (!(r & AT91_PMC_LOCKA)); - - /* PCK/x = MCK Master Clock from SLOW */ - writel(cfg->pmc_mckr1, pmc + AT91_PMC_MCKR); - pmc_check_mckrdy(); - - /* PCK/x = MCK Master Clock from PLLA */ - writel(cfg->pmc_mckr2, pmc + AT91_PMC_MCKR); - pmc_check_mckrdy(); - - /* Init SDRAM */ - at91sam926x_sdramc_init(cfg); - - /* User reset enable*/ - writel(cfg->rstc_rmr, AT91SAM926X_BASE_RSTC + AT91_RSTC_MR); - - /* - * When boot from external boot - * we need to enable mck and ohter clock - * so enable all of them - * We will shutdown what we don't need later - */ - writel(0xffffffff, pmc + AT91_PMC_PCER); -} - -#include <mach/at91sam9260.h> -static void __always_inline at91sam9260_board_init(struct at91sam926x_board_cfg *cfg) -{ - at91sam926x_board_init(IOMEM(AT91SAM9260_BASE_SMC), cfg); -} - -#include <mach/at91sam9261.h> -static void __always_inline at91sam9261_board_init(struct at91sam926x_board_cfg *cfg) -{ - at91sam926x_board_init(IOMEM(AT91SAM9261_BASE_SMC), cfg); -} - -#include <mach/at91sam9263.h> -static void __always_inline at91sam9263_board_init(struct at91sam926x_board_cfg *cfg) -{ - at91sam926x_board_init(IOMEM(AT91SAM9263_BASE_SMC0), cfg); -} - -#endif /* __AT91SAM926X_BOARD_INIT_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h deleted file mode 100644 index 496cf70701..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Header file for the Atmel DDR/SDR SDRAM Controller - * - * Copyright (C) 2010 Atmel Corporation - * Nicolas Ferre <nicolas.ferre@atmel.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#ifndef AT91SAM9_DDRSDR_H -#define AT91SAM9_DDRSDR_H - -#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ -#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ -#define AT91_DDRSDRC_MODE_NORMAL 0 -#define AT91_DDRSDRC_MODE_NOP 1 -#define AT91_DDRSDRC_MODE_PRECHARGE 2 -#define AT91_DDRSDRC_MODE_LMR 3 -#define AT91_DDRSDRC_MODE_REFRESH 4 -#define AT91_DDRSDRC_MODE_EXT_LMR 5 -#define AT91_DDRSDRC_MODE_DEEP 6 - -#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ -#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ -#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_DDRSDRC_NC_SDR8 (0 << 0) -#define AT91_DDRSDRC_NC_SDR9 (1 << 0) -#define AT91_DDRSDRC_NC_SDR10 (2 << 0) -#define AT91_DDRSDRC_NC_SDR11 (3 << 0) -#define AT91_DDRSDRC_NC_DDR9 (0 << 0) -#define AT91_DDRSDRC_NC_DDR10 (1 << 0) -#define AT91_DDRSDRC_NC_DDR11 (2 << 0) -#define AT91_DDRSDRC_NC_DDR12 (3 << 0) -#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_DDRSDRC_NR_11 (0 << 2) -#define AT91_DDRSDRC_NR_12 (1 << 2) -#define AT91_DDRSDRC_NR_13 (2 << 2) -#define AT91_DDRSDRC_NR_14 (3 << 2) -#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ -#define AT91_DDRSDRC_CAS_2 (2 << 4) -#define AT91_DDRSDRC_CAS_3 (3 << 4) -#define AT91_DDRSDRC_CAS_25 (6 << 4) -#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ -#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ -#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ -#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ -#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ -#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ -#define AT91_DDRSDRC_NB (1 << 20) /* Number of -Banks [not SAM9G45] */ -#define AT91_SDRAMC_NB_4 (0 << 20) -#define AT91_SDRAMC_NB_8 (1 << 20) - -#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ -#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ -#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ -#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ -#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ -#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ -#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ -#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ -#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ -#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ -#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ - -#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ -#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ -#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ -#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ -#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ - -#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ -#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ -#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ -#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ -#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ - -#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ -#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */ -#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_DDRSDRC_LPCB_DISABLE 0 -#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 -#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 -#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ -#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ -#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */ -#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ - -#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ -#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */ -#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ -#define AT91_DDRSDRC_MD_SDR 0 -#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 -#define AT91CAP9_DDRSDRC_MD_DDR 2 -#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 -#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ -#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ -#define AT91_DDRSDRC_DBW_32BITS (0 << 4) -#define AT91_DDRSDRC_DBW_16BITS (1 << 4) - -#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ -#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */ -#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ -#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ -#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ -#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ -#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ -#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ -#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ -#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ -#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ - -#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ -#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ - -#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ - -#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ -#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ -#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ -#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ - -#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ -#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ -#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ - -#ifndef __ASSEMBLY__ -#include <io.h> -#include <mach/hardware.h> - -static inline u32 at91_get_ddram_size(void __iomem *base, bool is_nb) -{ - u32 cr; - u32 mdr; - u32 size; - bool is_sdram; - - cr = readl(base + AT91_DDRSDRC_CR); - mdr = readl(base + AT91_DDRSDRC_MDR); - - /* will always be false for sama5d2, sama5d3 or sama5d4 */ - is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR; - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (cr & AT91_DDRSDRC_NC) + 8; - if (!is_sdram) - size ++; - /* ROW */ - size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; - /* BANK */ - if (is_nb) - size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; - else - size = 4 << size; - - /* bandwidth */ - if (!(mdr & AT91_DDRSDRC_DBW)) - size <<= 1; - - return size; -} - -static inline u32 at91sam9g45_get_ddram_size(int bank) -{ - switch (bank) { - case 0: - return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false); - case 1: - return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false); - default: - return 0; - } -} - -static inline u32 at91sam9x5_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); -} - -static inline u32 at91sam9n12_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); -} - -static inline u32 at91sama5d3_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true); -} - -static inline u32 at91sama5d4_get_ddram_size(void) -{ - return at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true); -} - -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h deleted file mode 100644 index 7bd887c8cb..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] - * - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * SDRAM Controllers (SDRAMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9_SDRAMC_H -#define AT91SAM9_SDRAMC_H - -/* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */ -#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ -#define AT91_SDRAMC_MODE_NORMAL 0 -#define AT91_SDRAMC_MODE_NOP 1 -#define AT91_SDRAMC_MODE_PRECHARGE 2 -#define AT91_SDRAMC_MODE_LMR 3 -#define AT91_SDRAMC_MODE_REFRESH 4 -#define AT91_SDRAMC_MODE_EXT_LMR 5 -#define AT91_SDRAMC_MODE_DEEP 6 - -#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */ -#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ - -#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */ -#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ -#define AT91_SDRAMC_NC_8 (0 << 0) -#define AT91_SDRAMC_NC_9 (1 << 0) -#define AT91_SDRAMC_NC_10 (2 << 0) -#define AT91_SDRAMC_NC_11 (3 << 0) -#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ -#define AT91_SDRAMC_NR_11 (0 << 2) -#define AT91_SDRAMC_NR_12 (1 << 2) -#define AT91_SDRAMC_NR_13 (2 << 2) -#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ -#define AT91_SDRAMC_NB_2 (0 << 4) -#define AT91_SDRAMC_NB_4 (1 << 4) -#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ -#define AT91_SDRAMC_CAS_1 (1 << 5) -#define AT91_SDRAMC_CAS_2 (2 << 5) -#define AT91_SDRAMC_CAS_3 (3 << 5) -#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ -#define AT91_SDRAMC_DBW_32 (0 << 7) -#define AT91_SDRAMC_DBW_16 (1 << 7) -#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ -#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ -#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ -#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ -#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ -#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ - -#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */ -#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ -#define AT91_SDRAMC_LPCB_DISABLE 0 -#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 -#define AT91_SDRAMC_LPCB_POWER_DOWN 2 -#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 -#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ -#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ -#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ -#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ -#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) -#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) -#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) - -#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */ -#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ - -#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */ -#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ -#define AT91_SDRAMC_MD_SDRAM 0 -#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 - -#ifndef __ASSEMBLY__ -#include <io.h> -static inline u32 at91_get_sdram_size(void *base) -{ - u32 val; - u32 size; - - val = readl(base + AT91_SDRAMC_CR); - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (val & AT91_SDRAMC_NC) + 8; - /* ROW */ - size += ((val & AT91_SDRAMC_NR) >> 2) + 11; - /* BANK */ - size = ((val & AT91_SDRAMC_NB) ? 4 : 2) << size; - /* bandwidth */ - if (!(val & AT91_SDRAMC_DBW)) - size <<= 1; - - return size; -} - - -static inline bool at91_is_low_power_sdram(void *base) -{ - return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM; -} - -#ifdef CONFIG_SOC_AT91SAM9260 -#include <mach/at91sam9260.h> -static inline u32 at91sam9260_get_sdram_size(void) -{ - return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)); -} - -static inline bool at91sam9260_is_low_power_sdram(void) -{ - return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC)); -} -#else -static inline u32 at91sam9260_get_sdram_size(void) -{ - return 0; -} - -static inline bool at91sam9260_is_low_power_sdram(void) -{ - return false; -} -#endif - -#ifdef CONFIG_SOC_AT91SAM9261 -#include <mach/at91sam9261.h> -static inline u32 at91sam9261_get_sdram_size(void) -{ - return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC)); -} - -static inline bool at91sam9261_is_low_power_sdram(void) -{ - return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC)); -} -#else -static inline u32 at91sam9261_get_sdram_size(void) -{ - return 0; -} - -static inline bool at91sam9261_is_low_power_sdram(void) -{ - return false; -} -#endif - -#ifdef CONFIG_SOC_AT91SAM9263 -#include <mach/at91sam9263.h> -static inline u32 at91sam9263_get_sdram_size(int bank) -{ - switch (bank) { - case 0: - return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0)); - case 1: - return at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC1)); - default: - return 0; - } -} - -static inline bool at91sam9263_is_low_power_sdram(int bank) -{ - switch (bank) { - case 0: - return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC0)); - case 1: - return at91_is_low_power_sdram(IOMEM(AT91SAM9263_BASE_SDRAMC1)); - default: - return false; - } -} -#else -static inline u32 at91sam9263_get_sdram_size(int bank) -{ - return 0; -} - -static inline bool at91sam9263_is_low_power_sdram(void) -{ - return false; -} -#endif - -#endif - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h deleted file mode 100644 index 0908f6df25..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] - * - * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. - * - * Static Memory Controllers (SMC) - System peripherals registers. - * Based on AT91SAM9261 datasheet revision D. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9_SMC_H -#define AT91SAM9_SMC_H - -#ifndef __ASSEMBLY__ -struct sam9_smc_config { - /* Setup register */ - u8 ncs_read_setup; - u8 nrd_setup; - u8 ncs_write_setup; - u8 nwe_setup; - - /* Pulse register */ - u8 ncs_read_pulse; - u8 nrd_pulse; - u8 ncs_write_pulse; - u8 nwe_pulse; - - /* Cycle register */ - u16 read_cycle; - u16 write_cycle; - - /* Mode register */ - u32 mode; - u8 tdf_cycles:4; - - /* Timings register */ - u8 tclr; - u8 tadl; - u8 tar; - u8 ocms; - u8 trr; - u8 twb; - u8 rbnsel; - u8 nfsel; -}; - -extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); - -extern void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config); -#endif - -#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ -#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ -#define AT91_SMC_NWESETUP_(x) ((x) << 0) -#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ -#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) -#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ -#define AT91_SMC_NRDSETUP_(x) ((x) << 16) -#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ -#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) - -#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ -#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ -#define AT91_SMC_NWEPULSE_(x) ((x) << 0) -#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ -#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) -#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ -#define AT91_SMC_NRDPULSE_(x) ((x) << 16) -#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ -#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) - -#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ -#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ -#define AT91_SMC_NWECYCLE_(x) ((x) << 0) -#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ -#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) - -#define AT91_SAMA5_SMC_TIMINGS 0x0c /* Timings register for CS n */ -#define AT91_SMC_TCLR (0x0f << 0) /* CLE to REN Low Delay */ -#define AT91_SMC_TCLR_(x) ((x) << 0) -#define AT91_SMC_TADL (0x0f << 4) /* ALE to Data Start */ -#define AT91_SMC_TADL_(x) ((x) << 4) -#define AT91_SMC_TAR (0x0f << 8) /* ALE to REN Low Delay */ -#define AT91_SMC_TAR_(x) ((x) << 8) -#define AT91_SMC_OCMS (0x1 << 12) /* Off Chip Memory Scrambling Enable */ -#define AT91_SMC_OCMS_(x) ((x) << 12) -#define AT91_SMC_TRR (0x0f << 16) /* Ready to REN Low Delay */ -#define AT91_SMC_TRR_(x) ((x) << 16) -#define AT91_SMC_TWB (0x0f << 24) /* WEN High to REN to Busy */ -#define AT91_SMC_TWB_(x) ((x) << 24) -#define AT91_SMC_RBNSEL (0x07 << 28) /* Ready/Busy Line Selection */ -#define AT91_SMC_RBNSEL_(x) ((x) << 28) -#define AT91_SMC_NFSEL (0x01 << 31) /* Nand Flash Selection */ -#define AT91_SMC_NFSEL_(x) ((x) << 31) - -#define AT91_SAM9_SMC_MODE 0xc -#define AT91_SAMA5_SMC_MODE 0x10 -#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ -#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ -#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ -#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) -#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) -#define AT91_SMC_EXNWMODE_READY (3 << 4) -#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ -#define AT91_SMC_BAT_SELECT (0 << 8) -#define AT91_SMC_BAT_WRITE (1 << 8) -#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ -#define AT91_SMC_DBW_8 (0 << 12) -#define AT91_SMC_DBW_16 (1 << 12) -#define AT91_SMC_DBW_32 (2 << 12) -#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ -#define AT91_SMC_TDF_(x) ((x) << 16) -#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ -#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ -#define AT91_SMC_PS (3 << 28) /* Page Size */ -#define AT91_SMC_PS_4 (0 << 28) -#define AT91_SMC_PS_8 (1 << 28) -#define AT91_SMC_PS_16 (2 << 28) -#define AT91_SMC_PS_32 (3 << 28) - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h deleted file mode 100644 index f79df0b8c3..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9G45 family - * - * Copyright (C) 2008-2009 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_H -#define AT91SAM9G45_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TCB0 0xfff7c000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TCB1 0xfffd4000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 - -/* - * System Peripherals - */ -#define AT91SAM9G45_BASE_ECC 0xffffe200 -#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400 -#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600 -#define AT91SAM9G45_BASE_DMA 0xffffec00 -#define AT91SAM9G45_BASE_SMC 0xffffe800 -#define AT91SAM9G45_BASE_MATRIX 0xffffea00 -#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 -#define AT91SAM9G45_BASE_PIOA 0xfffff200 -#define AT91SAM9G45_BASE_PIOB 0xfffff400 -#define AT91SAM9G45_BASE_PIOC 0xfffff600 -#define AT91SAM9G45_BASE_PIOD 0xfffff800 -#define AT91SAM9G45_BASE_PIOE 0xfffffa00 -#define AT91SAM9G45_BASE_RSTC 0xfffffd00 -#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 -#define AT91SAM9G45_BASE_RTT 0xfffffd20 -#define AT91SAM9G45_BASE_PIT 0xfffffd30 -#define AT91SAM9G45_BASE_WDT 0xfffffd40 -#define AT91SAM9G45_BASE_RTC 0xfffffdb0 -#define AT91SAM9G45_BASE_GPBR 0xfffffd60 - -/* - * Internal Memory. - */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h deleted file mode 100644 index 53f50fef8f..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9G45 family - * - * Copyright (C) 2008-2009 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9G45 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9G45_MATRIX_H -#define AT91SAM9G45_MATRIX_H - -#define AT91SAM9G45_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9G45_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9G45_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9G45_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9G45_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9G45_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9G45_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */ -#define AT91SAM9G45_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */ -#define AT91SAM9G45_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */ -#define AT91SAM9G45_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */ -#define AT91SAM9G45_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */ -#define AT91SAM9G45_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */ -#define AT91SAM9G45_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9G45_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9G45_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9G45_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9G45_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9G45_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91SAM9G45_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91SAM9G45_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91SAM9G45_MATRIX_ULBT_128 (7 << 0) - -#define AT91SAM9G45_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9G45_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9G45_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9G45_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9G45_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9G45_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */ -#define AT91SAM9G45_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */ -#define AT91SAM9G45_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */ -#define AT91SAM9G45_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9G45_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9G45_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9G45_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */ -#define AT91SAM9G45_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9G45_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */ -#define AT91SAM9G45_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9G45_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */ -#define AT91SAM9G45_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9G45_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */ -#define AT91SAM9G45_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9G45_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */ -#define AT91SAM9G45_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */ -#define AT91SAM9G45_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */ -#define AT91SAM9G45_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */ -#define AT91SAM9G45_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */ -#define AT91SAM9G45_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */ -#define AT91SAM9G45_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */ -#define AT91SAM9G45_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9G45_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9G45_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9G45_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9G45_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9G45_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91SAM9G45_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91SAM9G45_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91SAM9G45_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91SAM9G45_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91SAM9G45_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91SAM9G45_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91SAM9G45_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9G45_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9G45_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9G45_MATRIX_RCB2 (1 << 2) -#define AT91SAM9G45_MATRIX_RCB3 (1 << 3) -#define AT91SAM9G45_MATRIX_RCB4 (1 << 4) -#define AT91SAM9G45_MATRIX_RCB5 (1 << 5) -#define AT91SAM9G45_MATRIX_RCB6 (1 << 6) -#define AT91SAM9G45_MATRIX_RCB7 (1 << 7) -#define AT91SAM9G45_MATRIX_RCB8 (1 << 8) -#define AT91SAM9G45_MATRIX_RCB9 (1 << 9) -#define AT91SAM9G45_MATRIX_RCB10 (1 << 10) -#define AT91SAM9G45_MATRIX_RCB11 (1 << 11) - -#define AT91SAM9G45_MATRIX_TCMR (0x110) /* TCM Configuration Register */ -#define AT91SAM9G45_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91SAM9G45_MATRIX_ITCM_0 (0 << 0) -#define AT91SAM9G45_MATRIX_ITCM_32 (6 << 0) -#define AT91SAM9G45_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91SAM9G45_MATRIX_DTCM_0 (0 << 4) -#define AT91SAM9G45_MATRIX_DTCM_32 (6 << 4) -#define AT91SAM9G45_MATRIX_DTCM_64 (7 << 4) -#define AT91SAM9G45_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91SAM9G45_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91SAM9G45_MATRIX_TCM_ONE_WS (0x1 << 11) - -#define AT91SAM9G45_MATRIX_VIDEO (0x118) /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) - -#define AT91SAM9G45_MATRIX_EBICSA (0x128) /* EBI Chip Select Assignment Register */ -#define AT91SAM9G45_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91SAM9G45_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91SAM9G45_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91SAM9G45_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91SAM9G45_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91SAM9G45_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9G45_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91SAM9G45_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) - -#define AT91SAM9G45_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */ -#define AT91SAM9G45_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91SAM9G45_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91SAM9G45_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91SAM9G45_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91SAM9G45_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */ -#define AT91SAM9G45_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91SAM9G45_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91SAM9G45_MATRIX_WPSR_WPV (1 << 0) -#define AT91SAM9G45_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h deleted file mode 100644 index dd9c0fc4e0..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9N12 SoC - * - * Copyright (C) 2011 Atmel Corporation - * - * Common definitions. - * Based on AT91SAM9N12 preliminary datasheet - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __MACH_AT91SAM9N12_H_ -#define __MACH_AT91SAM9N12_H_ - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -/* Reserved 4 */ -#define AT91SAM9N12_ID_USART0 5 /* USART 0 */ -#define AT91SAM9N12_ID_USART1 6 /* USART 1 */ -#define AT91SAM9N12_ID_USART2 7 /* USART 2 */ -#define AT91SAM9N12_ID_USART3 8 /* USART 3 */ -#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */ -/* Reserved 11 */ -#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9N12_ID_UART0 15 /* UART 0 */ -#define AT91SAM9N12_ID_UART1 16 /* UART 1 */ -#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9N12_ID_DMA 20 /* DMA Controller 0 */ -/* Reserved 21 */ -#define AT91SAM9N12_ID_UHPFS 22 /* USB Host Full Speed */ -#define AT91SAM9N12_ID_UDPFS 23 /* USB Device Full Speed */ -/* Reserved 24 */ -#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */ -/* Reserved 26 */ -/* Reserved 27 */ -#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */ -/* Reserved 29 */ -#define AT91SAM9N12_ID_TRNG 30 /* True Random Number Generator */ -#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9N12_BASE_SPI0 0xf0000000 -#define AT91SAM9N12_BASE_SPI1 0xf0004000 -#define AT91SAM9N12_BASE_MCI 0xf0008000 -#define AT91SAM9N12_BASE_SSC 0xf0010000 -#define AT91SAM9N12_BASE_TCB0 0xf8008000 -#define AT91SAM9N12_BASE_TC0 0xf8008000 -#define AT91SAM9N12_BASE_TC1 0xf8008040 -#define AT91SAM9N12_BASE_TC2 0xf8008080 -#define AT91SAM9N12_BASE_TCB1 0xf800c000 -#define AT91SAM9N12_BASE_TC3 0xf800c000 -#define AT91SAM9N12_BASE_TC4 0xf800c040 -#define AT91SAM9N12_BASE_TC5 0xf800c080 -#define AT91SAM9N12_BASE_TWI0 0xf8010000 -#define AT91SAM9N12_BASE_TWI1 0xf8014000 -#define AT91SAM9N12_BASE_USART0 0xf801c000 -#define AT91SAM9N12_BASE_USART1 0xf8020000 -#define AT91SAM9N12_BASE_USART2 0xf8024000 -#define AT91SAM9N12_BASE_USART3 0xf8028000 -#define AT91SAM9N12_BASE_PWMC 0xf8034000 -#define AT91SAM9N12_BASE_LCDC 0xf8038000 -#define AT91SAM9N12_BASE_UDPFS 0xf803c000 -#define AT91SAM9N12_BASE_UART0 0xf8040000 -#define AT91SAM9N12_BASE_UART1 0xf8044000 -#define AT91SAM9N12_BASE_TRNG 0xf8048000 -#define AT91SAM9N12_BASE_ADC 0xf804c000 - -/* - * System Peripherals - */ -#define AT91SAM9N12_BASE_FUSE 0xffffdc00 -#define AT91SAM9N12_BASE_MATRIX 0xffffde00 -#define AT91SAM9N12_BASE_PMECC 0xffffe000 -#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600 -#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800 -#define AT91SAM9N12_BASE_SMC 0xffffea00 -#define AT91SAM9N12_BASE_DMA 0xffffec00 -#define AT91SAM9N12_BASE_AIC 0xfffff000 -#define AT91SAM9N12_BASE_DBGU 0xfffff200 -#define AT91SAM9N12_BASE_PIOA 0xfffff400 -#define AT91SAM9N12_BASE_PIOB 0xfffff600 -#define AT91SAM9N12_BASE_PIOC 0xfffff800 -#define AT91SAM9N12_BASE_PIOD 0xfffffa00 -#define AT91SAM9N12_BASE_PMC 0xfffffc00 -#define AT91SAM9N12_BASE_RSTC 0xfffffe00 -#define AT91SAM9N12_BASE_SHDWC 0xfffffe10 -#define AT91SAM9N12_BASE_PIT 0xfffffe30 -#define AT91SAM9N12_BASE_WDT 0xfffffe40 -#define AT91SAM9N12_BASE_GPBR 0xfffffe60 -#define AT91SAM9N12_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9N12_ROM_SIZE SZ_1M /* Internal ROM size (1Mb) */ - -#define AT91SAM9N12_SMD_BASE 0x00400000 /* SMD Controller */ -#define AT91SAM9N12_OHCI_BASE 0x00500000 /* USB Host controller (OHCI) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h deleted file mode 100644 index bdb0211abc..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Matrix-Centric header file for the AT91SAM9N12 SoC - * - * Copyright (C) 2011 Atmel Corporation - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9N12 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _AT91SAM9N12_MATRIX_H_ -#define _AT91SAM9N12_MATRIX_H_ - -#define AT91SAM9N12_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9N12_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9N12_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9N12_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9N12_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9N12_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9N12_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9N12_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9N12_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9N12_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9N12_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9N12_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91SAM9N12_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91SAM9N12_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91SAM9N12_MATRIX_ULBT_128 (7 << 0) - -#define AT91SAM9N12_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9N12_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9N12_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9N12_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9N12_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9N12_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9N12_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9N12_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9N12_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9N12_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9N12_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9N12_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9N12_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9N12_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9N12_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9N12_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9N12_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9N12_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91SAM9N12_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9N12_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9N12_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9N12_MATRIX_RCB2 (1 << 2) -#define AT91SAM9N12_MATRIX_RCB3 (1 << 3) -#define AT91SAM9N12_MATRIX_RCB4 (1 << 4) -#define AT91SAM9N12_MATRIX_RCB5 (1 << 5) - -#define AT91SAM9N12_MATRIX_EBICSA (0x118) /* EBI Chip Select Assignment Register */ -#define AT91SAM9N12_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9N12_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91SAM9N12_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91SAM9N12_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) -#define AT91SAM9N12_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9N12_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91SAM9N12_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91SAM9N12_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */ -#define AT91SAM9N12_MATRIX_EBI_DBPD_ON (0 << 9) -#define AT91SAM9N12_MATRIX_EBI_DBPD_OFF (1 << 9) -#define AT91SAM9N12_MATRIX_EBI_DRIVE (1 << 17) /* EBI I/O Drive Configuration */ -#define AT91SAM9N12_MATRIX_EBI_LOW_DRIVE (0 << 17) -#define AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE (1 << 17) -#define AT91SAM9N12_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ -#define AT91SAM9N12_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91SAM9N12_MATRIX_NFD0_ON_D16 (1 << 24) - -#define AT91SAM9N12_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */ -#define AT91SAM9N12_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91SAM9N12_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91SAM9N12_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91SAM9N12_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91SAM9N12_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */ -#define AT91SAM9N12_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91SAM9N12_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91SAM9N12_MATRIX_WPSR_WPV (1 << 0) -#define AT91SAM9N12_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h deleted file mode 100644 index f9d54df601..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Chip-specific header file for the AT91SAM9x5 family - * - * Copyright (C) 2009-2010 Atmel Corporation. - * - * Common definitions. - * Based on AT91SAM9x5 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9X5_H -#define AT91SAM9X5_H - -/* - * Peripheral identifiers/interrupts. - */ -#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */ -#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */ -#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */ -#define AT91SAM9X5_ID_USART0 5 /* USART 0 */ -#define AT91SAM9X5_ID_USART1 6 /* USART 1 */ -#define AT91SAM9X5_ID_USART2 7 /* USART 2 */ -#define AT91SAM9X5_ID_USART3 8 /* USART 3 */ -#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */ -#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */ -#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */ -#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */ -#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */ -#define AT91SAM9X5_ID_UART0 15 /* UART 0 */ -#define AT91SAM9X5_ID_UART1 16 /* UART 1 */ -#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */ -#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */ -#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */ -#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */ -#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */ -#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */ -#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */ -#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */ -#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */ -#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */ -#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */ -#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -/* - * User Peripheral physical base addresses. - */ -#define AT91SAM9X5_BASE_SPI0 0xf0000000 -#define AT91SAM9X5_BASE_SPI1 0xf0004000 -#define AT91SAM9X5_BASE_MCI0 0xf0008000 -#define AT91SAM9X5_BASE_MCI1 0xf000c000 -#define AT91SAM9X5_BASE_SSC 0xf0010000 -#define AT91SAM9X5_BASE_CAN0 0xf8000000 -#define AT91SAM9X5_BASE_CAN1 0xf8004000 -#define AT91SAM9X5_BASE_TCB0 0xf8008000 -#define AT91SAM9X5_BASE_TC0 0xf8008000 -#define AT91SAM9X5_BASE_TC1 0xf8008040 -#define AT91SAM9X5_BASE_TC2 0xf8008080 -#define AT91SAM9X5_BASE_TCB1 0xf800c000 -#define AT91SAM9X5_BASE_TC3 0xf800c000 -#define AT91SAM9X5_BASE_TC4 0xf800c040 -#define AT91SAM9X5_BASE_TC5 0xf800c080 -#define AT91SAM9X5_BASE_TWI0 0xf8010000 -#define AT91SAM9X5_BASE_TWI1 0xf8014000 -#define AT91SAM9X5_BASE_TWI2 0xf8018000 -#define AT91SAM9X5_BASE_USART0 0xf801c000 -#define AT91SAM9X5_BASE_USART1 0xf8020000 -#define AT91SAM9X5_BASE_USART2 0xf8024000 -#define AT91SAM9X5_BASE_USART3 0xf8028000 -#define AT91SAM9X5_BASE_EMAC0 0xf802c000 -#define AT91SAM9X5_BASE_EMAC1 0xf8030000 -#define AT91SAM9X5_BASE_PWMC 0xf8034000 -#define AT91SAM9X5_BASE_LCDC 0xf8038000 -#define AT91SAM9X5_BASE_UDPHS 0xf803c000 -#define AT91SAM9X5_BASE_UART0 0xf8040000 -#define AT91SAM9X5_BASE_UART1 0xf8044000 -#define AT91SAM9X5_BASE_ISI 0xf8048000 -#define AT91SAM9X5_BASE_ADC 0xf804c000 - -/* - * System Peripherals - */ -#define AT91SAM9X5_BASE_MATRIX 0xffffde00 -#define AT91SAM9X5_BASE_PMECC 0xffffe000 -#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600 -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 -#define AT91SAM9X5_BASE_SMC 0xffffea00 -#define AT91SAM9X5_BASE_DMA0 0xffffec00 -#define AT91SAM9X5_BASE_DMA1 0xffffee00 -#define AT91SAM9X5_BASE_AIC 0xfffff000 -#define AT91SAM9X5_BASE_DBGU 0xfffff200 -#define AT91SAM9X5_BASE_PIOA 0xfffff400 -#define AT91SAM9X5_BASE_PIOB 0xfffff600 -#define AT91SAM9X5_BASE_PIOC 0xfffff800 -#define AT91SAM9X5_BASE_PIOD 0xfffffa00 -#define AT91SAM9X5_BASE_PMC 0xfffffc00 -#define AT91SAM9X5_BASE_RSTC 0xfffffe00 -#define AT91SAM9X5_BASE_SHDWC 0xfffffe10 -#define AT91SAM9X5_BASE_PIT 0xfffffe30 -#define AT91SAM9X5_BASE_WDT 0xfffffe40 -#define AT91SAM9X5_BASE_GPBR 0xfffffe60 -#define AT91SAM9X5_BASE_RTC 0xfffffeb0 - -/* - * Internal Memory. - */ -#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */ - -#define AT91SAM9X5_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ - -#define AT91SAM9X5_SMD_BASE 0x00400000 /* SMD Controller */ -#define AT91SAM9X5_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ -#define AT91SAM9X5_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */ -#define AT91SAM9X5_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h deleted file mode 100644 index fca7646d35..0000000000 --- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Matrix-centric header file for the AT91SAM9x5 family - * - * Copyright (C) 2009-2010 Atmel Corporation. - * - * Memory Controllers (MATRIX, EBI) - System peripherals registers. - * Based on AT91SAM9x5 preliminary datasheet. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91SAM9X5_MATRIX_H -#define AT91SAM9X5_MATRIX_H - -#define AT91SAM9X5_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */ -#define AT91SAM9X5_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */ -#define AT91SAM9X5_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */ -#define AT91SAM9X5_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */ -#define AT91SAM9X5_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */ -#define AT91SAM9X5_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */ -#define AT91SAM9X5_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */ -#define AT91SAM9X5_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */ -#define AT91SAM9X5_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */ -#define AT91SAM9X5_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */ -#define AT91SAM9X5_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */ -#define AT91SAM9X5_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */ -#define AT91SAM9X5_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91SAM9X5_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91SAM9X5_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91SAM9X5_MATRIX_ULBT_FOUR (2 << 0) -#define AT91SAM9X5_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91SAM9X5_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91SAM9X5_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91SAM9X5_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91SAM9X5_MATRIX_ULBT_128 (7 << 0) - -#define AT91SAM9X5_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */ -#define AT91SAM9X5_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */ -#define AT91SAM9X5_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */ -#define AT91SAM9X5_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */ -#define AT91SAM9X5_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */ -#define AT91SAM9X5_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */ -#define AT91SAM9X5_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */ -#define AT91SAM9X5_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */ -#define AT91SAM9X5_MATRIX_SCFG8 (0x60) /* Slave Configuration Register 8 */ -#define AT91SAM9X5_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91SAM9X5_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ - -#define AT91SAM9X5_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */ -#define AT91SAM9X5_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */ -#define AT91SAM9X5_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */ -#define AT91SAM9X5_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */ -#define AT91SAM9X5_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */ -#define AT91SAM9X5_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */ -#define AT91SAM9X5_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */ -#define AT91SAM9X5_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */ -#define AT91SAM9X5_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */ -#define AT91SAM9X5_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */ -#define AT91SAM9X5_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */ -#define AT91SAM9X5_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */ -#define AT91SAM9X5_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */ -#define AT91SAM9X5_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */ -#define AT91SAM9X5_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */ -#define AT91SAM9X5_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */ -#define AT91SAM9X5_MATRIX_PRAS8 (0xC0) /* Priority Register A for Slave 8 */ -#define AT91SAM9X5_MATRIX_PRBS8 (0xC4) /* Priority Register B for Slave 8 */ -#define AT91SAM9X5_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91SAM9X5_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91SAM9X5_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91SAM9X5_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91SAM9X5_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91SAM9X5_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91SAM9X5_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91SAM9X5_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91SAM9X5_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91SAM9X5_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91SAM9X5_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91SAM9X5_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ - -#define AT91SAM9X5_MATRIX_MRCR (0x100) /* Master Remap Control Register */ -#define AT91SAM9X5_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91SAM9X5_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91SAM9X5_MATRIX_RCB2 (1 << 2) -#define AT91SAM9X5_MATRIX_RCB3 (1 << 3) -#define AT91SAM9X5_MATRIX_RCB4 (1 << 4) -#define AT91SAM9X5_MATRIX_RCB5 (1 << 5) -#define AT91SAM9X5_MATRIX_RCB6 (1 << 6) -#define AT91SAM9X5_MATRIX_RCB7 (1 << 7) -#define AT91SAM9X5_MATRIX_RCB8 (1 << 8) -#define AT91SAM9X5_MATRIX_RCB9 (1 << 9) -#define AT91SAM9X5_MATRIX_RCB10 (1 << 10) -#define AT91SAM9X5_MATRIX_RCB11 (1 << 11) - -#define AT91SAM9X5_MATRIX_EBICSA (0x120) /* EBI Chip Select Assignment Register */ -#define AT91SAM9X5_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91SAM9X5_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91SAM9X5_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91SAM9X5_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3) -#define AT91SAM9X5_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91SAM9X5_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91SAM9X5_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) -#define AT91SAM9X5_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */ -#define AT91SAM9X5_MATRIX_NFD0_ON_D0 (0 << 24) -#define AT91SAM9X5_MATRIX_NFD0_ON_D16 (1 << 24) -#define AT91SAM9X5_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */ -#define AT91SAM9X5_MATRIX_MP_OFF (0 << 25) -#define AT91SAM9X5_MATRIX_MP_ON (1 << 25) - -#define AT91SAM9X5_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */ -#define AT91SAM9X5_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91SAM9X5_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91SAM9X5_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91SAM9X5_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ - -#define AT91SAM9X5_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */ -#define AT91SAM9X5_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91SAM9X5_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91SAM9X5_MATRIX_WPSR_WPV (1 << 0) -#define AT91SAM9X5_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h deleted file mode 100644 index e1aa693818..0000000000 --- a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h +++ /dev/null @@ -1,757 +0,0 @@ -/* - * Header file for AT91 High end LCD Controller - * - * Data structure and register user interface - * - * Copyright (C) 2010 Atmel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE. See the - * GNU General Public License for more details. - * - */ -#ifndef __MACH_ATMEL_HLCD_H__ -#define __MACH_ATMEL_HLCD_H__ - -/* Lcdc hardware registers */ -#define ATMEL_LCDC_LCDCFG0 0x0000 -#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) -#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) -#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) -#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) -#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) -#define LCDC_LCDCFG0_CGDISOVR2 (0x1 << 10) -#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) -#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) -#define LCDC_LCDCFG0_CGDISPP (0x1 << 13) -#define LCDC_LCDCFG0_CLKDIV_OFFSET 16 -#define LCDC_LCDCFG0_CLKDIV (0xff << LCDC_LCDCFG0_CLKDIV_OFFSET) - -#define ATMEL_LCDC_LCDCFG1 0x0004 -#define LCDC_LCDCFG1_HSPW_OFFSET 0 -#define LCDC_LCDCFG1_HSPW (0x3f << LCDC_LCDCFG1_HSPW_OFFSET) -#define LCDC_LCDCFG1_VSPW_OFFSET 16 -#define LCDC_LCDCFG1_VSPW (0x3f << LCDC_LCDCFG1_VSPW_OFFSET) - -#define ATMEL_LCDC_LCDCFG2 0x0008 -#define LCDC_LCDCFG2_VFPW_OFFSET 0 -#define LCDC_LCDCFG2_VFPW (0x3f << LCDC_LCDCFG2_VFPW_OFFSET) -#define LCDC_LCDCFG2_VBPW_OFFSET 16 -#define LCDC_LCDCFG2_VBPW (0x3f << LCDC_LCDCFG2_VBPW_OFFSET) - -#define ATMEL_LCDC_LCDCFG3 0x000C -#define LCDC_LCDCFG3_HFPW_OFFSET 0 -#define LCDC_LCDCFG3_HFPW (0xff << LCDC_LCDCFG3_HFPW_OFFSET) -#define LCDC2_LCDCFG3_HFPW (0x1ff << LCDC_LCDCFG3_HFPW_OFFSET) -#define LCDC_LCDCFG3_HBPW_OFFSET 16 -#define LCDC_LCDCFG3_HBPW (0xff << LCDC_LCDCFG3_HBPW_OFFSET) -#define LCDC2_LCDCFG3_HBPW (0x1ff << LCDC_LCDCFG3_HBPW_OFFSET) - -#define ATMEL_LCDC_LCDCFG4 0x0010 -#define LCDC_LCDCFG4_PPL_OFFSET 0 -#define LCDC_LCDCFG4_PPL (0x7ff << LCDC_LCDCFG4_PPL_OFFSET) -#define LCDC_LCDCFG4_RPF_OFFSET 16 -#define LCDC_LCDCFG4_RPF (0x7ff << LCDC_LCDCFG4_RPF_OFFSET) - -#define ATMEL_LCDC_LCDCFG5 0x0014 -#define LCDC_LCDCFG5_HSPOL (0x1 << 0) -#define LCDC_LCDCFG5_VSPOL (0x1 << 1) -#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) -#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) -#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) -#define LCDC_LCDCFG5_SERIAL (0x1 << 5) -#define LCDC_LCDCFG5_DITHER (0x1 << 6) -#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) -#define LCDC_LCDCFG5_MODE_OFFSET 8 -#define LCDC_LCDCFG5_MODE (0x3 << LCDC_LCDCFG5_MODE_OFFSET) -#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) -#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) -#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) -#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) -#define LCDC_LCDCFG5_PP (0x1 << 10) -#define LCDC_LCDCFG5_VSPSU (0x1 << 12) -#define LCDC_LCDCFG5_VSPHO (0x1 << 13) -#define LCDC_LCDCFG5_GUARDTIME_OFFSET 16 -#define LCDC_LCDCFG5_GUARDTIME (0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET) - -#define ATMEL_LCDC_LCDCFG6 0x0018 -#define LCDC_LCDCFG6_PWMPS_OFFSET 0 -#define LCDC_LCDCFG6_PWMPS (0x7 << LCDC_LCDCFG6_PWMPS_OFFSET) -#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) -#define LCDC_LCDCFG6_PWMCVAL_OFFSET 8 -#define LCDC_LCDCFG6_PWMCVAL (0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET) - -#define ATMEL_LCDC_LCDEN 0x0020 -#define LCDC_LCDEN_CLKEN (0x1 << 0) -#define LCDC_LCDEN_SYNCEN (0x1 << 1) -#define LCDC_LCDEN_DISPEN (0x1 << 2) -#define LCDC_LCDEN_PWMEN (0x1 << 3) - -#define ATMEL_LCDC_LCDDIS 0x0024 -#define LCDC_LCDDIS_CLKDIS (0x1 << 0) -#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) -#define LCDC_LCDDIS_DISPDIS (0x1 << 2) -#define LCDC_LCDDIS_PWMDIS (0x1 << 3) -#define LCDC_LCDDIS_CLKRST (0x1 << 8) -#define LCDC_LCDDIS_SYNCRST (0x1 << 9) -#define LCDC_LCDDIS_DISPRST (0x1 << 10) -#define LCDC_LCDDIS_PWMRST (0x1 << 11) - -#define ATMEL_LCDC_LCDSR 0x0028 -#define LCDC_LCDSR_CLKSTS (0x1 << 0) -#define LCDC_LCDSR_LCDSTS (0x1 << 1) -#define LCDC_LCDSR_DISPSTS (0x1 << 2) -#define LCDC_LCDSR_PWMSTS (0x1 << 3) -#define LCDC_LCDSR_SIPSTS (0x1 << 4) - -#define ATMEL_LCDC_LCDIER 0x002C -#define LCDC_LCDIER_SOFIE (0x1 << 0) -#define LCDC_LCDIER_DISIE (0x1 << 1) -#define LCDC_LCDIER_DISPIE (0x1 << 2) -#define LCDC_LCDIER_FIFOERRIE (0x1 << 4) -#define LCDC_LCDIER_BASEIE (0x1 << 8) -#define LCDC_LCDIER_OVR1IE (0x1 << 9) -#define LCDC_LCDIER_OVR2IE (0x1 << 10) -#define LCDC_LCDIER_HEOIE (0x1 << 11) -#define LCDC_LCDIER_HCRIE (0x1 << 12) -#define LCDC_LCDIER_PPIE (0x1 << 13) - -#define ATMEL_LCDC_LCDIDR 0x0030 -#define LCDC_LCDIDR_SOFID (0x1 << 0) -#define LCDC_LCDIDR_DISID (0x1 << 1) -#define LCDC_LCDIDR_DISPID (0x1 << 2) -#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) -#define LCDC_LCDIDR_BASEID (0x1 << 8) -#define LCDC_LCDIDR_OVR1ID (0x1 << 9) -#define LCDC_LCDIDR_OVR2ID (0x1 << 10) -#define LCDC_LCDIDR_HEOID (0x1 << 11) -#define LCDC_LCDIDR_HCRID (0x1 << 12) -#define LCDC_LCDIDR_PPID (0x1 << 13) - -#define ATMEL_LCDC_LCDIMR 0x0034 -#define LCDC_LCDIMR_SOFIM (0x1 << 0) -#define LCDC_LCDIMR_DISIM (0x1 << 1) -#define LCDC_LCDIMR_DISPIM (0x1 << 2) -#define LCDC_LCDIMR_FIFOERRIM (0x1 << 4) -#define LCDC_LCDIMR_BASEIM (0x1 << 8) -#define LCDC_LCDIMR_OVR1IM (0x1 << 9) -#define LCDC_LCDIMR_OVR2IM (0x1 << 10) -#define LCDC_LCDIMR_HEOIM (0x1 << 11) -#define LCDC_LCDIMR_HCRIM (0x1 << 12) -#define LCDC_LCDIMR_PPIM (0x1 << 13) - -#define ATMEL_LCDC_LCDISR 0x0038 -#define LCDC_LCDISR_SOF (0x1 << 0) -#define LCDC_LCDISR_DIS (0x1 << 1) -#define LCDC_LCDISR_DISP (0x1 << 2) -#define LCDC_LCDISR_FIFOERR (0x1 << 4) -#define LCDC_LCDISR_BASE (0x1 << 8) -#define LCDC_LCDISR_OVR1 (0x1 << 9) -#define LCDC_LCDISR_OVR2 (0x1 << 10) -#define LCDC_LCDISR_HEO (0x1 << 11) -#define LCDC_LCDISR_HCR (0x1 << 12) -#define LCDC_LCDISR_PP (0x1 << 13) - -#define ATMEL_LCDC_BASECHER 0x0040 -#define LCDC_BASECHER_CHEN (0x1 << 0) -#define LCDC_BASECHER_UPDATEEN (0x1 << 1) -#define LCDC_BASECHER_A2QEN (0x1 << 2) - -#define ATMEL_LCDC_BASECHDR 0x0044 -#define LCDC_BASECHDR_CHDIS (0x1 << 0) -#define LCDC_BASECHDR_CHRST (0x1 << 8) - -#define ATMEL_LCDC_BASECHSR 0x0048 -#define LCDC_BASECHSR_CHSR (0x1 << 0) -#define LCDC_BASECHSR_UPDATESR (0x1 << 1) -#define LCDC_BASECHSR_A2QSR (0x1 << 2) - -#define ATMEL_LCDC_BASEIER 0x004C -#define LCDC_BASEIER_DMA (0x1 << 2) -#define LCDC_BASEIER_DSCR (0x1 << 3) -#define LCDC_BASEIER_ADD (0x1 << 4) -#define LCDC_BASEIER_DONE (0x1 << 5) -#define LCDC_BASEIER_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEIDR 0x0050 -#define LCDC_BASEIDR_DMA (0x1 << 2) -#define LCDC_BASEIDR_DSCR (0x1 << 3) -#define LCDC_BASEIDR_ADD (0x1 << 4) -#define LCDC_BASEIDR_DONE (0x1 << 5) -#define LCDC_BASEIDR_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEIMR 0x0054 -#define LCDC_BASEIMR_DMA (0x1 << 2) -#define LCDC_BASEIMR_DSCR (0x1 << 3) -#define LCDC_BASEIMR_ADD (0x1 << 4) -#define LCDC_BASEIMR_DONE (0x1 << 5) -#define LCDC_BASEIMR_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEISR 0x0058 -#define LCDC_BASEISR_DMA (0x1 << 2) -#define LCDC_BASEISR_DSCR (0x1 << 3) -#define LCDC_BASEISR_ADD (0x1 << 4) -#define LCDC_BASEISR_DONE (0x1 << 5) -#define LCDC_BASEISR_OVR (0x1 << 6) - -#define ATMEL_LCDC_BASEHEAD 0x005C - -#define ATMEL_LCDC_BASEADDR 0x0060 - -#define ATMEL_LCDC_BASECTRL 0x0064 -#define LCDC_BASECTRL_DFETCH (0x1 << 0) -#define LCDC_BASECTRL_LFETCH (0x1 << 1) -#define LCDC_BASECTRL_DMAIEN (0x1 << 2) -#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) -#define LCDC_BASECTRL_ADDIEN (0x1 << 4) -#define LCDC_BASECTRL_DONEIEN (0x1 << 5) - -#define ATMEL_LCDC_BASENEXT 0x0068 - -#define ATMEL_LCDC_BASECFG0 0x006C -#define LCDC_BASECFG0_SIF (0x1 << 0) -#define LCDC_BASECFG0_BLEN_OFFSET 4 -#define LCDC_BASECFG0_BLEN (0x3 << LCDC_BASECFG0_BLEN_OFFSET) -#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) -#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) -#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) -#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) -#define LCDC_BASECFG0_DLBO (0x1 << 8) - -#define ATMEL_LCDC_BASECFG1 0x0070 -#define LCDC_BASECFG1_CLUTEN (0x1 << 0) -#define LCDC_BASECFG1_RGBMODE_OFFSET 4 -#define LCDC_BASECFG1_RGBMODE (0xf << LCDC_BASECFG1_RGBMODE_OFFSET) -#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) -#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) -#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) -#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) -#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) -#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) -#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) -#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) -#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) -#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) -#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) -#define LCDC_BASECFG1_CLUTMODE_OFFSET 8 -#define LCDC_BASECFG1_CLUTMODE (0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET) -#define LCDC_BASECFG1_CLUTMODE_1BPP (0x0 << 8) -#define LCDC_BASECFG1_CLUTMODE_2BPP (0x1 << 8) -#define LCDC_BASECFG1_CLUTMODE_4BPP (0x2 << 8) -#define LCDC_BASECFG1_CLUTMODE_8BPP (0x3 << 8) - -#define ATMEL_LCDC_BASECFG2 0x0074 - -#define ATMEL_LCDC_BASECFG3 0x0078 -#define LCDC_BASECFG3_BDEF_OFFSET 0 -#define LCDC_BASECFG3_BDEF (0xff << LCDC_BASECFG3_BDEF_OFFSET) -#define LCDC_BASECFG3_GDEF_OFFSET 8 -#define LCDC_BASECFG3_GDEF (0xff << LCDC_BASECFG3_GDEF_OFFSET) -#define LCDC_BASECFG3_RDEF_OFFSET 16 -#define LCDC_BASECFG3_RDEF (0xff << LCDC_BASECFG3_RDEF_OFFSET) - -#define ATMEL_LCDC_BASECFG4 0x007C -#define LCDC_BASECFG4_DMA (0x1 << 8) -#define LCDC_BASECFG4_REP (0x1 << 9) -#define LCDC_BASECFG4_DISCEN (0x1 << 11) - -#define ATMEL_LCDC_BASECFG5 0x0080 -#define LCDC_BASECFG5_DISCXPOS_OFFSET 0 -#define LCDC_BASECFG5_DISCXPOS (0x7ff << LCDC_BASECFG5_DISCXPOS_OFFSET) -#define LCDC_BASECFG5_DISCYPOS_OFFSET 16 -#define LCDC_BASECFG5_DISCYPOS (0x7ff << LCDC_BASECFG5_DISCYPOS_OFFSET) - -#define ATMEL_LCDC_BASECFG6 0x0084 -#define LCDC_BASECFG6_DISCXSIZE_OFFSET 0 -#define LCDC_BASECFG6_DISCXSIZE (0x7ff << LCDC_BASECFG6_DISCXSIZE_OFFSET) -#define LCDC_BASECFG6_DISCYSIZE_OFFSET 16 -#define LCDC_BASECFG6_DISCYSIZE (0x7ff << LCDC_BASECFG6_DISCYSIZE_OFFSET) - -#define ATMEL_LCDC_HEOCHER 0x0280 -#define ATMEL_LCDC2_HEOCHER 0x0340 -#define LCDC_HEOCHER_CHEN (0x1 << 0) -#define LCDC_HEOCHER_UPDATEEN (0x1 << 1) -#define LCDC_HEOCHER_A2QEN (0x1 << 2) - -#define ATMEL_LCDC_HEOCHDR 0x0284 -#define LCDC_HEOCHDR_CHDIS (0x1 << 0) -#define LCDC_HEOCHDR_CHRST (0x1 << 8) - -#define ATMEL_LCDC_HEOCHSR 0x0288 -#define LCDC_HEOCHSR_CHSR (0x1 << 0) -#define LCDC_HEOCHSR_UPDATESR (0x1 << 1) -#define LCDC_HEOCHSR_A2QSR (0x1 << 2) - -#define ATMEL_LCDC_HEOIER 0x028C -#define LCDC_HEOIER_DMA (0x1 << 2) -#define LCDC_HEOIER_DSCR (0x1 << 3) -#define LCDC_HEOIER_ADD (0x1 << 4) -#define LCDC_HEOIER_DONE (0x1 << 5) -#define LCDC_HEOIER_OVR (0x1 << 6) -#define LCDC_HEOIER_UDMA (0x1 << 10) -#define LCDC_HEOIER_UDSCR (0x1 << 11) -#define LCDC_HEOIER_UADD (0x1 << 12) -#define LCDC_HEOIER_UDONE (0x1 << 13) -#define LCDC_HEOIER_UOVR (0x1 << 14) -#define LCDC_HEOIER_VDMA (0x1 << 18) -#define LCDC_HEOIER_VDSCR (0x1 << 19) -#define LCDC_HEOIER_VADD (0x1 << 20) -#define LCDC_HEOIER_VDONE (0x1 << 21) -#define LCDC_HEOIER_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOIDR 0x0290 -#define LCDC_HEOIDR_DMA (0x1 << 2) -#define LCDC_HEOIDR_DSCR (0x1 << 3) -#define LCDC_HEOIDR_ADD (0x1 << 4) -#define LCDC_HEOIDR_DONE (0x1 << 5) -#define LCDC_HEOIDR_OVR (0x1 << 6) -#define LCDC_HEOIDR_UDMA (0x1 << 10) -#define LCDC_HEOIDR_UDSCR (0x1 << 11) -#define LCDC_HEOIDR_UADD (0x1 << 12) -#define LCDC_HEOIDR_UDONE (0x1 << 13) -#define LCDC_HEOIDR_UOVR (0x1 << 14) -#define LCDC_HEOIDR_VDMA (0x1 << 18) -#define LCDC_HEOIDR_VDSCR (0x1 << 19) -#define LCDC_HEOIDR_VADD (0x1 << 20) -#define LCDC_HEOIDR_VDONE (0x1 << 21) -#define LCDC_HEOIDR_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOIMR 0x0294 -#define LCDC_HEOIMR_DMA (0x1 << 2) -#define LCDC_HEOIMR_DSCR (0x1 << 3) -#define LCDC_HEOIMR_ADD (0x1 << 4) -#define LCDC_HEOIMR_DONE (0x1 << 5) -#define LCDC_HEOIMR_OVR (0x1 << 6) -#define LCDC_HEOIMR_UDMA (0x1 << 10) -#define LCDC_HEOIMR_UDSCR (0x1 << 11) -#define LCDC_HEOIMR_UADD (0x1 << 12) -#define LCDC_HEOIMR_UDONE (0x1 << 13) -#define LCDC_HEOIMR_UOVR (0x1 << 14) -#define LCDC_HEOIMR_VDMA (0x1 << 18) -#define LCDC_HEOIMR_VDSCR (0x1 << 19) -#define LCDC_HEOIMR_VADD (0x1 << 20) -#define LCDC_HEOIMR_VDONE (0x1 << 21) -#define LCDC_HEOIMR_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOISR 0x0298 -#define LCDC_HEOISR_DMA (0x1 << 2) -#define LCDC_HEOISR_DSCR (0x1 << 3) -#define LCDC_HEOISR_ADD (0x1 << 4) -#define LCDC_HEOISR_DONE (0x1 << 5) -#define LCDC_HEOISR_OVR (0x1 << 6) -#define LCDC_HEOISR_UDMA (0x1 << 10) -#define LCDC_HEOISR_UDSCR (0x1 << 11) -#define LCDC_HEOISR_UADD (0x1 << 12) -#define LCDC_HEOISR_UDONE (0x1 << 13) -#define LCDC_HEOISR_UOVR (0x1 << 14) -#define LCDC_HEOISR_VDMA (0x1 << 18) -#define LCDC_HEOISR_VDSCR (0x1 << 19) -#define LCDC_HEOISR_VADD (0x1 << 20) -#define LCDC_HEOISR_VDONE (0x1 << 21) -#define LCDC_HEOISR_VOVR (0x1 << 22) - -#define ATMEL_LCDC_HEOHEAD 0x029C - -#define ATMEL_LCDC_HEOADDR 0x02A0 - -#define ATMEL_LCDC_HEOCTRL 0x02A4 -#define LCDC_HEOCTRL_DFETCH (0x1 << 0) -#define LCDC_HEOCTRL_LFETCH (0x1 << 1) -#define LCDC_HEOCTRL_DMAIEN (0x1 << 2) -#define LCDC_HEOCTRL_DSCRIEN (0x1 << 3) -#define LCDC_HEOCTRL_ADDIEN (0x1 << 4) -#define LCDC_HEOCTRL_DONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HEONEXT 0x02A8 - -#define ATMEL_LCDC_HEOUHEAD 0x02AC - -#define ATMEL_LCDC_HEOUADDR 0x02B0 - -#define ATMEL_LCDC_HEOUCTRL 0x02B4 -#define LCDC_HEOUCTRL_UDFETCH (0x1 << 0) -#define LCDC_HEOUCTRL_UDMAIEN (0x1 << 2) -#define LCDC_HEOUCTRL_UDSCRIEN (0x1 << 3) -#define LCDC_HEOUCTRL_UADDIEN (0x1 << 4) -#define LCDC_HEOUCTRL_UDONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HEOUNEXT 0x02B8 - -#define ATMEL_LCDC_HEOVHEAD 0x02BC - -#define ATMEL_LCDC_HEOVADDR 0x02C0 - -#define ATMEL_LCDC_HEOVCTRL 0x02C4 -#define LCDC_HEOVCTRL_VDFETCH (0x1 << 0) -#define LCDC_HEOVCTRL_VDMAIEN (0x1 << 2) -#define LCDC_HEOVCTRL_VDSCRIEN (0x1 << 3) -#define LCDC_HEOVCTRL_VADDIEN (0x1 << 4) -#define LCDC_HEOVCTRL_VDONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HEOVNEXT 0x02C8 - -#define ATMEL_LCDC_HEOCFG0 0x02CC -#define LCDC_HEOCFG0_BLEN_OFFSET 4 -#define LCDC_HEOCFG0_BLEN (0x3 << LCDC_HEOCFG0_BLEN_OFFSET) -#define LCDC_HEOCFG0_BLEN_AHB_SINGLE (0x0 << 4) -#define LCDC_HEOCFG0_BLEN_AHB_INCR4 (0x1 << 4) -#define LCDC_HEOCFG0_BLEN_AHB_INCR8 (0x2 << 4) -#define LCDC_HEOCFG0_BLEN_AHB_INCR16 (0x3 << 4) -#define LCDC_HEOCFG0_BLENUV_OFFSET 6 -#define LCDC_HEOCFG0_BLENUV (0x3 << LCDC_HEOCFG0_BLENUV_OFFSET) -#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0 << 6) -#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1 << 6) -#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2 << 6) -#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3 << 6) -#define LCDC_HEOCFG0_DLBO (0x1 << 8) -#define LCDC_HEOCFG0_ROTDIS (0x1 << 12) -#define LCDC_HEOCFG0_LOCKDIS (0x1 << 13) - -#define ATMEL_LCDC_HEOCFG1 0x02D0 -#define LCDC_HEOCFG1_CLUTEN (0x1 << 0) -#define LCDC_HEOCFG1_YUVEN (0x1 << 1) -#define LCDC_HEOCFG1_RGBMODE_OFFSET 4 -#define LCDC_HEOCFG1_RGBMODE (0xf << LCDC_HEOCFG1_RGBMODE_OFFSET) -#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) -#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) -#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) -#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) -#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) -#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) -#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) -#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) -#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) -#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) -#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) -#define LCDC_HEOCFG1_CLUTMODE_OFFSET 8 -#define LCDC_HEOCFG1_CLUTMODE (0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET) -#define LCDC_HEOCFG1_CLUTMODE_1BPP (0x0 << 8) -#define LCDC_HEOCFG1_CLUTMODE_2BPP (0x1 << 8) -#define LCDC_HEOCFG1_CLUTMODE_4BPP (0x2 << 8) -#define LCDC_HEOCFG1_CLUTMODE_8BPP (0x3 << 8) -#define LCDC_HEOCFG1_YUVMODE_OFFSET 12 -#define LCDC_HEOCFG1_YUVMODE (0xf << LCDC_HEOCFG1_YUVMODE_OFFSET) -#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5 << 12) -#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6 << 12) -#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7 << 12) -#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8 << 12) -#define LCDC_HEOCFG1_YUV422ROT (0x1 << 16) -#define LCDC_HEOCFG1_YUV422SWP (0x1 << 17) - -#define ATMEL_LCDC_HEOCFG2 0x02D4 -#define LCDC_HEOCFG2_XOFFSET_OFFSET 0 -#define LCDC_HEOCFG2_XOFFSET (0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET) -#define LCDC_HEOCFG2_YOFFSET_OFFSET 16 -#define LCDC_HEOCFG2_YOFFSET (0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET) - -#define ATMEL_LCDC_HEOCFG3 0x02D8 -#define LCDC_HEOCFG3_XSIZE_OFFSET 0 -#define LCDC_HEOCFG3_XSIZE (0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET) -#define LCDC_HEOCFG3_YSIZE_OFFSET 16 -#define LCDC_HEOCFG3_YSIZE (0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET) - -#define ATMEL_LCDC_HEOCFG4 0x02DC -#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET 0 -#define LCDC_HEOCFG4_XMEM_SIZE (0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET) -#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET 16 -#define LCDC_HEOCFG4_YMEM_SIZE (0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET) - -#define ATMEL_LCDC_HEOCFG5 0x02E0 - -#define ATMEL_LCDC_HEOCFG6 0x02E4 - -#define ATMEL_LCDC_HEOCFG7 0x02E8 - -#define ATMEL_LCDC_HEOCFG8 0x02EC - -#define ATMEL_LCDC_HEOCFG9 0x02F0 -#define LCDC_HEOCFG9_BDEF_OFFSET 0 -#define LCDC_HEOCFG9_BDEF (0xff << LCDC_HEOCFG9_BDEF_OFFSET) -#define LCDC_HEOCFG9_GDEF_OFFSET 8 -#define LCDC_HEOCFG9_GDEF (0xff << LCDC_HEOCFG9_GDEF_OFFSET) -#define LCDC_HEOCFG9_RDEF_OFFSET 16 -#define LCDC_HEOCFG9_RDEF (0xff << LCDC_HEOCFG9_RDEF_OFFSET) - -#define ATMEL_LCDC_HEOCFG10 0x02F4 -#define LCDC_HEOCFG10_BKEY_OFFSET 0 -#define LCDC_HEOCFG10_BKEY (0xff << LCDC_HEOCFG10_BKEY_OFFSET) -#define LCDC_HEOCFG10_GKEY_OFFSET 8 -#define LCDC_HEOCFG10_GKEY (0xff << LCDC_HEOCFG10_GKEY_OFFSET) -#define LCDC_HEOCFG10_RKEY_OFFSET 16 -#define LCDC_HEOCFG10_RKEY (0xff << LCDC_HEOCFG10_RKEY_OFFSET) - -#define ATMEL_LCDC_HEOCFG11 0x02F8 -#define LCDC_HEOCFG11_BMASK_OFFSET 0 -#define LCDC_HEOCFG11_BMASK (0xff << LCDC_HEOCFG11_BMASK_OFFSET) -#define LCDC_HEOCFG11_GMASK_OFFSET 8 -#define LCDC_HEOCFG11_GMASK (0xff << LCDC_HEOCFG11_GMASK_OFFSET) -#define LCDC_HEOCFG11_RMASK_OFFSET 16 -#define LCDC_HEOCFG11_RMASK (0xff << LCDC_HEOCFG11_RMASK_OFFSET) - -#define ATMEL_LCDC_HEOCFG12 0x02FC -#define LCDC_HEOCFG12_CRKEY (0x1 << 0) -#define LCDC_HEOCFG12_INV (0x1 << 1) -#define LCDC_HEOCFG12_ITER2BL (0x1 << 2) -#define LCDC_HEOCFG12_ITER (0x1 << 3) -#define LCDC_HEOCFG12_REVALPHA (0x1 << 4) -#define LCDC_HEOCFG12_GAEN (0x1 << 5) -#define LCDC_HEOCFG12_LAEN (0x1 << 6) -#define LCDC_HEOCFG12_OVR (0x1 << 7) -#define LCDC_HEOCFG12_DMA (0x1 << 8) -#define LCDC_HEOCFG12_REP (0x1 << 9) -#define LCDC_HEOCFG12_DSTKEY (0x1 << 10) -#define LCDC_HEOCFG12_VIDPRI (0x1 << 12) -#define LCDC_HEOCFG12_GA_OFFSET 16 -#define LCDC_HEOCFG12_GA (0xff << LCDC_HEOCFG12_GA_OFFSET) - -#define ATMEL_LCDC_HEOCFG13 0x0300 -#define LCDC_HEOCFG13_XFACTOR_OFFSET 0 -#define LCDC_HEOCFG13_XFACTOR (0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET) -#define LCDC_HEOCFG13_YFACTOR_OFFSET 16 -#define LCDC_HEOCFG13_YFACTOR (0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET) -#define LCDC_HEOCFG13_SCALEN (0x1 << 31) - -#define ATMEL_LCDC_HEOCFG14 0x0304 -#define LCDC_HEOCFG14_CSCRY_OFFSET 0 -#define LCDC_HEOCFG14_CSCRY (0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET) -#define LCDC_HEOCFG14_CSCRU_OFFSET 10 -#define LCDC_HEOCFG14_CSCRU (0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET) -#define LCDC_HEOCFG14_CSCRV_OFFSET 20 -#define LCDC_HEOCFG14_CSCRV (0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET) -#define LCDC_HEOCFG14_CSCYOFF (0x1 << 30) - -#define ATMEL_LCDC_HEOCFG15 0x0308 -#define LCDC_HEOCFG15_CSCGY_OFFSET 0 -#define LCDC_HEOCFG15_CSCGY (0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET) -#define LCDC_HEOCFG15_CSCGU_OFFSET 10 -#define LCDC_HEOCFG15_CSCGU (0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET) -#define LCDC_HEOCFG15_CSCGV_OFFSET 20 -#define LCDC_HEOCFG15_CSCGV (0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET) -#define LCDC_HEOCFG15_CSCUOFF (0x1 << 30) - -#define ATMEL_LCDC_HEOCFG16 0x030C -#define LCDC_HEOCFG16_CSCBY_OFFSET 0 -#define LCDC_HEOCFG16_CSCBY (0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET) -#define LCDC_HEOCFG16_CSCBU_OFFSET 10 -#define LCDC_HEOCFG16_CSCBU (0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET) -#define LCDC_HEOCFG16_CSCBV_OFFSET 20 -#define LCDC_HEOCFG16_CSCBV (0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET) -#define LCDC_HEOCFG16_CSCVOFF (0x1 << 30) - -#define ATMEL_LCDC_HCRCHER 0x0340 -#define LCDC_HCRCHER_CHEN (0x1 << 0) -#define LCDC_HCRCHER_UPDATEEN (0x1 << 1) -#define LCDC_HCRCHER_A2QEN (0x1 << 2) - -#define ATMEL_LCDC_HCRCHDR 0x0344 -#define LCDC_HCRCHDR_CHDIS (0x1 << 0) -#define LCDC_HCRCHDR_CHRST (0x1 << 8) - -#define ATMEL_LCDC_HCRCHSR 0x0348 -#define LCDC_HCRCHSR_CHSR (0x1 << 0) -#define LCDC_HCRCHSR_UPDATESR (0x1 << 1) -#define LCDC_HCRCHSR_A2QSR (0x1 << 2) - -#define ATMEL_LCDC_HCRIER 0x034C -#define LCDC_HCRIER_DMA (0x1 << 2) -#define LCDC_HCRIER_DSCR (0x1 << 3) -#define LCDC_HCRIER_ADD (0x1 << 4) -#define LCDC_HCRIER_DONE (0x1 << 5) -#define LCDC_HCRIER_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRIDR 0x0350 -#define LCDC_HCRIDR_DMA (0x1 << 2) -#define LCDC_HCRIDR_DSCR (0x1 << 3) -#define LCDC_HCRIDR_ADD (0x1 << 4) -#define LCDC_HCRIDR_DONE (0x1 << 5) -#define LCDC_HCRIDR_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRIMR 0x0354 -#define LCDC_HCRIMR_DMA (0x1 << 2) -#define LCDC_HCRIMR_DSCR (0x1 << 3) -#define LCDC_HCRIMR_ADD (0x1 << 4) -#define LCDC_HCRIMR_DONE (0x1 << 5) -#define LCDC_HCRIMR_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRISR 0x0358 -#define LCDC_HCRISR_DMA (0x1 << 2) -#define LCDC_HCRISR_DSCR (0x1 << 3) -#define LCDC_HCRISR_ADD (0x1 << 4) -#define LCDC_HCRISR_DONE (0x1 << 5) -#define LCDC_HCRISR_OVR (0x1 << 6) - -#define ATMEL_LCDC_HCRHEAD 0x035C - -#define ATMEL_LCDC_HCRADDR 0x0360 - -#define ATMEL_LCDC_HCRCTRL 0x0364 -#define LCDC_HCRCTRL_DFETCH (0x1 << 0) -#define LCDC_HCRCTRL_LFETCH (0x1 << 1) -#define LCDC_HCRCTRL_DMAIEN (0x1 << 2) -#define LCDC_HCRCTRL_DSCRIEN (0x1 << 3) -#define LCDC_HCRCTRL_ADDIEN (0x1 << 4) -#define LCDC_HCRCTRL_DONEIEN (0x1 << 5) - -#define ATMEL_LCDC_HCRNEXT 0x0368 - -#define ATMEL_LCDC_HCRCFG0 0x036C -#define LCDC_HCRCFG0_BLEN_OFFSET 4 -#define LCDC_HCRCFG0_BLEN (0x3 << LCDC_HCRCFG0_BLEN_OFFSET) -#define LCDC_HCRCFG0_BLEN_AHB_SINGLE (0x0 << 4) -#define LCDC_HCRCFG0_BLEN_AHB_INCR4 (0x1 << 4) -#define LCDC_HCRCFG0_BLEN_AHB_INCR8 (0x2 << 4) -#define LCDC_HCRCFG0_BLEN_AHB_INCR16 (0x3 << 4) -#define LCDC_HCRCFG0_DLBO (0x1 << 8) - -#define ATMEL_LCDC_HCRCFG1 0x0370 -#define LCDC_HCRCFG1_CLUTEN (0x1 << 0) -#define LCDC_HCRCFG1_RGBMODE_OFFSET 4 -#define LCDC_HCRCFG1_RGBMODE (0xf << LCDC_HCRCFG1_RGBMODE_OFFSET) -#define LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) -#define LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) -#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) -#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) -#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) -#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) -#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) -#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) -#define LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) -#define LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) -#define LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) -#define LCDC_HCRCFG1_CLUTMODE_OFFSET 8 -#define LCDC_HCRCFG1_CLUTMODE (0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET) -#define LCDC_HCRCFG1_CLUTMODE_1BPP (0x0 << 8) -#define LCDC_HCRCFG1_CLUTMODE_2BPP (0x1 << 8) -#define LCDC_HCRCFG1_CLUTMODE_4BPP (0x2 << 8) -#define LCDC_HCRCFG1_CLUTMODE_8BPP (0x3 << 8) - -#define ATMEL_LCDC_HCRCFG2 0x0374 -#define LCDC_HCRCFG2_XOFFSET_OFFSET 0 -#define LCDC_HCRCFG2_XOFFSET (0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET) -#define LCDC_HCRCFG2_YOFFSET_OFFSET 16 -#define LCDC_HCRCFG2_YOFFSET (0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET) - -#define ATMEL_LCDC_HCRCFG3 0x0378 -#define LCDC_HCRCFG3_XSIZE_OFFSET 0 -#define LCDC_HCRCFG3_XSIZE (0x7f << LCDC_HCRCFG3_XSIZE_OFFSET) -#define LCDC_HCRCFG3_YSIZE_OFFSET 16 -#define LCDC_HCRCFG3_YSIZE (0x7f << LCDC_HCRCFG3_YSIZE_OFFSET) - -#define ATMEL_LCDC_HCRCFG4 0x037C - -#define ATMEL_LCDC_HCRCFG6 0x0384 -#define LCDC_HCRCFG6_BDEF_OFFSET 0 -#define LCDC_HCRCFG6_BDEF (0xff << LCDC_HCRCFG6_BDEF_OFFSET) -#define LCDC_HCRCFG6_GDEF_OFFSET 8 -#define LCDC_HCRCFG6_GDEF (0xff << LCDC_HCRCFG6_GDEF_OFFSET) -#define LCDC_HCRCFG6_RDEF_OFFSET 16 -#define LCDC_HCRCFG6_RDEF (0xff << LCDC_HCRCFG6_RDEF_OFFSET) - -#define ATMEL_LCDC_HCRCFG7 0x0388 -#define LCDC_HCRCFG7_BKEY_OFFSET 0 -#define LCDC_HCRCFG7_BKEY (0xff << LCDC_HCRCFG7_BKEY_OFFSET) -#define LCDC_HCRCFG7_GKEY_OFFSET 8 -#define LCDC_HCRCFG7_GKEY (0xff << LCDC_HCRCFG7_GKEY_OFFSET) -#define LCDC_HCRCFG7_RKEY_OFFSET 16 -#define LCDC_HCRCFG7_RKEY (0xff << LCDC_HCRCFG7_RKEY_OFFSET) - -#define ATMEL_LCDC_HCRCFG8 0x038C -#define LCDC_HCRCFG8_BMASK_OFFSET 0 -#define LCDC_HCRCFG8_BMASK (0xff << LCDC_HCRCFG8_BMASK_OFFSET) -#define LCDC_HCRCFG8_GMASK_OFFSET 8 -#define LCDC_HCRCFG8_GMASK (0xff << LCDC_HCRCFG8_GMASK_OFFSET) -#define LCDC_HCRCFG8_RMASK_OFFSET 16 -#define LCDC_HCRCFG8_RMASK (0xff << LCDC_HCRCFG8_RMASK_OFFSET) - -#define ATMEL_LCDC_HCRCFG9 0x0390 -#define LCDC_HCRCFG9_CRKEY (0x1 << 0) -#define LCDC_HCRCFG9_INV (0x1 << 1) -#define LCDC_HCRCFG9_ITER2BL (0x1 << 2) -#define LCDC_HCRCFG9_ITER (0x1 << 3) -#define LCDC_HCRCFG9_REVALPHA (0x1 << 4) -#define LCDC_HCRCFG9_GAEN (0x1 << 5) -#define LCDC_HCRCFG9_LAEN (0x1 << 6) -#define LCDC_HCRCFG9_OVR (0x1 << 7) -#define LCDC_HCRCFG9_DMA (0x1 << 8) -#define LCDC_HCRCFG9_REP (0x1 << 9) -#define LCDC_HCRCFG9_DSTKEY (0x1 << 10) -#define LCDC_HCRCFG9_GA_OFFSET 16 -#define LCDC_HCRCFG9_GA_Msk (0xff << LCDC_HCRCFG9_GA_OFFSET) - -#define ATMEL_LCDC_BASECLUT 0x400 -#define ATMEL_LCDC2_BASECLUT 0x600 -#define LCDC_BASECLUT_BCLUT_OFFSET 0 -#define LCDC_BASECLUT_BCLUT (0xff << LCDC_BASECLUT_BCLUT_OFFSET) -#define LCDC_BASECLUT_GCLUT_OFFSET 8 -#define LCDC_BASECLUT_GCLUT (0xff << LCDC_BASECLUT_GCLUT_OFFSET) -#define LCDC_BASECLUT_RCLUT_OFFSET 16 -#define LCDC_BASECLUT_RCLUT (0xff << LCDC_BASECLUT_RCLUT_OFFSET) - -#define ATMEL_LCDC_OVR1CLUT 0x800 -#define ATMEL_LCDC2_OVR1CLUT 0xa00 -#define LCDC_OVR1CLUT_BCLUT_OFFSET 0 -#define LCDC_OVR1CLUT_BCLUT (0xff << LCDC_OVR1CLUT_BCLUT_OFFSET) -#define LCDC_OVR1CLUT_GCLUT_OFFSET 8 -#define LCDC_OVR1CLUT_GCLUT (0xff << LCDC_OVR1CLUT_GCLUT_OFFSET) -#define LCDC_OVR1CLUT_RCLUT_OFFSET 16 -#define LCDC_OVR1CLUT_RCLUT (0xff << LCDC_OVR1CLUT_RCLUT_OFFSET) -#define LCDC_OVR1CLUT_ACLUT_OFFSET 24 -#define LCDC_OVR1CLUT_ACLUT (0xff << LCDC_OVR1CLUT_ACLUT_OFFSET) - -#define ATMEL_LCDC_OVR2CLUT 0xe00 -#define LCDC_OVR2CLUT_BCLUT_OFFSET 0 -#define LCDC_OVR2CLUT_BCLUT (0xff << LCDC_OVR2CLUT_BCLUT_OFFSET) -#define LCDC_OVR2CLUT_GCLUT_OFFSET 8 -#define LCDC_OVR2CLUT_GCLUT (0xff << LCDC_OVR2CLUT_GCLUT_OFFSET) -#define LCDC_OVR2CLUT_RCLUT_OFFSET 16 -#define LCDC_OVR2CLUT_RCLUT (0xff << LCDC_OVR2CLUT_RCLUT_OFFSET) -#define LCDC_OVR2CLUT_ACLUT_OFFSET 24 -#define LCDC_OVR2CLUT_ACLUT (0xff << LCDC_OVR2CLUT_ACLUT_OFFSET) - -#define ATMEL_LCDC_HEOCLUT 0x1000 -#define ATMEL_LCDC2_HEOCLUT 0x1200 -#define LCDC_HEOCLUT_BCLUT_OFFSET 0 -#define LCDC_HEOCLUT_BCLUT (0xff << LCDC_HEOCLUT_BCLUT_OFFSET) -#define LCDC_HEOCLUT_GCLUT_OFFSET 8 -#define LCDC_HEOCLUT_GCLUT (0xff << LCDC_HEOCLUT_GCLUT_OFFSET) -#define LCDC_HEOCLUT_RCLUT_OFFSET 16 -#define LCDC_HEOCLUT_RCLUT (0xff << LCDC_HEOCLUT_RCLUT_OFFSET) -#define LCDC_HEOCLUT_ACLUT_OFFSET 24 -#define LCDC_HEOCLUT_ACLUT (0xff << LCDC_HEOCLUT_ACLUT_OFFSET) - -#define ATMEL_LCDC_HCRCLUT 0x1400 -#define ATMEL_LCDC2_HCRCLUT 0x1600 -#define LCDC_HCRCLUT_BCLUT_OFFSET 0 -#define LCDC_HCRCLUT_BCLUT (0xff << LCDC_HCRCLUT_BCLUT_OFFSET) -#define LCDC_HCRCLUT_GCLUT_OFFSET 8 -#define LCDC_HCRCLUT_GCLUT (0xff << LCDC_HCRCLUT_GCLUT_OFFSET) -#define LCDC_HCRCLUT_RCLUT_OFFSET 16 -#define LCDC_HCRCLUT_RCLUT (0xff << LCDC_HCRCLUT_RCLUT_OFFSET) -#define LCDC_HCRCLUT_ACLUT_OFFSET 24 -#define LCDC_HCRCLUT_ACLUT (0xff << LCDC_HCRCLUT_ACLUT_OFFSET) - -/* Base layer CLUT */ -#define ATMEL_HLCDC_LUT 0x0400 - - -#endif /* __MACH_ATMEL_HLCDC4_H__ */ diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h deleted file mode 100644 index e0e07500a2..0000000000 --- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef __MACH_ARM_HEAD_H -#define __MACH_ARM_HEAD_H - -#ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM -#define AT91_EXV6 ".word _barebox_image_size\n" -#else -#define AT91_EXV6 ".word _barebox_bare_init_size\n" -#endif - -static inline void __barebox_arm_head(void) -{ - __asm__ __volatile__ ( -#ifdef CONFIG_THUMB2_BAREBOX -#error Thumb2 is not supported -#else - "b 2f\n" - "1: b 1b\n" - "1: b 1b\n" - "1: b 1b\n" - "1: b 1b\n" - AT91_EXV6 /* image size to load by the bootrom */ - "1: b 1b\n" - "1: b 1b\n" -#endif - ".asciz \"barebox\"\n" - ".word _text\n" /* text base. If copied there, - * barebox can skip relocation - */ - ".word _barebox_image_size\n" /* image size to copy */ - ".rept 8\n" - ".word 0x55555555\n" - ".endr\n" - "2:\n" - ); -} - -static inline void barebox_arm_head(void) -{ - __barebox_arm_head(); - __asm__ __volatile__ ( - "b barebox_arm_reset_vector\n" - ); -} - -#endif /* __MACH_ARM_HEAD_H */ diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h deleted file mode 100644 index 4c4b51180c..0000000000 --- a/arch/arm/mach-at91/include/mach/board.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * [origin Linux: arch/arm/mach-at91/include/mach/board.h] - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include <mach/hardware.h> -#include <linux/sizes.h> -#include <net.h> -#include <i2c/i2c.h> -#include <spi/spi.h> -#include <linux/mtd/mtd.h> -#include <fb.h> -#include <video/atmel_lcdc.h> -#include <mach/atmel_hlcdc.h> -#include <linux/phy.h> -#include <platform_data/macb.h> - -void at91_set_main_clock(unsigned long rate); - -#define AT91_MAX_USBH_PORTS 3 - - /* USB Host */ -struct at91_usbh_data { - u8 ports; /* number of ports on root hub */ - int vbus_pin[AT91_MAX_USBH_PORTS]; /* port power-control pin */ - u8 vbus_pin_active_low[AT91_MAX_USBH_PORTS]; /* vbus polarity */ -}; -extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); -extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data); - -void atmel_nand_load_image(void *dest, int size, int pagesize, int blocksize); - - /* USB Device */ -struct at91_udc_data { - int vbus_pin; /* high == host powering us */ - u8 vbus_active_low; /* vbus polarity */ - u8 vbus_polled; /* Use polling, not interrupt */ - int pullup_pin; /* active == D+ pulled up */ - u8 pullup_active_low; /* true == pullup_pin is active low */ -}; -extern void __init at91_add_device_udc(struct at91_udc_data *data); - - /* NAND / SmartMedia */ -struct atmel_nand_data { - int enable_pin; /* chip enable */ - int det_pin; /* card detect */ - int rdy_pin; /* ready/busy */ - u8 ale; /* address line number connected to ALE */ - u8 cle; /* address line number connected to CLE */ - u8 bus_width_16; /* buswidth is 16 bit */ - u8 ecc_mode; /* NAND_ECC_* */ - u8 ecc_strength; /* number of bits to correct per ECC step */ - u8 ecc_size_shift; /* data bytes covered by a single ECC step.*/ - u8 on_flash_bbt; /* Use flash based bbt */ - u8 has_pmecc; /* Use PMECC */ - u8 bus_on_d0; - - u8 pmecc_corr_cap; - u16 pmecc_sector_size; - u32 pmecc_lookup_table_offset; -}; - -void at91_add_device_nand(struct atmel_nand_data *data); - - /* Ethernet (EMAC & MACB) */ -#define AT91SAM_ETX2_ETX3_ALTERNATIVE (1 << 0) - -void at91_add_device_eth(int id, struct macb_platform_data *data); - -void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices); - -/* SDRAM */ -void at91_add_device_sdram(u32 size); - - /* Serial */ -#define ATMEL_UART_CTS 0x01 -#define ATMEL_UART_RTS 0x02 -#define ATMEL_UART_DSR 0x04 -#define ATMEL_UART_DTR 0x08 -#define ATMEL_UART_DCD 0x10 -#define ATMEL_UART_RI 0x20 - -resource_size_t __init at91_configure_dbgu(void); -resource_size_t __init at91_configure_usart0(unsigned pins); -resource_size_t __init at91_configure_usart1(unsigned pins); -resource_size_t __init at91_configure_usart2(unsigned pins); -resource_size_t __init at91_configure_usart3(unsigned pins); -resource_size_t __init at91_configure_usart4(unsigned pins); -resource_size_t __init at91_configure_usart5(unsigned pins); -resource_size_t __init at91_configure_usart6(unsigned pins); - -#if defined(CONFIG_DRIVER_SERIAL_ATMEL) -static inline struct device_d * at91_register_uart(unsigned id, unsigned pins) -{ - resource_size_t start; - resource_size_t size = SZ_16K; - - switch (id) { - case 0: /* DBGU */ - start = at91_configure_dbgu(); - size = 512; - break; - case 1: - start = at91_configure_usart0(pins); - break; - case 2: - start = at91_configure_usart1(pins); - break; - case 3: - start = at91_configure_usart2(pins); - break; - case 4: - start = at91_configure_usart3(pins); - break; - case 5: - start = at91_configure_usart4(pins); - break; - case 6: - start = at91_configure_usart5(pins); - break; - default: - return NULL; - } - - return add_generic_device("atmel_usart", id, NULL, start, size, - IORESOURCE_MEM, NULL); -} -#else -static inline struct device_d * at91_register_uart(unsigned id, unsigned pins) -{ - return NULL; -} -#endif - -/* Multimedia Card Interface */ -struct atmel_mci_platform_data { - unsigned slot_b; - unsigned bus_width; - int detect_pin; - int wp_pin; - char *devname; -}; - -void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data); - -/* SPI Master platform data */ -struct at91_spi_platform_data { - int *chipselect; /* array of gpio_pins */ - int num_chipselect; /* chipselect array entry count */ -}; - -void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata); - -void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data); - -void at91sam_phy_reset(void __iomem *rstc_base); - -void at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr); -void at91sam9g45_reset(void __iomem *sdram, void __iomem *rstc_cr); - -#endif diff --git a/arch/arm/mach-at91/include/mach/bootstrap.h b/arch/arm/mach-at91/include/mach/bootstrap.h deleted file mode 100644 index a3d19dd54a..0000000000 --- a/arch/arm/mach-at91/include/mach/bootstrap.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - * - * Under GPLv2 - */ - -#ifndef __MACH_BOOTSTRAP_H__ -#define __MACH_BOOTSTRAP_H__ - -#ifdef CONFIG_MTD_M25P80 -void * bootstrap_board_read_m25p80(void); -#else -static inline void * bootstrap_board_read_m25p80(void) -{ - return NULL; -} -#endif - -#ifdef CONFIG_MTD_DATAFLASH -void * bootstrap_board_read_dataflash(void); -#else -static inline void * bootstrap_board_read_dataflash(void) -{ - return NULL; -} -#endif - -#endif /* __MACH_BOOTSTRAP_H__ */ diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h deleted file mode 100644 index 6e0f25f325..0000000000 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/cpu.h - * - * Copyright (C) 2006 SAN People - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __MACH_CPU_H__ -#define __MACH_CPU_H__ - -#define ARCH_ID_AT91RM9200 0x09290780 -#define ARCH_ID_AT91SAM9260 0x019803a0 -#define ARCH_ID_AT91SAM9261 0x019703a0 -#define ARCH_ID_AT91SAM9263 0x019607a0 -#define ARCH_ID_AT91SAM9G10 0x019903a0 -#define ARCH_ID_AT91SAM9G20 0x019905a0 -#define ARCH_ID_AT91SAM9RL64 0x019b03a0 -#define ARCH_ID_AT91SAM9G45 0x819b05a0 -#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ -#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ -#define ARCH_ID_AT91SAM9X5 0x819a05a0 -#define ARCH_ID_AT91SAM9N12 0x819a07a0 -#define ARCH_ID_SAMA5 0x8A5C07C0 - -#define ARCH_ID_AT91SAM9XE128 0x329973a0 -#define ARCH_ID_AT91SAM9XE256 0x329a93a0 -#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 - -#define ARCH_ID_AT91M40800 0x14080044 -#define ARCH_ID_AT91R40807 0x44080746 -#define ARCH_ID_AT91M40807 0x14080745 -#define ARCH_ID_AT91R40008 0x44000840 - -#define ARCH_EXID_AT91SAM9M11 0x00000001 -#define ARCH_EXID_AT91SAM9M10 0x00000002 -#define ARCH_EXID_AT91SAM9G46 0x00000003 -#define ARCH_EXID_AT91SAM9G45 0x00000004 - -#define ARCH_EXID_AT91SAM9G15 0x00000000 -#define ARCH_EXID_AT91SAM9G35 0x00000001 -#define ARCH_EXID_AT91SAM9X35 0x00000002 -#define ARCH_EXID_AT91SAM9G25 0x00000003 -#define ARCH_EXID_AT91SAM9X25 0x00000004 - -#define ARCH_EXID_AT91SAM9N12 0x00000006 -#define ARCH_EXID_AT91SAM9CN11 0x00000009 -#define ARCH_EXID_AT91SAM9CN12 0x00000005 - -#define ARCH_EXID_SAMA5D21CU 0x0000005a -#define ARCH_EXID_SAMA5D225C_D1M 0x00000053 -#define ARCH_EXID_SAMA5D22CU 0x00000059 -#define ARCH_EXID_SAMA5D22CN 0x00000069 -#define ARCH_EXID_SAMA5D23CU 0x00000058 -#define ARCH_EXID_SAMA5D24CX 0x00000004 -#define ARCH_EXID_SAMA5D24CU 0x00000014 -#define ARCH_EXID_SAMA5D26CU 0x00000012 -#define ARCH_EXID_SAMA5D27C_D1G 0x00000033 -#define ARCH_EXID_SAMA5D27C_D5M 0x00000032 -#define ARCH_EXID_SAMA5D27CU 0x00000011 -#define ARCH_EXID_SAMA5D27CN 0x00000021 -#define ARCH_EXID_SAMA5D28C_D1G 0x00000013 -#define ARCH_EXID_SAMA5D28CU 0x00000010 -#define ARCH_EXID_SAMA5D28CN 0x00000020 - -#define ARCH_EXID_SAMA5D3 0x00004300 -#define ARCH_EXID_SAMA5D31 0x00444300 -#define ARCH_EXID_SAMA5D33 0x00414300 -#define ARCH_EXID_SAMA5D34 0x00414301 -#define ARCH_EXID_SAMA5D35 0x00584300 -#define ARCH_EXID_SAMA5D36 0x00004301 - -#define ARCH_EXID_SAMA5D4 0x00000007 -#define ARCH_EXID_SAMA5D41 0x00000001 -#define ARCH_EXID_SAMA5D42 0x00000002 -#define ARCH_EXID_SAMA5D43 0x00000003 -#define ARCH_EXID_SAMA5D44 0x00000004 - -#define ARCH_FAMILY_AT91X92 0x09200000 -#define ARCH_FAMILY_AT91SAM9 0x01900000 -#define ARCH_FAMILY_AT91SAM9XE 0x02900000 - -/* RM9200 type */ -#define ARCH_REVISON_9200_BGA (0 << 0) -#define ARCH_REVISON_9200_PQFP (1 << 0) - -#ifndef __ASSEMBLY__ -enum at91_soc_type { - /* 920T */ - AT91_SOC_RM9200, - - /* SAM92xx */ - AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, - - /* SAM9Gxx */ - AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, - - /* SAM9RL */ - AT91_SOC_SAM9RL, - - /* SAM9X5 */ - AT91_SOC_SAM9X5, - - /* SAM9N12 */ - AT91_SOC_SAM9N12, - - /* SAMA5D2 */ - AT91_SOC_SAMA5D2, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D3, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D4, - - /* Unknown type */ - AT91_SOC_NONE -}; - -enum at91_soc_subtype { - /* RM9200 */ - AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, - - /* SAM9260 */ - AT91_SOC_SAM9XE, - - /* SAM9G45 */ - AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, - - /* SAM9X5 */ - AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, - AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, - - /* SAM9N12 */ - AT91_SOC_SAM9CN11, AT91_SOC_SAM9CN12, - - /* SAMA5D2 */ - AT91_SOC_SAMA5D21CU, - AT91_SOC_SAMA5D225C_D1M, AT91_SOC_SAMA5D22CU, AT91_SOC_SAMA5D22CN, - AT91_SOC_SAMA5D23CU, AT91_SOC_SAMA5D24CX, AT91_SOC_SAMA5D24CU, - AT91_SOC_SAMA5D26CU, AT91_SOC_SAMA5D27C_D1G, AT91_SOC_SAMA5D27C_D5M, - AT91_SOC_SAMA5D27CU, AT91_SOC_SAMA5D27CN, AT91_SOC_SAMA5D28C_D1G, - AT91_SOC_SAMA5D28CU, AT91_SOC_SAMA5D28CN, - - /* SAMA5D3 */ - AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, - AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, - - /* SAMA5D4 */ - AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43, - AT91_SOC_SAMA5D44, - - /* Unknown subtype */ - AT91_SOC_SUBTYPE_NONE -}; - -struct at91_socinfo { - unsigned int type, subtype; - unsigned int cidr, exid; -}; - -extern struct at91_socinfo at91_soc_initdata; -const char *at91_get_soc_type(struct at91_socinfo *c); -const char *at91_get_soc_subtype(struct at91_socinfo *c); - -static inline int at91_soc_is_detected(void) -{ - return at91_soc_initdata.type != AT91_SOC_NONE; -} - -#ifdef CONFIG_SOC_AT91RM9200 -#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) -#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) -#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) -#else -#define cpu_is_at91rm9200() (0) -#define cpu_is_at91rm9200_bga() (0) -#define cpu_is_at91rm9200_pqfp() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9260 -#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) -#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) -#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) -#else -#define cpu_is_at91sam9xe() (0) -#define cpu_is_at91sam9260() (0) -#define cpu_is_at91sam9g20() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9261 -#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) -#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) -#else -#define cpu_is_at91sam9261() (0) -#define cpu_is_at91sam9g10() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9263 -#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) -#else -#define cpu_is_at91sam9263() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9RL -#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) -#else -#define cpu_is_at91sam9rl() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9G45 -#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) -#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) -#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) -#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46) -#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11) -#else -#define cpu_is_at91sam9g45() (0) -#define cpu_is_at91sam9g45es() (0) -#define cpu_is_at91sam9m10() (0) -#define cpu_is_at91sam9g46() (0) -#define cpu_is_at91sam9m11() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9X5 -#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) -#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) -#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) -#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35) -#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25) -#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25) -#else -#define cpu_is_at91sam9x5() (0) -#define cpu_is_at91sam9g15() (0) -#define cpu_is_at91sam9g35() (0) -#define cpu_is_at91sam9x35() (0) -#define cpu_is_at91sam9g25() (0) -#define cpu_is_at91sam9x25() (0) -#endif - -#ifdef CONFIG_SOC_AT91SAM9N12 -#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12) -#else -#define cpu_is_at91sam9n12() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D2 -#define cpu_is_sama5d2() (at91_soc_initdata.type == AT91_SOC_SAMA5D2) -#define cpu_is_sama5d21() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D21CU) -#define cpu_is_sama5d22() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D225C_D1M \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D225C_D1M \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D22CU \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D22CN) -#define cpu_is_sama5d23() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D23CU) -#define cpu_is_sama5d24() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D24CX \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D24CU) -#define cpu_is_sama5d26() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D26CU) -#define cpu_is_sama5d27() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D27C_D1G \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D27C_D5M \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D27CU \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D27CN) -#define cpu_is_sama5d28() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D28C_D1G \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D28CU \ - || at91_soc_initdata.subtype == AT91_SOC_SAMA5D28CN) -#else -#define cpu_is_sama5d2() (0) -#define cpu_is_sama5d21() (0) -#define cpu_is_sama5d22() (0) -#define cpu_is_sama5d23() (0) -#define cpu_is_sama5d24() (0) -#define cpu_is_sama5d26() (0) -#define cpu_is_sama5d27() (0) -#define cpu_is_sama5d28() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D3 -#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) -#define cpu_is_sama5d31() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D31) -#define cpu_is_sama5d33() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D33) -#define cpu_is_sama5d34() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D34) -#define cpu_is_sama5d35() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D35) -#define cpu_is_sama5d36() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D36) -#else -#define cpu_is_sama5d3() (0) -#define cpu_is_sama5d31() (0) -#define cpu_is_sama5d33() (0) -#define cpu_is_sama5d34() (0) -#define cpu_is_sama5d35() (0) -#define cpu_is_sama5d36() (0) -#endif - -#ifdef CONFIG_SOC_SAMA5D4 -#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4) -#define cpu_is_sama5d41() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D41) -#define cpu_is_sama5d42() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D42) -#define cpu_is_sama5d43() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D43) -#define cpu_is_sama5d44() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D44) -#else -#define cpu_is_sama5d4() (0) -#define cpu_is_sama5d41() (0) -#define cpu_is_sama5d42() (0) -#define cpu_is_sama5d43() (0) -#define cpu_is_sama5d44() (0) -#endif - -/* - * Since this is ARM, we will never run on any AVR32 CPU. But these - * definitions may reduce clutter in common drivers. - */ -#define cpu_is_at32ap7000() (0) -#endif /* __ASSEMBLY__ */ - -#endif /* __MACH_CPU_H__ */ diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h deleted file mode 100644 index b713930424..0000000000 --- a/arch/arm/mach-at91/include/mach/debug_ll.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2012 - * Jean-Christophe PLAGNIOL-VILLARD <planioj@jcrosoft.com> - * - * Under GPLv2 - */ - -#ifndef __MACH_DEBUG_LL_H__ -#define __MACH_DEBUG_LL_H__ - -#include <asm/io.h> - -#define ATMEL_US_CSR 0x0014 -#define ATMEL_US_THR 0x001c -#define ATMEL_US_TXRDY (1 << 1) -#define ATMEL_US_TXEMPTY (1 << 9) - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static inline void PUTC_LL(char c) -{ - while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY)) - barrier(); - writel(c, CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_THR); - - while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) - barrier(); -} -#endif diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h deleted file mode 100644 index ddd6971e37..0000000000 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 only - */ - -#ifndef __AT91_GPIO_H__ -#define __AT91_GPIO_H__ - -#include <dt-bindings/gpio/gpio.h> -#include <asm/io.h> -#include <mach/at91_pio.h> - -#define MAX_NB_GPIO_PER_BANK 32 - -enum at91_mux { - AT91_MUX_GPIO = 0, - AT91_MUX_PERIPH_A = 1, - AT91_MUX_PERIPH_B = 2, - AT91_MUX_PERIPH_C = 3, - AT91_MUX_PERIPH_D = 4, - AT91_MUX_PERIPH_E = 5, - AT91_MUX_PERIPH_F = 6, - AT91_MUX_PERIPH_G = 7, -}; - -static inline unsigned pin_to_bank(unsigned pin) -{ - return pin / MAX_NB_GPIO_PER_BANK; -} - -static inline unsigned pin_to_bank_offset(unsigned pin) -{ - return pin % MAX_NB_GPIO_PER_BANK; -} - -static inline unsigned pin_to_mask(unsigned pin) -{ - return 1 << pin_to_bank_offset(pin); -} - -static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_IDR); -} - -static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) -{ - writel(mask, pio + (on ? PIO_PUER : PIO_PUDR)); -} - -static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) -{ - writel(mask, pio + (on ? PIO_MDER : PIO_MDDR)); -} - -static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_ASR); -} - -static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_BSR); -} - -static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); - writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); -} - -static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) -{ - writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); -} - -static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) -{ - if (is_on) - writel(mask, pio + PIO_IFSCDR); - at91_mux_set_deglitch(pio, mask, is_on); -} - -static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, - bool is_on, u32 div) -{ - if (is_on) { - writel(mask, pio + PIO_IFSCER); - writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); - writel(mask, pio + PIO_IFER); - } else { - writel(mask, pio + PIO_IFDR); - } -} - -static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) -{ - writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); -} - -static inline void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) -{ - writel(readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); -} - -static inline void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_PDR); -} - -static inline void at91_mux_gpio_enable(void __iomem *pio, unsigned mask) -{ - writel(mask, pio + PIO_PER); -} - -static inline void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input) -{ - writel(mask, pio + (input ? PIO_ODR : PIO_OER)); -} - -static inline void at91_mux_gpio_set(void __iomem *pio, unsigned mask, -int value) -{ - writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); -} - -static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask) -{ - u32 pdsr; - - pdsr = readl(pio + PIO_PDSR); - return (pdsr & mask) != 0; -} - -static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask, - enum at91_mux mux, int gpio_state) -{ - at91_mux_disable_interrupt(pio, mask); - - switch(mux) { - case AT91_MUX_GPIO: - at91_mux_gpio_enable(pio, mask); - break; - case AT91_MUX_PERIPH_A: - at91_mux_pio3_set_A_periph(pio, mask); - break; - case AT91_MUX_PERIPH_B: - at91_mux_pio3_set_B_periph(pio, mask); - break; - case AT91_MUX_PERIPH_C: - at91_mux_pio3_set_C_periph(pio, mask); - break; - case AT91_MUX_PERIPH_D: - at91_mux_pio3_set_D_periph(pio, mask); - break; - default: - /* ignore everything else */ - break; - } - if (mux != AT91_MUX_GPIO) - at91_mux_gpio_disable(pio, mask); - - at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP); - at91_mux_pio3_set_pulldown(pio, mask, gpio_state & GPIO_PULL_DOWN); -} - -/* helpers for PIO4 pinctrl (>= sama5d2) */ - -static inline void at91_mux_pio4_set_periph(void __iomem *pio, unsigned mask, u32 func) -{ - writel(mask, pio + PIO4_MSKR); - writel(func, pio + PIO4_CFGR); -} - -static inline void at91_mux_pio4_set_A_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_A); -} - -static inline void at91_mux_pio4_set_B_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_B); -} - -static inline void at91_mux_pio4_set_C_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_C); -} - -static inline void at91_mux_pio4_set_D_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_D); -} - -static inline void at91_mux_pio4_set_E_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_E); -} - -static inline void at91_mux_pio4_set_F_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_F); -} - -static inline void at91_mux_pio4_set_G_periph(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_periph(pio, mask, AT91_MUX_PERIPH_G); -} - -static inline void at91_mux_pio4_set_func(void __iomem *pio, - unsigned pin_mask, - unsigned cfgr_and_mask, - unsigned cfgr_or_mask) -{ - u32 reg; - writel(pin_mask, pio + PIO4_MSKR); - reg = readl(pio + PIO4_CFGR); - reg &= cfgr_and_mask; - reg |= cfgr_or_mask; - writel(reg, pio + PIO4_CFGR); -} - -static inline void at91_mux_pio4_set_bistate(void __iomem *pio, - unsigned pin_mask, - unsigned func_mask, - bool is_on) -{ - at91_mux_pio4_set_func(pio, pin_mask, ~func_mask, - is_on ? func_mask : 0); -} - -static inline void at91_mux_pio4_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_IFEN_MASK, is_on); -} - -static inline void at91_mux_pio4_set_debounce(void __iomem *pio, unsigned mask, - bool is_on, u32 div) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_IFEN_MASK, is_on); - at91_mux_pio4_set_bistate(pio, mask, PIO4_IFSCEN_MASK, is_on); -} - -static inline void at91_mux_pio4_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_PDEN_MASK, is_on); -} - -static inline void at91_mux_pio4_disable_schmitt_trig(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_bistate(pio, mask, PIO4_SCHMITT_MASK, false); -} - -static inline void at91_mux_gpio4_enable(void __iomem *pio, unsigned mask) -{ - at91_mux_pio4_set_func(pio, mask, ~PIO4_CFGR_FUNC_MASK, AT91_MUX_GPIO); -} - -static inline void at91_mux_gpio4_input(void __iomem *pio, unsigned mask, bool input) -{ - u32 cfgr; - - writel(mask, pio + PIO4_MSKR); - - cfgr = readl(pio + PIO4_CFGR); - if (input) - cfgr &= ~PIO4_DIR_MASK; - else - cfgr |= PIO4_DIR_MASK; - writel(cfgr, pio + PIO4_CFGR); -} - -static inline void at91_mux_gpio4_set(void __iomem *pio, unsigned mask, - int value) -{ - writel(mask, pio + (value ? PIO4_SODR : PIO4_CODR)); -} - -static inline int at91_mux_gpio4_get(void __iomem *pio, unsigned mask) -{ - u32 pdsr; - - pdsr = readl(pio + PIO4_PDSR); - return (pdsr & mask) != 0; -} - -#endif /* __AT91_GPIO_H__ */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h deleted file mode 100644 index 3ae54247e0..0000000000 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] - * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* DBGU base */ -/* rm9200, 9260/9g20, 9261/9g10, 9rl */ -#define AT91_BASE_DBGU0 0xfffff200 -/* 9263, 9g45 */ -#define AT91_BASE_DBGU1 0xffffee00 -/* sama5d4 */ -#define AT91_BASE_DBGU2 0xfc069000 - -#include <mach/at91rm9200.h> -#include <mach/at91sam9260.h> -#include <mach/at91sam9261.h> -#include <mach/at91sam9263.h> -#include <mach/at91sam9g45.h> -#include <mach/at91sam9n12.h> -#include <mach/at91sam9x5.h> -#include <mach/sama5d2.h> -#include <mach/sama5d3.h> -#include <mach/sama5d4.h> - -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -#define SAMA5_CHIPSELECT_0 0x10000000 -#define SAMA5_DDRCS 0x20000000 -#define SAMA5_CHIPSELECT_1 0x40000000 -#define SAMA5_CHIPSELECT_2 0x50000000 -#define SAMA5_CHIPSELECT_3 0x60000000 - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/iomux.h b/arch/arm/mach-at91/include/mach/iomux.h deleted file mode 100644 index 0c91b22a8f..0000000000 --- a/arch/arm/mach-at91/include/mach/iomux.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91_GPIO_H -#define __ASM_ARCH_AT91_GPIO_H - -#include <io.h> -#include <asm-generic/errno.h> -#include <mach/at91_pio.h> -#include <mach/hardware.h> -#include <mach/gpio.h> - -#define AT91_PIN_PA0 (0x00 + 0) -#define AT91_PIN_PA1 (0x00 + 1) -#define AT91_PIN_PA2 (0x00 + 2) -#define AT91_PIN_PA3 (0x00 + 3) -#define AT91_PIN_PA4 (0x00 + 4) -#define AT91_PIN_PA5 (0x00 + 5) -#define AT91_PIN_PA6 (0x00 + 6) -#define AT91_PIN_PA7 (0x00 + 7) -#define AT91_PIN_PA8 (0x00 + 8) -#define AT91_PIN_PA9 (0x00 + 9) -#define AT91_PIN_PA10 (0x00 + 10) -#define AT91_PIN_PA11 (0x00 + 11) -#define AT91_PIN_PA12 (0x00 + 12) -#define AT91_PIN_PA13 (0x00 + 13) -#define AT91_PIN_PA14 (0x00 + 14) -#define AT91_PIN_PA15 (0x00 + 15) -#define AT91_PIN_PA16 (0x00 + 16) -#define AT91_PIN_PA17 (0x00 + 17) -#define AT91_PIN_PA18 (0x00 + 18) -#define AT91_PIN_PA19 (0x00 + 19) -#define AT91_PIN_PA20 (0x00 + 20) -#define AT91_PIN_PA21 (0x00 + 21) -#define AT91_PIN_PA22 (0x00 + 22) -#define AT91_PIN_PA23 (0x00 + 23) -#define AT91_PIN_PA24 (0x00 + 24) -#define AT91_PIN_PA25 (0x00 + 25) -#define AT91_PIN_PA26 (0x00 + 26) -#define AT91_PIN_PA27 (0x00 + 27) -#define AT91_PIN_PA28 (0x00 + 28) -#define AT91_PIN_PA29 (0x00 + 29) -#define AT91_PIN_PA30 (0x00 + 30) -#define AT91_PIN_PA31 (0x00 + 31) - -#define AT91_PIN_PB0 (0x20 + 0) -#define AT91_PIN_PB1 (0x20 + 1) -#define AT91_PIN_PB2 (0x20 + 2) -#define AT91_PIN_PB3 (0x20 + 3) -#define AT91_PIN_PB4 (0x20 + 4) -#define AT91_PIN_PB5 (0x20 + 5) -#define AT91_PIN_PB6 (0x20 + 6) -#define AT91_PIN_PB7 (0x20 + 7) -#define AT91_PIN_PB8 (0x20 + 8) -#define AT91_PIN_PB9 (0x20 + 9) -#define AT91_PIN_PB10 (0x20 + 10) -#define AT91_PIN_PB11 (0x20 + 11) -#define AT91_PIN_PB12 (0x20 + 12) -#define AT91_PIN_PB13 (0x20 + 13) -#define AT91_PIN_PB14 (0x20 + 14) -#define AT91_PIN_PB15 (0x20 + 15) -#define AT91_PIN_PB16 (0x20 + 16) -#define AT91_PIN_PB17 (0x20 + 17) -#define AT91_PIN_PB18 (0x20 + 18) -#define AT91_PIN_PB19 (0x20 + 19) -#define AT91_PIN_PB20 (0x20 + 20) -#define AT91_PIN_PB21 (0x20 + 21) -#define AT91_PIN_PB22 (0x20 + 22) -#define AT91_PIN_PB23 (0x20 + 23) -#define AT91_PIN_PB24 (0x20 + 24) -#define AT91_PIN_PB25 (0x20 + 25) -#define AT91_PIN_PB26 (0x20 + 26) -#define AT91_PIN_PB27 (0x20 + 27) -#define AT91_PIN_PB28 (0x20 + 28) -#define AT91_PIN_PB29 (0x20 + 29) -#define AT91_PIN_PB30 (0x20 + 30) -#define AT91_PIN_PB31 (0x20 + 31) - -#define AT91_PIN_PC0 (0x40 + 0) -#define AT91_PIN_PC1 (0x40 + 1) -#define AT91_PIN_PC2 (0x40 + 2) -#define AT91_PIN_PC3 (0x40 + 3) -#define AT91_PIN_PC4 (0x40 + 4) -#define AT91_PIN_PC5 (0x40 + 5) -#define AT91_PIN_PC6 (0x40 + 6) -#define AT91_PIN_PC7 (0x40 + 7) -#define AT91_PIN_PC8 (0x40 + 8) -#define AT91_PIN_PC9 (0x40 + 9) -#define AT91_PIN_PC10 (0x40 + 10) -#define AT91_PIN_PC11 (0x40 + 11) -#define AT91_PIN_PC12 (0x40 + 12) -#define AT91_PIN_PC13 (0x40 + 13) -#define AT91_PIN_PC14 (0x40 + 14) -#define AT91_PIN_PC15 (0x40 + 15) -#define AT91_PIN_PC16 (0x40 + 16) -#define AT91_PIN_PC17 (0x40 + 17) -#define AT91_PIN_PC18 (0x40 + 18) -#define AT91_PIN_PC19 (0x40 + 19) -#define AT91_PIN_PC20 (0x40 + 20) -#define AT91_PIN_PC21 (0x40 + 21) -#define AT91_PIN_PC22 (0x40 + 22) -#define AT91_PIN_PC23 (0x40 + 23) -#define AT91_PIN_PC24 (0x40 + 24) -#define AT91_PIN_PC25 (0x40 + 25) -#define AT91_PIN_PC26 (0x40 + 26) -#define AT91_PIN_PC27 (0x40 + 27) -#define AT91_PIN_PC28 (0x40 + 28) -#define AT91_PIN_PC29 (0x40 + 29) -#define AT91_PIN_PC30 (0x40 + 30) -#define AT91_PIN_PC31 (0x40 + 31) - -#define AT91_PIN_PD0 (0x60 + 0) -#define AT91_PIN_PD1 (0x60 + 1) -#define AT91_PIN_PD2 (0x60 + 2) -#define AT91_PIN_PD3 (0x60 + 3) -#define AT91_PIN_PD4 (0x60 + 4) -#define AT91_PIN_PD5 (0x60 + 5) -#define AT91_PIN_PD6 (0x60 + 6) -#define AT91_PIN_PD7 (0x60 + 7) -#define AT91_PIN_PD8 (0x60 + 8) -#define AT91_PIN_PD9 (0x60 + 9) -#define AT91_PIN_PD10 (0x60 + 10) -#define AT91_PIN_PD11 (0x60 + 11) -#define AT91_PIN_PD12 (0x60 + 12) -#define AT91_PIN_PD13 (0x60 + 13) -#define AT91_PIN_PD14 (0x60 + 14) -#define AT91_PIN_PD15 (0x60 + 15) -#define AT91_PIN_PD16 (0x60 + 16) -#define AT91_PIN_PD17 (0x60 + 17) -#define AT91_PIN_PD18 (0x60 + 18) -#define AT91_PIN_PD19 (0x60 + 19) -#define AT91_PIN_PD20 (0x60 + 20) -#define AT91_PIN_PD21 (0x60 + 21) -#define AT91_PIN_PD22 (0x60 + 22) -#define AT91_PIN_PD23 (0x60 + 23) -#define AT91_PIN_PD24 (0x60 + 24) -#define AT91_PIN_PD25 (0x60 + 25) -#define AT91_PIN_PD26 (0x60 + 26) -#define AT91_PIN_PD27 (0x60 + 27) -#define AT91_PIN_PD28 (0x60 + 28) -#define AT91_PIN_PD29 (0x60 + 29) -#define AT91_PIN_PD30 (0x60 + 30) -#define AT91_PIN_PD31 (0x60 + 31) - -#define AT91_PIN_PE0 (0x80 + 0) -#define AT91_PIN_PE1 (0x80 + 1) -#define AT91_PIN_PE2 (0x80 + 2) -#define AT91_PIN_PE3 (0x80 + 3) -#define AT91_PIN_PE4 (0x80 + 4) -#define AT91_PIN_PE5 (0x80 + 5) -#define AT91_PIN_PE6 (0x80 + 6) -#define AT91_PIN_PE7 (0x80 + 7) -#define AT91_PIN_PE8 (0x80 + 8) -#define AT91_PIN_PE9 (0x80 + 9) -#define AT91_PIN_PE10 (0x80 + 10) -#define AT91_PIN_PE11 (0x80 + 11) -#define AT91_PIN_PE12 (0x80 + 12) -#define AT91_PIN_PE13 (0x80 + 13) -#define AT91_PIN_PE14 (0x80 + 14) -#define AT91_PIN_PE15 (0x80 + 15) -#define AT91_PIN_PE16 (0x80 + 16) -#define AT91_PIN_PE17 (0x80 + 17) -#define AT91_PIN_PE18 (0x80 + 18) -#define AT91_PIN_PE19 (0x80 + 19) -#define AT91_PIN_PE20 (0x80 + 20) -#define AT91_PIN_PE21 (0x80 + 21) -#define AT91_PIN_PE22 (0x80 + 22) -#define AT91_PIN_PE23 (0x80 + 23) -#define AT91_PIN_PE24 (0x80 + 24) -#define AT91_PIN_PE25 (0x80 + 25) -#define AT91_PIN_PE26 (0x80 + 26) -#define AT91_PIN_PE27 (0x80 + 27) -#define AT91_PIN_PE28 (0x80 + 28) -#define AT91_PIN_PE29 (0x80 + 29) -#define AT91_PIN_PE30 (0x80 + 30) -#define AT91_PIN_PE31 (0x80 + 31) - -/* - * mux the pin - */ -int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup); - -/* - * mux the pin to the "GPIO" peripheral role. - */ -static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_GPIO, use_pullup); -} - -/* - * mux the pin to the "A" internal peripheral role. - */ -static inline int at91_set_A_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_A, use_pullup); -} - -/* - * mux the pin to the "B" internal peripheral role. - */ -static inline int at91_set_B_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_B, use_pullup); -} - -/* - * mux the pin to the "C" internal peripheral role. - */ -static inline int at91_set_C_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_C, use_pullup); -} - -/* - * mux the pin to the "C" internal peripheral role. - */ -static inline int at91_set_D_periph(unsigned pin, int use_pullup) -{ - return at91_mux_pin(pin, AT91_MUX_PERIPH_D, use_pullup); -} - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and - * configure it for an input. - */ -int at91_set_gpio_input(unsigned pin, int use_pullup); - -/* - * mux the pin to the gpio controller (instead of "A" or "B" peripheral), - * and configure it for an output. - */ -int at91_set_gpio_output(unsigned pin, int value); - -/* - * enable/disable the glitch filter; mostly used with IRQ handling. - */ -int at91_set_deglitch(unsigned pin, int is_on); - -/* - * enable/disable the multi-driver; This is only valid for output and - * allows the output pin to run as an open collector output. - */ -int at91_set_multi_drive(unsigned pin, int is_on); - -extern int at91_set_debounce(unsigned pin, int is_on, int div); -extern int at91_set_pulldown(unsigned pin, int is_on); -extern int at91_disable_schmitt_trig(unsigned pin); - -#endif /* __ASM_ARCH_AT91SAM9_GPIO_H */ diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h deleted file mode 100644 index 3dad7d9c9c..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ /dev/null @@ -1,261 +0,0 @@ -// SPDX-License-Identifier: BSD-1-Clause -/* - * Chip-specific header file for the SAMA5D2 family - * - * Copyright (c) 2015, Atmel Corporation - * Copyright (c) 2019 Ahmad Fatoum, Pengutronix - * - * Common definitions. - * Based on SAMA5D2 datasheet: - * http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-Sheet-DS60001476C.pdf - * - */ - -#ifndef SAMA5D2_H -#define SAMA5D2_H - -/* - * Peripheral identifiers/interrupts. (Table 18-9) - */ -#define SAMA5D2_ID_FIQ 0 /* FIQ Interrupt ID */ -/* 1 */ -#define SAMA5D2_ID_ARM 2 /* Performance Monitor Unit */ -#define SAMA5D2_ID_PIT 3 /* Periodic Interval Timer Interrupt */ -#define SAMA5D2_ID_WDT 4 /* Watchdog Timer Interrupt */ -#define SAMA5D2_ID_GMAC 5 /* Ethernet MAC */ -#define SAMA5D2_ID_XDMAC0 6 /* DMA Controller 0 */ -#define SAMA5D2_ID_XDMAC1 7 /* DMA Controller 1 */ -#define SAMA5D2_ID_ICM 8 /* Integrity Check Monitor */ -#define SAMA5D2_ID_AES 9 /* Advanced Encryption Standard */ -#define SAMA5D2_ID_AESB 10 /* AES bridge */ -#define SAMA5D2_ID_TDES 11 /* Triple Data Encryption Standard */ -#define SAMA5D2_ID_SHA 12 /* SHA Signature */ -#define SAMA5D2_ID_MPDDRC 13 /* MPDDR Controller */ -#define SAMA5D2_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ -#define SAMA5D2_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ -#define SAMA5D2_ID_SECUMOD 16 /* Secure Module */ -#define SAMA5D2_ID_HSMC 17 /* Multi-bit ECC interrupt */ -#define SAMA5D2_ID_PIOA 18 /* Parallel I/O Controller A */ -#define SAMA5D2_ID_FLEXCOM0 19 /* FLEXCOM0 */ -#define SAMA5D2_ID_FLEXCOM1 20 /* FLEXCOM1 */ -#define SAMA5D2_ID_FLEXCOM2 21 /* FLEXCOM2 */ -#define SAMA5D2_ID_FLEXCOM3 22 /* FLEXCOM3 */ -#define SAMA5D2_ID_FLEXCOM4 23 /* FLEXCOM4 */ -#define SAMA5D2_ID_UART0 24 /* UART0 */ -#define SAMA5D2_ID_UART1 25 /* UART1 */ -#define SAMA5D2_ID_UART2 26 /* UART2 */ -#define SAMA5D2_ID_UART3 27 /* UART3 */ -#define SAMA5D2_ID_UART4 28 /* UART4 */ -#define SAMA5D2_ID_TWI0 29 /* Two-wire Interface 0 */ -#define SAMA5D2_ID_TWI1 30 /* Two-wire Interface 1 */ -#define SAMA5D2_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */ -#define SAMA5D2_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */ -#define SAMA5D2_ID_SPI0 33 /* Serial Peripheral Interface 0 */ -#define SAMA5D2_ID_SPI1 34 /* Serial Peripheral Interface 1 */ -#define SAMA5D2_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ -#define SAMA5D2_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ -/* 37 */ -#define SAMA5D2_ID_PWM 38 /* Pulse Width Modulation Controller0 (ch. 0,1,2,3) */ -/* 39 */ -#define SAMA5D2_ID_ADC 40 /* Touch Screen ADC Controller */ -#define SAMA5D2_ID_UHPHS 41 /* USB Host High Speed */ -#define SAMA5D2_ID_UDPHS 42 /* USB Device High Speed */ -#define SAMA5D2_ID_SSC0 43 /* Serial Synchronous Controller 0 */ -#define SAMA5D2_ID_SSC1 44 /* Serial Synchronous Controller 1 */ -#define SAMA5D2_ID_LCDC 45 /* LCD Controller */ -#define SAMA5D2_ID_ISI 46 /* Image Sensor Interface */ -#define SAMA5D2_ID_TRNG 47 /* True Random Number Generator */ -#define SAMA5D2_ID_PDMIC 48 /* Pulse Density Modulation Interface Controller */ -#define SAMA5D2_ID_IRQ 49 /* IRQ Interrupt ID */ -#define SAMA5D2_ID_SFC 50 /* Fuse Controller */ -#define SAMA5D2_ID_SECURAM 51 /* Secure RAM */ -#define SAMA5D2_ID_QSPI0 52 /* QSPI0 */ -#define SAMA5D2_ID_QSPI1 53 /* QSPI1 */ -#define SAMA5D2_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ -#define SAMA5D2_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ -#define SAMA5D2_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ -#define SAMA5D2_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ -#define SAMA5D2_ID_PTC 58 /* Peripheral Touch Controller */ -#define SAMA5D2_ID_CLASSD 59 /* Audio Class D Amplifier */ -#define SAMA5D2_ID_SFR 60 /* Special Function Register */ -#define SAMA5D2_ID_SAIC 61 /* Secured Advanced Interrupt Controller */ -#define SAMA5D2_ID_AIC 62 /* Advanced Interrupt Controller */ -#define SAMA5D2_ID_L2CC 63 /* L2 Cache Controller */ -#define SAMA5D2_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ -#define SAMA5D2_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ -#define SAMA5D2_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ -#define SAMA5D2_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ -#define SAMA5D2_ID_PIOB 68 /* Parallel I/O Controller B */ -#define SAMA5D2_ID_PIOC 69 /* Parallel I/O Controller C */ -#define SAMA5D2_ID_PIOD 70 /* Parallel I/O Controller D */ -#define SAMA5D2_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 */ -#define SAMA5D2_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 */ -/* 73 */ -#define SAMA5D2_ID_SYS 74 /* System Controller Interrupt */ -#define SAMA5D2_ID_ACC 75 /* Analog Comparator */ -#define SAMA5D2_ID_RXLP 76 /* UART Low-Power */ -#define SAMA5D2_ID_SFRBU 77 /* Special Function Register BackUp */ -#define SAMA5D2_ID_CHIPID 78 /* Chip ID */ - -/* - * User Peripheral physical base addresses. - */ - -#define SAMA5D2_BASE_LCDC 0xf0000000 -#define SAMA5D2_BASE_XDMAC1 0xf0004000 -#define SAMA5D2_BASE_HXISI 0xf0008000 -#define SAMA5D2_BASE_MPDDRC 0xf000c000 -#define SAMA5D2_BASE_XDMAC0 0xf0010000 -#define SAMA5D2_BASE_PMC 0xf0014000 -#define SAMA5D2_BASE_MATRIX64 0xf0018000 /* MATRIX0 */ -#define SAMA5D2_BASE_AESB 0xf001c000 -#define SAMA5D2_BASE_QSPI0 0xf0020000 -#define SAMA5D2_BASE_QSPI1 0xf0024000 -#define SAMA5D2_BASE_SHA 0xf0028000 -#define SAMA5D2_BASE_AES 0xf002c000 - -#define SAMA5D2_BASE_SPI0 0xf8000000 -#define SAMA5D2_BASE_SSC0 0xf8004000 -#define SAMA5D2_BASE_GMAC 0xf8008000 -#define SAMA5D2_BASE_TC0 0xf800c000 -#define SAMA5D2_BASE_TC1 0xf8010000 -#define SAMA5D2_BASE_HSMC 0xf8014000 -#define SAMA5D2_BASE_PDMIC 0xf8018000 -#define SAMA5D2_BASE_UART0 0xf801c000 -#define SAMA5D2_BASE_UART1 0xf8020000 -#define SAMA5D2_BASE_UART2 0xf8024000 -#define SAMA5D2_BASE_TWI0 0xf8028000 -#define SAMA5D2_BASE_PWMC 0xf802c000 -#define SAMA5D2_BASE_SFR 0xf8030000 -#define SAMA5D2_BASE_FLEXCOM0 0xf8034000 -#define SAMA5D2_BASE_FLEXCOM1 0xf8038000 -#define SAMA5D2_BASE_SAIC 0xf803c000 -#define SAMA5D2_BASE_ICM 0xf8040000 -#define SAMA5D2_BASE_SECURAM 0xf8044000 -#define SAMA5D2_BASE_SYSC 0xf8048000 -#define SAMA5D2_BASE_ACC 0xf804a000 -#define SAMA5D2_BASE_SFC 0xf804c000 -#define SAMA5D2_BASE_I2SC0 0xf8050000 -#define SAMA5D2_BASE_CAN0 0xf8054000 - -#define SAMA5D2_BASE_SPI1 0xfc000000 -#define SAMA5D2_BASE_SSC1 0xfc004000 -#define SAMA5D2_BASE_UART3 0xfc008000 -#define SAMA5D2_BASE_UART4 0xfc00c000 -#define SAMA5D2_BASE_FLEXCOM2 0xfc010000 -#define SAMA5D2_BASE_FLEXCOM3 0xfc014000 -#define SAMA5D2_BASE_FLEXCOM4 0xfc018000 -#define SAMA5D2_BASE_TRNG 0xfc01c000 -#define SAMA5D2_BASE_AIC 0xfc020000 -#define SAMA5D2_BASE_TWI1 0xfc028000 -#define SAMA5D2_BASE_UDPHS 0xfc02c000 -#define SAMA5D2_BASE_ADC 0xfc030000 - -#define SAMA5D2_BASE_PIOA 0xfc038000 -#define SAMA5D2_BASE_MATRIX32 0xfc03c000 /* MATRIX1 */ -#define SAMA5D2_BASE_SECUMOD 0xfc040000 -#define SAMA5D2_BASE_TDES 0xfc044000 -#define SAMA5D2_BASE_CLASSD 0xfc048000 -#define SAMA5D2_BASE_I2SC1 0xfc04c000 -#define SAMA5D2_BASE_CAN1 0xfc050000 -#define SAMA5D2_BASE_SFRBU 0xfc05c000 -#define SAMA5D2_BASE_CHIPID 0xfc069000 - -/* - * Address Memory Space - */ -#define SAMA5D2_BASE_INTERNAL_MEM 0x00000000 -#define SAMA5D2_BASE_CS0 0x10000000 -#define SAMA5D2_BASE_DDRCS 0x20000000 -#define SAMA5D2_BASE_DDRCS_AES 0x40000000 -#define SAMA5D2_BASE_CS1 0x60000000 -#define SAMA5D2_BASE_CS2 0x70000000 -#define SAMA5D2_BASE_CS3 0x80000000 -#define SAMA5D2_BASE_QSPI0_AES_MEM 0x90000000 -#define SAMA5D2_BASE_QSPI1_AES_MEM 0x98000000 -#define SAMA5D2_BASE_SDHC0 0xa0000000 -#define SAMA5D2_BASE_SDHC1 0xb0000000 -#define SAMA5D2_BASE_NFC_CMD_REG 0xc0000000 -#define SAMA5D2_BASE_QSPI0_MEM 0xd0000000 -#define SAMA5D2_BASE_QSPI1_MEM 0xd8000000 -#define SAMA5D2_BASE_PERIPH 0xf0000000 - -/* - * Internal Memories - */ -#define SAMA5D2_BASE_ROM 0x00000000 /* ROM */ -#define SAMA5D2_BASE_ECC_ROM 0x00060000 /* ECC ROM */ -#define SAMA5D2_BASE_NFC_SRAM 0x00100000 /* NFC SRAM */ -#define SAMA5D2_BASE_SRAM0 0x00200000 /* SRAM0 */ -#define SAMA5D2_BASE_SRAM1 0x00220000 /* SRAM1 */ -#define SAMA5D2_BASE_UDPHS_SRAM 0x00300000 /* UDPHS RAM */ -#define SAMA5D2_BASE_UHP_OHCI 0x00400000 /* UHP OHCI */ -#define SAMA5D2_BASE_UHP_EHCI 0x00500000 /* UHP EHCI */ -#define SAMA5D2_BASE_AXI_MATRIX 0x00600000 /* AXI Maxtrix */ -#define SAMA5D2_BASE_DAP 0x00700000 /* DAP */ -#define SAMA5D2_BASE_PTC 0x00800000 /* PTC */ -#define SAMA5D2_BASE_L2CC 0x00A00000 /* L2CC */ - -/* - * Other misc defines - */ -#define SAMA5D2_BASE_PMECC (SAMA5D2_BASE_HSMC + 0x70) -#define SAMA5D2_BASE_PMERRLOC (SAMA5D2_BASE_HSMC + 0x500) - -#define SAMA5D2_PMECC (SAMA5D2_BASE_PMECC - SAMA5D2_BASE_SYS) -#define SAMA5D2_PMERRLOC (SAMA5D2_BASE_PMERRLOC - SAMA5D2_BASE_SYS) - -#define SAMA5D2_BASE_PIOB (SAMA5D2_BASE_PIOA + 0x40) -#define SAMA5D2_BASE_PIOC (SAMA5D2_BASE_PIOB + 0x40) -#define SAMA5D2_BASE_PIOD (SAMA5D2_BASE_PIOC + 0x40) - -/* SYSC spawns */ -#define SAMA5D2_BASE_RSTC SAMA5D2_BASE_SYSC -#define SAMA5D2_BASE_SHDC (SAMA5D2_BASE_SYSC + 0x10) -#define SAMA5D2_BASE_PITC (SAMA5D2_BASE_SYSC + 0x30) -#define SAMA5D2_BASE_WDT (SAMA5D2_BASE_SYSC + 0x40) -#define SAMA5D2_BASE_SCKCR (SAMA5D2_BASE_SYSC + 0x50) -#define SAMA5D2_BASE_RTCC (SAMA5D2_BASE_SYSC + 0xb0) - -#define SAMA5D2_BASE_SMC (SAMA5D2_BASE_HSMC + 0x700) - -#define SAMA5D2_NUM_PIO 4 -#define SAMA5D2_NUM_TWI 2 - -/* AICREDIR Unlock Key */ -#define SAMA5D2_AICREDIR_KEY 0xB6D81C4D - -/* - * Matrix Slaves ID - */ -/* MATRIX0(H64MX) Matrix Slaves */ -/* Bridge from H64MX to AXIMX (Internal ROM, Cryto Library, PKCC RAM) */ -#define SAMA5D2_H64MX_SLAVE_BRIDGE_TO_AXIMX 0 -#define SAMA5D2_H64MX_SLAVE_PERI_BRIDGE 1 /* H64MX Peripheral Bridge */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_0 2 /* DDR2 Port0-AESOTF */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_1 3 /* DDR2 Port1 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_2 4 /* DDR2 Port2 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_3 5 /* DDR2 Port3 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_4 6 /* DDR2 Port4 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_5 7 /* DDR2 Port5 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_6 8 /* DDR2 Port6 */ -#define SAMA5D2_H64MX_SLAVE_DDR2_PORT_7 9 /* DDR2 Port7 */ -#define SAMA5D2_H64MX_SLAVE_INTERNAL_SRAM 10 /* Internal SRAM 128K */ -#define SAMA5D2_H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K (Cache L2) */ -#define SAMA5D2_H64MX_SLAVE_QSPI0 12 /* QSPI0 */ -#define SAMA5D2_H64MX_SLAVE_QSPI1 13 /* QSPI1 */ -#define SAMA5D2_H64MX_SLAVE_AESB 14 /* AESB */ - -/* MATRIX1(H32MX) Matrix Slaves */ -#define SAMA5D2_H32MX_BRIDGE_TO_H64MX 0 /* Bridge from H32MX to H64MX */ -#define SAMA5D2_H32MX_PERI_BRIDGE_0 1 /* H32MX Peripheral Bridge 0 */ -#define SAMA5D2_H32MX_PERI_BRIDGE_1 2 /* H32MX Peripheral Bridge 1 */ -#define SAMA5D2_H32MX_EXTERNAL_EBI 3 /* External Bus Interface */ -#define SAMA5D2_H32MX_NFC_CMD_REG 3 /* NFC command Register */ -#define SAMA5D2_H32MX_NFC_SRAM 4 /* NFC SRAM */ -#define SAMA5D2_H32MX_USB 5 - -#define SAMA5D2_SRAM_BASE SAMA5D2_BASE_SRAM0 -#define SAMA5D2_SRAM_SIZE (128 * SZ_1K) - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h deleted file mode 100644 index cd2102c20e..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D3 family - * - * Copyright (C) 2009-2012 Atmel Corporation. - * - * Common definitions. - * Based on SAMA5D3 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D3_H -#define SAMA5D3_H - -/* - * Peripheral identifiers/interrupts. - */ -#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ -#define SAMA5D3_ID_PIT 3 /* Periodic Interval Timer Interrupt */ -#define SAMA5D3_ID_WDT 4 /* Watchdog timer Interrupt */ -#define SAMA5D3_ID_HSMC5 5 /* Static Memory Controller */ -#define SAMA5D3_ID_PIOA 6 /* Parallel I/O Controller A */ -#define SAMA5D3_ID_PIOB 7 /* Parallel I/O Controller B */ -#define SAMA5D3_ID_PIOC 8 /* Parallel I/O Controller C */ -#define SAMA5D3_ID_PIOD 9 /* Parallel I/O Controller D */ -#define SAMA5D3_ID_PIOE 10 /* Parallel I/O Controller E */ -#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ -#define SAMA5D3_ID_USART0 12 /* USART0 */ -#define SAMA5D3_ID_USART1 13 /* USART1 */ -#define SAMA5D3_ID_USART2 14 /* USART2 */ -#define SAMA5D3_ID_USART3 15 /* USART3 */ -#define SAMA5D3_ID_UART0 16 /* UART0 */ -#define SAMA5D3_ID_UART1 17 /* UART1 */ -#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ -#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ -#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ -#define SAMA5D3_ID_HSMCI0 21 /* High Speed Multimedia Card Interface 0 */ -#define SAMA5D3_ID_HSMCI1 22 /* High Speed Multimedia Card Interface 1 */ -#define SAMA5D3_ID_HSMCI2 23 /* High Speed Multimedia Card Interface 2 */ -#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ -#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ -#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 (ch. 0, 1, 2) */ -#define SAMA5D3_ID_TC1 27 /* Timer Counter 1 (ch. 3, 4, 5) */ -#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ -#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ -#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ -#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ -#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ -#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ -#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ -#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ -#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ -#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ -#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ -#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ -#define SAMA5D3_ID_CAN0 40 /* CAN controller 0 */ -#define SAMA5D3_ID_CAN1 41 /* CAN controller 1 */ -#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ -#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ -#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ -#define SAMA5D3_ID_TRNG 45 /* True Random Number Generator */ -#define SAMA5D3_ID_ARM 46 /* Performance Monitor Unit */ -#define SAMA5D3_ID_AIC 47 /* Advanced Interrupt Controller */ -#define SAMA5D3_ID_FUSE 48 /* Fuse Controller */ -#define SAMA5D3_ID_MPDDRC 49 /* MPDDR controller */ - -/* - * User Peripheral physical base addresses. - */ - -#define SAMA5D3_BASE_HSMCI0 0xf0000000 /* (MMCI) Base Address */ -#define SAMA5D3_BASE_SPI0 0xf0004000 -#define SAMA5D3_BASE_TC0 0xf0010000 /* (TC0) Base Address */ -#define SAMA5D3_BASE_TC1 0xf0010040 /* (TC1) Base Address */ -#define SAMA5D3_BASE_USART0 0xf001c000 -#define SAMA5D3_BASE_USART1 0xf0020000 -#define SAMA5D3_BASE_GMAC 0xf0028000 /* (GMAC) Base Address */ -#define SAMA5D3_BASE_LCDC 0xf0030000 /* (HLCDC5) Base Address */ -#define SAMA5D3_BASE_HSMCI1 0xf8000000 -#define SAMA5D3_BASE_HSMCI2 0xf8004000 -#define SAMA5D3_BASE_SPI1 0xf8008000 -#define SAMA5D3_BASE_EMAC 0xf802c000 /* (EMAC) Base Address */ -#define SAMA5D3_BASE_UDPHS 0xf8030000 - -#define SAMA5D3_BASE_PIOA 0xfffff200 -#define SAMA5D3_BASE_PIOB 0xfffff400 -#define SAMA5D3_BASE_PIOC 0xfffff600 -#define SAMA5D3_BASE_PIOD 0xfffff800 -#define SAMA5D3_BASE_PIOE 0xfffffa00 -#define SAMA5D3_BASE_MPDDRC 0xffffea00 -#define SAMA5D3_BASE_HSMC 0xffffc000 -#define SAMA5D3_BASE_RSTC 0xfffffe00 -#define SAMA5D3_BASE_PIT 0xfffffe30 -#define SAMA5D3_BASE_WDT 0xfffffe40 -#define SAMA5D3_BASE_PMC 0xfffffc00 -#define SAMA5D3_BASE_PMECC 0xffffc070 -#define SAMA5D3_BASE_PMERRLOC 0xffffc500 - -/* - * Internal Memory. - */ -#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ - -#define SAMA5D3_ROM_BASE 0x00100000 -#define SAMA5D3_ROM_SIZE SZ_1M - -#define SAMA5D3_UDPHS_FIFO 0x00500000 -#define SAMA5D3_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */ -#define SAMA5D3_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h deleted file mode 100644 index 6d621e0111..0000000000 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Chip-specific header file for the SAMA5D4 family - * - * Copyright (C) 2014 Atmel Corporation, - * Bo Shen <voice.shen@atmel.com> - * - * Common definitions. - * Based on SAMA5D4 datasheet. - * - * Licensed under GPLv2 or later. - */ - -#ifndef SAMA5D4_H -#define SAMA5D4_H - -/* - * Peripheral identifiers/interrupts. - */ -#define SAMA5D4_ID_PIT 3 -#define SAMA5D4_ID_WDT 4 -#define SAMA5D4_ID_PIOD 5 -#define SAMA5D4_ID_USART0 6 -#define SAMA5D4_ID_USART1 7 -#define SAMA5D4_ID_DMA0 8 -#define SAMA5D4_ID_ICM 9 -#define SAMA5D4_ID_PKCC 10 -#define SAMA5D4_ID_SCI 11 -#define SAMA5D4_ID_AES 12 -#define SAMA5D4_ID_AESB 13 -#define SAMA5D4_ID_TDES 14 -#define SAMA5D4_ID_SHA 15 -#define SAMA5D4_ID_MPDDRC 16 -#define SAMA5D4_ID_MATRIX1 17 -#define SAMA5D4_ID_MATRIX0 18 -#define SAMA5D4_ID_VDEC 19 -#define SAMA5D4_ID_SECUMOD 20 -#define SAMA5D4_ID_MSADCC 21 -#define SAMA5D4_ID_HSMC 22 -#define SAMA5D4_ID_PIOA 23 -#define SAMA5D4_ID_PIOB 24 -#define SAMA5D4_ID_PIOC 25 -#define SAMA5D4_ID_PIOE 26 -#define SAMA5D4_ID_UART0 27 -#define SAMA5D4_ID_UART1 28 -#define SAMA5D4_ID_USART2 29 -#define SAMA5D4_ID_USART3 30 -#define SAMA5D4_ID_USART4 31 -#define SAMA5D4_ID_TWI0 32 -#define SAMA5D4_ID_TWI1 33 -#define SAMA5D4_ID_TWI2 34 -#define SAMA5D4_ID_HSMCI0 35 -#define SAMA5D4_ID_HSMCI1 36 -#define SAMA5D4_ID_SPI0 37 -#define SAMA5D4_ID_SPI1 38 -#define SAMA5D4_ID_SPI2 39 -#define SAMA5D4_ID_TC0 40 -#define SAMA5D4_ID_TC1 41 -#define SAMA5D4_ID_TC2 42 -#define SAMA5D4_ID_PWM 43 -#define SAMA5D4_ID_ADC 44 -#define SAMA5D4_ID_DBGU 45 -#define SAMA5D4_ID_UHPHS 46 -#define SAMA5D4_ID_UDPHS 47 -#define SAMA5D4_ID_SSC0 48 -#define SAMA5D4_ID_SSC1 49 -#define SAMA5D4_ID_DMA1 50 -#define SAMA5D4_ID_LCDC 51 -#define SAMA5D4_ID_ISI 52 -#define SAMA5D4_ID_TRNG 53 -#define SAMA5D4_ID_GMAC0 54 -#define SAMA5D4_ID_IRQ 56 -#define SAMA5D4_ID_IRQ 56 -#define SAMA5D4_ID_SFC 57 -#define SAMA5D4_ID_SECURAM 59 -#define SAMA5D4_ID_CTB 60 -#define SAMA5D4_ID_SMD 61 -#define SAMA5D4_ID_TWI3 62 -#define SAMA5D4_ID_CATB 63 -#define SAMA5D4_ID_SFR 64 -#define SAMA5D4_ID_AIC 65 -#define SAMA5D4_ID_SAIC 66 -#define SAMA5D4_ID_L2CC 67 - -/* - * User Peripheral physical base addresses. - */ - -#define SAMA5D4_BASE_LCDC 0xf0000000 /* (HLCDC5) Base Address */ -#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */ -#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */ -#define SAMA5D4_BASE_HSMCI0 0xf8000000 /* (MMCI0) Base Address */ -#define SAMA5D4_BASE_UART0 0xf8004000 /* (UART0) Base Address */ -#define SAMA5D4_BASE_SPI0 0xf8010000 /* (SPI0) Base Address */ -#define SAMA5D4_BASE_TC0 0xf801c000 /* (TC0) Base Address */ -#define SAMA5D4_BASE_GMAC0 0xf8020000 /* (GMAC0) Base Address */ -#define SAMA5D4_BASE_USART0 0xf802c000 /* (USART0) Base Address */ -#define SAMA5D4_BASE_USART1 0xf8030000 /* (USART1) Base Address */ -#define SAMA5D4_BASE_HSMCI1 0xfc000000 /* (HSMCI1) Base Address */ -#define SAMA5D4_BASE_UART1 0xfc004000 /* (UART1) Base Address */ -#define SAMA5D4_BASE_USART2 0xfc008000 /* (USART2) Base Address */ -#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3) Base Address */ -#define SAMA5D4_BASE_USART4 0xfc010000 /* (USART4) Base Address */ -#define SAMA5D4_BASE_SPI1 0xfc018000 /* (SPI1) Base Address */ -#define SAMA5D4_BASE_GMAC1 0xfc028000 /* (GMAC1) Base Address */ -#define SAMA5D4_BASE_HSMC 0xfc05c000 /* (HSMC) Base Address */ -#define SAMA5D4_BASE_PMECC 0xfc05c070 /* (PMECC) Base Address */ -#define SAMA5D4_BASE_PMERRLOC 0xfc05c500 /* (PMERRLOC) Base Address */ -#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */ -#define SAMA5D4_BASE_RSTC 0xfc068600 -#define SAMA5D4_BASE_PIT 0xfc068630 /* (PIT) Base Address */ -#define SAMA5D4_BASE_DBGU 0xfc069000 /* (DBGU) Base Address */ -#define SAMA5D4_BASE_PIOA 0xfc06a000 /* (PIOA) Base Address */ -#define SAMA5D4_BASE_PIOB 0xfc06b000 /* (PIOB) Base Address */ -#define SAMA5D4_BASE_PIOC 0xfc06c000 /* (PIOC) Base Address */ -#define SAMA5D4_BASE_PIOE 0xfc06d000 /* (PIOE) Base Address */ -#define SAMA5D4_BASE_AIC 0xfc06e000 /* (AIC) Base Address */ - -#define SAMA5D4_CHIPSELECT_3 0x80000000 - -/* - * Internal Memory. - */ -#define SAMA5D4_SRAM_BASE 0x00200000 /* Internal SRAM base address */ -#define SAMA5D4_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size */ - -#endif diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c new file mode 100644 index 0000000000..39ac3648f4 --- /dev/null +++ b/arch/arm/mach-at91/matrix.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-1-Clause */ +/* + * Copyright (c) 2013, Atmel Corporation + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + */ + +#include <io.h> +#include <mach/at91/tz_matrix.h> +#include <mach/at91/matrix.h> + +static inline void matrix_write(void __iomem *base, + unsigned int offset, + const unsigned int value) +{ + writel(value, base + offset); +} + +static inline unsigned int matrix_read(void __iomem *base, unsigned int offset) +{ + return readl(base + offset); +} + +void at91_matrix_write_protect_enable(void __iomem *matrix_base) +{ + matrix_write(matrix_base, MATRIX_WPMR, + MATRIX_WPMR_WPKEY_PASSWD | MATRIX_WPMR_WPEN_ENABLE); +} + +void at91_matrix_write_protect_disable(void __iomem *matrix_base) +{ + matrix_write(matrix_base, MATRIX_WPMR, MATRIX_WPMR_WPKEY_PASSWD); +} + +void at91_matrix_configure_slave_security(void __iomem *matrix_base, + unsigned int slave, + unsigned int srtop_setting, + unsigned int srsplit_setting, + unsigned int ssr_setting) +{ + matrix_write(matrix_base, MATRIX_SSR(slave), ssr_setting); + matrix_write(matrix_base, MATRIX_SRTSR(slave), srtop_setting); + matrix_write(matrix_base, MATRIX_SASSR(slave), srsplit_setting); +} diff --git a/arch/arm/mach-at91/sam9263_ll.c b/arch/arm/mach-at91/sam9263_ll.c new file mode 100644 index 0000000000..a60d3c7a25 --- /dev/null +++ b/arch/arm/mach-at91/sam9263_ll.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause +// SPDX-FileCopyrightText: 2017, Microchip Corporation + +#include <mach/at91/at91sam9263_matrix.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/at91_wdt.h> +#include <mach/at91/sam92_ll.h> + +static void sam9263_pmc_init(u32 plla, u32 pllb) +{ + unsigned flags = AT91_PMC_LL_AT91SAM9263; + u32 mckr_settings; + + at91_pmc_init(IOMEM(AT91SAM926X_BASE_PMC), flags); + + /* Setting PLL A and divider A */ + at91_pmc_cfg_plla(IOMEM(AT91SAM926X_BASE_PMC), plla, flags); + + /* Selection of Master Clock and Processor Clock */ + mckr_settings = AT91_PMC_PRES_1 | AT91SAM9_PMC_MDIV_2 | AT91_PMC_PDIV_1; + + /* PCK = PLLA = 2 * MCK */ + at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC), + AT91_PMC_CSS_SLOW | mckr_settings, flags); + + /* Switch MCK on PLLA output */ + at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC), + AT91_PMC_CSS_PLLA | mckr_settings, flags); + + if (pllb) + at91_pmc_cfg_pllb(IOMEM(AT91SAM926X_BASE_PMC), pllb, flags); +} + +static inline void matrix_wr(unsigned int offset, const unsigned int value) +{ + writel(value, IOMEM(AT91SAM9263_BASE_MATRIX + offset)); +} + +static void sam9263_matrix_init(void) +{ + /* Bus Matrix Master Configuration Register */ + matrix_wr(AT91SAM9263_MATRIX_MCFG0, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* OHCI */ + matrix_wr(AT91SAM9263_MATRIX_MCFG1, AT91SAM9263_MATRIX_ULBT_EIGHT); /* ISI */ + matrix_wr(AT91SAM9263_MATRIX_MCFG2, AT91SAM9263_MATRIX_ULBT_EIGHT); /* 2D */ + matrix_wr(AT91SAM9263_MATRIX_MCFG3, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DMAC */ + matrix_wr(AT91SAM9263_MATRIX_MCFG4, AT91SAM9263_MATRIX_ULBT_FOUR); /* MACB */ + matrix_wr(AT91SAM9263_MATRIX_MCFG5, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* LCDC */ + matrix_wr(AT91SAM9263_MATRIX_MCFG6, AT91SAM9263_MATRIX_ULBT_SINGLE); /* PDC */ + matrix_wr(AT91SAM9263_MATRIX_MCFG7, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DBUS */ + matrix_wr(AT91SAM9263_MATRIX_MCFG8, AT91SAM9263_MATRIX_ULBT_EIGHT); /* IBUS */ + + /* Bus Matrix Slave Configuration Registers */ + + /* ROM */ + matrix_wr(AT91SAM9263_MATRIX_SCFG0, + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(32)); + + /* RAM80K */ + matrix_wr(AT91SAM9263_MATRIX_SCFG1, + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(32)); + + /* RAM16K */ + matrix_wr(AT91SAM9263_MATRIX_SCFG2, + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(16)); + + /* PERIPHERALS */ + matrix_wr(AT91SAM9263_MATRIX_SCFG3, + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(4)); + + /* EBI0 */ + matrix_wr(AT91SAM9263_MATRIX_SCFG4, + AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(32)); + + /* EBI1 */ + matrix_wr(AT91SAM9263_MATRIX_SCFG5, + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(64)); + + /* APB */ + matrix_wr(AT91SAM9263_MATRIX_SCFG6, + AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY + | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D + | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST + | AT91SAM9263_MATRIX_SLOT_CYCLE_(4)); + + /* ROM */ + matrix_wr(AT91SAM9263_MATRIX_PRAS0, + AT91SAM9263_MATRIX_M0PR_(1) + | AT91SAM9263_MATRIX_M1PR_(0) + | AT91SAM9263_MATRIX_M2PR_(2) + | AT91SAM9263_MATRIX_M3PR_(1) + | AT91SAM9263_MATRIX_M4PR_(0) + | AT91SAM9263_MATRIX_M5PR_(3) + | AT91SAM9263_MATRIX_M6PR_(2) + | AT91SAM9263_MATRIX_M7PR_(3)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS0, AT91SAM9263_MATRIX_M8PR_(0)); + + /* RAM80K */ + matrix_wr(AT91SAM9263_MATRIX_PRAS1, + AT91SAM9263_MATRIX_M0PR_(1) + | AT91SAM9263_MATRIX_M1PR_(2) + | AT91SAM9263_MATRIX_M2PR_(1) + | AT91SAM9263_MATRIX_M3PR_(3) + | AT91SAM9263_MATRIX_M4PR_(0) + | AT91SAM9263_MATRIX_M5PR_(0) + | AT91SAM9263_MATRIX_M6PR_(3) + | AT91SAM9263_MATRIX_M7PR_(0)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS1, AT91SAM9263_MATRIX_M8PR_(2)); + + /* RAM16K */ + matrix_wr(AT91SAM9263_MATRIX_PRAS2, + AT91SAM9263_MATRIX_M0PR_(1) + | AT91SAM9263_MATRIX_M1PR_(0) + | AT91SAM9263_MATRIX_M2PR_(2) + | AT91SAM9263_MATRIX_M3PR_(1) + | AT91SAM9263_MATRIX_M4PR_(0) + | AT91SAM9263_MATRIX_M5PR_(3) + | AT91SAM9263_MATRIX_M6PR_(3) + | AT91SAM9263_MATRIX_M7PR_(2)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS2, AT91SAM9263_MATRIX_M8PR_(0)); + + /* PERIPHERALS */ + matrix_wr(AT91SAM9263_MATRIX_PRAS3, + AT91SAM9263_MATRIX_M0PR_(0) + | AT91SAM9263_MATRIX_M1PR_(1) + | AT91SAM9263_MATRIX_M2PR_(0) + | AT91SAM9263_MATRIX_M3PR_(2) + | AT91SAM9263_MATRIX_M4PR_(1) + | AT91SAM9263_MATRIX_M5PR_(0) + | AT91SAM9263_MATRIX_M6PR_(3) + | AT91SAM9263_MATRIX_M7PR_(2)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS3, AT91SAM9263_MATRIX_M8PR_(3)); + + /* EBI0 */ + matrix_wr(AT91SAM9263_MATRIX_PRAS4, + AT91SAM9263_MATRIX_M0PR_(1) + | AT91SAM9263_MATRIX_M1PR_(3) + | AT91SAM9263_MATRIX_M2PR_(0) + | AT91SAM9263_MATRIX_M3PR_(2) + | AT91SAM9263_MATRIX_M4PR_(3) + | AT91SAM9263_MATRIX_M5PR_(0) + | AT91SAM9263_MATRIX_M6PR_(0) + | AT91SAM9263_MATRIX_M7PR_(1)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS4, AT91SAM9263_MATRIX_M8PR_(2)); + + /* EBI1 */ + matrix_wr(AT91SAM9263_MATRIX_PRAS5, + AT91SAM9263_MATRIX_M0PR_(0) + | AT91SAM9263_MATRIX_M1PR_(1) + | AT91SAM9263_MATRIX_M2PR_(0) + | AT91SAM9263_MATRIX_M3PR_(0) + | AT91SAM9263_MATRIX_M4PR_(3) + | AT91SAM9263_MATRIX_M5PR_(2) + | AT91SAM9263_MATRIX_M6PR_(3) + | AT91SAM9263_MATRIX_M7PR_(2)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS5, AT91SAM9263_MATRIX_M8PR_(1)); + + /* APB */ + matrix_wr(AT91SAM9263_MATRIX_PRAS6, + AT91SAM9263_MATRIX_M0PR_(1) + | AT91SAM9263_MATRIX_M1PR_(0) + | AT91SAM9263_MATRIX_M2PR_(2) + | AT91SAM9263_MATRIX_M3PR_(1) + | AT91SAM9263_MATRIX_M4PR_(0) + | AT91SAM9263_MATRIX_M5PR_(0) + | AT91SAM9263_MATRIX_M6PR_(3) + | AT91SAM9263_MATRIX_M7PR_(3)); + + matrix_wr(AT91SAM9263_MATRIX_PRBS6, AT91SAM9263_MATRIX_M8PR_(2)); +} + +static void sam9263_rstc_init(void) +{ + writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, IOMEM(AT91SAM926X_BASE_RSTC + AT91_RSTC_MR)); +} + +void sam9263_lowlevel_init(u32 plla, u32 pllb) +{ + at91_wdt_disable(IOMEM(AT91SAM9263_BASE_WDT)); + sam9263_pmc_init(plla, pllb); + sam9263_matrix_init(); + sam9263_rstc_init(); +} diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index 05584c0711..ef58a0153a 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -1,21 +1,16 @@ -/* - * linux/arch/arm/mach-at91/sam9_smc.c - * - * Copyright (C) 2008 Andrew Victor - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2008 Andrew Victor + +/* linux/arch/arm/mach-at91/sam9_smc.c */ #include <common.h> #include <init.h> #include <io.h> -#include <mach/hardware.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/cpu.h> #include <linux/err.h> -#include <mach/at91sam9_smc.h> +#include <mach/at91/at91sam9_smc.h> #define AT91_SAM9_SMC_CS_STRIDE 0x10 #define AT91_SAMA5_SMC_CS_STRIDE 0x14 @@ -173,7 +168,7 @@ void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config) sam9_smc_cs_write_timings(AT91_SMC_CS(id, cs), config); } -static int at91sam9_smc_probe(struct device_d *dev) +static int at91sam9_smc_probe(struct device *dev) { struct resource *iores; int id = dev->id; @@ -195,13 +190,9 @@ static int at91sam9_smc_probe(struct device_d *dev) return 0; } -static struct driver_d at91sam9_smc_driver = { +static struct driver at91sam9_smc_driver = { .name = "at91sam9-smc", .probe = at91sam9_smc_probe, }; -static int at91sam9_smc_init(void) -{ - return platform_driver_register(&at91sam9_smc_driver); -} -coredevice_initcall(at91sam9_smc_init); +postcore_platform_driver(at91sam9_smc_driver); diff --git a/arch/arm/mach-at91/sama5_bootsource.c b/arch/arm/mach-at91/sama5_bootsource.c new file mode 100644 index 0000000000..4ede256e8f --- /dev/null +++ b/arch/arm/mach-at91/sama5_bootsource.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <mach/at91/sama5_bootsource.h> +#include <linux/export.h> +#include <bootsource.h> +#include <init.h> +#include <of.h> + +/* + * sama5_bootsource_init - initialize bootsource + * + * BootROM will populate r4 when loading first stage bootloader + * with information about boot source. The entry points for + * multi-image capable SAMA5 boards will pass this information + * along. If you use a bootloader before barebox, you need to + * ensure that r4 is initialized for $bootsource to be correct + * in barebox. Example implementing it for AT91Bootstrap: + * https://github.com/linux4sam/at91bootstrap/pull/159 + */ +static int sama5_bootsource_init(void) +{ + if (!of_machine_is_compatible("atmel,sama5")) + return 0; + + at91_bootsource = __sama5d2_stashed_bootrom_r4; + + if (at91_bootsource) + bootsource_set_raw(sama5_bootsource(at91_bootsource), + sama5_bootsource_instance(at91_bootsource)); + + return 0; +} +postcore_initcall(sama5_bootsource_init); diff --git a/arch/arm/mach-at91/sama5d2.c b/arch/arm/mach-at91/sama5d2.c new file mode 100644 index 0000000000..f629d1df33 --- /dev/null +++ b/arch/arm/mach-at91/sama5d2.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <of.h> +#include <init.h> +#include <mach/at91/aic.h> +#include <mach/at91/sama5d2.h> +#include <asm/cache-l2x0.h> +#include <asm/mmu.h> +#include <mach/at91/cpu.h> + +#define SFR_CAN 0x48 +#define SFR_L2CC_HRAMC 0x58 + +static void sama5d2_can_ram_init(void) +{ + writel(0x00210021, SAMA5D2_BASE_SFR + SFR_CAN); +} + +static void sama5d2_l2x0_init(void) +{ + void __iomem *l2x0_base = SAMA5D2_BASE_L2CC; + u32 cfg; + + writel(0x1, SAMA5D2_BASE_SFR + SFR_L2CC_HRAMC); + + /* Prefetch Control */ + cfg = readl(l2x0_base + L2X0_PREFETCH_CTRL); + /* prefetch offset: TODO find proper values */ + cfg |= 0x1; + cfg |= L2X0_INCR_DOUBLE_LINEFILL_EN | L2X0_PREFETCH_DROP_EN + | L2X0_DOUBLE_LINEFILL_EN; + cfg |= L2X0_DATA_PREFETCH_EN | L2X0_INSTRUCTION_PREFETCH_EN; + writel(cfg, l2x0_base + L2X0_PREFETCH_CTRL); + + /* Power Control */ + cfg = readl(l2x0_base + L2X0_POWER_CTRL); + cfg |= L2X0_STNDBY_MODE_EN | L2X0_DYNAMIC_CLK_GATING_EN; + writel(cfg, l2x0_base + L2X0_POWER_CTRL); + + l2x0_init(l2x0_base, 0x0, ~0UL); +} + +static int sama5d2_init(void) +{ + if (!of_machine_is_compatible("atmel,sama5d2")) + return 0; + + at91_aic_redir(SAMA5D2_BASE_SFR, SAMA5D2_AICREDIR_KEY); + sama5d2_can_ram_init(); + sama5d2_l2x0_init(); + + return 0; +} +postmmu_initcall(sama5d2_init); diff --git a/arch/arm/mach-at91/sama5d2_ll.c b/arch/arm/mach-at91/sama5d2_ll.c new file mode 100644 index 0000000000..c0adf220a2 --- /dev/null +++ b/arch/arm/mach-at91/sama5d2_ll.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: BSD-1-Clause +/* + * Copyright (c) 2017, Microchip Corporation + * + * Microchip's name may not be used to endorse or promote products derived + * from this software without specific prior written permission. + */ + +#include <mach/at91/sama5d2_ll.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/ddramc.h> +#include <mach/at91/early_udelay.h> +#include <mach/at91/tz_matrix.h> +#include <mach/at91/matrix.h> +#include <mach/at91/at91_rstc.h> +#include <asm/barebox-arm.h> + +#define sama5d2_pmc_write(off, val) writel(val, SAMA5D2_BASE_PMC + off) +#define sama5d2_pmc_read(off) readl(SAMA5D2_BASE_PMC + off) + +void sama5d2_ddr2_init(const struct at91_ddramc_register *ddramc_reg_config) +{ + unsigned int reg; + + /* enable ddr2 clock */ + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_MPDDRC); + sama5d2_pmc_write(AT91_PMC_SCER, AT91CAP9_PMC_DDR); + + reg = AT91_MPDDRC_RD_DATA_PATH_ONE_CYCLES; + writel(reg, SAMA5D2_BASE_MPDDRC + AT91_MPDDRC_RD_DATA_PATH); + + reg = readl(SAMA5D2_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR); + reg &= ~AT91_MPDDRC_RDIV; + reg &= ~AT91_MPDDRC_TZQIO; + reg |= AT91_MPDDRC_RDIV_DDR2_RZQ_50; + reg |= AT91_MPDDRC_TZQIO_(101); + writel(reg, SAMA5D2_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR); + + /* DDRAM2 Controller initialize */ + at91_ddram_initialize(SAMA5D2_BASE_MPDDRC, IOMEM(SAMA5_DDRCS), + ddramc_reg_config); +} + +static void sama5d2_pmc_init(void) +{ + at91_pmc_init(SAMA5D2_BASE_PMC, AT91_PMC_LL_SAMA5D2); + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + sama5d2_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA); + sama5d2_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA + | AT91_PMC3_MUL_(40) | AT91_PMC_OUT_0 + | AT91_PMC_PLLCOUNT + | AT91_PMC_DIV_BYPASS); + + while (!(sama5d2_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKA)) + ; + + /* Initialize PLLA charge pump */ + /* No need: we keep what is set in ROM code */ + //sama5d2_pmc_write(AT91_PMC_PLLICPR, AT91_PMC_IPLLA_3); + + /* Switch PCK/MCK on PLLA output */ + at91_pmc_cfg_mck(SAMA5D2_BASE_PMC, + AT91_PMC_H32MXDIV + | AT91_PMC_PLLADIV2_ON + | AT91SAM9_PMC_MDIV_3 + | AT91_PMC_CSS_PLLA, + AT91_PMC_LL_SAMA5D2); +} + +static void matrix_configure_slave(void) +{ + u32 ddr_port; + u32 ssr_setting, sasplit_setting, srtop_setting; + + /* + * Matrix 0 (H64MX) + */ + + /* + * 0: Bridge from H64MX to AXIMX + * (Internal ROM, Crypto Library, PKCC RAM): Always Secured + */ + + /* 1: H64MX Peripheral Bridge */ + + /* 2 ~ 9 DDR2 Port0 ~ 7: Non-Secure */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128M); + ssr_setting = MATRIX_LANSECH_NS(0) | + MATRIX_RDNSECH_NS(0) | + MATRIX_WRNSECH_NS(0); + for (ddr_port = 0; ddr_port < 8; ddr_port++) { + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX64, + SAMA5D2_H64MX_SLAVE_DDR2_PORT_0 + ddr_port, + srtop_setting, + sasplit_setting, + ssr_setting); + } + + /* + * 10: Internal SRAM 128K + * TOP0 is set to 128K + * SPLIT0 is set to 64K + * LANSECH0 is set to 0, the low area of region 0 is the Securable one + * RDNSECH0 is set to 0, region 0 Securable area is secured for reads. + * WRNSECH0 is set to 0, region 0 Securable area is secured for writes + */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128K); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_64K); + ssr_setting = MATRIX_LANSECH_S(0) | + MATRIX_RDNSECH_S(0) | + MATRIX_WRNSECH_S(0); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX64, + SAMA5D2_H64MX_SLAVE_INTERNAL_SRAM, + srtop_setting, + sasplit_setting, + ssr_setting); + + /* 11: Internal SRAM 128K (Cache L2) */ + /* 12: QSPI0 */ + /* 13: QSPI1 */ + /* 14: AESB */ + + /* + * Matrix 1 (H32MX) + */ + + /* 0: Bridge from H32MX to H64MX: Not Secured */ + + /* 1: H32MX Peripheral Bridge 0: Not Secured */ + + /* 2: H32MX Peripheral Bridge 1: Not Secured */ + + /* + * 3: External Bus Interface + * EBI CS0 Memory(256M) ----> Slave Region 0, 1 + * EBI CS1 Memory(256M) ----> Slave Region 2, 3 + * EBI CS2 Memory(256M) ----> Slave Region 4, 5 + * EBI CS3 Memory(128M) ----> Slave Region 6 + * NFC Command Registers(128M) -->Slave Region 7 + * + * NANDFlash(EBI CS3) --> Slave Region 6: Non-Secure + */ + srtop_setting = MATRIX_SRTOP(6, MATRIX_SRTOP_VALUE_128M) | + MATRIX_SRTOP(7, MATRIX_SRTOP_VALUE_128M); + sasplit_setting = MATRIX_SASPLIT(6, MATRIX_SASPLIT_VALUE_128M) | + MATRIX_SASPLIT(7, MATRIX_SASPLIT_VALUE_128M); + ssr_setting = MATRIX_LANSECH_NS(6) | + MATRIX_RDNSECH_NS(6) | + MATRIX_WRNSECH_NS(6) | + MATRIX_LANSECH_NS(7) | + MATRIX_RDNSECH_NS(7) | + MATRIX_WRNSECH_NS(7); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX32, + SAMA5D2_H32MX_EXTERNAL_EBI, + srtop_setting, + sasplit_setting, + ssr_setting); + + /* 4: NFC SRAM (4K): Non-Secure */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_8K); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8K); + ssr_setting = MATRIX_LANSECH_NS(0) | + MATRIX_RDNSECH_NS(0) | + MATRIX_WRNSECH_NS(0); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX32, + SAMA5D2_H32MX_NFC_SRAM, + srtop_setting, + sasplit_setting, + ssr_setting); + + /* 5: + * USB Device High Speed Dual Port RAM (DPR): 1M + * USB Host OHCI registers: 1M + * USB Host EHCI registers: 1M + */ + srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M) | + MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_1M) | + MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_1M); + sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M) | + MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_1M) | + MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_1M); + ssr_setting = MATRIX_LANSECH_NS(0) | + MATRIX_LANSECH_NS(1) | + MATRIX_LANSECH_NS(2) | + MATRIX_RDNSECH_NS(0) | + MATRIX_RDNSECH_NS(1) | + MATRIX_RDNSECH_NS(2) | + MATRIX_WRNSECH_NS(0) | + MATRIX_WRNSECH_NS(1) | + MATRIX_WRNSECH_NS(2); + at91_matrix_configure_slave_security(SAMA5D2_BASE_MATRIX32, + SAMA5D2_H32MX_USB, + srtop_setting, + sasplit_setting, + ssr_setting); +} + +static void sama5d2_matrix_init(void) +{ + at91_matrix_write_protect_disable(SAMA5D2_BASE_MATRIX64); + at91_matrix_write_protect_disable(SAMA5D2_BASE_MATRIX32); + + matrix_configure_slave(); +} + +static void sama5d2_rstc_init(void) +{ + writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, + SAMA5D2_BASE_RSTC + AT91_RSTC_MR); +} + +void sama5d2_lowlevel_init(void) +{ + arm_cpu_lowlevel_init(); + sama5d2_pmc_init(); + sama5d2_matrix_init(); + sama5d2_rstc_init(); +} diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index a5d464eca0..447ac711b4 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c @@ -1,12 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only + #include <common.h> #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/cpu.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/cpu.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include <linux/clk.h> #include "generic.h" @@ -397,7 +399,7 @@ static void sama5d3_initialize(void) at91_add_pit(SAMA5D3_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D3_BASE_HSMC + 0x600, 0xa0); - restart_handler_register_fn(sama5d3_restart); + restart_handler_register_fn("soc", sama5d3_restart); } static int sama5d3_setup(void) diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c index bf4a03d404..f6d5617e5f 100644 --- a/arch/arm/mach-at91/sama5d3_devices.c +++ b/arch/arm/mach-at91/sama5d3_devices.c @@ -1,26 +1,20 @@ -/* - * On-Chip devices setup code for the AT91SAM9x5 family - * - * Copyright (C) 2010 Atmel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2010 Atmel Corporation + +/* On-Chip devices setup code for the AT91SAM9x5 family */ + #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/board.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9x5_matrix.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/iomux.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9x5_matrix.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/cpu.h> #include <i2c/i2c-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-at91/sama5d3_ll.c b/arch/arm/mach-at91/sama5d3_ll.c new file mode 100644 index 0000000000..65eea93723 --- /dev/null +++ b/arch/arm/mach-at91/sama5d3_ll.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause +// SPDX-FileCopyrightText: 2017, Microchip Corporation + +#include <mach/at91/at91_wdt.h> +#include <mach/at91/barebox-arm.h> +#include <mach/at91/sama5d3_ll.h> + +void sama5d3_lowlevel_init(void) +{ + arm_cpu_lowlevel_init(); + + at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT)); + at91_pmc_init(IOMEM(SAMA5D3_BASE_PMC), AT91_PMC_LL_SAMA5D3); + + /* At this stage the main oscillator + * is supposed to be enabled PCK = MCK = MOSC + */ + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + at91_pmc_cfg_plla(IOMEM(SAMA5D3_BASE_PMC), AT91_PMC3_MUL_(43) + | AT91_PMC_OUT_0 | AT91_PMC_PLLCOUNT + | AT91_PMC_DIV_BYPASS, AT91_PMC_LL_SAMA5D3); + + /* Initialize PLLA charge pump */ + at91_pmc_init_pll(IOMEM(SAMA5D3_BASE_PMC), AT91_PMC_IPLLA_3); + + /* Switch PCK/MCK on Main clock output */ + at91_pmc_cfg_mck(IOMEM(SAMA5D3_BASE_PMC), AT91SAM9_PMC_MDIV_4 + | AT91_PMC_CSS_MAIN, AT91_PMC_LL_SAMA5D3); + + /* Switch PCK/MCK on PLLA output */ + at91_pmc_cfg_mck(IOMEM(SAMA5D3_BASE_PMC), AT91SAM9_PMC_MDIV_4 + | AT91_PMC_CSS_PLLA, AT91_PMC_LL_SAMA5D3); +} diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c index ca09dfe425..8417dedbd1 100644 --- a/arch/arm/mach-at91/sama5d4.c +++ b/arch/arm/mach-at91/sama5d4.c @@ -11,11 +11,11 @@ #include <gpio.h> #include <init.h> #include <restart.h> -#include <mach/hardware.h> -#include <mach/at91_pmc.h> -#include <mach/cpu.h> -#include <mach/board.h> -#include <mach/at91_rstc.h> +#include <mach/at91/hardware.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/cpu.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_rstc.h> #include <linux/clk.h> #include "generic.h" @@ -305,7 +305,7 @@ static void sama5d4_initialize(void) at91_add_pit(SAMA5D4_BASE_PIT); at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D4_BASE_HSMC + 0x600, 0xa0); - restart_handler_register_fn(sama5d4_restart); + restart_handler_register_fn("soc", sama5d4_restart); } static int sama5d4_setup(void) diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c index 5a1109dc0e..e438bd0d10 100644 --- a/arch/arm/mach-at91/sama5d4_devices.c +++ b/arch/arm/mach-at91/sama5d4_devices.c @@ -1,27 +1,20 @@ -/* - * On-Chip devices setup code for the SAMA5D4 family - * - * Copyright (C) 2014 Atmel Corporation. - * Bo Shen <voice.shen@atmel.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ +// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-FileCopyrightText: 2014 Atmel Corporation (Bo Shen <voice.shen@atmel.com>) + +/* On-Chip devices setup code for the SAMA5D4 family */ #include <common.h> #include <init.h> #include <linux/sizes.h> #include <gpio.h> #include <asm/armlinux.h> -#include <mach/hardware.h> -#include <mach/board.h> -#include <mach/at91_pmc.h> -#include <mach/at91sam9x5_matrix.h> -#include <mach/at91sam9_ddrsdr.h> -#include <mach/iomux.h> -#include <mach/cpu.h> +#include <mach/at91/hardware.h> +#include <mach/at91/board.h> +#include <mach/at91/at91_pmc.h> +#include <mach/at91/at91sam9x5_matrix.h> +#include <mach/at91/at91_ddrsdrc.h> +#include <mach/at91/iomux.h> +#include <mach/at91/cpu.h> #include <i2c/i2c-gpio.h> #include "generic.h" diff --git a/arch/arm/mach-at91/sdramc.c b/arch/arm/mach-at91/sdramc.c new file mode 100644 index 0000000000..655f24ecd9 --- /dev/null +++ b/arch/arm/mach-at91/sdramc.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Ahmad Fatoum <a.fatoum@pengutronix.de> + */ + +#include <common.h> +#include <init.h> +#include <mach/at91/hardware.h> +#include <asm/barebox-arm.h> +#include <mach/at91/at91sam9_sdramc.h> +#include <asm/memory.h> +#include <pbl.h> +#include <io.h> + +void __noreturn at91sam9260_barebox_entry(void *boarddata) +{ + barebox_arm_entry(AT91_CHIPSELECT_1, + at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), + boarddata); +} + +static int at91_sdramc_probe(struct device *dev) +{ + struct resource *iores; + void __iomem *base; + + iores = dev_request_mem_resource(dev, 0); + if (IS_ERR(iores)) + return PTR_ERR(iores); + base = IOMEM(iores->start); + + return arm_add_mem_device("ram0", AT91_CHIPSELECT_1, + at91_get_sdram_size(base)); +} + +static struct of_device_id at91_sdramc_dt_ids[] = { + { .compatible = "atmel,at91sam9260-sdramc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, at91_sdramc_dt_ids); + +static struct driver at91_sdramc_driver = { + .name = "at91sam9260-sdramc", + .probe = at91_sdramc_probe, + .of_compatible = at91_sdramc_dt_ids, +}; +mem_platform_driver(at91_sdramc_driver); diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index b7a66aa0ae..708c946192 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -11,11 +11,11 @@ #include <restart.h> #include <linux/clk.h> -#include <mach/hardware.h> -#include <mach/cpu.h> -#include <mach/at91_dbgu.h> -#include <mach/at91_rstc.h> -#include <mach/board.h> +#include <mach/at91/hardware.h> +#include <mach/at91/cpu.h> +#include <mach/at91/at91_dbgu.h> +#include <mach/at91/at91_rstc.h> +#include <mach/at91/board.h> #include "generic.h" @@ -371,7 +371,7 @@ postcore_initcall(at91_detect); static int at91_soc_device(void) { - struct device_d *dev; + struct device *dev; dev = add_generic_device_res("soc", DEVICE_ID_SINGLE, NULL, 0, NULL); dev_add_param_fixed(dev, "name", (char*)at91_get_soc_type(&at91_soc_initdata)); diff --git a/arch/arm/mach-at91/xload-mmc.c b/arch/arm/mach-at91/xload-mmc.c new file mode 100644 index 0000000000..9c03d2119c --- /dev/null +++ b/arch/arm/mach-at91/xload-mmc.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <common.h> +#include <mach/at91/xload.h> +#include <mach/at91/sama5_bootsource.h> +#include <mach/at91/hardware.h> +#include <mach/at91/sama5d2_ll.h> +#include <mach/at91/sama5d3_ll.h> +#include <mach/at91/gpio.h> +#include <linux/sizes.h> +#include <asm/cache.h> +#include <pbl/bio.h> + +static void at91_fat_start_image(struct pbl_bio *bio, + void *buf, unsigned int len, + u32 r4) +{ + void __noreturn (*bb)(void); + int ret; + + ret = pbl_fat_load(bio, "barebox.bin", buf, len); + if (ret < 0) { + pr_err("pbl_fat_load: error %d\n", ret); + return; + } + + bb = buf; + + sync_caches_for_execution(); + + sama5_boot_xload(bb, r4); +} + +static const struct sdhci_instance { + void __iomem *base; + unsigned id; + u8 periph; + s8 pins[15]; +} sdhci_instances[] = { + [0] = { + .base = SAMA5D2_BASE_SDHC0, .id = SAMA5D2_ID_SDMMC0, .periph = AT91_MUX_PERIPH_A, + .pins = { 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 13, 10, 11, 12, -1 } + }, + [1] = { + .base = SAMA5D2_BASE_SDHC1, .id = SAMA5D2_ID_SDMMC1, .periph = AT91_MUX_PERIPH_E, + .pins = { 18, 19, 20, 21, 22, 28, 30, -1 } + }, +}; + +/** + * sama5d2_sdhci_start_image - Load and start an image from FAT-formatted SDHCI + * @r4: value of r4 passed by BootROM + */ +void __noreturn sama5d2_sdhci_start_image(u32 r4) +{ + void *buf = (void *)SAMA5_DDRCS; + const struct sdhci_instance *instance; + struct pbl_bio bio; + const s8 *pin; + int ret; + + ret = sama5_bootsource_instance(r4); + if (ret > 1) + panic("Couldn't determine boot MCI instance\n"); + + instance = &sdhci_instances[ret]; + + sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOA); + for (pin = instance->pins; *pin >= 0; pin++) { + at91_mux_pio4_set_periph(SAMA5D2_BASE_PIOA, + BIT(*pin), instance->periph); + } + + sama5d2_pmc_enable_periph_clock(instance->id); + sama5d2_pmc_enable_generic_clock(instance->id, AT91_PMC_GCKCSS_UPLL_CLK, 1); + + ret = at91_sdhci_bio_init(&bio, instance->base); + if (ret) + goto out_panic; + + /* TODO: eMMC boot partition handling: they are not FAT-formatted */ + + at91_fat_start_image(&bio, buf, SZ_16M, r4); + +out_panic: + panic("FAT chainloading failed\n"); +} + +static const struct atmci_instance { + void __iomem *base; + unsigned id; + u8 periph; + s8 pins[15]; +} sama5d3_atmci_instances[] = { + [0] = { + .base = IOMEM(SAMA5D3_BASE_HSMCI0), + .id = SAMA5D3_ID_HSMCI0, + .periph = AT91_MUX_PERIPH_A, + .pins = { + AT91_PIN_PD0, AT91_PIN_PD1, AT91_PIN_PD2, AT91_PIN_PD3, + AT91_PIN_PD4, AT91_PIN_PD5, AT91_PIN_PD6, AT91_PIN_PD7, + AT91_PIN_PD8, AT91_PIN_PD9, -1 } + }, +}; + +void __noreturn sama5d3_atmci_start_image(u32 boot_src, unsigned int clock, + unsigned int slot) +{ + void *buf = (void *)SAMA5_DDRCS; + const struct atmci_instance *instance; + struct pbl_bio bio; + const s8 *pin; + int ret; + + ret = sama5_bootsource_instance(boot_src); + if (ret > ARRAY_SIZE(sama5d3_atmci_instances) - 1) + panic("Couldn't determine boot MCI instance\n"); + + instance = &sama5d3_atmci_instances[boot_src]; + + sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOD); + for (pin = instance->pins; *pin >= 0; pin++) { + at91_mux_pio3_pin(IOMEM(SAMA5D3_BASE_PIOD), + pin_to_mask(*pin), instance->periph, 0); + } + + sama5d3_pmc_enable_periph_clock(instance->id); + + ret = at91_mci_bio_init(&bio, instance->base, clock, slot); + if (ret) + goto out_panic; + + at91_fat_start_image(&bio, buf, SZ_16M, boot_src); + +out_panic: + panic("FAT chainloading failed\n"); +} |