diff options
Diffstat (limited to 'arch/arm/mach-at91')
37 files changed, 3224 insertions, 62 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index f2a2ee781d..14bab550c3 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -18,11 +18,18 @@ config SOC_AT91SAM9 select AT91SAM9_SMC select AT91SAM9_TIMER +config SOC_SAMA5 + bool + select CPU_V7 + select AT91SAM9_SMC + select AT91SAM9_TIMER + config ARCH_TEXT_BASE hex default 0x73f00000 if ARCH_AT91SAM9G45 default 0x26f00000 if ARCH_AT91SAM9X5 default 0x20f00000 if ARCH_AT91RM9200 + default 0x21f00000 if MACH_ANIMEO_IP default 0x23f00000 config BOARDINFO @@ -32,9 +39,11 @@ config BOARDINFO default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK default "Atmel at91sam9g10-ek" if MACH_AT91SAM9G10EK default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK + default "Atmel at91sam9m10ihd" if MACH_AT91SAM9M10IHD default "Atmel at91sam9m10g45-ek" if MACH_AT91SAM9M10G45EK default "Atmel at91sam9n12-ek" if MACH_AT91SAM9N12EK default "Atmel at91sam9x5-ek" if MACH_AT91SAM9X5EK + default "Atmel sama5d3x-ek" if MACH_SAMA5D3XEK default "Bucyrus MMC-CPU" if MACH_MMCCPU default "Calao USB-A9260" if MACH_USB_A9260 default "Calao USB-A9263" if MACH_USB_A9263 @@ -47,6 +56,8 @@ config BOARDINFO default "Calao TNY-A9263" if MACH_TNY_A9263 default "Calao TNY-A9G20" if MACH_TNY_A9G20 default "Calao QIL-A9260" if MACH_QIL_A9260 + default "Somfy Animeo IP" if MACH_ANIMEO_IP + default "Telit EVK-PRO3" if MACH_GE863 config HAVE_NAND_ATMEL_BUSWIDTH_16 bool @@ -60,6 +71,12 @@ config AT91SAM9_RESET config AT91SAM9G45_RESET bool +config HAVE_AT91_LOAD_BAREBOX_SRAM + bool + +config AT91SAM9_LOWLEVEL_INIT + bool + comment "Atmel AT91 System-on-Chip" config SOC_AT91RM9200 @@ -75,6 +92,7 @@ config SOC_AT91SAM9260 select HAVE_AT91_DBGU0 select HAS_MACB select AT91SAM9_RESET + select AT91SAM9_LOWLEVEL_INIT help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE or AT91SAM9G20 SoC. @@ -84,6 +102,7 @@ config SOC_AT91SAM9261 select SOC_AT91SAM9 select HAVE_AT91_DBGU0 select AT91SAM9_RESET + select AT91SAM9_LOWLEVEL_INIT help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. @@ -93,6 +112,8 @@ config SOC_AT91SAM9263 select HAVE_AT91_DBGU1 select HAS_MACB select AT91SAM9_RESET + select AT91SAM9_LOWLEVEL_INIT + select HAVE_AT91_LOAD_BAREBOX_SRAM config SOC_AT91SAM9G45 bool @@ -140,6 +161,7 @@ config ARCH_AT91SAM9260 config ARCH_AT91SAM9261 bool "AT91SAM9261" select SOC_AT91SAM9261 + select HAVE_AT91_LOAD_BAREBOX_SRAM config ARCH_AT91SAM9263 bool "AT91SAM9263" @@ -165,6 +187,13 @@ config ARCH_AT91SAM9N12 bool "AT91SAM9N12" select SOC_AT91SAM9N12 +config ARCH_SAMA5D3 + bool "SAMA5D3x" + select SOC_SAMA5 + select HAVE_AT91_DBGU1 + select HAS_MACB + select AT91SAM9G45_RESET + endchoice config ARCH_BAREBOX_MAX_BARE_INIT_SIZE @@ -177,6 +206,7 @@ config ARCH_BAREBOX_MAX_BARE_INIT_SIZE default 0xF000 if ARCH_AT91SAM9G45 default 0x6000 if ARCH_AT91SAM9X5 default 0x6000 if ARCH_AT91SAM9N12 + default 0x6000 if ARCH_SAMA5D3 default 0xffffffff config SUPPORT_CALAO_DAB_MMX @@ -210,6 +240,9 @@ if ARCH_AT91SAM9260 choice prompt "AT91SAM9260 Board Type" +config MACH_ANIMEO_IP + bool "Somfy Animeo IP" + config MACH_AT91SAM9260EK bool "Atmel AT91SAM9260-EK" select HAVE_NAND_ATMEL_BUSWIDTH_16 @@ -236,6 +269,13 @@ config MACH_USB_A9260 Select this if you are using a Calao Systems USB-A9260. <http://www.calao-systems.com> +config MACH_GE863 + bool "Telit EVK-PRO3" + select HAVE_DEFAULT_ENVIRONMENT_NEW + help + Say y here if you are using Telit EVK-PRO3 with GE863-PRO3 + <http://www.telit.com> + endchoice endif @@ -250,6 +290,8 @@ choice config MACH_AT91SAM9261EK bool "Atmel AT91SAM9261-EK Evaluation Kit" select HAS_DM9000 + select HAVE_AT91_DATAFLASH_CARD + select MACH_HAS_LOWLEVEL_INIT select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. @@ -352,12 +394,14 @@ config MACH_PM9263 config MACH_TNY_A9263 bool "CALAO TNY-A9263" select SUPPORT_CALAO_MOB_TNY_MD2 + select MACH_HAS_LOWLEVEL_INIT help Select this if you are using a Calao Systems TNY-A9263. <http://www.calao-systems.com> config MACH_USB_A9263 bool "CALAO USB-A9263" + select MACH_HAS_LOWLEVEL_INIT help Select this if you are using a Calao Systems USB-A9263. <http://www.calao-systems.com> @@ -371,6 +415,11 @@ if ARCH_AT91SAM9G45 choice prompt "AT91SAM9G45 or AT91SAM9M10 Board Type" +config MACH_AT91SAM9M10IHD + bool "Atmel AT91SAM9M10IDH Tablet" + help + Select this if you are using Atmel's AT91SAM9M10IHD Tablet + config MACH_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK Evaluation Kit" select HAVE_NAND_ATMEL_BUSWIDTH_16 @@ -423,6 +472,22 @@ endif # ---------------------------------------------------------- +if ARCH_SAMA5D3 + +choice + prompt "SAMA5D3 Board Type" + +config MACH_SAMA5D3XEK + bool "Atmel SAMA5D3X Evaluation Kit" + help + Select this if you are using Atmel's SAMA5D3X-EK Evaluation Kit. + +endchoice + +endif + +# ---------------------------------------------------------- + comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD @@ -480,8 +545,33 @@ config CALAO_MB_QIL_A9260 bool "MB-QIL A9260 Motherboard Board support" depends on MACH_QIL_A9260 +if COMMAND_SUPPORT + config CMD_AT91MUX bool "at91mux dump command" default y +config CMD_AT91CLK + bool "at91clk dump command" + default y + +config CMD_AT91_BOOT_TEST + bool "at91_boot_test" + help + allow to upload a boot binary to sram and execute it + useful to test bootstrap or barebox lowlevel init + +endif + +config AT91_BOOTSTRAP + bool "at91 bootstrap" + depends on MACH_HAS_LOWLEVEL_INIT + select BOOTSTRAP + +config AT91_LOAD_BAREBOX_SRAM + bool "at91 laad barebox in sram" + depends on MACH_HAS_LOWLEVEL_INIT + depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM + default y if SHELL_NONE + endif diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 53b4dd89ab..f6c8500840 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,6 +1,11 @@ obj-y += setup.o clock.o gpio.o +obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o -lowlevel_init-y = at91sam926x_lowlevel_init.o +obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o +lowlevel_init-$(CONFIG_AT91SAM9_LOWLEVEL_INIT) = at91sam926x_lowlevel_init.o +lowlevel_init-$(CONFIG_SOC_AT91SAM9260) += at91sam9260_lowlevel_init.o +lowlevel_init-$(CONFIG_SOC_AT91SAM9261) += at91sam9261_lowlevel_init.o +lowlevel_init-$(CONFIG_SOC_AT91SAM9263) += at91sam9263_lowlevel_init.o lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y) @@ -22,3 +27,4 @@ obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o +obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 4109172a5f..82862d7c3b 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -25,6 +25,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91rm9200_get_sdram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -37,9 +40,18 @@ void at91_add_device_sdram(u32 size) #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { + int i; + if (!data) return; + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91RM9200_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } @@ -91,7 +103,7 @@ void __init at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index a893a9581a..6e8c37b141 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -42,9 +42,18 @@ void at91_add_device_sdram(u32 size) #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { + int i; + if (!data) return; + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9260_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } @@ -89,7 +98,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ diff --git a/arch/arm/mach-at91/at91sam9260_lowlevel_init.c b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c new file mode 100644 index 0000000000..c2cf8bfcb5 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9260_lowlevel_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#define __LOWLEVEL_INIT__ + +#include <common.h> +#include <asm/system.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/at91_pio.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91_lowlevel_init.h> +#include <mach/io.h> +#include <init.h> +#include <sizes.h> + +void __naked __bare_init reset(void) +{ + common_reset(); + + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + + at91sam926x_lowlevel_init(IOMEM(AT91SAM9260_BASE_PIOC), false, + AT91_MATRIX_EBICSA); +} diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index becd25f376..e9ca51c820 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -45,9 +45,18 @@ void at91_add_device_sdram(u32 size) #if defined(CONFIG_USB_OHCI) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) { + int i; + if (!data) return; + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9261_UHP_BASE, 1024 * 1024, IORESOURCE_MEM, data); } @@ -199,6 +208,59 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + data->have_intensity_bit = true; + +#if defined(CONFIG_FB_ATMEL_STN) + at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ +#else + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ +#endif + + add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9261_LCDC_BASE, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + resource_size_t __init at91_configure_dbgu(void) { at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ diff --git a/arch/arm/mach-at91/at91sam9261_lowlevel_init.c b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c new file mode 100644 index 0000000000..a2e065fe73 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9261_lowlevel_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#define __LOWLEVEL_INIT__ + +#include <common.h> +#include <asm/system.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/at91_pio.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91_lowlevel_init.h> +#include <mach/io.h> +#include <init.h> +#include <sizes.h> + +void __naked __bare_init reset(void) +{ + common_reset(); + + arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16); + + at91sam926x_lowlevel_init(IOMEM(AT91SAM9261_BASE_PIOC), false, + AT91_MATRIX_EBICSA); +} diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index eeea1cea20..49d280dd07 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -175,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91rm9200-gpio3", &pioCDE_clk), CLKDEV_DEV_ID("at91rm9200-gpio4", &pioCDE_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index b72cc5a84a..528a07b7ac 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -50,7 +50,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9263_UHP_BASE, @@ -96,7 +97,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ @@ -249,6 +250,48 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + data->have_intensity_bit = true; + + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ + + add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9263_LCDC_BASE, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + resource_size_t __init at91_configure_dbgu(void) { at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ diff --git a/arch/arm/mach-at91/at91sam9263_lowlevel_init.c b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c new file mode 100644 index 0000000000..5260658547 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9263_lowlevel_init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#define __LOWLEVEL_INIT__ + +#include <common.h> +#include <asm/system.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/at91_pio.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_smc.h> +#include <mach/at91_lowlevel_init.h> +#include <mach/io.h> +#include <init.h> +#include <sizes.h> + +void __naked __bare_init reset(void) +{ + common_reset(); + + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16); + + at91sam926x_lowlevel_init(IOMEM(AT91SAM9263_BASE_PIOD), true, + AT91_MATRIX_EBI0CSA); +} diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c index cfae9824d3..8b9b33e2ef 100644 --- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c +++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c @@ -19,8 +19,10 @@ #include <mach/at91sam9_matrix.h> #include <mach/at91sam9_sdramc.h> #include <mach/at91sam9_smc.h> +#include <mach/at91_lowlevel_init.h> #include <mach/io.h> #include <init.h> +#include <sizes.h> static void inline access_sdram(void) { @@ -36,51 +38,54 @@ static void inline pmc_check_mckrdy(void) } while (!(r & AT91_PMC_MCKRDY)); } -void __naked __bare_init reset(void) +static int inline running_in_sram(void) +{ + u32 addr = get_pc(); + + addr >>= 28; + return addr == 0; +} + +void __bare_init at91sam926x_lowlevel_init(void *pio, bool is_pio_asr, + u32 matrix_csa) { u32 r; int i; + int in_sram = running_in_sram(); + struct at91sam926x_lowlevel_cfg cfg; - common_reset(); + at91sam926x_lowlevel_board_config(&cfg); - __raw_writel(CONFIG_SYS_WDTC_WDMR_VAL, AT91_BASE_WDT + AT91_WDT_MR); + __raw_writel(cfg.wdt_mr, AT91_BASE_WDT + AT91_WDT_MR); /* configure PIOx as EBI0 D[16-31] */ -#ifdef CONFIG_ARCH_AT91SAM9263 - __raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR); - __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR); - __raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR); -#else - __raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR); - __raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR); -#endif + __raw_writel(cfg.ebi_pio_pdr, pio + PIO_PDR); + __raw_writel(cfg.ebi_pio_ppudr, pio + PIO_PUDR); + if (is_pio_asr) + __raw_writel(cfg.ebi_pio_ppudr, pio + PIO_ASR); -#if defined(AT91_MATRIX_EBI0CSA) - at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL); -#else /* AT91_MATRIX_EBICSA */ - at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL); -#endif + at91_sys_write(matrix_csa, cfg.ebi_csa); /* flash */ - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_MODE, CONFIG_SYS_SMC_MODE_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_MODE, cfg.smc_mode); - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_CYCLE, CONFIG_SYS_SMC_CYCLE_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_CYCLE, cfg.smc_cycle); - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_PULSE, CONFIG_SYS_SMC_PULSE_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_PULSE, cfg.smc_pulse); - at91_smc_write(CONFIG_SYS_SMC_CS, AT91_SMC_SETUP, CONFIG_SYS_SMC_SETUP_VAL); + at91_smc_write(cfg.smc_cs, AT91_SMC_SETUP, cfg.smc_setup); /* * PMC Check if the PLL is already initialized */ r = at91_pmc_read(AT91_PMC_MCKR); - if (r & AT91_PMC_CSS) + if (r & AT91_PMC_CSS && !in_sram) goto end; /* * Enable the Main Oscillator */ - at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL); + at91_pmc_write(AT91_CKGR_MOR, cfg.pmc_mor); do { r = at91_pmc_read(AT91_PMC_SR); @@ -89,7 +94,7 @@ void __naked __bare_init reset(void) /* * PLLAR: x MHz for PCK */ - at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL); + at91_pmc_write(AT91_CKGR_PLLAR, cfg.pmc_pllar); do { r = at91_pmc_read(AT91_PMC_SR); @@ -98,14 +103,14 @@ void __naked __bare_init reset(void) /* * PCK/x = MCK Master Clock from SLOW */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL); + at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr1); pmc_check_mckrdy(); /* * PCK/x = MCK Master Clock from PLLA */ - at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL); + at91_pmc_write(AT91_PMC_MCKR, cfg.pmc_mckr2); pmc_check_mckrdy(); @@ -117,20 +122,20 @@ void __naked __bare_init reset(void) * SDRAMC Check if Refresh Timer Counter is already initialized */ r = at91_sys_read(AT91_SDRAMC_TR); - if (r) + if (r && !in_sram) goto end; /* SDRAMC_MR : Normal Mode */ at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); /* SDRAMC_TR - Refresh Timer register */ - at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1); + at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr1); /* SDRAMC_CR - Configuration register*/ - at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL); + at91_sys_write(AT91_SDRAMC_CR, cfg.sdrc_cr); /* Memory Device Type */ - at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL); + at91_sys_write(AT91_SDRAMC_MDR, cfg.sdrc_mdr); /* SDRAMC_MR : Precharge All */ at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE); @@ -158,18 +163,25 @@ void __naked __bare_init reset(void) access_sdram(); /* SDRAMC_TR : Refresh Timer Counter */ - at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2); + at91_sys_write(AT91_SDRAMC_TR, cfg.sdrc_tr2); /* access SDRAM */ access_sdram(); /* User reset enable*/ - at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL); + at91_sys_write(AT91_RSTC_MR, cfg.rstc_rmr); #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF); #endif + /* + * When boot from external boot + * we need to enable mck and ohter clock + * so enable all of them + * We will shutdown what we don't need later + */ + at91_pmc_write(AT91_PMC_PCER, 0xffffffff); end: board_init_lowlevel_return(); diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 7118efe9a4..deb9b62954 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -187,6 +187,7 @@ static struct clk *periph_clocks[] __initdata = { static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), + CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), @@ -197,6 +198,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk), CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index d2746da9df..bde3429edd 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -15,6 +15,7 @@ #include <asm/hardware.h> #include <mach/at91_pmc.h> #include <mach/at91sam9g45_matrix.h> +#include <mach/at91sam9_ddrsdr.h> #include <mach/board.h> #include <mach/gpio.h> #include <mach/io.h> @@ -24,6 +25,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91sam9g45_get_ddram_size(1); + arm_add_mem_device("ram0", AT91_CHIPSELECT_6, size); add_mem_device("sram0", AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -44,7 +48,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9G45_OHCI_BASE, @@ -54,6 +59,28 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #endif +#if defined(CONFIG_USB_EHCI) +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) +{ + int i; + + if (!data) + return; + + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + + add_generic_device("atmel-ehci", DEVICE_ID_SINGLE, NULL, AT91SAM9G45_EHCI_BASE, + 1024 * 1024, IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {} +#endif + #if defined(CONFIG_DRIVER_NET_MACB) void at91_add_device_eth(int id, struct at91_ether_platform_data *data) { @@ -72,7 +99,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ @@ -374,3 +401,52 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) #else void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ + + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ + + add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9G45_LCDC_BASE, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index c177975f33..e5aabd11e1 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -156,6 +156,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk), CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c index 3f41f3e3b5..aeac2aab77 100644 --- a/arch/arm/mach-at91/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/at91sam9n12_devices.c @@ -17,6 +17,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9n12_matrix.h> +#include <mach/at91sam9_ddrsdr.h> #include <mach/gpio.h> #include <mach/io.h> #include <mach/cpu.h> @@ -26,6 +27,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91sam9n12_get_ddram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -46,7 +50,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9N12_OHCI_BASE, @@ -308,6 +313,56 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif /* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDPWM */ + + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PC28, 0); /* LCDHSYNC */ + + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDDISP */ + at91_set_A_periph(AT91_PIN_PC29, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* LCDPCK */ + + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC4, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC20, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PC21, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD23 */ + + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9N12_BASE_LCDC, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + +/* -------------------------------------------------------------------- * UART * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 5d43423eb3..01eac18883 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -206,6 +206,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("macb_clk", "macb0", &macb0_clk), CLKDEV_CON_DEV_ID("macb_clk", "macb1", &macb1_clk), CLKDEV_CON_ID("ohci_clk", &uhphs_clk), + CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), @@ -215,6 +216,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioCD_clk), CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioCD_clk), CLKDEV_DEV_ID("at91-pit", &mck), + CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c index e92fa0de21..9f211e3bdd 100644 --- a/arch/arm/mach-at91/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/at91sam9x5_devices.c @@ -16,6 +16,7 @@ #include <mach/board.h> #include <mach/at91_pmc.h> #include <mach/at91sam9x5_matrix.h> +#include <mach/at91sam9_ddrsdr.h> #include <mach/gpio.h> #include <mach/io.h> #include <mach/cpu.h> @@ -25,6 +26,9 @@ void at91_add_device_sdram(u32 size) { + if (!size) + size = at91sam9x5_get_ddram_size(); + arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size); add_mem_device("sram0", AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); @@ -45,7 +49,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) /* Enable VBus control for UHP ports */ for (i = 0; i < data->ports; i++) { if (gpio_is_valid(data->vbus_pin[i])) - at91_set_gpio_output(data->vbus_pin[i], 0); + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); } add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9X5_OHCI_BASE, @@ -55,6 +60,28 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} #endif +#if defined(CONFIG_USB_EHCI) +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) +{ + int i; + + if (!data) + return; + + /* Enable VBus control for UHP ports */ + for (i = 0; i < data->ports; i++) { + if (gpio_is_valid(data->vbus_pin[i])) + at91_set_gpio_output(data->vbus_pin[i], + data->vbus_pin_active_low[i]); + } + + add_generic_device("atmel-ehci", DEVICE_ID_SINGLE, NULL, AT91SAM9X5_EHCI_BASE, + 1024 * 1024, IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {} +#endif + #if defined(CONFIG_DRIVER_NET_MACB) void at91_add_device_eth(int id, struct at91_ether_platform_data *data) { @@ -84,7 +111,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) at91_set_A_periph(AT91_PIN_PB5, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PB6, 0); /* EMDC */ - if (!data->is_rmii) { + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { at91_set_A_periph(AT91_PIN_PB16, 0); /* ECRS */ at91_set_A_periph(AT91_PIN_PB17, 0); /* ECOL */ at91_set_A_periph(AT91_PIN_PB13, 0); /* ERX2 */ @@ -97,7 +124,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) break; case 1: start = AT91SAM9X5_BASE_EMAC1; - if (!data->is_rmii) + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) pr_warn("AT91: Only RMII available on interface macb%d.\n", id); /* Pins used for RMII */ @@ -364,6 +391,61 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} #endif /* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + if (cpu_is_at91sam9g25() || cpu_is_at91sam9x25()) { + pr_warn("AT91: no lcd on at91sam9g25 or at91sam9x25\n"); + return; + } + + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDPWM */ + + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PC28, 0); /* LCDHSYNC */ + + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDDISP */ + at91_set_A_periph(AT91_PIN_PC29, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PC30, 0); /* LCDPCK */ + + at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PC4, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PC20, 0); /* LCDD20 */ + at91_set_A_periph(AT91_PIN_PC21, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD23 */ + + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9X5_BASE_LCDC, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + +/* -------------------------------------------------------------------- * UART * -------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/boot_test_cmd.c b/arch/arm/mach-at91/boot_test_cmd.c new file mode 100644 index 0000000000..aa5c020469 --- /dev/null +++ b/arch/arm/mach-at91/boot_test_cmd.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 only + */ + +#include <common.h> +#include <command.h> +#include <libbb.h> +#include <getopt.h> +#include <fs.h> +#include <fcntl.h> +#include <malloc.h> +#include <errno.h> + +static int do_at91_boot_test(int argc, char *argv[]) +{ + int opt; + u32 *buf32; + void *buf; + void (*jump)(void) = NULL; + int fd; + int ret = 1; + char *sram = "/dev/sram0"; + u32 read_size, write_size; + u32 tmp = 0; + + while ((opt = getopt(argc, argv, "j:s:")) > 0) { + switch (opt) { + case 'j': + jump = (void*)simple_strtoul(optarg, NULL, 0); + break; + case 's': + sram = optarg; + break; + default: + return COMMAND_ERROR_USAGE; + } + } + + if (argc < optind + 1) + return COMMAND_ERROR_USAGE; + + buf32 = buf = read_file(argv[optind], &read_size); + if (!buf) + return -EINVAL; + + write_size = buf32[5]; + + printf("size of the size %d\n", read_size); + printf("size to load in sram %d\n", write_size); + + if (write_size > read_size) { + printf("file smaller than requested sram loading size (%d < %d)\n", write_size, read_size); + goto err; + } + + fd = open(sram, O_WRONLY); + if (fd < 0) { + printf("could not open %s: %s\n", sram, errno_str()); + ret = fd; + goto err; + } + + while (write_size) { + tmp = write(fd, buf, write_size); + if (tmp < 0) { + perror("write"); + goto err_open; + } + buf += tmp; + write_size -= tmp; + } + + shutdown_barebox(); + + jump(); + +err_open: + close(fd); +err: + free(buf); + return ret; +} + +BAREBOX_CMD_HELP_START(at91_boot_test) +BAREBOX_CMD_HELP_USAGE("at91_boot_test [-j <jump addr>] [-s <sram>] file\n") +BAREBOX_CMD_HELP_SHORT("upload the binary to sram and jump as will do the romcode\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(at91_boot_test) + .cmd = do_at91_boot_test, + .usage = "upload the binary to sram and jump as will do the romcode", + BAREBOX_CMD_HELP(cmd_at91_boot_test_help) +BAREBOX_CMD_END diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c new file mode 100644 index 0000000000..4149304c92 --- /dev/null +++ b/arch/arm/mach-at91/bootstrap.c @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Under GPLv2 + */ + +#include <common.h> +#include <bootstrap.h> +#include <mach/bootstrap.h> +#include <sizes.h> +#include <malloc.h> +#include <init.h> +#include <menu.h> + +#if defined(CONFIG_MCI_ATMEL) +#define is_mmc() 1 +#else +#define is_mmc() 0 +#endif + +#ifdef CONFIG_NAND_ATMEL +#define is_nand() 1 +#else +#define is_nand() 0 +#endif + +#ifdef CONFIG_MTD_M25P80 +#define is_m25p80() 1 +#else +#define is_m25p80() 0 +#endif + +#ifdef CONFIG_MTD_DATAFLASH +#define is_dataflash() 1 +#else +#define is_dataflash() 0 +#endif + +#if defined(CONFIG_MENU) && !defined(CONFIG_NONE) +#define is_menu() 1 +#else +#define is_menu() 0 +#endif + +static char* is_barebox_to_str(bool is_barebox) +{ + return is_barebox ? "barebox" : "unknown"; +} + +static void at91bootstrap_boot_m25p80(bool is_barebox) +{ + char *name = is_barebox_to_str(is_barebox); + int (*func)(void) = NULL; + + func = bootstrap_board_read_m25p80(); + printf("Boot %s from m25p80\n", name); + bootstrap_boot(func, is_barebox); + bootstrap_err("... failed\n"); + free(func); +} + +static void at91bootstrap_boot_dataflash(bool is_barebox) +{ + char *name = is_barebox_to_str(is_barebox); + int (*func)(void) = NULL; + + printf("Boot %s from dataflash\n", name); + func = bootstrap_board_read_dataflash(); + bootstrap_boot(func, is_barebox); + bootstrap_err("... failed\n"); + free(func); +} + +static void at91bootstrap_boot_nand(bool is_barebox) +{ + char *name = is_barebox_to_str(is_barebox); + int (*func)(void) = NULL; + + printf("Boot %s from nand\n", name); + func = bootstrap_read_devfs("nand0", true, SZ_128K, SZ_256K, SZ_1M); + bootstrap_boot(func, is_barebox); + bootstrap_err("... failed\n"); + free(func); +} + +static void at91bootstrap_boot_mmc(void) +{ + int (*func)(void) = NULL; + + printf("Boot from mmc\n"); + func = bootstrap_read_disk("disk0.0", NULL); + bootstrap_boot(func, false); + bootstrap_err("... failed\n"); + free(func); +} + +static void boot_nand_barebox_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(true); + + getc(); +} + +static void boot_nand_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(false); + + getc(); +} + +static void boot_m25p80_barebox_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(true); + + getc(); +} + +static void boot_m25p80_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_nand(false); + + getc(); +} + +static void boot_dataflash_barebox_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_dataflash(true); + + getc(); +} + +static void boot_dataflash_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_dataflash(false); + + getc(); +} + +static void boot_mmc_disk_action(struct menu *m, struct menu_entry *me) +{ + at91bootstrap_boot_mmc(); + + getc(); +} + +static void boot_reset_action(struct menu *m, struct menu_entry *me) +{ + reset_cpu(0); +} + +void at91_bootstrap_menu(void) +{ + struct menu *m; + struct menu_entry *me; + + m = menu_alloc(); + m->display = m->name = "boot"; + + menu_add(m); + + if (is_mmc()) { + me = menu_entry_alloc(); + me->action = boot_mmc_disk_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "mmc"; + menu_add_entry(m, me); + } + + if (is_m25p80()) { + me = menu_entry_alloc(); + me->action = boot_m25p80_barebox_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "m25p80 (barebox)"; + menu_add_entry(m, me); + + me = menu_entry_alloc(); + me->action = boot_m25p80_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "m25p80"; + menu_add_entry(m, me); + } + + if (is_dataflash()) { + me = menu_entry_alloc(); + me->action = boot_dataflash_barebox_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "dataflash (barebox)"; + menu_add_entry(m, me); + + me = menu_entry_alloc(); + me->action = boot_dataflash_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "dataflash"; + menu_add_entry(m, me); + } + + if (is_nand()) { + me = menu_entry_alloc(); + me->action = boot_nand_barebox_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "nand (barebox)"; + menu_add_entry(m, me); + + me = menu_entry_alloc(); + me->action = boot_nand_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "nand"; + menu_add_entry(m, me); + } + + me = menu_entry_alloc(); + me->action = boot_reset_action; + me->type = MENU_ENTRY_NORMAL; + me->display = "reset"; + menu_add_entry(m, me); + + menu_show(m); +} + +static void boot_seq(bool is_barebox) +{ + if (is_m25p80()) + at91bootstrap_boot_m25p80(is_barebox); + + if (is_dataflash()) + at91bootstrap_boot_dataflash(is_barebox); + + if (is_nand()) + at91bootstrap_boot_nand(is_barebox); +} + +static int at91_bootstrap(void) +{ + if (is_menu()) { + printf("press 'm' to start the menu\n"); + if (tstc() && getc() == 'm') + at91_bootstrap_menu(); + } + + if (is_mmc()) + at91bootstrap_boot_mmc(); + + /* First only bootstrap_boot a barebox */ + boot_seq(true); + /* Second bootstrap_boot any */ + boot_seq(false); + + bootstrap_err("bootstrap_booting failed\n"); + while (1); + + return 0; +} + +static int at91_set_bootstrap(void) +{ + barebox_main = at91_bootstrap; + + return 0; +} +late_initcall(at91_set_bootstrap); diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index b231ec0789..2dde6325a7 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -11,6 +11,8 @@ */ #include <common.h> +#include <command.h> +#include <complete.h> #include <linux/list.h> #include <errno.h> #include <linux/err.h> @@ -42,7 +44,10 @@ */ #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3()) + +#define cpu_has_1056M_plla() (cpu_is_sama5d3()) #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ || cpu_is_at91sam9g45() \ @@ -63,7 +68,8 @@ || cpu_is_at91sam9n12())) #define cpu_has_upll() (cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3()) /* USB host HS & FS */ #define cpu_has_uhp() (!cpu_is_at91sam9rl()) @@ -71,18 +77,22 @@ /* USB device FS only */ #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5())) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3())) #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) static LIST_HEAD(clocks); @@ -204,10 +214,26 @@ struct clk mck = { static void pmc_periph_mode(struct clk *clk, int is_on) { - if (is_on) - at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); - else - at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); + u32 regval = 0; + + /* + * With sama5d3 chips, you have more than 32 peripherals so only one + * register is not enough to manage their clocks. A peripheral + * control register has been introduced to solve this issue. + */ + if (cpu_is_sama5d3()) { + regval |= AT91_PMC_PCR_CMD; /* write command */ + regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ + regval |= AT91_PMC_PCR_DIV(clk->div); + if (is_on) + regval |= AT91_PMC_PCR_EN; /* enable clock */ + at91_pmc_write(AT91_PMC_PCR, regval); + } else { + if (is_on) + at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); + else + at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); + } } static struct clk *at91_css_to_clk(unsigned long css) @@ -429,6 +455,8 @@ int clk_register(struct clk *clk) if (clk_is_peripheral(clk)) { if (!clk->parent) clk->parent = &mck; + if (cpu_is_sama5d3()) + clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, 1 << clk->div); clk->mode = pmc_periph_mode; } else if (clk_is_sys(clk)) { @@ -454,7 +482,10 @@ static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg) unsigned mul, div; div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; + if (cpu_is_sama5d3()) + mul = (reg >> 18) & 0x7ff; + else + mul = (reg >> 16) & 0x7ff; if (div && mul) { freq /= div; freq *= mul + 1; @@ -609,12 +640,18 @@ int at91_clock_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); - if (cpu_has_300M_plla()) { + if (cpu_has_1056M_plla()) { + if (plla.rate_hz > 1056000000) + pll_overclock = 1; + } else if (cpu_has_300M_plla()) { if (plla.rate_hz > 300000000) pll_overclock = 1; } else if (cpu_has_800M_plla()) { if (plla.rate_hz > 800000000) pll_overclock = 1; + } else if (cpu_has_300M_plla()) { + if (plla.rate_hz > 300000000) + pll_overclock = 1; } else if (cpu_has_240M_plla()) { if (plla.rate_hz > 240000000) pll_overclock = 1; @@ -734,6 +771,7 @@ postconsole_initcall(at91_clock_display); static int at91_clock_reset(void) { unsigned long pcdr = 0; + unsigned long pcdr1 = 0; unsigned long scdr = 0; struct clk *clk; @@ -741,8 +779,17 @@ static int at91_clock_reset(void) if (clk->users > 0) continue; - if (clk->mode == pmc_periph_mode) - pcdr |= clk->pmc_mask; + if (clk->mode == pmc_periph_mode) { + if (cpu_is_sama5d3()) { + u32 pmc_mask = 1 << (clk->pid % 32); + + if (clk->pid > 31) + pcdr1 |= pmc_mask; + else + pcdr |= pmc_mask; + } else + pcdr |= clk->pmc_mask; + } if (clk->mode == pmc_sys_mode) scdr |= clk->pmc_mask; @@ -751,8 +798,91 @@ static int at91_clock_reset(void) } at91_pmc_write(AT91_PMC_PCDR, pcdr); + if (cpu_is_sama5d3()) + at91_pmc_write(AT91_PMC_PCDR1, pcdr1); at91_pmc_write(AT91_PMC_SCDR, scdr); return 0; } late_initcall(at91_clock_reset); + +#ifdef CONFIG_CMD_AT91CLK +static int do_at91clk(int argc, char *argv[]) +{ + u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr; + struct clk *clk; + + scsr = at91_pmc_read(AT91_PMC_SCSR); + pcsr = at91_pmc_read(AT91_PMC_PCSR); + if (cpu_is_sama5d3()) + pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); + sr = at91_pmc_read(AT91_PMC_SR); + printf("SCSR = %8x\n", scsr); + printf("PCSR = %8x\n", pcsr); + if (cpu_is_sama5d3()) + printf("PCSR1 = %8x\n", pcsr1); + printf("MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); + printf("MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); + printf("PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); + if (cpu_has_pllb()) + printf("PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR)); + if (cpu_has_utmi()) { + uckr = at91_pmc_read(AT91_CKGR_UCKR); + printf("UCKR = %8x\n", uckr); + } + printf("MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); + if (cpu_has_upll()) + printf("USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); + printf("SR = %8x\n", sr); + + printf("\n"); + + list_for_each_entry(clk, &clocks, node) { + char *state; + char *mode = ""; + + if (clk->mode == pmc_sys_mode) { + state = (scsr & clk->pmc_mask) ? "on" : "off"; + mode = "sys"; + } else if (clk->mode == pmc_periph_mode) { + if (cpu_is_sama5d3()) { + u32 pmc_mask = 1 << (clk->pid % 32); + + if (clk->pid > 31) + state = (pcsr1 & pmc_mask) ? "on" : "off"; + else + state = (pcsr & pmc_mask) ? "on" : "off"; + } else { + state = (pcsr & clk->pmc_mask) ? "on" : "off"; + } + mode = "periph"; + } else if (clk->mode == pmc_uckr_mode) { + state = (uckr & clk->pmc_mask) ? "on" : "off"; + mode = "uckr"; + } else if (clk->pmc_mask) { + state = (sr & clk->pmc_mask) ? "on" : "off"; + } else if (clk == &clk32k || clk == &main_clk) { + state = "on"; + } else { + state = ""; + } + + printf("%-10s %-7s users=%2d %-3s %10lu Hz %s\n", + clk->name, mode, clk->users, state, clk_get_rate(clk), + clk->parent ? clk->parent->name : ""); + } + return 0; +} + +BAREBOX_CMD_HELP_START(at91clk) +BAREBOX_CMD_HELP_USAGE("at91clk\n") +BAREBOX_CMD_HELP_SHORT("dump current clock configuration\n"); +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(at91clk) + .cmd = do_at91clk, + .usage = "dump current clock configuration", + BAREBOX_CMD_HELP(cmd_at91clk_help) + BAREBOX_CMD_COMPLETE(empty_complete) +BAREBOX_CMD_END +#endif diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h index cacc0b5469..8af8d963c8 100644 --- a/arch/arm/mach-at91/clock.h +++ b/arch/arm/mach-at91/clock.h @@ -20,7 +20,9 @@ struct clk { const char *name; /* unique clock name */ struct clk_lookup cl; unsigned long rate_hz; + unsigned div; /* parent clock divider */ struct clk *parent; + unsigned pid; /* peripheral ID */ u32 pmc_mask; void (*mode)(struct clk *, int); unsigned id:3; /* PCK0..4, or 32k/main/a/b */ diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h new file mode 100644 index 0000000000..8c53ce799b --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_init.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Under GPLv2 + */ + +#ifndef __AT91_LOWLEVEL_INIT_H__ +#define __AT91_LOWLEVEL_INIT_H__ + +struct at91sam926x_lowlevel_cfg { + u32 wdt_mr; + u32 ebi_pio_pdr; + u32 ebi_pio_ppudr; + u32 ebi_csa; + u32 smc_cs; + u32 smc_mode; + u32 smc_cycle; + u32 smc_pulse; + u32 smc_setup; + u32 pmc_mor; + u32 pmc_pllar; + u32 pmc_mckr1; + u32 pmc_mckr2; + u32 sdrc_cr; + u32 sdrc_tr1; + u32 sdrc_mdr; + u32 sdrc_tr2; + u32 rstc_rmr; +}; + +void at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg); +void at91sam926x_lowlevel_init(void *pio, bool is_pio_asr, u32 matrix_csa); + +#endif /* __AT91_LOWLEVEL_INIT_H__ */ diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 6fcbf40729..61078717c6 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -163,13 +163,19 @@ #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#define AT91_PMC_VER 0xfc /* PMC Module Version [AT91CAP9 only] */ -#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */ +#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ -#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ -#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) +#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor value */ +#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ +#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ +#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ +#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ +#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 */ +#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Disable Register 1 */ +#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Status Register 1 */ #endif diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h index d34e4ed893..fc44a61090 100644 --- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h @@ -157,4 +157,34 @@ #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ +#ifndef __ASSEMBLY__ +#include <mach/io.h> +static inline u32 at91rm9200_get_sdram_size(void) +{ + u32 cr, mr; + u32 size; + + cr = at91_sys_read(AT91_SDRAMC_CR); + mr = at91_sys_read(AT91_SDRAMC_MR); + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_SDRAMC_NC) + 8; + /* ROW */ + size += ((cr & AT91_SDRAMC_NR) >> 2) + 11; + /* BANK */ + size = ((cr & AT91_SDRAMC_NB) ? 4 : 2) << size; + /* bandwidth */ + if (!(mr & AT91_SDRAMC_DBW)) + size <<= 1; + + return size; +} +#endif + #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index 070f730618..88796a6a2c 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h @@ -50,6 +50,10 @@ #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ +#define AT91_DDRSDRC_NB (1 << 20) /* Number of +Banks [not SAM9G45] */ +#define AT91_SDRAMC_NB_4 (0 << 20) +#define AT91_SDRAMC_NB_8 (1 << 20) #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ @@ -131,4 +135,126 @@ #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ +#ifndef __ASSEMBLY__ +#include <mach/io.h> + +static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb) +{ + u32 cr; + u32 mdr; + u32 size; + bool is_sdram; + + cr = __raw_readl(base + AT91_DDRSDRC_CR); + mdr = __raw_readl(base + AT91_DDRSDRC_MDR); + + is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR; + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_DDRSDRC_NC) + 8; + if (!is_sdram) + size ++; + /* ROW */ + size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; + /* BANK */ + if (is_nb) + size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; + else + size = 4 << size; + + /* bandwidth */ + if (!(mdr & AT91_DDRSDRC_DBW)) + size <<= 1; + + return size; +} + +#ifdef CONFIG_SOC_AT91SAM9G45 +static inline u32 at91sam9g45_get_ddram_size(int bank) +{ + switch (bank) { + case 0: + return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false); + case 1: + return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false); + default: + return 0; + } +} +#else +static inline u32 at91sam9g45_get_ddram_size(int bank) +{ + return 0; +} +#endif + +#ifdef CONFIG_SOC_AT91SAM9X5 +static inline u32 at91sam9x5_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); +} +#else +static inline u32 at91sam9x5_get_ddram_size(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SOC_AT91SAM9N12 +static inline u32 at91sam9n12_get_ddram_size(void) +{ + return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); +} +#else +static inline u32 at91sam9n12_get_ddram_size(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_SOC_SAMA5 +static inline u32 at91sama5_get_ddram_size(void) +{ + u32 cr; + u32 mdr; + u32 size; + void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC); + + cr = __raw_readl(base + AT91_DDRSDRC_CR); + mdr = __raw_readl(base + AT91_DDRSDRC_MDR); + + /* Formula: + * size = bank << (col + row + 1); + * if (bandwidth == 32 bits) + * size <<= 1; + */ + size = 1; + /* COL */ + size += (cr & AT91_DDRSDRC_NC) + 9; + /* ROW */ + size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; + /* BANK */ + size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; + + /* bandwidth */ + if (!(mdr & AT91_DDRSDRC_DBW)) + size <<= 1; + + return size; +} +#else +static inline u32 at91sama5_get_ddram_size(void) +{ + return 0; +} +#endif + +#endif + #endif diff --git a/arch/arm/mach-at91/include/mach/atmel_hlcdc.h b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h new file mode 100644 index 0000000000..71ccb96264 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel_hlcdc.h @@ -0,0 +1,760 @@ +/* + * Header file for AT91 High end LCD Controller + * + * Data structure and register user interface + * + * Copyright (C) 2010 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PUROFFSETE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __MACH_ATMEL_HLCD_H__ +#define __MACH_ATMEL_HLCD_H__ + +/* Lcdc hardware registers */ +#define ATMEL_LCDC_LCDCFG0 0x0000 +#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) +#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) +#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) +#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) +#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) +#define LCDC_LCDCFG0_CGDISOVR2 (0x1 << 10) +#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) +#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) +#define LCDC_LCDCFG0_CGDISPP (0x1 << 13) +#define LCDC_LCDCFG0_CLKDIV_OFFSET 16 +#define LCDC_LCDCFG0_CLKDIV (0xff << LCDC_LCDCFG0_CLKDIV_OFFSET) + +#define ATMEL_LCDC_LCDCFG1 0x0004 +#define LCDC_LCDCFG1_HSPW_OFFSET 0 +#define LCDC_LCDCFG1_HSPW (0x3f << LCDC_LCDCFG1_HSPW_OFFSET) +#define LCDC_LCDCFG1_VSPW_OFFSET 16 +#define LCDC_LCDCFG1_VSPW (0x3f << LCDC_LCDCFG1_VSPW_OFFSET) + +#define ATMEL_LCDC_LCDCFG2 0x0008 +#define LCDC_LCDCFG2_VFPW_OFFSET 0 +#define LCDC_LCDCFG2_VFPW (0x3f << LCDC_LCDCFG2_VFPW_OFFSET) +#define LCDC_LCDCFG2_VBPW_OFFSET 16 +#define LCDC_LCDCFG2_VBPW (0x3f << LCDC_LCDCFG2_VBPW_OFFSET) + +#define ATMEL_LCDC_LCDCFG3 0x000C +#define LCDC_LCDCFG3_HFPW_OFFSET 0 +#define LCDC_LCDCFG3_HFPW (0xff << LCDC_LCDCFG3_HFPW_OFFSET) +#define LCDC2_LCDCFG3_HFPW (0x1ff << LCDC_LCDCFG3_HFPW_OFFSET) +#define LCDC_LCDCFG3_HBPW_OFFSET 16 +#define LCDC_LCDCFG3_HBPW (0xff << LCDC_LCDCFG3_HBPW_OFFSET) +#define LCDC2_LCDCFG3_HBPW (0x1ff << LCDC_LCDCFG3_HBPW_OFFSET) + +#define ATMEL_LCDC_LCDCFG4 0x0010 +#define LCDC_LCDCFG4_PPL_OFFSET 0 +#define LCDC_LCDCFG4_PPL (0x7ff << LCDC_LCDCFG4_PPL_OFFSET) +#define LCDC_LCDCFG4_RPF_OFFSET 16 +#define LCDC_LCDCFG4_RPF (0x7ff << LCDC_LCDCFG4_RPF_OFFSET) + +#define ATMEL_LCDC_LCDCFG5 0x0014 +#define LCDC_LCDCFG5_HSPOL (0x1 << 0) +#define LCDC_LCDCFG5_VSPOL (0x1 << 1) +#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) +#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) +#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) +#define LCDC_LCDCFG5_SERIAL (0x1 << 5) +#define LCDC_LCDCFG5_DITHER (0x1 << 6) +#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) +#define LCDC_LCDCFG5_MODE_OFFSET 8 +#define LCDC_LCDCFG5_MODE (0x3 << LCDC_LCDCFG5_MODE_OFFSET) +#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) +#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) +#define LCDC_LCDCFG5_PP (0x1 << 10) +#define LCDC_LCDCFG5_VSPSU (0x1 << 12) +#define LCDC_LCDCFG5_VSPHO (0x1 << 13) +#define LCDC_LCDCFG5_GUARDTIME_OFFSET 16 +#define LCDC_LCDCFG5_GUARDTIME (0x1f << LCDC_LCDCFG5_GUARDTIME_OFFSET) + +#define ATMEL_LCDC_LCDCFG6 0x0018 +#define LCDC_LCDCFG6_PWMPS_OFFSET 0 +#define LCDC_LCDCFG6_PWMPS (0x7 << LCDC_LCDCFG6_PWMPS_OFFSET) +#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) +#define LCDC_LCDCFG6_PWMCVAL_OFFSET 8 +#define LCDC_LCDCFG6_PWMCVAL (0xff << LCDC_LCDCFG6_PWMCVAL_OFFSET) + +#define ATMEL_LCDC_LCDEN 0x0020 +#define LCDC_LCDEN_CLKEN (0x1 << 0) +#define LCDC_LCDEN_SYNCEN (0x1 << 1) +#define LCDC_LCDEN_DISPEN (0x1 << 2) +#define LCDC_LCDEN_PWMEN (0x1 << 3) + +#define ATMEL_LCDC_LCDDIS 0x0024 +#define LCDC_LCDDIS_CLKDIS (0x1 << 0) +#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) +#define LCDC_LCDDIS_DISPDIS (0x1 << 2) +#define LCDC_LCDDIS_PWMDIS (0x1 << 3) +#define LCDC_LCDDIS_CLKRST (0x1 << 8) +#define LCDC_LCDDIS_SYNCRST (0x1 << 9) +#define LCDC_LCDDIS_DISPRST (0x1 << 10) +#define LCDC_LCDDIS_PWMRST (0x1 << 11) + +#define ATMEL_LCDC_LCDSR 0x0028 +#define LCDC_LCDSR_CLKSTS (0x1 << 0) +#define LCDC_LCDSR_LCDSTS (0x1 << 1) +#define LCDC_LCDSR_DISPSTS (0x1 << 2) +#define LCDC_LCDSR_PWMSTS (0x1 << 3) +#define LCDC_LCDSR_SIPSTS (0x1 << 4) + +#define ATMEL_LCDC_LCDIER 0x002C +#define LCDC_LCDIER_SOFIE (0x1 << 0) +#define LCDC_LCDIER_DISIE (0x1 << 1) +#define LCDC_LCDIER_DISPIE (0x1 << 2) +#define LCDC_LCDIER_FIFOERRIE (0x1 << 4) +#define LCDC_LCDIER_BASEIE (0x1 << 8) +#define LCDC_LCDIER_OVR1IE (0x1 << 9) +#define LCDC_LCDIER_OVR2IE (0x1 << 10) +#define LCDC_LCDIER_HEOIE (0x1 << 11) +#define LCDC_LCDIER_HCRIE (0x1 << 12) +#define LCDC_LCDIER_PPIE (0x1 << 13) + +#define ATMEL_LCDC_LCDIDR 0x0030 +#define LCDC_LCDIDR_SOFID (0x1 << 0) +#define LCDC_LCDIDR_DISID (0x1 << 1) +#define LCDC_LCDIDR_DISPID (0x1 << 2) +#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) +#define LCDC_LCDIDR_BASEID (0x1 << 8) +#define LCDC_LCDIDR_OVR1ID (0x1 << 9) +#define LCDC_LCDIDR_OVR2ID (0x1 << 10) +#define LCDC_LCDIDR_HEOID (0x1 << 11) +#define LCDC_LCDIDR_HCRID (0x1 << 12) +#define LCDC_LCDIDR_PPID (0x1 << 13) + +#define ATMEL_LCDC_LCDIMR 0x0034 +#define LCDC_LCDIMR_SOFIM (0x1 << 0) +#define LCDC_LCDIMR_DISIM (0x1 << 1) +#define LCDC_LCDIMR_DISPIM (0x1 << 2) +#define LCDC_LCDIMR_FIFOERRIM (0x1 << 4) +#define LCDC_LCDIMR_BASEIM (0x1 << 8) +#define LCDC_LCDIMR_OVR1IM (0x1 << 9) +#define LCDC_LCDIMR_OVR2IM (0x1 << 10) +#define LCDC_LCDIMR_HEOIM (0x1 << 11) +#define LCDC_LCDIMR_HCRIM (0x1 << 12) +#define LCDC_LCDIMR_PPIM (0x1 << 13) + +#define ATMEL_LCDC_LCDISR 0x0038 +#define LCDC_LCDISR_SOF (0x1 << 0) +#define LCDC_LCDISR_DIS (0x1 << 1) +#define LCDC_LCDISR_DISP (0x1 << 2) +#define LCDC_LCDISR_FIFOERR (0x1 << 4) +#define LCDC_LCDISR_BASE (0x1 << 8) +#define LCDC_LCDISR_OVR1 (0x1 << 9) +#define LCDC_LCDISR_OVR2 (0x1 << 10) +#define LCDC_LCDISR_HEO (0x1 << 11) +#define LCDC_LCDISR_HCR (0x1 << 12) +#define LCDC_LCDISR_PP (0x1 << 13) + +#define ATMEL_LCDC_BASECHER 0x0040 +#define LCDC_BASECHER_CHEN (0x1 << 0) +#define LCDC_BASECHER_UPDATEEN (0x1 << 1) +#define LCDC_BASECHER_A2QEN (0x1 << 2) + +#define ATMEL_LCDC_BASECHDR 0x0044 +#define LCDC_BASECHDR_CHDIS (0x1 << 0) +#define LCDC_BASECHDR_CHRST (0x1 << 8) + +#define ATMEL_LCDC_BASECHSR 0x0048 +#define LCDC_BASECHSR_CHSR (0x1 << 0) +#define LCDC_BASECHSR_UPDATESR (0x1 << 1) +#define LCDC_BASECHSR_A2QSR (0x1 << 2) + +#define ATMEL_LCDC_BASEIER 0x004C +#define LCDC_BASEIER_DMA (0x1 << 2) +#define LCDC_BASEIER_DSCR (0x1 << 3) +#define LCDC_BASEIER_ADD (0x1 << 4) +#define LCDC_BASEIER_DONE (0x1 << 5) +#define LCDC_BASEIER_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEIDR 0x0050 +#define LCDC_BASEIDR_DMA (0x1 << 2) +#define LCDC_BASEIDR_DSCR (0x1 << 3) +#define LCDC_BASEIDR_ADD (0x1 << 4) +#define LCDC_BASEIDR_DONE (0x1 << 5) +#define LCDC_BASEIDR_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEIMR 0x0054 +#define LCDC_BASEIMR_DMA (0x1 << 2) +#define LCDC_BASEIMR_DSCR (0x1 << 3) +#define LCDC_BASEIMR_ADD (0x1 << 4) +#define LCDC_BASEIMR_DONE (0x1 << 5) +#define LCDC_BASEIMR_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEISR 0x0058 +#define LCDC_BASEISR_DMA (0x1 << 2) +#define LCDC_BASEISR_DSCR (0x1 << 3) +#define LCDC_BASEISR_ADD (0x1 << 4) +#define LCDC_BASEISR_DONE (0x1 << 5) +#define LCDC_BASEISR_OVR (0x1 << 6) + +#define ATMEL_LCDC_BASEHEAD 0x005C + +#define ATMEL_LCDC_BASEADDR 0x0060 + +#define ATMEL_LCDC_BASECTRL 0x0064 +#define LCDC_BASECTRL_DFETCH (0x1 << 0) +#define LCDC_BASECTRL_LFETCH (0x1 << 1) +#define LCDC_BASECTRL_DMAIEN (0x1 << 2) +#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) +#define LCDC_BASECTRL_ADDIEN (0x1 << 4) +#define LCDC_BASECTRL_DONEIEN (0x1 << 5) + +#define ATMEL_LCDC_BASENEXT 0x0068 + +#define ATMEL_LCDC_BASECFG0 0x006C +#define LCDC_BASECFG0_SIF (0x1 << 0) +#define LCDC_BASECFG0_BLEN_OFFSET 4 +#define LCDC_BASECFG0_BLEN (0x3 << LCDC_BASECFG0_BLEN_OFFSET) +#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_BASECFG0_DLBO (0x1 << 8) + +#define ATMEL_LCDC_BASECFG1 0x0070 +#define LCDC_BASECFG1_CLUTEN (0x1 << 0) +#define LCDC_BASECFG1_RGBMODE_OFFSET 4 +#define LCDC_BASECFG1_RGBMODE (0xf << LCDC_BASECFG1_RGBMODE_OFFSET) +#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) +#define LCDC_BASECFG1_CLUTMODE_OFFSET 8 +#define LCDC_BASECFG1_CLUTMODE (0x3 << LCDC_BASECFG1_CLUTMODE_OFFSET) +#define LCDC_BASECFG1_CLUTMODE_1BPP (0x0 << 8) +#define LCDC_BASECFG1_CLUTMODE_2BPP (0x1 << 8) +#define LCDC_BASECFG1_CLUTMODE_4BPP (0x2 << 8) +#define LCDC_BASECFG1_CLUTMODE_8BPP (0x3 << 8) + +#define ATMEL_LCDC_BASECFG2 0x0074 + +#define ATMEL_LCDC_BASECFG3 0x0078 +#define LCDC_BASECFG3_BDEF_OFFSET 0 +#define LCDC_BASECFG3_BDEF (0xff << LCDC_BASECFG3_BDEF_OFFSET) +#define LCDC_BASECFG3_GDEF_OFFSET 8 +#define LCDC_BASECFG3_GDEF (0xff << LCDC_BASECFG3_GDEF_OFFSET) +#define LCDC_BASECFG3_RDEF_OFFSET 16 +#define LCDC_BASECFG3_RDEF (0xff << LCDC_BASECFG3_RDEF_OFFSET) + +#define ATMEL_LCDC_BASECFG4 0x007C +#define LCDC_BASECFG4_DMA (0x1 << 8) +#define LCDC_BASECFG4_REP (0x1 << 9) +#define LCDC_BASECFG4_DISCEN (0x1 << 11) + +#define ATMEL_LCDC_BASECFG5 0x0080 +#define LCDC_BASECFG5_DISCXPOS_OFFSET 0 +#define LCDC_BASECFG5_DISCXPOS (0x7ff << LCDC_BASECFG5_DISCXPOS_OFFSET) +#define LCDC_BASECFG5_DISCYPOS_OFFSET 16 +#define LCDC_BASECFG5_DISCYPOS (0x7ff << LCDC_BASECFG5_DISCYPOS_OFFSET) + +#define ATMEL_LCDC_BASECFG6 0x0084 +#define LCDC_BASECFG6_DISCXSIZE_OFFSET 0 +#define LCDC_BASECFG6_DISCXSIZE (0x7ff << LCDC_BASECFG6_DISCXSIZE_OFFSET) +#define LCDC_BASECFG6_DISCYSIZE_OFFSET 16 +#define LCDC_BASECFG6_DISCYSIZE (0x7ff << LCDC_BASECFG6_DISCYSIZE_OFFSET) + +#define ATMEL_LCDC_HEOCHER 0x0280 +#define ATMEL_LCDC2_HEOCHER 0x0340 +#define LCDC_HEOCHER_CHEN (0x1 << 0) +#define LCDC_HEOCHER_UPDATEEN (0x1 << 1) +#define LCDC_HEOCHER_A2QEN (0x1 << 2) + +#define ATMEL_LCDC_HEOCHDR 0x0284 +#define LCDC_HEOCHDR_CHDIS (0x1 << 0) +#define LCDC_HEOCHDR_CHRST (0x1 << 8) + +#define ATMEL_LCDC_HEOCHSR 0x0288 +#define LCDC_HEOCHSR_CHSR (0x1 << 0) +#define LCDC_HEOCHSR_UPDATESR (0x1 << 1) +#define LCDC_HEOCHSR_A2QSR (0x1 << 2) + +#define ATMEL_LCDC_HEOIER 0x028C +#define LCDC_HEOIER_DMA (0x1 << 2) +#define LCDC_HEOIER_DSCR (0x1 << 3) +#define LCDC_HEOIER_ADD (0x1 << 4) +#define LCDC_HEOIER_DONE (0x1 << 5) +#define LCDC_HEOIER_OVR (0x1 << 6) +#define LCDC_HEOIER_UDMA (0x1 << 10) +#define LCDC_HEOIER_UDSCR (0x1 << 11) +#define LCDC_HEOIER_UADD (0x1 << 12) +#define LCDC_HEOIER_UDONE (0x1 << 13) +#define LCDC_HEOIER_UOVR (0x1 << 14) +#define LCDC_HEOIER_VDMA (0x1 << 18) +#define LCDC_HEOIER_VDSCR (0x1 << 19) +#define LCDC_HEOIER_VADD (0x1 << 20) +#define LCDC_HEOIER_VDONE (0x1 << 21) +#define LCDC_HEOIER_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOIDR 0x0290 +#define LCDC_HEOIDR_DMA (0x1 << 2) +#define LCDC_HEOIDR_DSCR (0x1 << 3) +#define LCDC_HEOIDR_ADD (0x1 << 4) +#define LCDC_HEOIDR_DONE (0x1 << 5) +#define LCDC_HEOIDR_OVR (0x1 << 6) +#define LCDC_HEOIDR_UDMA (0x1 << 10) +#define LCDC_HEOIDR_UDSCR (0x1 << 11) +#define LCDC_HEOIDR_UADD (0x1 << 12) +#define LCDC_HEOIDR_UDONE (0x1 << 13) +#define LCDC_HEOIDR_UOVR (0x1 << 14) +#define LCDC_HEOIDR_VDMA (0x1 << 18) +#define LCDC_HEOIDR_VDSCR (0x1 << 19) +#define LCDC_HEOIDR_VADD (0x1 << 20) +#define LCDC_HEOIDR_VDONE (0x1 << 21) +#define LCDC_HEOIDR_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOIMR 0x0294 +#define LCDC_HEOIMR_DMA (0x1 << 2) +#define LCDC_HEOIMR_DSCR (0x1 << 3) +#define LCDC_HEOIMR_ADD (0x1 << 4) +#define LCDC_HEOIMR_DONE (0x1 << 5) +#define LCDC_HEOIMR_OVR (0x1 << 6) +#define LCDC_HEOIMR_UDMA (0x1 << 10) +#define LCDC_HEOIMR_UDSCR (0x1 << 11) +#define LCDC_HEOIMR_UADD (0x1 << 12) +#define LCDC_HEOIMR_UDONE (0x1 << 13) +#define LCDC_HEOIMR_UOVR (0x1 << 14) +#define LCDC_HEOIMR_VDMA (0x1 << 18) +#define LCDC_HEOIMR_VDSCR (0x1 << 19) +#define LCDC_HEOIMR_VADD (0x1 << 20) +#define LCDC_HEOIMR_VDONE (0x1 << 21) +#define LCDC_HEOIMR_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOISR 0x0298 +#define LCDC_HEOISR_DMA (0x1 << 2) +#define LCDC_HEOISR_DSCR (0x1 << 3) +#define LCDC_HEOISR_ADD (0x1 << 4) +#define LCDC_HEOISR_DONE (0x1 << 5) +#define LCDC_HEOISR_OVR (0x1 << 6) +#define LCDC_HEOISR_UDMA (0x1 << 10) +#define LCDC_HEOISR_UDSCR (0x1 << 11) +#define LCDC_HEOISR_UADD (0x1 << 12) +#define LCDC_HEOISR_UDONE (0x1 << 13) +#define LCDC_HEOISR_UOVR (0x1 << 14) +#define LCDC_HEOISR_VDMA (0x1 << 18) +#define LCDC_HEOISR_VDSCR (0x1 << 19) +#define LCDC_HEOISR_VADD (0x1 << 20) +#define LCDC_HEOISR_VDONE (0x1 << 21) +#define LCDC_HEOISR_VOVR (0x1 << 22) + +#define ATMEL_LCDC_HEOHEAD 0x029C + +#define ATMEL_LCDC_HEOADDR 0x02A0 + +#define ATMEL_LCDC_HEOCTRL 0x02A4 +#define LCDC_HEOCTRL_DFETCH (0x1 << 0) +#define LCDC_HEOCTRL_LFETCH (0x1 << 1) +#define LCDC_HEOCTRL_DMAIEN (0x1 << 2) +#define LCDC_HEOCTRL_DSCRIEN (0x1 << 3) +#define LCDC_HEOCTRL_ADDIEN (0x1 << 4) +#define LCDC_HEOCTRL_DONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HEONEXT 0x02A8 + +#define ATMEL_LCDC_HEOUHEAD 0x02AC + +#define ATMEL_LCDC_HEOUADDR 0x02B0 + +#define ATMEL_LCDC_HEOUCTRL 0x02B4 +#define LCDC_HEOUCTRL_UDFETCH (0x1 << 0) +#define LCDC_HEOUCTRL_UDMAIEN (0x1 << 2) +#define LCDC_HEOUCTRL_UDSCRIEN (0x1 << 3) +#define LCDC_HEOUCTRL_UADDIEN (0x1 << 4) +#define LCDC_HEOUCTRL_UDONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HEOUNEXT 0x02B8 + +#define ATMEL_LCDC_HEOVHEAD 0x02BC + +#define ATMEL_LCDC_HEOVADDR 0x02C0 + +#define ATMEL_LCDC_HEOVCTRL 0x02C4 +#define LCDC_HEOVCTRL_VDFETCH (0x1 << 0) +#define LCDC_HEOVCTRL_VDMAIEN (0x1 << 2) +#define LCDC_HEOVCTRL_VDSCRIEN (0x1 << 3) +#define LCDC_HEOVCTRL_VADDIEN (0x1 << 4) +#define LCDC_HEOVCTRL_VDONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HEOVNEXT 0x02C8 + +#define ATMEL_LCDC_HEOCFG0 0x02CC +#define LCDC_HEOCFG0_BLEN_OFFSET 4 +#define LCDC_HEOCFG0_BLEN (0x3 << LCDC_HEOCFG0_BLEN_OFFSET) +#define LCDC_HEOCFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_HEOCFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_HEOCFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_HEOCFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_HEOCFG0_BLENUV_OFFSET 6 +#define LCDC_HEOCFG0_BLENUV (0x3 << LCDC_HEOCFG0_BLENUV_OFFSET) +#define LCDC_HEOCFG0_BLENUV_AHB_SINGLE (0x0 << 6) +#define LCDC_HEOCFG0_BLENUV_AHB_INCR4 (0x1 << 6) +#define LCDC_HEOCFG0_BLENUV_AHB_INCR8 (0x2 << 6) +#define LCDC_HEOCFG0_BLENUV_AHB_INCR16 (0x3 << 6) +#define LCDC_HEOCFG0_DLBO (0x1 << 8) +#define LCDC_HEOCFG0_ROTDIS (0x1 << 12) +#define LCDC_HEOCFG0_LOCKDIS (0x1 << 13) + +#define ATMEL_LCDC_HEOCFG1 0x02D0 +#define LCDC_HEOCFG1_CLUTEN (0x1 << 0) +#define LCDC_HEOCFG1_YUVEN (0x1 << 1) +#define LCDC_HEOCFG1_RGBMODE_OFFSET 4 +#define LCDC_HEOCFG1_RGBMODE (0xf << LCDC_HEOCFG1_RGBMODE_OFFSET) +#define LCDC_HEOCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_HEOCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_HEOCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_HEOCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_HEOCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_HEOCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_HEOCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_HEOCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) +#define LCDC_HEOCFG1_CLUTMODE_OFFSET 8 +#define LCDC_HEOCFG1_CLUTMODE (0x3 << LCDC_HEOCFG1_CLUTMODE_OFFSET) +#define LCDC_HEOCFG1_CLUTMODE_1BPP (0x0 << 8) +#define LCDC_HEOCFG1_CLUTMODE_2BPP (0x1 << 8) +#define LCDC_HEOCFG1_CLUTMODE_4BPP (0x2 << 8) +#define LCDC_HEOCFG1_CLUTMODE_8BPP (0x3 << 8) +#define LCDC_HEOCFG1_YUVMODE_OFFSET 12 +#define LCDC_HEOCFG1_YUVMODE (0xf << LCDC_HEOCFG1_YUVMODE_OFFSET) +#define LCDC_HEOCFG1_YUVMODE_32BPP_AYCBCR (0x0 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE0 (0x1 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE1 (0x2 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE2 (0x3 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_MODE3 (0x4 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_SEMIPLANAR (0x5 << 12) +#define LCDC_HEOCFG1_YUVMODE_16BPP_YCBCR_PLANAR (0x6 << 12) +#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_SEMIPLANAR (0x7 << 12) +#define LCDC_HEOCFG1_YUVMODE_12BPP_YCBCR_PLANAR (0x8 << 12) +#define LCDC_HEOCFG1_YUV422ROT (0x1 << 16) +#define LCDC_HEOCFG1_YUV422SWP (0x1 << 17) + +#define ATMEL_LCDC_HEOCFG2 0x02D4 +#define LCDC_HEOCFG2_XOFFSET_OFFSET 0 +#define LCDC_HEOCFG2_XOFFSET (0x7ff << LCDC_HEOCFG2_XOFFSET_OFFSET) +#define LCDC_HEOCFG2_YOFFSET_OFFSET 16 +#define LCDC_HEOCFG2_YOFFSET (0x7ff << LCDC_HEOCFG2_YOFFSET_OFFSET) + +#define ATMEL_LCDC_HEOCFG3 0x02D8 +#define LCDC_HEOCFG3_XSIZE_OFFSET 0 +#define LCDC_HEOCFG3_XSIZE (0x7ff << LCDC_HEOCFG3_XSIZE_OFFSET) +#define LCDC_HEOCFG3_YSIZE_OFFSET 16 +#define LCDC_HEOCFG3_YSIZE (0x7ff << LCDC_HEOCFG3_YSIZE_OFFSET) + +#define ATMEL_LCDC_HEOCFG4 0x02DC +#define LCDC_HEOCFG4_XMEM_SIZE_OFFSET 0 +#define LCDC_HEOCFG4_XMEM_SIZE (0x7ff << LCDC_HEOCFG4_XMEM_SIZE_OFFSET) +#define LCDC_HEOCFG4_YMEM_SIZE_OFFSET 16 +#define LCDC_HEOCFG4_YMEM_SIZE (0x7ff << LCDC_HEOCFG4_YMEM_SIZE_OFFSET) + +#define ATMEL_LCDC_HEOCFG5 0x02E0 + +#define ATMEL_LCDC_HEOCFG6 0x02E4 + +#define ATMEL_LCDC_HEOCFG7 0x02E8 + +#define ATMEL_LCDC_HEOCFG8 0x02EC + +#define ATMEL_LCDC_HEOCFG9 0x02F0 +#define LCDC_HEOCFG9_BDEF_OFFSET 0 +#define LCDC_HEOCFG9_BDEF (0xff << LCDC_HEOCFG9_BDEF_OFFSET) +#define LCDC_HEOCFG9_GDEF_OFFSET 8 +#define LCDC_HEOCFG9_GDEF (0xff << LCDC_HEOCFG9_GDEF_OFFSET) +#define LCDC_HEOCFG9_RDEF_OFFSET 16 +#define LCDC_HEOCFG9_RDEF (0xff << LCDC_HEOCFG9_RDEF_OFFSET) + +#define ATMEL_LCDC_HEOCFG10 0x02F4 +#define LCDC_HEOCFG10_BKEY_OFFSET 0 +#define LCDC_HEOCFG10_BKEY (0xff << LCDC_HEOCFG10_BKEY_OFFSET) +#define LCDC_HEOCFG10_GKEY_OFFSET 8 +#define LCDC_HEOCFG10_GKEY (0xff << LCDC_HEOCFG10_GKEY_OFFSET) +#define LCDC_HEOCFG10_RKEY_OFFSET 16 +#define LCDC_HEOCFG10_RKEY (0xff << LCDC_HEOCFG10_RKEY_OFFSET) + +#define ATMEL_LCDC_HEOCFG11 0x02F8 +#define LCDC_HEOCFG11_BMASK_OFFSET 0 +#define LCDC_HEOCFG11_BMASK (0xff << LCDC_HEOCFG11_BMASK_OFFSET) +#define LCDC_HEOCFG11_GMASK_OFFSET 8 +#define LCDC_HEOCFG11_GMASK (0xff << LCDC_HEOCFG11_GMASK_OFFSET) +#define LCDC_HEOCFG11_RMASK_OFFSET 16 +#define LCDC_HEOCFG11_RMASK (0xff << LCDC_HEOCFG11_RMASK_OFFSET) + +#define ATMEL_LCDC_HEOCFG12 0x02FC +#define LCDC_HEOCFG12_CRKEY (0x1 << 0) +#define LCDC_HEOCFG12_INV (0x1 << 1) +#define LCDC_HEOCFG12_ITER2BL (0x1 << 2) +#define LCDC_HEOCFG12_ITER (0x1 << 3) +#define LCDC_HEOCFG12_REVALPHA (0x1 << 4) +#define LCDC_HEOCFG12_GAEN (0x1 << 5) +#define LCDC_HEOCFG12_LAEN (0x1 << 6) +#define LCDC_HEOCFG12_OVR (0x1 << 7) +#define LCDC_HEOCFG12_DMA (0x1 << 8) +#define LCDC_HEOCFG12_REP (0x1 << 9) +#define LCDC_HEOCFG12_DSTKEY (0x1 << 10) +#define LCDC_HEOCFG12_VIDPRI (0x1 << 12) +#define LCDC_HEOCFG12_GA_OFFSET 16 +#define LCDC_HEOCFG12_GA (0xff << LCDC_HEOCFG12_GA_OFFSET) + +#define ATMEL_LCDC_HEOCFG13 0x0300 +#define LCDC_HEOCFG13_XFACTOR_OFFSET 0 +#define LCDC_HEOCFG13_XFACTOR (0x1fff << LCDC_HEOCFG13_XFACTOR_OFFSET) +#define LCDC_HEOCFG13_YFACTOR_OFFSET 16 +#define LCDC_HEOCFG13_YFACTOR (0x1fff << LCDC_HEOCFG13_YFACTOR_OFFSET) +#define LCDC_HEOCFG13_SCALEN (0x1 << 31) + +#define ATMEL_LCDC_HEOCFG14 0x0304 +#define LCDC_HEOCFG14_CSCRY_OFFSET 0 +#define LCDC_HEOCFG14_CSCRY (0x3ff << LCDC_HEOCFG14_CSCRY_OFFSET) +#define LCDC_HEOCFG14_CSCRU_OFFSET 10 +#define LCDC_HEOCFG14_CSCRU (0x3ff << LCDC_HEOCFG14_CSCRU_OFFSET) +#define LCDC_HEOCFG14_CSCRV_OFFSET 20 +#define LCDC_HEOCFG14_CSCRV (0x3ff << LCDC_HEOCFG14_CSCRV_OFFSET) +#define LCDC_HEOCFG14_CSCYOFF (0x1 << 30) + +#define ATMEL_LCDC_HEOCFG15 0x0308 +#define LCDC_HEOCFG15_CSCGY_OFFSET 0 +#define LCDC_HEOCFG15_CSCGY (0x3ff << LCDC_HEOCFG15_CSCGY_OFFSET) +#define LCDC_HEOCFG15_CSCGU_OFFSET 10 +#define LCDC_HEOCFG15_CSCGU (0x3ff << LCDC_HEOCFG15_CSCGU_OFFSET) +#define LCDC_HEOCFG15_CSCGV_OFFSET 20 +#define LCDC_HEOCFG15_CSCGV (0x3ff << LCDC_HEOCFG15_CSCGV_OFFSET) +#define LCDC_HEOCFG15_CSCUOFF (0x1 << 30) + +#define ATMEL_LCDC_HEOCFG16 0x030C +#define LCDC_HEOCFG16_CSCBY_OFFSET 0 +#define LCDC_HEOCFG16_CSCBY (0x3ff << LCDC_HEOCFG16_CSCBY_OFFSET) +#define LCDC_HEOCFG16_CSCBU_OFFSET 10 +#define LCDC_HEOCFG16_CSCBU (0x3ff << LCDC_HEOCFG16_CSCBU_OFFSET) +#define LCDC_HEOCFG16_CSCBV_OFFSET 20 +#define LCDC_HEOCFG16_CSCBV (0x3ff << LCDC_HEOCFG16_CSCBV_OFFSET) +#define LCDC_HEOCFG16_CSCVOFF (0x1 << 30) + +#define ATMEL_LCDC_HCRCHER 0x0340 +#define LCDC_HCRCHER_CHEN (0x1 << 0) +#define LCDC_HCRCHER_UPDATEEN (0x1 << 1) +#define LCDC_HCRCHER_A2QEN (0x1 << 2) + +#define ATMEL_LCDC_HCRCHDR 0x0344 +#define LCDC_HCRCHDR_CHDIS (0x1 << 0) +#define LCDC_HCRCHDR_CHRST (0x1 << 8) + +#define ATMEL_LCDC_HCRCHSR 0x0348 +#define LCDC_HCRCHSR_CHSR (0x1 << 0) +#define LCDC_HCRCHSR_UPDATESR (0x1 << 1) +#define LCDC_HCRCHSR_A2QSR (0x1 << 2) + +#define ATMEL_LCDC_HCRIER 0x034C +#define LCDC_HCRIER_DMA (0x1 << 2) +#define LCDC_HCRIER_DSCR (0x1 << 3) +#define LCDC_HCRIER_ADD (0x1 << 4) +#define LCDC_HCRIER_DONE (0x1 << 5) +#define LCDC_HCRIER_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRIDR 0x0350 +#define LCDC_HCRIDR_DMA (0x1 << 2) +#define LCDC_HCRIDR_DSCR (0x1 << 3) +#define LCDC_HCRIDR_ADD (0x1 << 4) +#define LCDC_HCRIDR_DONE (0x1 << 5) +#define LCDC_HCRIDR_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRIMR 0x0354 +#define LCDC_HCRIMR_DMA (0x1 << 2) +#define LCDC_HCRIMR_DSCR (0x1 << 3) +#define LCDC_HCRIMR_ADD (0x1 << 4) +#define LCDC_HCRIMR_DONE (0x1 << 5) +#define LCDC_HCRIMR_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRISR 0x0358 +#define LCDC_HCRISR_DMA (0x1 << 2) +#define LCDC_HCRISR_DSCR (0x1 << 3) +#define LCDC_HCRISR_ADD (0x1 << 4) +#define LCDC_HCRISR_DONE (0x1 << 5) +#define LCDC_HCRISR_OVR (0x1 << 6) + +#define ATMEL_LCDC_HCRHEAD 0x035C + +#define ATMEL_LCDC_HCRADDR 0x0360 + +#define ATMEL_LCDC_HCRCTRL 0x0364 +#define LCDC_HCRCTRL_DFETCH (0x1 << 0) +#define LCDC_HCRCTRL_LFETCH (0x1 << 1) +#define LCDC_HCRCTRL_DMAIEN (0x1 << 2) +#define LCDC_HCRCTRL_DSCRIEN (0x1 << 3) +#define LCDC_HCRCTRL_ADDIEN (0x1 << 4) +#define LCDC_HCRCTRL_DONEIEN (0x1 << 5) + +#define ATMEL_LCDC_HCRNEXT 0x0368 + +#define ATMEL_LCDC_HCRCFG0 0x036C +#define LCDC_HCRCFG0_BLEN_OFFSET 4 +#define LCDC_HCRCFG0_BLEN (0x3 << LCDC_HCRCFG0_BLEN_OFFSET) +#define LCDC_HCRCFG0_BLEN_AHB_SINGLE (0x0 << 4) +#define LCDC_HCRCFG0_BLEN_AHB_INCR4 (0x1 << 4) +#define LCDC_HCRCFG0_BLEN_AHB_INCR8 (0x2 << 4) +#define LCDC_HCRCFG0_BLEN_AHB_INCR16 (0x3 << 4) +#define LCDC_HCRCFG0_DLBO (0x1 << 8) + +#define ATMEL_LCDC_HCRCFG1 0x0370 +#define LCDC_HCRCFG1_CLUTEN (0x1 << 0) +#define LCDC_HCRCFG1_RGBMODE_OFFSET 4 +#define LCDC_HCRCFG1_RGBMODE (0xf << LCDC_HCRCFG1_RGBMODE_OFFSET) +#define LCDC_HCRCFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) +#define LCDC_HCRCFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) +#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) +#define LCDC_HCRCFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) +#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) +#define LCDC_HCRCFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) +#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) +#define LCDC_HCRCFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) +#define LCDC_HCRCFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) +#define LCDC_HCRCFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) +#define LCDC_HCRCFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) +#define LCDC_HCRCFG1_CLUTMODE_OFFSET 8 +#define LCDC_HCRCFG1_CLUTMODE (0x3 << LCDC_HCRCFG1_CLUTMODE_OFFSET) +#define LCDC_HCRCFG1_CLUTMODE_1BPP (0x0 << 8) +#define LCDC_HCRCFG1_CLUTMODE_2BPP (0x1 << 8) +#define LCDC_HCRCFG1_CLUTMODE_4BPP (0x2 << 8) +#define LCDC_HCRCFG1_CLUTMODE_8BPP (0x3 << 8) + +#define ATMEL_LCDC_HCRCFG2 0x0374 +#define LCDC_HCRCFG2_XOFFSET_OFFSET 0 +#define LCDC_HCRCFG2_XOFFSET (0x7ff << LCDC_HCRCFG2_XOFFSET_OFFSET) +#define LCDC_HCRCFG2_YOFFSET_OFFSET 16 +#define LCDC_HCRCFG2_YOFFSET (0x7ff << LCDC_HCRCFG2_YOFFSET_OFFSET) + +#define ATMEL_LCDC_HCRCFG3 0x0378 +#define LCDC_HCRCFG3_XSIZE_OFFSET 0 +#define LCDC_HCRCFG3_XSIZE (0x7f << LCDC_HCRCFG3_XSIZE_OFFSET) +#define LCDC_HCRCFG3_YSIZE_OFFSET 16 +#define LCDC_HCRCFG3_YSIZE (0x7f << LCDC_HCRCFG3_YSIZE_OFFSET) + +#define ATMEL_LCDC_HCRCFG4 0x037C + +#define ATMEL_LCDC_HCRCFG6 0x0384 +#define LCDC_HCRCFG6_BDEF_OFFSET 0 +#define LCDC_HCRCFG6_BDEF (0xff << LCDC_HCRCFG6_BDEF_OFFSET) +#define LCDC_HCRCFG6_GDEF_OFFSET 8 +#define LCDC_HCRCFG6_GDEF (0xff << LCDC_HCRCFG6_GDEF_OFFSET) +#define LCDC_HCRCFG6_RDEF_OFFSET 16 +#define LCDC_HCRCFG6_RDEF (0xff << LCDC_HCRCFG6_RDEF_OFFSET) + +#define ATMEL_LCDC_HCRCFG7 0x0388 +#define LCDC_HCRCFG7_BKEY_OFFSET 0 +#define LCDC_HCRCFG7_BKEY (0xff << LCDC_HCRCFG7_BKEY_OFFSET) +#define LCDC_HCRCFG7_GKEY_OFFSET 8 +#define LCDC_HCRCFG7_GKEY (0xff << LCDC_HCRCFG7_GKEY_OFFSET) +#define LCDC_HCRCFG7_RKEY_OFFSET 16 +#define LCDC_HCRCFG7_RKEY (0xff << LCDC_HCRCFG7_RKEY_OFFSET) + +#define ATMEL_LCDC_HCRCFG8 0x038C +#define LCDC_HCRCFG8_BMASK_OFFSET 0 +#define LCDC_HCRCFG8_BMASK (0xff << LCDC_HCRCFG8_BMASK_OFFSET) +#define LCDC_HCRCFG8_GMASK_OFFSET 8 +#define LCDC_HCRCFG8_GMASK (0xff << LCDC_HCRCFG8_GMASK_OFFSET) +#define LCDC_HCRCFG8_RMASK_OFFSET 16 +#define LCDC_HCRCFG8_RMASK (0xff << LCDC_HCRCFG8_RMASK_OFFSET) + +#define ATMEL_LCDC_HCRCFG9 0x0390 +#define LCDC_HCRCFG9_CRKEY (0x1 << 0) +#define LCDC_HCRCFG9_INV (0x1 << 1) +#define LCDC_HCRCFG9_ITER2BL (0x1 << 2) +#define LCDC_HCRCFG9_ITER (0x1 << 3) +#define LCDC_HCRCFG9_REVALPHA (0x1 << 4) +#define LCDC_HCRCFG9_GAEN (0x1 << 5) +#define LCDC_HCRCFG9_LAEN (0x1 << 6) +#define LCDC_HCRCFG9_OVR (0x1 << 7) +#define LCDC_HCRCFG9_DMA (0x1 << 8) +#define LCDC_HCRCFG9_REP (0x1 << 9) +#define LCDC_HCRCFG9_DSTKEY (0x1 << 10) +#define LCDC_HCRCFG9_GA_OFFSET 16 +#define LCDC_HCRCFG9_GA_Msk (0xff << LCDC_HCRCFG9_GA_OFFSET) + +#define ATMEL_LCDC_BASECLUT 0x400 +#define ATMEL_LCDC2_BASECLUT 0x600 +#define LCDC_BASECLUT_BCLUT_OFFSET 0 +#define LCDC_BASECLUT_BCLUT (0xff << LCDC_BASECLUT_BCLUT_OFFSET) +#define LCDC_BASECLUT_GCLUT_OFFSET 8 +#define LCDC_BASECLUT_GCLUT (0xff << LCDC_BASECLUT_GCLUT_OFFSET) +#define LCDC_BASECLUT_RCLUT_OFFSET 16 +#define LCDC_BASECLUT_RCLUT (0xff << LCDC_BASECLUT_RCLUT_OFFSET) + +#define ATMEL_LCDC_OVR1CLUT 0x800 +#define ATMEL_LCDC2_OVR1CLUT 0xa00 +#define LCDC_OVR1CLUT_BCLUT_OFFSET 0 +#define LCDC_OVR1CLUT_BCLUT (0xff << LCDC_OVR1CLUT_BCLUT_OFFSET) +#define LCDC_OVR1CLUT_GCLUT_OFFSET 8 +#define LCDC_OVR1CLUT_GCLUT (0xff << LCDC_OVR1CLUT_GCLUT_OFFSET) +#define LCDC_OVR1CLUT_RCLUT_OFFSET 16 +#define LCDC_OVR1CLUT_RCLUT (0xff << LCDC_OVR1CLUT_RCLUT_OFFSET) +#define LCDC_OVR1CLUT_ACLUT_OFFSET 24 +#define LCDC_OVR1CLUT_ACLUT (0xff << LCDC_OVR1CLUT_ACLUT_OFFSET) + +#define ATMEL_LCDC_OVR2CLUT 0xe00 +#define LCDC_OVR2CLUT_BCLUT_OFFSET 0 +#define LCDC_OVR2CLUT_BCLUT (0xff << LCDC_OVR2CLUT_BCLUT_OFFSET) +#define LCDC_OVR2CLUT_GCLUT_OFFSET 8 +#define LCDC_OVR2CLUT_GCLUT (0xff << LCDC_OVR2CLUT_GCLUT_OFFSET) +#define LCDC_OVR2CLUT_RCLUT_OFFSET 16 +#define LCDC_OVR2CLUT_RCLUT (0xff << LCDC_OVR2CLUT_RCLUT_OFFSET) +#define LCDC_OVR2CLUT_ACLUT_OFFSET 24 +#define LCDC_OVR2CLUT_ACLUT (0xff << LCDC_OVR2CLUT_ACLUT_OFFSET) + +#define ATMEL_LCDC_HEOCLUT 0x1000 +#define ATMEL_LCDC2_HEOCLUT 0x1200 +#define LCDC_HEOCLUT_BCLUT_OFFSET 0 +#define LCDC_HEOCLUT_BCLUT (0xff << LCDC_HEOCLUT_BCLUT_OFFSET) +#define LCDC_HEOCLUT_GCLUT_OFFSET 8 +#define LCDC_HEOCLUT_GCLUT (0xff << LCDC_HEOCLUT_GCLUT_OFFSET) +#define LCDC_HEOCLUT_RCLUT_OFFSET 16 +#define LCDC_HEOCLUT_RCLUT (0xff << LCDC_HEOCLUT_RCLUT_OFFSET) +#define LCDC_HEOCLUT_ACLUT_OFFSET 24 +#define LCDC_HEOCLUT_ACLUT (0xff << LCDC_HEOCLUT_ACLUT_OFFSET) + +#define ATMEL_LCDC_HCRCLUT 0x1400 +#define ATMEL_LCDC2_HCRCLUT 0x1600 +#define LCDC_HCRCLUT_BCLUT_OFFSET 0 +#define LCDC_HCRCLUT_BCLUT (0xff << LCDC_HCRCLUT_BCLUT_OFFSET) +#define LCDC_HCRCLUT_GCLUT_OFFSET 8 +#define LCDC_HCRCLUT_GCLUT (0xff << LCDC_HCRCLUT_GCLUT_OFFSET) +#define LCDC_HCRCLUT_RCLUT_OFFSET 16 +#define LCDC_HCRCLUT_RCLUT (0xff << LCDC_HCRCLUT_RCLUT_OFFSET) +#define LCDC_HCRCLUT_ACLUT_OFFSET 24 +#define LCDC_HCRCLUT_ACLUT (0xff << LCDC_HCRCLUT_ACLUT_OFFSET) + +/* Base layer CLUT */ +#define ATMEL_HLCDC_LUT 0x0400 + + +#endif /* __MACH_ATMEL_HLCDC4_H__ */ diff --git a/arch/arm/mach-at91/include/mach/barebox-arm-head.h b/arch/arm/mach-at91/include/mach/barebox-arm-head.h index a9c8dd44a7..7d6a009e2f 100644 --- a/arch/arm/mach-at91/include/mach/barebox-arm-head.h +++ b/arch/arm/mach-at91/include/mach/barebox-arm-head.h @@ -1,7 +1,7 @@ #ifndef __MACH_ARM_HEAD_H #define __MACH_ARM_HEAD_H -#ifdef CONFIG_SHELL_NONE +#ifdef CONFIG_AT91_LOAD_BAREBOX_SRAM #define AT91_EXV6 ".word _barebox_image_size\n" #else #define AT91_EXV6 ".word _barebox_bare_init_size\n" diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 9a72474d7a..71267e11e6 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h @@ -24,13 +24,19 @@ #include <i2c/i2c.h> #include <spi/spi.h> #include <linux/mtd/mtd.h> +#include <fb.h> +#include <video/atmel_lcdc.h> +#include <mach/atmel_hlcdc.h> +#include <linux/phy.h> /* USB Host */ struct at91_usbh_data { u8 ports; /* number of ports on root hub */ int vbus_pin[2]; /* port power-control pin */ + u8 vbus_pin_active_low[2]; /* vbus polarity */ }; extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); +extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data); void atmel_nand_load_image(void *dest, int size, int pagesize, int blocksize); @@ -70,7 +76,7 @@ struct at91_ether_platform_data { unsigned int phy_flags; unsigned int flags; int phy_addr; - int is_rmii; + phy_interface_t phy_interface; int (*get_ethaddr)(struct eth_device*, unsigned char *adr); }; @@ -160,4 +166,6 @@ struct at91_spi_platform_data { }; void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata); + +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data); #endif diff --git a/arch/arm/mach-at91/include/mach/bootstrap.h b/arch/arm/mach-at91/include/mach/bootstrap.h new file mode 100644 index 0000000000..a3d19dd54a --- /dev/null +++ b/arch/arm/mach-at91/include/mach/bootstrap.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Under GPLv2 + */ + +#ifndef __MACH_BOOTSTRAP_H__ +#define __MACH_BOOTSTRAP_H__ + +#ifdef CONFIG_MTD_M25P80 +void * bootstrap_board_read_m25p80(void); +#else +static inline void * bootstrap_board_read_m25p80(void) +{ + return NULL; +} +#endif + +#ifdef CONFIG_MTD_DATAFLASH +void * bootstrap_board_read_dataflash(void); +#else +static inline void * bootstrap_board_read_dataflash(void) +{ + return NULL; +} +#endif + +#endif /* __MACH_BOOTSTRAP_H__ */ diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index b6504c19d5..7132489132 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -26,6 +26,7 @@ #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_AT91SAM9N12 0x819a07a0 +#define ARCH_ID_SAMA5D3 0x8A5C07C0 #define ARCH_ID_AT91SAM9XE128 0x329973a0 #define ARCH_ID_AT91SAM9XE256 0x329a93a0 @@ -47,6 +48,11 @@ #define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9X25 0x00000004 +#define ARCH_EXID_SAMA5D31 0x00444300 +#define ARCH_EXID_SAMA5D33 0x00414300 +#define ARCH_EXID_SAMA5D34 0x00414301 +#define ARCH_EXID_SAMA5D35 0x00584300 + #define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000 @@ -75,6 +81,9 @@ enum at91_soc_type { /* SAM9N12 */ AT91_SOC_SAM9N12, + /* SAMA5D3 */ + AT91_SOC_SAMA5D3, + /* Unknown type */ AT91_SOC_NONE }; @@ -93,6 +102,10 @@ enum at91_soc_subtype { AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, + /* SAMA5D3 */ + AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, + AT91_SOC_SAMA5D35, + /* Unknown subtype */ AT91_SOC_SUBTYPE_NONE }; @@ -187,6 +200,20 @@ static inline int at91_soc_is_detected(void) #define cpu_is_at91sam9n12() (0) #endif +#ifdef CONFIG_ARCH_SAMA5D3 +#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) +#define cpu_is_sama5d31() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D31) +#define cpu_is_sama5d33() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D33) +#define cpu_is_sama5d34() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D34) +#define cpu_is_sama5d35() (at91_soc_initdata.subtype == AT91_SOC_SAMA5D35) +#else +#define cpu_is_sama5d3() (0) +#define cpu_is_sama5d31() (0) +#define cpu_is_sama5d33() (0) +#define cpu_is_sama5d34() (0) +#define cpu_is_sama5d35() (0) +#endif + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index e283b9d9ad..8f004deb42 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -38,6 +38,8 @@ #include <mach/at91sam9n12.h> #elif defined(CONFIG_ARCH_AT91SAM9X5) #include <mach/at91sam9x5.h> +#elif defined(CONFIG_ARCH_SAMA5D3) +#include <mach/sama5d3.h> #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9.h> #elif defined(CONFIG_ARCH_AT91X40) @@ -56,6 +58,12 @@ #define AT91_CHIPSELECT_6 0x70000000 #define AT91_CHIPSELECT_7 0x80000000 +#define SAMA5_CHIPSELECT_0 0x10000000 +#define SAMA5_DDRCS 0x20000000 +#define SAMA5_CHIPSELECT_1 0x40000000 +#define SAMA5_CHIPSELECT_2 0x50000000 +#define SAMA5_CHIPSELECT_3 0x60000000 + /* SDRAM */ #ifdef CONFIG_DRAM_BASE #define AT91_SDRAM_BASE CONFIG_DRAM_BASE diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h new file mode 100644 index 0000000000..6884ff6a7e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -0,0 +1,152 @@ +/* + * Chip-specific header file for the SAMA5D3 family + * + * Copyright (C) 2009-2012 Atmel Corporation. + * + * Common definitions. + * Based on SAMA5D3 datasheet. + * + * Licensed under GPLv2 or later. + */ + +#ifndef SAMA5D3_H +#define SAMA5D3_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ +#define SAMA5D3_ID_PIT 3 /* Periodic Interval Timer Interrupt */ +#define SAMA5D3_ID_WDT 4 /* Watchdog timer Interrupt */ +#define SAMA5D3_ID_HSMC5 5 /* Static Memory Controller */ +#define SAMA5D3_ID_PIOA 6 /* Parallel I/O Controller A */ +#define SAMA5D3_ID_PIOB 7 /* Parallel I/O Controller B */ +#define SAMA5D3_ID_PIOC 8 /* Parallel I/O Controller C */ +#define SAMA5D3_ID_PIOD 9 /* Parallel I/O Controller D */ +#define SAMA5D3_ID_PIOE 10 /* Parallel I/O Controller E */ +#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ +#define SAMA5D3_ID_USART0 12 /* USART0 */ +#define SAMA5D3_ID_USART1 13 /* USART1 */ +#define SAMA5D3_ID_USART2 14 /* USART2 */ +#define SAMA5D3_ID_USART3 15 /* USART3 */ +#define SAMA5D3_ID_UART0 16 /* UART0 */ +#define SAMA5D3_ID_UART1 17 /* UART1 */ +#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ +#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ +#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ +#define SAMA5D3_ID_HSMCI0 21 /* High Speed Multimedia Card Interface 0 */ +#define SAMA5D3_ID_HSMCI1 22 /* High Speed Multimedia Card Interface 1 */ +#define SAMA5D3_ID_HSMCI2 23 /* High Speed Multimedia Card Interface 2 */ +#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ +#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ +#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 (ch. 0, 1, 2) */ +#define SAMA5D3_ID_TC1 27 /* Timer Counter 1 (ch. 3, 4, 5) */ +#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ +#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ +#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ +#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ +#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ +#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ +#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ +#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ +#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ +#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ +#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ +#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ +#define SAMA5D3_ID_CAN0 40 /* CAN controller 0 */ +#define SAMA5D3_ID_CAN1 41 /* CAN controller 1 */ +#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ +#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ +#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ +#define SAMA5D3_ID_TRNG 45 /* True Random Number Generator */ +#define SAMA5D3_ID_ARM 46 /* Performance Monitor Unit */ +#define SAMA5D3_ID_AIC 47 /* Advanced Interrupt Controller */ +#define SAMA5D3_ID_FUSE 48 /* Fuse Controller */ +#define SAMA5D3_ID_MPDDRC 49 /* MPDDR controller */ + +/* + * User Peripheral physical base addresses. + */ + +#define SAMA5D3_BASE_HSMCI0 0xf0000000 /* (MMCI) Base Address */ +#define SAMA5D3_BASE_SPI0 0xf0004000 +#define SAMA5D3_BASE_TC0 0xf0010000 /* (TC0) Base Address */ +#define SAMA5D3_BASE_TC1 0xf0010040 /* (TC1) Base Address */ +#define SAMA5D3_BASE_USART0 0xf001c000 +#define SAMA5D3_BASE_USART1 0xf0020000 +#define SAMA5D3_BASE_GMAC 0xf0028000 /* (GMAC) Base Address */ +#define SAMA5D3_BASE_LCDC 0xf0030000 /* (HLCDC5) Base Address */ +#define SAMA5D3_BASE_HSMCI1 0xf8000000 +#define SAMA5D3_BASE_HSMCI2 0xf8004000 +#define SAMA5D3_BASE_SPI1 0xf8008000 +#define SAMA5D3_BASE_EMAC 0xf802c000 /* (EMAC) Base Address */ +#define SAMA5D3_BASE_UDPHS 0xf8030000 +#define AT91_BASE_SYS 0xffffc000 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) // KO OAR_TEMP, NO GPBR, error while building in "drivers/rtc/rtc-at91sam9.c" +#define AT91_DDRSDRC0 (0xffffea00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS) + +#define SAMA5D3_BASE_PIOA 0xfffff200 +#define SAMA5D3_BASE_PIOB 0xfffff400 +#define SAMA5D3_BASE_PIOC 0xfffff600 +#define SAMA5D3_BASE_PIOD 0xfffff800 +#define SAMA5D3_BASE_PIOE 0xfffffa00 +#define SAMA5D3_BASE_MPDDRC 0xffffea00 +#define SAMA5D3_BASE_HSMC 0xffffc000 +#define SAMA5D3_BASE_PIT 0xfffffe30 +#define SAMA5D3_BASE_WDT 0xfffffe40 + +#define SAMA5D3_BASE_PMECC 0xffffc070 +#define SAMA5D3_BASE_PMERRLOC 0xffffc500 + +#define AT91_NB_USART 3 + +/* + * Internal Memory. + */ +#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ + +#define SAMA5D3_ROM_BASE 0x00100000 +#define SAMA5D3_ROM_SIZE SZ_1M + +#define SAMA5D3_UDPHS_FIFO 0x00500000 +#define SAMA5D3_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */ +#define SAMA5D3_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */ + +/* + * DMA0 peripheral identifiers + * for hardware handshaking interface + */ +#define SAMA5_DMA_ID_MCI0 0 +#define SAMA5_DMA_ID_SPI0_TX 1 +#define SAMA5_DMA_ID_SPI0_RX 2 +#define SAMA5_DMA_ID_USART0_TX 3 +#define SAMA5_DMA_ID_USART0_RX 4 +#define SAMA5_DMA_ID_USART1_TX 5 +#define SAMA5_DMA_ID_USART1_RX 6 +#define SAMA5_DMA_ID_TWI0_TX 7 +#define SAMA5_DMA_ID_TWI0_RX 8 +#define SAMA5_DMA_ID_TWI1_TX 9 +#define SAMA5_DMA_ID_TWI1_RX 10 +#define SAMA5_DMA_ID_UART0_TX 11 +#define SAMA5_DMA_ID_UART0_RX 12 +#define SAMA5_DMA_ID_SSC0_TX 13 +#define SAMA5_DMA_ID_SSC0_RX 14 +#define SAMA5_DMA_ID_SMD_TX 15 +#define SAMA5_DMA_ID_SMD_RX 16 + +/* + * DMA1 peripheral identifiers + * for hardware handshaking interface + */ +#define SAMA5_DMA_ID_MCI1 0 + +#endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3_matrix.h b/arch/arm/mach-at91/include/mach/sama5d3_matrix.h new file mode 100644 index 0000000000..8176b38bd3 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d3_matrix.h @@ -0,0 +1,15 @@ +/* + * Matrix-centric header file for the SAMA5D3 family + * + * Copyright (C) 2009-2012 Atmel Corporation. + * + * Only EBI related registers. + * Write Protect register definitions may be useful. + * + * Licensed under GPLv2 or later. + */ + +#ifndef SAMA5D3_MATRIX_H +#define SAMA5D3_MATRIX_H + +#endif diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c new file mode 100644 index 0000000000..0eec696f6e --- /dev/null +++ b/arch/arm/mach-at91/sama5d3.c @@ -0,0 +1,397 @@ +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <asm/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/io.h> +#include <mach/cpu.h> +#include <linux/clk.h> + +#include "soc.h" +#include "generic.h" +#include "clock.h" + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ + + +static struct clk pit_clk = { + .name = "pit_clk", + .pid = SAMA5D3_ID_PIT, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk smc_clk = { + .name = "smc_clk", + .pid = SAMA5D3_ID_HSMC5, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioA_clk = { + .name = "pioA_clk", + .pid = SAMA5D3_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pid = SAMA5D3_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pid = SAMA5D3_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioD_clk = { + .name = "pioD_clk", + .pid = SAMA5D3_ID_PIOD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioE_clk = { + .name = "pioE_clk", + .pid = SAMA5D3_ID_PIOE, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk smd_clk = { + .name = "smd_clk", + .pid = SAMA5D3_ID_SMD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pid = SAMA5D3_ID_USART0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pid = SAMA5D3_ID_USART1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pid = SAMA5D3_ID_USART2, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pid = SAMA5D3_ID_USART3, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk uart0_clk = { + .name = "uart0_clk", + .pid = SAMA5D3_ID_UART0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk uart1_clk = { + .name = "uart1_clk", + .pid = SAMA5D3_ID_UART1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk twi0_clk = { + .name = "twi0_clk", + .pid = SAMA5D3_ID_TWI0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk twi1_clk = { + .name = "twi1_clk", + .pid = SAMA5D3_ID_TWI1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk twi2_clk = { + .name = "twi2_clk", + .pid = SAMA5D3_ID_TWI2, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk mmc0_clk = { + .name = "mci0_clk", + .pid = SAMA5D3_ID_HSMCI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc1_clk = { + .name = "mci1_clk", + .pid = SAMA5D3_ID_HSMCI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc2_clk = { + .name = "mci2_clk", + .pid = SAMA5D3_ID_HSMCI2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pid = SAMA5D3_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pid = SAMA5D3_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tcb0_clk = { + .name = "tcb0_clk", + .pid = SAMA5D3_ID_TC0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk tcb1_clk = { + .name = "tcb1_clk", + .pid = SAMA5D3_ID_TC1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk pwm_clk = { + .name = "pwm_clk", + .pid = SAMA5D3_ID_PWM, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk adc_clk = { + .name = "adc_clk", + .pid = SAMA5D3_ID_ADC, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk dma0_clk = { + .name = "dma0_clk", + .pid = SAMA5D3_ID_DMA0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma1_clk = { + .name = "dma1_clk", + .pid = SAMA5D3_ID_DMA1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk uhphs_clk = { + .name = "uhphs", + .pid = SAMA5D3_ID_UHPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pid = SAMA5D3_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +/* gmac only for sama5d33, sama5d34, sama5d35 */ +static struct clk macb0_clk = { + .name = "macb0_clk", + .pid = SAMA5D3_ID_GMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +/* emac only for sama5d31, sama5d35 */ +static struct clk macb1_clk = { + .name = "macb1_clk", + .pid = SAMA5D3_ID_EMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +/* lcd only for sama5d31, sama5d33, sama5d34 */ +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pid = SAMA5D3_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; +/* isi only for sama5d33, sama5d35 */ +static struct clk isi_clk = { + .name = "isi_clk", + .pid = SAMA5D3_ID_ISI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pid = SAMA5D3_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pid = SAMA5D3_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk can0_clk = { + .name = "can0_clk", + .pid = SAMA5D3_ID_CAN0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk can1_clk = { + .name = "can1_clk", + .pid = SAMA5D3_ID_CAN1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk sha_clk = { + .name = "sha_clk", + .pid = SAMA5D3_ID_SHA, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV8, +}; +static struct clk aes_clk = { + .name = "aes_clk", + .pid = SAMA5D3_ID_AES, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tdes_clk = { + .name = "tdes_clk", + .pid = SAMA5D3_ID_TDES, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pit_clk, + &smc_clk, + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioD_clk, + &pioE_clk, + &smd_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &usart3_clk, + &uart0_clk, + &uart1_clk, + &twi0_clk, + &twi1_clk, + &twi2_clk, + &mmc0_clk, + &mmc1_clk, + &mmc2_clk, + &spi0_clk, + &spi1_clk, + &tcb0_clk, + &tcb1_clk, + &pwm_clk, + &adc_clk, + &dma0_clk, + &dma1_clk, + &uhphs_clk, + &udphs_clk, + &ssc0_clk, + &ssc1_clk, + &can0_clk, + &can1_clk, + &sha_clk, + &aes_clk, + &tdes_clk, +}; + +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; + +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; + +static struct clk_lookup periph_clocks_lookups[] = { + CLKDEV_CON_DEV_ID("macb_clk", "macb0", &macb0_clk), + CLKDEV_CON_DEV_ID("macb_clk", "macb1", &macb1_clk), + CLKDEV_CON_ID("ohci_clk", &uhphs_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), + CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), + CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), + CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), + CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci2", &mmc2_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio0", &pioA_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio1", &pioB_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio2", &pioC_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio3", &pioD_clk), + CLKDEV_DEV_ID("at91sam9x5-gpio4", &pioE_clk), + CLKDEV_DEV_ID("at91-pit", &pit_clk), + CLKDEV_CON_DEV_ID("hck1", "atmel_hlcdfb", &lcdc_clk), +}; + +static struct clk_lookup usart_clocks_lookups[] = { + CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck), + CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart2", &usart1_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk), + CLKDEV_CON_DEV_ID("usart", "atmel_usart4", &usart3_clk), +}; + +static void __init sama5d3_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clkdev_add_table(periph_clocks_lookups, + ARRAY_SIZE(periph_clocks_lookups)); + clkdev_add_table(usart_clocks_lookups, + ARRAY_SIZE(usart_clocks_lookups)); + + if ( cpu_is_sama5d33() + || cpu_is_sama5d34() + || cpu_is_sama5d35() ) + clk_register(&macb0_clk); + + if ( cpu_is_sama5d31() + || cpu_is_sama5d35() ) + clk_register(&macb1_clk); + + if (!cpu_is_sama5d35()) + clk_register(&lcdc_clk); + + clk_register(&isi_clk); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); + + /* ensure dma are enabled */ + //clk_enable(&dma0_clk); + //clk_enable(&dma1_clk); +} + +/* -------------------------------------------------------------------- + * AT91SAM9x5 processor initialization + * -------------------------------------------------------------------- */ + +static void sama5d3_initialize(void) +{ + /* Init clock subsystem */ + at91_clock_init(AT91_MAIN_CLOCK); + + /* Register the processor-specific clocks */ + sama5d3_register_clocks(); + + /* Register GPIO subsystem */ + at91_add_sam9x5_gpio(0, SAMA5D3_BASE_PIOA); + at91_add_sam9x5_gpio(1, SAMA5D3_BASE_PIOB); + at91_add_sam9x5_gpio(2, SAMA5D3_BASE_PIOC); + at91_add_sam9x5_gpio(3, SAMA5D3_BASE_PIOD); + at91_add_sam9x5_gpio(4, SAMA5D3_BASE_PIOE); + + at91_add_pit(SAMA5D3_BASE_PIT); + at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D3_BASE_HSMC + 0x600, 0xa0); +} + +AT91_SOC_START(sama5d3) + .init = sama5d3_initialize, +AT91_SOC_END diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c new file mode 100644 index 0000000000..3e4531e8a9 --- /dev/null +++ b/arch/arm/mach-at91/sama5d3_devices.c @@ -0,0 +1,497 @@ +/* + * On-Chip devices setup code for the AT91SAM9x5 family + * + * Copyright (C) 2010 Atmel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <common.h> +#include <init.h> +#include <sizes.h> +#include <asm/armlinux.h> +#include <asm/hardware.h> +#include <mach/board.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9x5_matrix.h> +#include <mach/at91sam9_ddrsdr.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/cpu.h> +#include <i2c/i2c-gpio.h> + +#include "generic.h" + +void at91_add_device_sdram(u32 size) +{ + if (!size) + size = at91sama5_get_ddram_size(); + + arm_add_mem_device("ram0", SAMA5_DDRCS, size); + add_mem_device("sram0", SAMA5D3_SRAM_BASE, + SAMA5D3_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE); +} + +/* -------------------------------------------------------------------- + * NAND / SmartMedia + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_NAND_ATMEL) +static struct resource nand_resources[] = { + [0] = { + .start = SAMA5_CHIPSELECT_3, + .end = SAMA5_CHIPSELECT_3 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SAMA5D3_BASE_PMECC, + .end = SAMA5D3_BASE_PMECC + 0x490 - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = SAMA5D3_BASE_PMERRLOC, + .end = SAMA5D3_BASE_PMERRLOC + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [3] = { + .start = SAMA5D3_ROM_BASE, + .end = SAMA5D3_ROM_BASE + SAMA5D3_ROM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +void __init at91_add_device_nand(struct atmel_nand_data *data) +{ + if (!data) + return; + + switch (data->pmecc_sector_size) { + case 512: + data->pmecc_lookup_table_offset = 0x10000; + break; + case 1024: + data->pmecc_lookup_table_offset = 0x18000; + break; + default: + pr_err("%s: invalid pmecc_sector_size (%d)\n", __func__, + data->pmecc_sector_size); + return; + } + + at91_set_A_periph(AT91_PIN_PE21, 1); /* ALE */ + at91_set_A_periph(AT91_PIN_PE22, 1); /* CLE */ + + /* enable pin */ + if (gpio_is_valid(data->enable_pin)) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (gpio_is_valid(data->rdy_pin)) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (gpio_is_valid(data->det_pin)) + at91_set_gpio_input(data->det_pin, 1); + + add_generic_device_res("atmel_nand", 0, nand_resources, + ARRAY_SIZE(nand_resources), data); +} +#else +void __init at91_add_device_nand(struct atmel_nand_data *data) {} +#endif + +#if defined(CONFIG_DRIVER_NET_MACB) +void at91_add_device_eth(int id, struct at91_ether_platform_data *data) +{ + if (!data) + return; + + switch (id) { + case 0: + if (cpu_is_sama5d31()) { + pr_warn("AT91: no gmac on sama5d31\n"); + return; + } + + at91_set_A_periph(AT91_PIN_PB16, 0); /* GMDC */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* GMDIO */ + + at91_set_A_periph(AT91_PIN_PB9, 0); /* GTXEN */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* GRXCK */ + at91_set_A_periph(AT91_PIN_PB13, 0); /* GRXER */ + + switch (data->phy_interface) { + case PHY_INTERFACE_MODE_GMII: + at91_set_B_periph(AT91_PIN_PB19, 0); /* GTX4 */ + at91_set_B_periph(AT91_PIN_PB20, 0); /* GTX5 */ + at91_set_B_periph(AT91_PIN_PB21, 0); /* GTX6 */ + at91_set_B_periph(AT91_PIN_PB22, 0); /* GTX7 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* GRX4 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* GRX5 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* GRX6 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* GRX7 */ + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + at91_set_A_periph(AT91_PIN_PB0, 0); /* GTX0 */ + at91_set_A_periph(AT91_PIN_PB1, 0); /* GTX1 */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* GTX2 */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* GTX3 */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* GRX0 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* GRX1 */ + at91_set_A_periph(AT91_PIN_PB6, 0); /* GRX2 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* GRX3 */ + break; + default: + return; + } + + switch (data->phy_interface) { + case PHY_INTERFACE_MODE_MII: + at91_set_A_periph(AT91_PIN_PB8, 0); /* GTXCK */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* GTXER */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* GRXDV */ + at91_set_A_periph(AT91_PIN_PB14, 0); /* GCRS */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* GCOL */ + break; + case PHY_INTERFACE_MODE_RGMII: + at91_set_A_periph(AT91_PIN_PB8, 0); /* GTXCK */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* G125CK */ + break; + case PHY_INTERFACE_MODE_GMII: + at91_set_A_periph(AT91_PIN_PB10, 0); /* GTXER */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* GRXDV */ + at91_set_A_periph(AT91_PIN_PB14, 0); /* GCRS */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* GCOL */ + at91_set_A_periph(AT91_PIN_PB27, 0); /* G125CK0 */ + break; + default: + return; + } + + add_generic_device("macb", id, NULL, SAMA5D3_BASE_GMAC, SZ_16K, + IORESOURCE_MEM, data); + break; + case 1: + if (cpu_is_sama5d33() || cpu_is_sama5d34()) { + pr_warn("AT91: no macb on sama5d33/d34\n"); + return; + } + + if (data->phy_interface != PHY_INTERFACE_MODE_RMII) { + pr_warn("AT91: Only RMII available on interfacr macb%d.\n", id); + return; + } + + at91_set_A_periph(AT91_PIN_PC7, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PC5, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PC2, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PC3, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PC6, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PC4, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PC0, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* EMDC */ + add_generic_device("macb", id, NULL, SAMA5D3_BASE_EMAC, SZ_16K, + IORESOURCE_MEM, data); + break; + default: + return; + } + +} +#else +void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {} +#endif + +#if defined(CONFIG_MCI_ATMEL) +/* Consider only one slot : slot 0 */ +void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) +{ + resource_size_t start = ~0; + + if (!data) + return; + + /* Must have at least one usable slot */ + if (!data->bus_width) + return; + + /* input/irq */ + if (gpio_is_valid(data->detect_pin)) { + at91_set_gpio_input(data->detect_pin, 1); + at91_set_deglitch(data->detect_pin, 1); + } + if (gpio_is_valid(data->wp_pin)) + at91_set_gpio_input(data->wp_pin, 1); + + switch (mmc_id) { + case 0: /* MCI0 */ + start = SAMA5D3_BASE_HSMCI0; + + /* CLK */ + at91_set_A_periph(AT91_PIN_PD9, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PD0, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PD1, 1); + switch (data->bus_width) { + case 8: + at91_set_A_periph(AT91_PIN_PD5, 1); + at91_set_A_periph(AT91_PIN_PD6, 1); + at91_set_A_periph(AT91_PIN_PD7, 1); + at91_set_A_periph(AT91_PIN_PD8, 1); + case 4: + at91_set_A_periph(AT91_PIN_PD2, 1); + at91_set_A_periph(AT91_PIN_PD3, 1); + at91_set_A_periph(AT91_PIN_PD4, 1); + }; + + break; + case 1: /* MCI1 */ + start = SAMA5D3_BASE_HSMCI1; + + /* CLK */ + at91_set_A_periph(AT91_PIN_PB24, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PB19, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PB20, 1); + if (data->bus_width == 4) { + at91_set_A_periph(AT91_PIN_PB21, 1); + at91_set_A_periph(AT91_PIN_PB22, 1); + at91_set_A_periph(AT91_PIN_PB23, 1); + } + break; + case 2: /* MCI2 */ + start = SAMA5D3_BASE_HSMCI2; + + /* CLK */ + at91_set_A_periph(AT91_PIN_PC15, 0); + + /* CMD */ + at91_set_A_periph(AT91_PIN_PC10, 1); + + /* DAT0, maybe DAT1..DAT3 */ + at91_set_A_periph(AT91_PIN_PC11, 1); + if (data->bus_width == 4) { + at91_set_A_periph(AT91_PIN_PC12, 1); + at91_set_A_periph(AT91_PIN_PC13, 1); + at91_set_A_periph(AT91_PIN_PC14, 1); + } + } + + add_generic_device("atmel_mci", mmc_id, NULL, start, SZ_16K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {} +#endif + +#if defined(CONFIG_I2C_GPIO) +static struct i2c_gpio_platform_data pdata_i2c [] = { + { + .sda_pin = AT91_PIN_PA30, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PA31, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + }, { + .sda_pin = AT91_PIN_PC26, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PC27, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + }, { + .sda_pin = AT91_PIN_PA18, + .sda_is_open_drain = 1, + .scl_pin = AT91_PIN_PA19, + .scl_is_open_drain = 1, + .udelay = 5, /* ~100 kHz */ + } +}; + +void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) +{ + struct i2c_gpio_platform_data *pdata; + + if (i2c_id > ARRAY_SIZE(pdata_i2c)) + return; + + i2c_register_board_info(i2c_id, devices, nr_devices); + + pdata = &pdata_i2c[i2c_id]; + + at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */ + at91_set_multi_drive(pdata->sda_pin, 1); + + at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */ + at91_set_multi_drive(pdata->scl_pin, 1); + + add_generic_device_res("i2c-gpio", i2c_id, NULL, 0, pdata); +} +#else +void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {} +#endif + +/* -------------------------------------------------------------------- + * SPI + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_SPI_ATMEL) +static unsigned spi0_standard_cs[4] = { AT91_PIN_PD13, AT91_PIN_PD14, AT91_PIN_PD15, AT91_PIN_PD16 }; + +static unsigned spi1_standard_cs[4] = { AT91_PIN_PC25, AT91_PIN_PC26, AT91_PIN_PC27, AT91_PIN_PC28 }; + +static struct at91_spi_platform_data spi_pdata[] = { + [0] = { + .chipselect = spi0_standard_cs, + .num_chipselect = ARRAY_SIZE(spi0_standard_cs), + }, + [1] = { + .chipselect = spi1_standard_cs, + .num_chipselect = ARRAY_SIZE(spi1_standard_cs), + }, +}; + +void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) +{ + int i; + int cs_pin; + resource_size_t start = ~0; + + BUG_ON(spi_id > 1); + + if (!pdata) + pdata = &spi_pdata[spi_id]; + + for (i = 0; i < pdata->num_chipselect; i++) { + cs_pin = pdata->chipselect[i]; + + /* enable chip-select pin */ + if (gpio_is_valid(cs_pin)) + at91_set_gpio_output(cs_pin, 1); + } + + /* Configure SPI bus(es) */ + switch (spi_id) { + case 0: + start = SAMA5D3_BASE_SPI0; + at91_set_A_periph(AT91_PIN_PD10, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PD11, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PD12, 0); /* SPI0_SPCK */ + break; + case 1: + start = SAMA5D3_BASE_SPI1; + at91_set_B_periph(AT91_PIN_PC22, 0); /* SPI1_MISO */ + at91_set_B_periph(AT91_PIN_PC23, 0); /* SPI1_MOSI */ + at91_set_B_periph(AT91_PIN_PC24, 0); /* SPI1_SPCK */ + break; + } + + add_generic_device("atmel_spi", spi_id, NULL, start, SZ_16K, + IORESOURCE_MEM, pdata); +} +#else +void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {} +#endif + +/* -------------------------------------------------------------------- + * LCD Controller + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) +{ + BUG_ON(!data); + + if (cpu_is_sama5d35()) { + pr_warn("AT91: no lcd on sama5d35\n"); + return; + } + + at91_set_A_periph(AT91_PIN_PA24, 0); /* LCDPWM */ + at91_set_A_periph(AT91_PIN_PA25, 0); /* LCDDISP */ + at91_set_A_periph(AT91_PIN_PA26, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PA27, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PA28, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PA29, 0); /* LCDDEN */ + + at91_set_A_periph(AT91_PIN_PA0, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PA3, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PA4, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PA5, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PA6, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PA7, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PA8, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PA9, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* LCDD15 */ + at91_set_C_periph(AT91_PIN_PC14, 0); /* LCDD16 */ + at91_set_C_periph(AT91_PIN_PC13, 0); /* LCDD17 */ + at91_set_C_periph(AT91_PIN_PC12, 0); /* LCDD18 */ + at91_set_C_periph(AT91_PIN_PC11, 0); /* LCDD19 */ + at91_set_C_periph(AT91_PIN_PC10, 0); /* LCDD20 */ + at91_set_C_periph(AT91_PIN_PC15, 0); /* LCDD21 */ + at91_set_C_periph(AT91_PIN_PE27, 0); /* LCDD22 */ + at91_set_C_periph(AT91_PIN_PE28, 0); /* LCDD23 */ + + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, SAMA5D3_BASE_LCDC, SZ_4K, + IORESOURCE_MEM, data); +} +#else +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {} +#endif + +/* -------------------------------------------------------------------- + * UART + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_DRIVER_SERIAL_ATMEL) +resource_size_t __init at91_configure_dbgu(void) +{ + at91_set_A_periph(AT91_PIN_PB30, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB31, 1); /* DTXD */ + + return AT91_BASE_DBGU1; +} + +resource_size_t __init at91_configure_usart0(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PD18, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PD17, 0); /* RXD0 */ + + if (pins & ATMEL_UART_RTS) + at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS0 */ + if (pins & ATMEL_UART_CTS) + at91_set_A_periph(AT91_PIN_PD15, 0); /* CTS0 */ + + return SAMA5D3_BASE_USART0; +} + +resource_size_t __init at91_configure_usart1(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PB29, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB28, 0); /* RXD1 */ + + if (pins & ATMEL_UART_RTS) + at91_set_A_periph(AT91_PIN_PB27, 0); /* RTS1 */ + if (pins & ATMEL_UART_CTS) + at91_set_A_periph(AT91_PIN_PB26, 0); /* CTS1 */ + + return SAMA5D3_BASE_USART1; +} +#endif diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 9b73bcf496..0444a5fdee 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -87,6 +87,11 @@ static void __init soc_detect(u32 dbgu_base) at91_soc_initdata.type = AT91_SOC_SAM9N12; at91_boot_soc = at91sam9n12_soc; break; + + case ARCH_ID_SAMA5D3: + at91_soc_initdata.type = AT91_SOC_SAMA5D3; + at91_boot_soc = at91sama5d3_soc; + break; } /* at91sam9g10 */ @@ -142,6 +147,23 @@ static void __init soc_detect(u32 dbgu_base) break; } } + + if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { + switch (at91_soc_initdata.exid) { + case ARCH_EXID_SAMA5D31: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D31; + break; + case ARCH_EXID_SAMA5D33: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D33; + break; + case ARCH_EXID_SAMA5D34: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D34; + break; + case ARCH_EXID_SAMA5D35: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; + break; + } + } } static const char *soc_name[] = { @@ -155,6 +177,7 @@ static const char *soc_name[] = { [AT91_SOC_SAM9RL] = "at91sam9rl", [AT91_SOC_SAM9X5] = "at91sam9x5", [AT91_SOC_SAM9N12] = "at91sam9n12", + [AT91_SOC_SAMA5D3] = "sama5d3", [AT91_SOC_NONE] = "Unknown" }; @@ -177,6 +200,10 @@ static const char *soc_subtype_name[] = { [AT91_SOC_SAM9X35] = "at91sam9x35", [AT91_SOC_SAM9G25] = "at91sam9g25", [AT91_SOC_SAM9X25] = "at91sam9x25", + [AT91_SOC_SAMA5D31] = "sama5d31", + [AT91_SOC_SAMA5D33] = "sama5d33", + [AT91_SOC_SAMA5D34] = "sama5d34", + [AT91_SOC_SAMA5D35] = "sama5d35", [AT91_SOC_SUBTYPE_NONE] = "Unknown" }; diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h index 8019ced861..b2278a5b32 100644 --- a/arch/arm/mach-at91/soc.h +++ b/arch/arm/mach-at91/soc.h @@ -18,6 +18,7 @@ extern struct at91_init_soc at91sam9g45_soc; extern struct at91_init_soc at91sam9rl_soc; extern struct at91_init_soc at91sam9x5_soc; extern struct at91_init_soc at91sam9n12_soc; +extern struct at91_init_soc at91sama5d3_soc; #define AT91_SOC_START(_name) \ struct at91_init_soc __initdata at91##_name##_soc \ @@ -64,3 +65,7 @@ static inline int at91_soc_is_enabled(void) #if !defined(CONFIG_SOC_AT91SAM9N12) #define at91sam9n12_soc at91_boot_soc #endif + +#if !defined(CONFIG_SOC_SAMA5) +#define at91sama5d3_soc at91_boot_soc +#endif |