diff options
Diffstat (limited to 'arch/arm/mach-clps711x')
| -rw-r--r-- | arch/arm/mach-clps711x/Kconfig | 13 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/clock.c | 126 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/devices.c | 108 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/include/mach/gpio.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-clps711x/lowlevel.c | 16 |
5 files changed, 157 insertions, 109 deletions
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig index d2873b4c0a..b774c540b8 100644 --- a/arch/arm/mach-clps711x/Kconfig +++ b/arch/arm/mach-clps711x/Kconfig @@ -12,14 +12,13 @@ endchoice menu "CLPS711X specific settings" -config CLPS711X_CPU_PLL_MULT - int "CPU PLL multiplier (20-50)" - range 20 50 - default "40" +config CLPS711X_RAISE_CPUFREQ + bool "Raise CPU frequency to 90 MHz" + depends on MACH_CLEP7212 help - Define CPU PLL multiplier. PLL is calculated by formula: - PLL Frequency = (PLL Multiplier / 2) * 3686400 Hz - Default value is 40, for achieve 73 MHz. + Raise CPU frequency to 90 MHz. This operation can be performed + only for devices which allow to operate at 90 MHz. + If option is not selected, CPU frequency will set to default 73 MHz. endmenu diff --git a/arch/arm/mach-clps711x/clock.c b/arch/arm/mach-clps711x/clock.c index 09cbaf961c..7658c9aa7c 100644 --- a/arch/arm/mach-clps711x/clock.c +++ b/arch/arm/mach-clps711x/clock.c @@ -9,103 +9,119 @@ #include <common.h> #include <init.h> -#include <clock.h> +#include <sizes.h> #include <asm/io.h> +#include <linux/clk.h> #include <linux/clkdev.h> #include <mach/clps711x.h> -static struct clk { - unsigned long rate; -} uart_clk, bus_clk; +#define CLPS711X_OSC_FREQ 3686400 +#define CLPS711X_EXT_FREQ 13000000 -static uint64_t clocksource_read(void) -{ - return ~readw(TC2D); -} - -static struct clocksource cs = { - .read = clocksource_read, - .mask = CLOCKSOURCE_MASK(16), +enum clps711x_clks { + dummy, cpu, bus, uart, timer_hf, timer_lf, tc1, tc2, clk_max }; -unsigned long clk_get_rate(struct clk *clk) -{ - return clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); +static struct { + const char *name; + struct clk *clk; +} clks[clk_max] = { + { "dummy", }, + { "cpu", }, + { "bus", }, + { "uart", }, + { "timer_hf", }, + { "timer_lf", }, + { "tc1", }, + { "tc2", }, +}; -int clk_enable(struct clk *clk) -{ - /* Do nothing */ - return 0; -} -EXPORT_SYMBOL(clk_enable); +static const char *tc_sel_clks[] = { + "timer_lf", + "timer_hf", +}; -void clk_disable(struct clk *clk) +static __init void clps711x_clk_register(enum clps711x_clks id) { - /* Do nothing */ + clk_register_clkdev(clks[id].clk, clks[id].name, NULL); } -EXPORT_SYMBOL(clk_disable); -static int clocks_init(void) +static __init int clps711x_clk_init(void) { - int osc, ext, pll, cpu, timer; + unsigned int f_cpu, f_bus, f_uart, f_timer_hf, f_timer_lf, pll; u32 tmp; - osc = 3686400; - ext = 13000000; - tmp = readl(PLLR) >> 24; if (tmp) - pll = (osc * tmp) / 2; + pll = (CLPS711X_OSC_FREQ * tmp) / 2; else pll = 73728000; /* Default value for old CPUs */ tmp = readl(SYSFLG2); if (tmp & SYSFLG2_CKMODE) { - cpu = ext; - bus_clk.rate = cpu; + f_cpu = CLPS711X_EXT_FREQ; + f_bus = CLPS711X_EXT_FREQ; } else { - cpu = pll; - if (cpu >= 36864000) - bus_clk.rate = cpu / 2; + f_cpu = pll; + if (f_cpu >= 36864000) + f_bus = f_cpu / 2; else - bus_clk.rate = 36864000 / 2; + f_bus = 36864000 / 2; } - uart_clk.rate = bus_clk.rate / 10; + f_uart = f_bus / 10; if (tmp & SYSFLG2_CKMODE) { tmp = readw(SYSCON2); if (tmp & SYSCON2_OSTB) - timer = ext / 26; + f_timer_hf = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26); else - timer = 541440; + f_timer_hf = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24); } else - timer = cpu / 144; + f_timer_hf = DIV_ROUND_CLOSEST(f_cpu, 144); + f_timer_lf = DIV_ROUND_CLOSEST(f_timer_hf, 256); + + /* Turn timers in free running mode */ tmp = readl(SYSCON1); - tmp &= ~SYSCON1_TC2M; /* Free running mode */ - tmp |= SYSCON1_TC2S; /* High frequency source */ + tmp &= ~(SYSCON1_TC1M | SYSCON1_TC2M); writel(tmp, SYSCON1); - clocks_calc_mult_shift(&cs.mult, &cs.shift, timer, NSEC_PER_SEC, 10); + clks[dummy].clk = clk_fixed(clks[dummy].name, 0); + clks[cpu].clk = clk_fixed(clks[cpu].name, f_cpu); + clks[bus].clk = clk_fixed(clks[bus].name, f_bus); + clks[uart].clk = clk_fixed(clks[uart].name, f_uart); + clks[timer_hf].clk = clk_fixed(clks[timer_hf].name, f_timer_hf); + clks[timer_lf].clk = clk_fixed(clks[timer_lf].name, f_timer_lf); + clks[tc1].clk = clk_mux(clks[tc1].name, IOMEM(SYSCON1), 5, 1, + tc_sel_clks, ARRAY_SIZE(tc_sel_clks)); + clks[tc2].clk = clk_mux(clks[tc2].name, IOMEM(SYSCON1), 7, 1, + tc_sel_clks, ARRAY_SIZE(tc_sel_clks)); + + clps711x_clk_register(dummy); + clps711x_clk_register(cpu); + clps711x_clk_register(bus); + clps711x_clk_register(uart); + clps711x_clk_register(timer_hf); + clps711x_clk_register(timer_lf); + clps711x_clk_register(tc1); + clps711x_clk_register(tc2); - return init_clock(&cs); + return 0; } -core_initcall(clocks_init); +postcore_initcall(clps711x_clk_init); -static struct clk_lookup clocks_lookups[] = { - CLKDEV_CON_ID("bus", &bus_clk), - CLKDEV_DEV_ID("clps711x_serial0", &uart_clk), - CLKDEV_DEV_ID("clps711x_serial1", &uart_clk), -}; +static const char *clps711x_clocksrc_name = "clps711x-cs"; -static int clkdev_init(void) +static __init int clps711x_core_init(void) { - clkdev_add_table(clocks_lookups, ARRAY_SIZE(clocks_lookups)); + /* Using TC2 in low frequency mode as clocksource */ + clk_set_parent(clks[tc2].clk, clks[timer_lf].clk); + clk_add_alias(NULL, clps711x_clocksrc_name, "tc2", NULL); + add_generic_device(clps711x_clocksrc_name, DEVICE_ID_SINGLE, NULL, + TC2D, SZ_2, IORESOURCE_MEM, NULL); return 0; } -postcore_initcall(clkdev_init); +coredevice_initcall(clps711x_core_init); diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c index 6c760db944..9eeff5c52f 100644 --- a/arch/arm/mach-clps711x/devices.c +++ b/arch/arm/mach-clps711x/devices.c @@ -14,6 +14,8 @@ #include <asm/io.h> #include <asm/memory.h> +#include <linux/clk.h> + #include <mach/clps711x.h> static int clps711x_mem_init(void) @@ -42,68 +44,92 @@ void clps711x_setup_memcfg(int bank, u32 val) case 0 ... 3: _clps711x_setup_memcfg(bank, MEMCFG1, val); break; - case 4 ... 7: + case 4 ... 5: _clps711x_setup_memcfg(bank - 4, MEMCFG2, val); break; } } static struct resource uart0_resources[] = { - { - .start = UBRLCR1, - .end = UBRLCR1, - .flags = IORESOURCE_MEM, - }, - { - .start = SYSCON1, - .end = SYSCON1, - .flags = IORESOURCE_MEM, - }, - { - .start = SYSFLG1, - .end = SYSFLG1, - .flags = IORESOURCE_MEM, - }, - { - .start = UARTDR1, - .end = UARTDR1, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(UBRLCR1, SZ_4), + DEFINE_RES_MEM(UARTDR1, SZ_4), }; static struct resource uart1_resources[] = { - { - .start = UBRLCR2, - .end = UBRLCR2, - .flags = IORESOURCE_MEM, - }, - { - .start = SYSCON2, - .end = SYSCON2, - .flags = IORESOURCE_MEM, - }, - { - .start = SYSFLG2, - .end = SYSFLG2, - .flags = IORESOURCE_MEM, - }, - { - .start = UARTDR2, - .end = UARTDR2, - .flags = IORESOURCE_MEM, - }, + DEFINE_RES_MEM(UBRLCR2, SZ_4), + DEFINE_RES_MEM(UARTDR2, SZ_4), }; void clps711x_add_uart(unsigned int id) { switch (id) { case 0: + clk_add_alias(NULL, "clps711x_serial0", "uart", NULL); add_generic_device_res("clps711x_serial", 0, uart0_resources, ARRAY_SIZE(uart0_resources), NULL); break; case 1: + clk_add_alias(NULL, "clps711x_serial1", "uart", NULL); add_generic_device_res("clps711x_serial", 1, uart1_resources, ARRAY_SIZE(uart1_resources), NULL); break; } } + +static struct resource gpio0_resources[] = { + DEFINE_RES_MEM(PADR, SZ_1), + DEFINE_RES_MEM(PADDR, SZ_1), +}; + +static struct resource gpio1_resources[] = { + DEFINE_RES_MEM(PBDR, SZ_1), + DEFINE_RES_MEM(PBDDR, SZ_1), +}; + +static struct resource gpio2_resources[] = { + DEFINE_RES_MEM(PCDR, SZ_1), + DEFINE_RES_MEM(PCDDR, SZ_1), +}; + +static struct resource gpio3_resources[] = { + DEFINE_RES_MEM(PDDR, SZ_1), + DEFINE_RES_MEM(PDDDR, SZ_1), +}; + +static struct resource gpio4_resources[] = { + DEFINE_RES_MEM(PEDR, SZ_1), + DEFINE_RES_MEM(PEDDR, SZ_1), +}; + +static __init int clps711x_gpio_init(void) +{ + add_generic_device_res("clps711x-gpio", 0, gpio0_resources, + ARRAY_SIZE(gpio0_resources), NULL); + add_generic_device_res("clps711x-gpio", 1, gpio1_resources, + ARRAY_SIZE(gpio1_resources), NULL); + add_generic_device_res("clps711x-gpio", 2, gpio2_resources, + ARRAY_SIZE(gpio2_resources), NULL); + add_generic_device_res("clps711x-gpio", 3, gpio3_resources, + ARRAY_SIZE(gpio3_resources), NULL); + add_generic_device_res("clps711x-gpio", 4, gpio4_resources, + ARRAY_SIZE(gpio4_resources), NULL); + + return 0; +} +coredevice_initcall(clps711x_gpio_init); + +static __init int clps711x_syscon_init(void) +{ + /* SYSCON1, SYSFLG1 */ + add_generic_device("clps711x-syscon", 1, NULL, SYSCON1, SZ_128, + IORESOURCE_MEM, NULL); + /* SYSCON2, SYSFLG2 */ + add_generic_device("clps711x-syscon", 2, NULL, SYSCON2, SZ_128, + IORESOURCE_MEM, NULL); + /* SYSCON3 */ + add_generic_device("clps711x-syscon", 3, NULL, SYSCON3, SZ_64, + IORESOURCE_MEM, NULL); + + return 0; +} +postcore_initcall(clps711x_syscon_init); diff --git a/arch/arm/mach-clps711x/include/mach/gpio.h b/arch/arm/mach-clps711x/include/mach/gpio.h new file mode 100644 index 0000000000..3428fe54bb --- /dev/null +++ b/arch/arm/mach-clps711x/include/mach/gpio.h @@ -0,0 +1,3 @@ +#include <asm-generic/gpio.h> + +#define CLPS711X_GPIO(prt,bit) ((prt) * 8 + (bit)) diff --git a/arch/arm/mach-clps711x/lowlevel.c b/arch/arm/mach-clps711x/lowlevel.c index 193f61aa6e..58306f29fc 100644 --- a/arch/arm/mach-clps711x/lowlevel.c +++ b/arch/arm/mach-clps711x/lowlevel.c @@ -21,12 +21,12 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult) { u32 cpu, bus; - /* Setup base clocking, Enable SDQM pins */ - writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); - asm("nop"); - /* Check if we running from external 13 MHz clock */ if (!(readl(SYSFLG2) & SYSFLG2_CKMODE)) { + /* Setup bus wait state scaling factor to 2 */ + writel(SYSCON3_CLKCTL0 | SYSCON3_CLKCTL1, SYSCON3); + asm("nop"); + /* Check valid multiplier, default to 74 MHz */ if ((pllmult < 20) || (pllmult > 50)) pllmult = 40; @@ -42,11 +42,15 @@ void __naked __bare_init clps711x_barebox_entry(u32 pllmult) cpu = pllmult * 3686400; if (cpu >= 36864000) - bus = cpu /2; + bus = cpu / 2; else bus = 36864000 / 2; - } else + } else { bus = 13000000; + /* Setup bus wait state scaling factor to 1 */ + writel(0, SYSCON3); + asm("nop"); + } /* CLKEN select, SDRAM width=32 */ writel(SYSCON2_CLKENSL, SYSCON2); |