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-rw-r--r--arch/arm/mach-imx/esdctl.c358
1 files changed, 253 insertions, 105 deletions
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 25e7c83ad9..701ca0ac1f 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -1,20 +1,7 @@
-/*
- * esdctl.c - i.MX sdram controller functions
- *
- * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
+/* esdctl.c - i.MX sdram controller functions */
#include <common.h>
#include <io.h>
@@ -26,26 +13,29 @@
#include <linux/bitfield.h>
#include <asm/barebox-arm.h>
#include <asm/memory.h>
-#include <mach/esdctl.h>
-#include <mach/esdctl-v4.h>
-#include <mach/imx6-mmdc.h>
-#include <mach/imx1-regs.h>
-#include <mach/imx21-regs.h>
-#include <mach/imx25-regs.h>
-#include <mach/imx27-regs.h>
-#include <mach/imx31-regs.h>
-#include <mach/imx35-regs.h>
-#include <mach/imx51-regs.h>
-#include <mach/imx53-regs.h>
-#include <mach/imx6-regs.h>
-#include <mach/vf610-ddrmc.h>
-#include <mach/imx8m-regs.h>
-#include <mach/imx7-regs.h>
+#include <mach/imx/esdctl.h>
+#include <mach/imx/esdctl-v4.h>
+#include <mach/imx/imx6-mmdc.h>
+#include <mach/imx/imx1-regs.h>
+#include <mach/imx/imx21-regs.h>
+#include <mach/imx/imx25-regs.h>
+#include <mach/imx/imx27-regs.h>
+#include <mach/imx/imx31-regs.h>
+#include <mach/imx/imx35-regs.h>
+#include <mach/imx/imx51-regs.h>
+#include <mach/imx/imx53-regs.h>
+#include <mach/imx/imx6-regs.h>
+#include <mach/imx/vf610-ddrmc.h>
+#include <mach/imx/imx8m-regs.h>
+#include <mach/imx/imx7-regs.h>
+#include <mach/imx/imx9-regs.h>
+#include <mach/imx/scratch.h>
+#include <tee/optee.h>
struct imx_esdctl_data {
unsigned long base0;
unsigned long base1;
- void (*add_mem)(void *esdctlbase, struct imx_esdctl_data *);
+ int (*add_mem)(void *esdctlbase, struct imx_esdctl_data *);
};
static int imx_esdctl_disabled;
@@ -195,9 +185,11 @@ static inline u64 __imx6_mmdc_sdram_size(void __iomem *mmdcbase, int cs)
return memory_sdram_size(cols, rows, banks, width);
}
-static void add_mem(unsigned long base0, unsigned long size0,
+static int add_mem(unsigned long base0, unsigned long size0,
unsigned long base1, unsigned long size1)
{
+ int ret0 = 0, ret1 = 0;
+
debug("%s: cs0 base: 0x%08lx cs0 size: 0x%08lx\n", __func__, base0, size0);
debug("%s: cs1 base: 0x%08lx cs1 size: 0x%08lx\n", __func__, base1, size1);
@@ -205,16 +197,16 @@ static void add_mem(unsigned long base0, unsigned long size0,
/*
* concatenate both chip selects to a single bank
*/
- arm_add_mem_device("ram0", base0, size0 + size1);
-
- return;
+ return arm_add_mem_device("ram0", base0, size0 + size1);
}
if (size0)
- arm_add_mem_device("ram0", base0, size0);
+ ret0 = arm_add_mem_device("ram0", base0, size0);
if (size1)
- arm_add_mem_device(size0 ? "ram1" : "ram0", base1, size1);
+ ret1 = arm_add_mem_device(size0 ? "ram1" : "ram0", base1, size1);
+
+ return ret0 ? ret0 : ret1;
}
/*
@@ -237,35 +229,35 @@ static inline void imx_esdctl_v2_disable_default(void __iomem *esdctlbase)
}
}
-static void imx_esdctl_v1_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v1_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
{
- add_mem(data->base0, imx_v1_sdram_size(esdctlbase, 0),
+ return add_mem(data->base0, imx_v1_sdram_size(esdctlbase, 0),
data->base1, imx_v1_sdram_size(esdctlbase, 1));
}
-static void imx_esdctl_v2_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v2_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
{
- add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
+ return add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
data->base1, imx_v2_sdram_size(esdctlbase, 1));
}
-static void imx_esdctl_v2_bug_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v2_bug_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
{
imx_esdctl_v2_disable_default(esdctlbase);
- add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
+ return add_mem(data->base0, imx_v2_sdram_size(esdctlbase, 0),
data->base1, imx_v2_sdram_size(esdctlbase, 1));
}
-static void imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v3_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
{
- add_mem(data->base0, imx_v3_sdram_size(esdctlbase, 0),
+ return add_mem(data->base0, imx_v3_sdram_size(esdctlbase, 0),
data->base1, imx_v3_sdram_size(esdctlbase, 1));
}
-static void imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
+static int imx_esdctl_v4_add_mem(void *esdctlbase, struct imx_esdctl_data *data)
{
- add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0),
+ return add_mem(data->base0, imx_v4_sdram_size(esdctlbase, 0),
data->base1, imx_v4_sdram_size(esdctlbase, 1));
}
@@ -294,9 +286,9 @@ static inline resource_size_t imx6_mmdc_sdram_size(void __iomem *mmdcbase)
return size;
}
-static void imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int imx6_mmdc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
{
- arm_add_mem_device("ram0", data->base0,
+ return arm_add_mem_device("ram0", data->base0,
imx6_mmdc_sdram_size(mmdcbase));
}
@@ -316,9 +308,9 @@ static inline resource_size_t vf610_ddrmc_sdram_size(void __iomem *ddrmc)
return memory_sdram_size(cols, rows, banks, width);
}
-static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
{
- arm_add_mem_device("ram0", data->base0,
+ return arm_add_mem_device("ram0", data->base0,
vf610_ddrmc_sdram_size(mmdcbase));
}
@@ -328,9 +320,11 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
#define DDRC_ADDRMAP0_CS_BIT0 GENMASK(4, 0)
#define DDRC_MSTR 0x0000
+#define DDRC_MSTR_DDR4 BIT(4)
#define DDRC_MSTR_LPDDR4 BIT(5)
#define DDRC_MSTR_DATA_BUS_WIDTH GENMASK(13, 12)
#define DDRC_MSTR_ACTIVE_RANKS GENMASK(27, 24)
+#define DDRC_MSTR_DEVICE_CONFIG GENMASK(31, 30)
#define DDRC_ADDRMAP0_CS_BIT1 GENMASK(12, 8)
@@ -357,24 +351,31 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
#define DDRC_ADDRMAP7_ROW_B17 GENMASK(11, 8)
#define DDRC_ADDRMAP7_ROW_B16 GENMASK( 3, 0)
+#define DDRC_ADDRMAP8_BG_B1 GENMASK(13, 8)
+#define DDRC_ADDRMAP8_BG_B0 GENMASK(4, 0)
+
+#define DDRC_ADDRMAP_LENGTH 9
+
static unsigned int
imx_ddrc_count_bits(unsigned int bits, const u8 config[],
unsigned int config_num)
{
unsigned int i;
- for (i = 0; i < config_num && config[i] == 0b1111; i++)
- bits--;
+
+ for (i = 0; i < config_num; i++) {
+ if (config[i] == 0b1111)
+ bits--;
+ }
return bits;
}
static resource_size_t
-imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
+imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[DDRC_ADDRMAP_LENGTH],
u8 col_max, const u8 col_b[], unsigned int col_b_num,
u8 row_max, const u8 row_b[], unsigned int row_b_num,
- bool reduced_adress_space)
+ bool reduced_adress_space, unsigned int mstr)
{
- const u32 mstr = readl(ddrc + DDRC_MSTR);
unsigned int banks, ranks, columns, rows, active_ranks, width;
resource_size_t size;
@@ -395,15 +396,22 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
BUG();
}
+ /*
+ * mstr is ignored for some SoCs/RAM types and may yield wrong
+ * results when used for calculation. Callers of this function
+ * are expected to fix it up as necessary.
+ * Bus width in bytes, 0 means half byte or 4-bit mode
+ */
+ width = (1 << FIELD_GET(DDRC_MSTR_DEVICE_CONFIG, mstr)) >> 1;
+
switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) {
case 0b00: /* Full DQ bus */
- width = 4;
break;
- case 0b01: /* Half DQ bus */
- width = 2;
+ case 0b01: /* Half DQ bus */
+ width >>= 1;
break;
case 0b10: /* Quarter DQ bus */
- width = 1;
+ width >>= 2;
break;
default:
BUG();
@@ -420,17 +428,43 @@ imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111)
banks++;
+ if (mstr & DDRC_MSTR_DDR4) {
+ /* FIXME: DDR register spreasheet claims this to be
+ * 6-bit and 63 meaning bank group address bit 0 is 0,
+ * but reference manual claims 5-bit without 'neutral' value
+ * See MX8M_Mini_DDR4_RPA_v17, MX8M_Nano_DDR4_RPA_v8
+ */
+ if (FIELD_GET(DDRC_ADDRMAP8_BG_B0, addrmap[8]) != 0b11111)
+ banks++;
+ if (FIELD_GET(DDRC_ADDRMAP8_BG_B1, addrmap[8]) != 0b111111)
+ banks++;
+ }
+
columns = imx_ddrc_count_bits(col_max, col_b, col_b_num);
rows = imx_ddrc_count_bits(row_max, row_b, row_b_num);
- size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks;
+ /*
+ * Special case when bus width is 0 or x4 mode,
+ * calculate the mem size and then divide the size by 2.
+ */
+ if (width)
+ size = memory_sdram_size(columns, rows, 1 << banks, width);
+ else
+ size = memory_sdram_size(columns, rows, 1 << banks, 1) >> 1;
+ size <<= ranks;
return reduced_adress_space ? size * 3 / 4 : size;
}
-static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
+static void imx_ddrc_set_mstr_device_config(u32 *mstr, unsigned bits)
+{
+ *mstr &= ~DDRC_MSTR_DEVICE_CONFIG;
+ *mstr |= FIELD_PREP(DDRC_MSTR_DEVICE_CONFIG, fls(bits / 8));
+}
+
+static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc, unsigned buswidth)
{
- const u32 addrmap[] = {
+ const u32 addrmap[DDRC_ADDRMAP_LENGTH] = {
readl(ddrc + DDRC_ADDRMAP(0)),
readl(ddrc + DDRC_ADDRMAP(1)),
readl(ddrc + DDRC_ADDRMAP(2)),
@@ -438,7 +472,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
readl(ddrc + DDRC_ADDRMAP(4)),
readl(ddrc + DDRC_ADDRMAP(5)),
readl(ddrc + DDRC_ADDRMAP(6)),
- readl(ddrc + DDRC_ADDRMAP(7))
+ readl(ddrc + DDRC_ADDRMAP(7)),
+ readl(ddrc + DDRC_ADDRMAP(8))
};
const u8 col_b[] = {
/*
@@ -456,15 +491,8 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
FIELD_GET(DDRC_ADDRMAP2_COL_B4, addrmap[2]),
};
const u8 row_b[] = {
- /*
- * FIXME: RM mentions the following fields as being
- * present, but looking at the code generated by DDR
- * tool it doesn't look like those registers are
- * really implemented/used.
- *
- * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
- * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
- */
+ FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
+ FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]),
FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]),
FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]),
@@ -473,22 +501,105 @@ static resource_size_t imx8m_ddrc_sdram_size(void __iomem *ddrc)
};
const bool reduced_adress_space =
FIELD_GET(DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, addrmap[6]);
+ u32 mstr = readl(ddrc + DDRC_MSTR);
+
+ /* Device config is ignored and taken as 32-bit for LPDDR4 */
+ if (mstr & DDRC_MSTR_LPDDR4)
+ imx_ddrc_set_mstr_device_config(&mstr, buswidth);
return imx_ddrc_sdram_size(ddrc, addrmap,
12, ARRAY_AND_SIZE(col_b),
- 16, ARRAY_AND_SIZE(row_b),
- reduced_adress_space);
+ 18, ARRAY_AND_SIZE(row_b),
+ reduced_adress_space, mstr);
+}
+
+static int _imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data,
+ unsigned int buswidth)
+{
+ resource_size_t size = imx8m_ddrc_sdram_size(mmdcbase, buswidth);
+ resource_size_t size0, size1;
+ int ret;
+
+ /*
+ * Split the available memory into multiple banks if the device does
+ * have more RAM than 3G. At the moment this is necessary to prevent
+ * memory_bank_first_find_space() from finding free space near the end
+ * of the 4G barrier which is the case in a 6G/8G setup. This is
+ * important for larger barebox-pbl binaries (e.g. debug enabled) and
+ * the barebox chainloading mechanism since the pbl init the MMU to 4G.
+ * In this case a MMU exception will be thrown if the barebox-pbl is
+ * placed near the 4G barrier.
+ */
+ size0 = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
+ size1 = size - size0;
+
+ ret = arm_add_mem_device("ram0", data->base0, size0);
+ if (ret || size1 == 0)
+ return ret;
+
+#ifdef CONFIG_64BIT
+ /*
+ * Albeit this hook is called on 64bit machines only, the driver serves
+ * 32bit machines as well. Guard the code to avoid compiler warnings.
+ */
+ ret = arm_add_mem_device("ram1", SZ_4G, size1);
+#endif
+
+ return ret;
+}
+
+static int imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+ return _imx8m_ddrc_add_mem(mmdcbase, data, 32);
+}
+
+static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+ return _imx8m_ddrc_add_mem(mmdcbase, data, 16);
}
-static void imx8m_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+#define IMX9_DDRC_CS_CONFIG(n) (0x80 + (n) * 4)
+#define IMX9_DDRC_CS_ROW_BITS GENMASK(10, 8)
+#define IMX9_DDRC_CS_COL_BITS GENMASK(2, 0)
+#define IMX9_DDRC_CS_EN BIT(31)
+
+resource_size_t imx9_ddrc_sdram_size(void)
+{
+ void __iomem *mmdcbase = IOMEM(MX9_DDR_CTL_BASE);
+ int width = 2;
+ int banks = 8;
+ resource_size_t mem = 0;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ int rows, cols;
+ u32 cs, col_bits;
+
+ cs = readl(mmdcbase + IMX9_DDRC_CS_CONFIG(i));
+ if (!(cs & IMX9_DDRC_CS_EN))
+ continue;
+
+ rows = FIELD_GET(IMX9_DDRC_CS_ROW_BITS, cs) + 12;
+ col_bits = FIELD_GET(IMX9_DDRC_CS_COL_BITS, cs);
+ if (col_bits == 7)
+ cols = 7;
+ else
+ cols = col_bits + 8;
+
+ mem += memory_sdram_size(cols, rows, banks, width);
+ }
+
+ return mem;
+}
+
+static int imx9_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
{
- arm_add_mem_device("ram0", data->base0,
- imx8m_ddrc_sdram_size(mmdcbase));
+ return arm_add_mem_device("ram0", data->base0, imx9_ddrc_sdram_size());
}
static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
{
- const u32 addrmap[] = {
+ const u32 addrmap[DDRC_ADDRMAP_LENGTH] = {
readl(ddrc + DDRC_ADDRMAP(0)),
readl(ddrc + DDRC_ADDRMAP(1)),
readl(ddrc + DDRC_ADDRMAP(2)),
@@ -515,20 +626,24 @@ static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
};
const bool reduced_adress_space =
FIELD_GET(DDRC_ADDRMAP6_LPDDR3_6GB_12GB, addrmap[6]);
+ u32 mstr = readl(ddrc + DDRC_MSTR);
+
+ /* Device config is unused on i.MX7, so rewrite it as 32-bit wide */
+ imx_ddrc_set_mstr_device_config(&mstr, 32);
return imx_ddrc_sdram_size(ddrc, addrmap,
11, ARRAY_AND_SIZE(col_b),
15, ARRAY_AND_SIZE(row_b),
- reduced_adress_space);
+ reduced_adress_space, mstr);
}
-static void imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+static int imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
{
- arm_add_mem_device("ram0", data->base0,
+ return arm_add_mem_device("ram0", data->base0,
imx7d_ddrc_sdram_size(mmdcbase));
}
-static int imx_esdctl_probe(struct device_d *dev)
+static int imx_esdctl_probe(struct device *dev)
{
struct resource *iores;
struct imx_esdctl_data *data;
@@ -547,9 +662,7 @@ static int imx_esdctl_probe(struct device_d *dev)
if (imx_esdctl_disabled)
return 0;
- data->add_mem(base, data);
-
- return 0;
+ return data->add_mem(base, data);
}
static __maybe_unused struct imx_esdctl_data imx1_data = {
@@ -614,11 +727,21 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
.add_mem = vf610_ddrmc_add_mem,
};
-static __maybe_unused struct imx_esdctl_data imx8mq_data = {
+static __maybe_unused struct imx_esdctl_data imx8m_data = {
.base0 = MX8M_DDR_CSD1_BASE_ADDR,
.add_mem = imx8m_ddrc_add_mem,
};
+static __maybe_unused struct imx_esdctl_data imx8mn_data = {
+ .base0 = MX8M_DDR_CSD1_BASE_ADDR,
+ .add_mem = imx8mn_ddrc_add_mem,
+};
+
+static __maybe_unused struct imx_esdctl_data imx9_data = {
+ .base0 = MX9_DDR_CSD1_BASE_ADDR,
+ .add_mem = imx9_ddrc_add_mem,
+};
+
static __maybe_unused struct imx_esdctl_data imx7d_data = {
.base0 = MX7_DDR_BASE_ADDR,
.add_mem = imx7d_ddrc_add_mem,
@@ -689,8 +812,14 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
.compatible = "fsl,vf610-ddrmc",
.data = &vf610_data
}, {
- .compatible = "fsl,imx8mq-ddrc",
- .data = &imx8mq_data
+ .compatible = "fsl,imx8m-ddrc",
+ .data = &imx8m_data
+ }, {
+ .compatible = "fsl,imx8mn-ddrc",
+ .data = &imx8mn_data
+ }, {
+ .compatible = "fsl,imx93-ddrc",
+ .data = &imx9_data
}, {
.compatible = "fsl,imx7d-ddrc",
.data = &imx7d_data
@@ -698,20 +827,15 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
/* sentinel */
}
};
+MODULE_DEVICE_TABLE(of, imx_esdctl_dt_ids);
-static struct driver_d imx_esdctl_driver = {
+static struct driver imx_esdctl_driver = {
.name = "imx-esdctl",
.probe = imx_esdctl_probe,
.id_table = imx_esdctl_ids,
.of_compatible = DRV_OF_COMPAT(imx_esdctl_dt_ids),
};
-
-static int imx_esdctl_init(void)
-{
- return platform_driver_register(&imx_esdctl_driver);
-}
-
-mem_initcall(imx_esdctl_init);
+mem_platform_driver(imx_esdctl_driver);
/*
* The i.MX SoCs usually have two SDRAM chipselects. The following
@@ -869,11 +993,11 @@ void __noreturn vf610_barebox_entry(void *boarddata)
boarddata);
}
-static void __noreturn imx8m_barebox_entry(void *boarddata)
+resource_size_t imx8m_barebox_earlymem_size(unsigned buswidth)
{
resource_size_t size;
- size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR));
+ size = imx8m_ddrc_sdram_size(IOMEM(MX8M_DDRC_CTL_BASE_ADDR), buswidth);
/*
* We artificially limit detected memory size to force malloc
* pool placement to be within 4GiB address space, so as to
@@ -883,18 +1007,35 @@ static void __noreturn imx8m_barebox_entry(void *boarddata)
* pool placement. The rest of the system should be able to
* detect and utilize full amount of memory.
*/
- size = min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
- barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR, size, boarddata);
+ return min_t(resource_size_t, SZ_4G - MX8M_DDR_CSD1_BASE_ADDR, size);
+}
+
+static void __noreturn imx8m_barebox_entry(void *boarddata, unsigned buswidth)
+{
+ imx8m_init_scratch_space(buswidth, false);
+ optee_set_membase(imx_scratch_get_optee_hdr());
+ barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
+ imx8m_barebox_earlymem_size(buswidth), boarddata);
}
void __noreturn imx8mm_barebox_entry(void *boarddata)
{
- imx8m_barebox_entry(boarddata);
+ imx8m_barebox_entry(boarddata, 32);
+}
+
+void __noreturn imx8mn_barebox_entry(void *boarddata)
+{
+ imx8m_barebox_entry(boarddata, 16);
+}
+
+void __noreturn imx8mp_barebox_entry(void *boarddata)
+{
+ imx8m_barebox_entry(boarddata, 32);
}
void __noreturn imx8mq_barebox_entry(void *boarddata)
{
- imx8m_barebox_entry(boarddata);
+ imx8m_barebox_entry(boarddata, 32);
}
void __noreturn imx7d_barebox_entry(void *boarddata)
@@ -904,4 +1045,11 @@ void __noreturn imx7d_barebox_entry(void *boarddata)
boarddata);
}
+void __noreturn imx93_barebox_entry(void *boarddata)
+{
+ imx93_init_scratch_space(false);
+ optee_set_membase(imx_scratch_get_optee_hdr());
+ barebox_arm_entry(MX9_DDR_CSD1_BASE_ADDR,
+ imx9_ddrc_sdram_size(), boarddata);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 18:19:34 +0000