diff options
Diffstat (limited to 'arch/arm/mach-imx/imx8m.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8m.c | 148 |
1 files changed, 15 insertions, 133 deletions
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index 8b275bd6f6..52e42ee9ef 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -2,24 +2,19 @@ #include <init.h> #include <common.h> +#include <linux/sizes.h> #include <io.h> #include <asm/syscounter.h> #include <asm/system.h> -#include <mach/generic.h> -#include <mach/revision.h> -#include <mach/imx8mq.h> -#include <mach/imx8m-ccm-regs.h> -#include <mach/reset-reason.h> -#include <mach/ocotp.h> -#include <mach/imx8mp-regs.h> -#include <mach/imx8mq-regs.h> +#include <mach/imx/generic.h> +#include <mach/imx/imx8m-ccm-regs.h> #include <soc/imx8m/clk-early.h> +#include <linux/bitfield.h> #include <linux/iopoll.h> -#include <linux/arm-smccc.h> -#define FSL_SIP_BUILDINFO 0xC2000003 -#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 +#define IMX_SIP_BUILDINFO 0xC2000003 +#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 void imx8m_clock_set_target_val(int clock_id, u32 val) { @@ -44,125 +39,6 @@ void imx8m_ccgr_clock_disable(int index) ccm + IMX8M_CCM_CCGRn_CLR(index)); } -u64 imx8m_uid(void) -{ - return imx_ocotp_read_uid(IOMEM(MX8M_OCOTP_BASE_ADDR)); -} - -static int imx8m_init(const char *cputypestr) -{ - void __iomem *src = IOMEM(MX8M_SRC_BASE_ADDR); - struct arm_smccc_res res; - - /* - * Reset reasons seem to be identical to that of i.MX7 - */ - imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons); - pr_info("%s unique ID: %llx\n", cputypestr, imx8m_uid()); - - if (IS_ENABLED(CONFIG_ARM_SMCCC) && - IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) { - arm_smccc_smc(FSL_SIP_BUILDINFO, - FSL_SIP_BUILDINFO_GET_COMMITHASH, - 0, 0, 0, 0, 0, 0, &res); - pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0); - } - - return 0; -} - -int imx8mm_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MM_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mm_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MM: - cputypestr = "i.MX8MM"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mm_cpu_revision()); - - return imx8m_init(cputypestr); -} - -int imx8mn_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MN_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mn_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MN: - cputypestr = "i.MX8MN"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mn_cpu_revision()); - - return imx8m_init(cputypestr); -} - -int imx8mp_init(void) -{ - void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MP_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mp_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MP: - cputypestr = "i.MX8MP"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mp_cpu_revision()); - - return imx8m_init(cputypestr); -} - -int imx8mq_init(void) -{ - void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); - uint32_t type = FIELD_GET(DIGPROG_MAJOR, - readl(anatop + MX8MQ_ANATOP_DIGPROG)); - const char *cputypestr; - - imx8mq_boot_save_loc(); - - switch (type) { - case IMX8M_CPUTYPE_IMX8MQ: - cputypestr = "i.MX8MQ"; - break; - default: - cputypestr = "unknown i.MX8M"; - break; - }; - - imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision()); - - return imx8m_init(cputypestr); -} - #define INTPLL_DIV20_CLKE_MASK BIT(27) #define INTPLL_DIV10_CLKE_MASK BIT(25) #define INTPLL_DIV8_CLKE_MASK BIT(23) @@ -180,7 +56,7 @@ int imx8mq_init(void) #define IMX8MM_CCM_ANALOG_SYS_PLL2_GEN_CTRL 0x104 #define IMX8MM_CCM_ANALOG_SYS_PLL3_GEN_CTRL 0x114 -static void __imx8mm_early_clock_init(unsigned long pll3_freq) /* and later */ +static void __imx8m_early_clock_init(unsigned long pll3_freq) /* and later */ { void __iomem *ana = IOMEM(MX8M_ANATOP_BASE_ADDR); void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); @@ -250,14 +126,20 @@ static void __imx8mm_early_clock_init(unsigned long pll3_freq) /* and later */ void imx8mm_early_clock_init(void) { - __imx8mm_early_clock_init(750000000UL); + __imx8m_early_clock_init(750000000UL); } void imx8mn_early_clock_init(void) { - __imx8mm_early_clock_init(600000000UL); + __imx8m_early_clock_init(600000000UL); } +void imx8mp_early_clock_init(void) +{ + __imx8m_early_clock_init(750000000UL); +} + + #define KEEP_ALIVE 0x18 #define VER_L 0x1c #define VER_H 0x20 |