diff options
Diffstat (limited to 'arch/arm/mach-imx/include')
| -rw-r--r-- | arch/arm/mach-imx/include/mach/esdctl.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/generic.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx-gpio.h | 46 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx6-regs.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx6.h | 88 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/reset-reason.h | 37 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/vf610-ddrmc.h | 18 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/vf610-regs.h | 5 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/vf610.h | 51 |
9 files changed, 211 insertions, 43 deletions
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 66dcc8974c..117e2bbad5 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -48,6 +48,7 @@ #define ESDMISC_MDDR_MDIS 0x00000010 #define ESDMISC_LHD 0x00000020 #define ESDMISC_SDRAMRDY 0x80000000 +#define ESDMISC_DDR2_8_BANK BIT(6) #define ESDCFGx_tXP_MASK 0x00600000 #define ESDCFGx_tXP_1 0x00000000 @@ -137,6 +138,7 @@ void __noreturn imx51_barebox_entry(void *boarddata); void __noreturn imx53_barebox_entry(void *boarddata); void __noreturn imx6q_barebox_entry(void *boarddata); void __noreturn imx6ul_barebox_entry(void *boarddata); +void __noreturn vf610_barebox_entry(void *boarddata); void imx_esdctl_disable(void); #endif diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index f68dc875b0..ad9d9cb022 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -15,6 +15,7 @@ void imx51_boot_save_loc(void); void imx53_boot_save_loc(void); void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); +void vf610_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); void imx35_get_boot_source(enum bootsource *src, int *instance); @@ -22,6 +23,7 @@ void imx51_get_boot_source(enum bootsource *src, int *instance); void imx53_get_boot_source(enum bootsource *src, int *instance); void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); +void vf610_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); int imx21_init(void); @@ -34,6 +36,7 @@ int imx51_init(void); int imx53_init(void); int imx6_init(void); int imx7_init(void); +int vf610_init(void); int imx1_devices_init(void); int imx21_devices_init(void); diff --git a/arch/arm/mach-imx/include/mach/imx-gpio.h b/arch/arm/mach-imx/include/mach/imx-gpio.h index 5e673beef9..891c33a3f4 100644 --- a/arch/arm/mach-imx/include/mach/imx-gpio.h +++ b/arch/arm/mach-imx/include/mach/imx-gpio.h @@ -8,15 +8,21 @@ * regular gpio functions outside of lowlevel code! */ -static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *dr, - int gpio, int value) +static inline void imx_gpio_direction(void __iomem *gdir, void __iomem *dr, + int gpio, int out, int value) { uint32_t val; val = readl(gdir); - val |= 1 << gpio; + if (out) + val |= 1 << gpio; + else + val &= ~(1 << gpio); writel(val, gdir); + if (!out) + return; + val = readl(dr); if (value) val |= 1 << gpio; @@ -28,7 +34,7 @@ static inline void imx_gpio_direction_output(void __iomem *gdir, void __iomem *d static inline void imx1_gpio_direction_output(void *base, int gpio, int value) { - imx_gpio_direction_output(base + 0x0, base + 0x1c, gpio, value); + imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 1, value); } #define imx21_gpio_direction_output(base, gpio, value) imx1_gpio_direction_output(base, gpio,value) @@ -36,7 +42,7 @@ static inline void imx1_gpio_direction_output(void *base, int gpio, int value) static inline void imx31_gpio_direction_output(void *base, int gpio, int value) { - imx_gpio_direction_output(base + 0x4, base + 0x0, gpio, value); + imx_gpio_direction(base + 0x4, base + 0x0, gpio, 1, value); } #define imx25_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) @@ -45,4 +51,34 @@ static inline void imx31_gpio_direction_output(void *base, int gpio, int value) #define imx53_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) #define imx6_gpio_direction_output(base, gpio, value) imx31_gpio_direction_output(base, gpio,value) +static inline void imx1_gpio_direction_input(void *base, int gpio, int value) +{ + imx_gpio_direction(base + 0x0, base + 0x1c, gpio, 0, 0); +} + +#define imx21_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio) +#define imx27_gpio_direction_input(base, gpio, value) imx1_gpio_direction_input(base, gpio) + +static inline void imx31_gpio_direction_input(void *base, int gpio) +{ + imx_gpio_direction(base + 0x4, base + 0x0, gpio, 0, 0); +} + +#define imx25_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx35_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx51_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx53_gpio_direction_input(base, gpio, value) imx31_gpio_direction_input(base, gpio) +#define imx6_gpio_direction_input(base, gpio) imx31_gpio_direction_input(base, gpio) + +#define imx1_gpio_val(base, gpio) readl(base + 0x1c) & (1 << gpio) ? 1 : 0 +#define imx21_gpio_val(base, gpio) imx1_gpio_val(base, gpio) +#define imx27_gpio_val(base, gpio) imx1_gpio_val(base, gpio) + +#define imx31_gpio_val(base, gpio) readl(base) & (1 << gpio) ? 1 : 0 +#define imx25_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx35_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx51_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx53_gpio_val(base, gpio) imx31_gpio_val(base, gpio) +#define imx6_gpio_val(base, gpio) imx31_gpio_val(base, gpio) + #endif /* __MACH_IMX_GPIO_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index ac2aa2109f..1ba22b5bc6 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -117,6 +117,8 @@ #define MX6_SATA_BASE_ADDR 0x02200000 -#define MX6_MMDC_PORT0_BASE_ADDR 0x10000000 +#define MX6_MMDC_PORT01_BASE_ADDR 0x10000000 +#define MX6_MMDC_PORT0_BASE_ADDR 0x80000000 + #endif /* __MACH_IMX6_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx6.h b/arch/arm/mach-imx/include/mach/imx6.h index 6b08e6a521..5701bd480c 100644 --- a/arch/arm/mach-imx/include/mach/imx6.h +++ b/arch/arm/mach-imx/include/mach/imx6.h @@ -16,7 +16,9 @@ void __noreturn imx6_pm_stby_poweroff(void); #define IMX6_CPUTYPE_IMX6DL 0x261 #define IMX6_CPUTYPE_IMX6SX 0x462 #define IMX6_CPUTYPE_IMX6D 0x263 +#define IMX6_CPUTYPE_IMX6DP 0x1263 #define IMX6_CPUTYPE_IMX6Q 0x463 +#define IMX6_CPUTYPE_IMX6QP 0x1463 #define IMX6_CPUTYPE_IMX6UL 0x164 #define IMX6_CPUTYPE_IMX6ULL 0x165 @@ -33,36 +35,51 @@ static inline int scu_get_core_count(void) return (ncores & 0x03) + 1; } -static inline int __imx6_cpu_type(void) +#define SI_REV_CPUTYPE(s) (((s) >> 16) & 0xff) +#define SI_REV_MAJOR(s) (((s) >> 8) & 0xf) +#define SI_REV_MINOR(s) ((s) & 0xf) + +static inline uint32_t __imx6_read_si_rev(void) { - uint32_t val; - - val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); - val = (val >> 16) & 0xff; - /* non-MX6-standard SI_REV reg offset for MX6SL */ - if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && - val < (IMX6_CPUTYPE_IMX6S & 0xff)) { - uint32_t tmp; - tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV); - tmp = (tmp >> 16) & 0xff; - if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp) - /* intentionally skip scu_get_core_count() for MX6SL */ - return IMX6_CPUTYPE_IMX6SL; - } + uint32_t si_rev; + uint32_t cpu_type; + + si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV); + cpu_type = SI_REV_CPUTYPE(si_rev); - val |= scu_get_core_count() << 8; + if (cpu_type >= 0x61 && cpu_type <= 0x65) + return si_rev; - return val; + /* try non-MX6-standard SI_REV reg offset for MX6SL */ + si_rev = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV); + cpu_type = SI_REV_CPUTYPE(si_rev); + + if (si_rev == 0x60) + return si_rev; + + return 0; } -static inline int imx6_cpu_type(void) +static inline int __imx6_cpu_type(void) { - if (!cpu_is_mx6()) - return 0; + uint32_t si_rev = __imx6_read_si_rev(); + uint32_t cpu_type = SI_REV_CPUTYPE(si_rev); + + /* intentionally skip scu_get_core_count() for MX6SL */ + if (cpu_type == IMX6_CPUTYPE_IMX6SL) + return IMX6_CPUTYPE_IMX6SL; - return __imx6_cpu_type(); + cpu_type |= scu_get_core_count() << 8; + + if ((cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) && + SI_REV_MAJOR(si_rev) >= 1) + cpu_type |= 0x1000; + + return cpu_type; } +int imx6_cpu_type(void); + #define DEFINE_MX6_CPU_TYPE(str, type) \ static inline int cpu_mx6_is_##str(void) \ { \ @@ -76,10 +93,19 @@ static inline int imx6_cpu_type(void) return cpu_mx6_is_##str(); \ } +/* + * Below are defined: + * + * cpu_is_mx6s(), cpu_is_mx6dl(), cpu_is_mx6q(), cpu_is_mx6qp(), cpu_is_mx6d(), + * cpu_is_mx6dp(), cpu_is_mx6sx(), cpu_is_mx6sl(), cpu_is_mx6ul(), + * cpu_is_mx6ull() + */ DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S); DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL); DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q); +DEFINE_MX6_CPU_TYPE(mx6qp, IMX6_CPUTYPE_IMX6QP); DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D); +DEFINE_MX6_CPU_TYPE(mx6dp, IMX6_CPUTYPE_IMX6DP); DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX); DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL); DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL); @@ -87,27 +113,15 @@ DEFINE_MX6_CPU_TYPE(mx6ull, IMX6_CPUTYPE_IMX6ULL); static inline int __imx6_cpu_revision(void) { - uint32_t rev; - uint32_t si_rev_offset = IMX6_ANATOP_SI_REV; + uint32_t si_rev = __imx6_read_si_rev(); u8 major_part, minor_part; - if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl()) - si_rev_offset = IMX6SL_ANATOP_SI_REV; - - rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset); - - major_part = (rev >> 8) & 0xf; - minor_part = rev & 0xf; + major_part = (si_rev >> 8) & 0xf; + minor_part = si_rev & 0xf; return ((major_part + 1) << 4) | minor_part; } -static inline int imx6_cpu_revision(void) -{ - if (!cpu_is_mx6()) - return 0; - - return __imx6_cpu_revision(); -} +int imx6_cpu_revision(void); #endif /* __MACH_IMX6_H */ diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h new file mode 100644 index 0000000000..0f644a8c1d --- /dev/null +++ b/arch/arm/mach-imx/include/mach/reset-reason.h @@ -0,0 +1,37 @@ +#ifndef __MACH_RESET_REASON_H__ +#define __MACH_RESET_REASON_H__ + +#include <reset_source.h> + +#define IMX_SRC_SRSR_IPP_RESET BIT(0) +#define IMX_SRC_SRSR_CSU_RESET BIT(2) +#define IMX_SRC_SRSR_IPP_USER_RESET BIT(3) +#define IMX_SRC_SRSR_WDOG1_RESET BIT(4) +#define IMX_SRC_SRSR_JTAG_RESET BIT(5) +#define IMX_SRC_SRSR_JTAG_SW_RESET BIT(6) +#define IMX_SRC_SRSR_WDOG3_RESET BIT(7) +#define IMX_SRC_SRSR_WDOG4_RESET BIT(8) +#define IMX_SRC_SRSR_TEMPSENSE_RESET BIT(9) +#define IMX_SRC_SRSR_WARM_BOOT BIT(16) + +#define IMX_SRC_SRSR 0x008 +#define IMX7_SRC_SRSR 0x05c + +#define VF610_SRC_SRSR_SW_RST BIT(18) +#define VF610_SRC_SRSR_RESETB BIT(7) +#define VF610_SRC_SRSR_JTAG_RST BIT(5) +#define VF610_SRC_SRSR_WDOG_M4 BIT(4) +#define VF610_SRC_SRSR_WDOG_A5 BIT(3) +#define VF610_SRC_SRSR_POR_RST BIT(0) + +struct imx_reset_reason { + uint32_t mask; + enum reset_src_type type; + int instance; +}; + +void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *); + +extern const struct imx_reset_reason imx_reset_reasons[]; + +#endif /* __MACH_RESET_REASON_H__ */ diff --git a/arch/arm/mach-imx/include/mach/vf610-ddrmc.h b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h new file mode 100644 index 0000000000..07feb036e5 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610-ddrmc.h @@ -0,0 +1,18 @@ +#ifndef __MACH_DDRMC_H +#define __MACH_DDRMC_H + +#include <mach/vf610-regs.h> + + +#define DDRMC_CR(x) ((x) * 4) + +#define DDRMC_CR01_MAX_COL_REG(reg) (((reg) >> 8) & 0b01111) +#define DDRMC_CR01_MAX_ROW_REG(reg) (((reg) >> 0) & 0b11111) +#define DDRMC_CR73_COL_DIFF(reg) (((reg) >> 16) & 0b00111) +#define DDRMC_CR73_ROW_DIFF(reg) (((reg) >> 8) & 0b00011) +#define DDRMC_CR73_BANK_DIFF(reg) (((reg) >> 0) & 0b00011) + +#define DDRMC_CR78_REDUC BIT(8) + + +#endif /* __MACH_MMDC_H */ diff --git a/arch/arm/mach-imx/include/mach/vf610-regs.h b/arch/arm/mach-imx/include/mach/vf610-regs.h index 8be220b68c..416b457aff 100644 --- a/arch/arm/mach-imx/include/mach/vf610-regs.h +++ b/arch/arm/mach-imx/include/mach/vf610-regs.h @@ -13,6 +13,8 @@ #define VF610_AIPS0_BASE_ADDR 0x40000000 #define VF610_AIPS1_BASE_ADDR 0x40080000 +#define VF610_RAM_BASE_ADDR 0x80000000 + /* AIPS 0 */ #define VF610_MSCM_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001000) #define VF610_MSCM_IR_BASE_ADDR (VF610_AIPS0_BASE_ADDR + 0x00001800) @@ -107,4 +109,7 @@ #define VF610_MSCM_IRSPRC_CP0_EN 1 #define VF610_MSCM_IRSPRC_NUM 112 +#define VF610_MSCM_CPxCOUNT 0x00c +#define VF610_MSCM_CPxCFG1 0x014 + #endif diff --git a/arch/arm/mach-imx/include/mach/vf610.h b/arch/arm/mach-imx/include/mach/vf610.h new file mode 100644 index 0000000000..6d00d2e457 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/vf610.h @@ -0,0 +1,51 @@ +#ifndef __MACH_VF610_H +#define __MACH_VF610_H + +#include <io.h> +#include <mach/generic.h> +#include <mach/vf610-regs.h> +#include <mach/revision.h> + +#define VF610_CPUTYPE_VFx10 0x010 + +#define VF610_CPUTYPE_VF610 0x610 +#define VF610_CPUTYPE_VF600 0x600 +#define VF610_CPUTYPE_VF510 0x510 +#define VF610_CPUTYPE_VF500 0x500 + +#define VF610_ROM_VERSION_OFFSET 0x80 + +static inline int __vf610_cpu_type(void) +{ + void __iomem *mscm = IOMEM(VF610_MSCM_BASE_ADDR); + const u32 cpxcount = readl(mscm + VF610_MSCM_CPxCOUNT); + const u32 cpxcfg1 = readl(mscm + VF610_MSCM_CPxCFG1); + int cpu_type; + + cpu_type = cpxcount ? VF610_CPUTYPE_VF600 : VF610_CPUTYPE_VF500; + + return cpxcfg1 ? cpu_type | VF610_CPUTYPE_VFx10 : cpu_type; +} + +static inline int vf610_cpu_type(void) +{ + if (!cpu_is_vf610()) + return 0; + + return __vf610_cpu_type(); +} + +static inline int vf610_cpu_revision(void) +{ + if (!cpu_is_vf610()) + return IMX_CHIP_REV_UNKNOWN; + + /* + * There doesn't seem to be a documented way of retreiving + * silicon revision on VFxxx cpus, so we just report Mask ROM + * version instead + */ + return readl(VF610_ROM_VERSION_OFFSET) & 0xff; +} + +#endif |