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-rw-r--r--arch/arm/mach-imx/Kconfig9
-rw-r--r--arch/arm/mach-imx/clk-pllv1.c5
-rw-r--r--arch/arm/mach-imx/clk-pllv2.c5
-rw-r--r--arch/arm/mach-imx/iim.c2
-rw-r--r--arch/arm/mach-imx/imx25.c8
-rw-r--r--arch/arm/mach-imx/include/mach/generic.h11
-rw-r--r--arch/arm/mach-imx/include/mach/imx-pll.h8
-rw-r--r--arch/arm/mach-imx/include/mach/imx35-regs.h17
-rw-r--r--arch/arm/mach-imx/include/mach/imx53-regs.h5
-rw-r--r--arch/arm/mach-imx/include/mach/imx_cpu_types.h14
-rw-r--r--arch/arm/mach-imx/include/mach/iomux-mx31.h34
-rw-r--r--arch/arm/mach-imx/include/mach/weim.h3
12 files changed, 60 insertions, 61 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5b648acbbc..80f8fd80ae 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -33,6 +33,7 @@ config ARCH_TEXT_BASE
default 0x17800000 if MACH_SABRESD
default 0x4fc00000 if MACH_REALQ7
default 0x4fc00000 if MACH_GK802
+ default 0x87f00000 if MACH_KINDLE3
default 0x2fc00000 if MACH_TQMA6X
default 0x4fc00000 if MACH_DFI_FS700_M60
default 0x4fc00000 if MACH_UDOO
@@ -453,6 +454,14 @@ config MACH_GUF_CUPID
Say Y here if you are using the Garz+Fricke Neso board equipped
with a Freescale i.MX35 Processor
+config MACH_KINDLE3
+ bool "Amazon Kindle3"
+ select ARCH_IMX35
+ select ARCH_HAS_L2X0
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ help
+ Say Y here if you are using the Amazon Model No. D00901 Kindle
+
# ----------------------------------------------------------
comment "i.MX51 Boards"
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 6785da0dee..f992134f7e 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -61,8 +61,9 @@ static unsigned long clk_pllv1_recalc_rate(struct clk *clk,
do_div(ll, mfd + 1);
if (mfn < 0)
- ll = -ll;
- ll = (freq * mfi) + ll;
+ ll = (freq * mfi) - ll;
+ else
+ ll = (freq * mfi) + ll;
return ll;
}
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
index a2b016f346..5ba07fa5e6 100644
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -113,8 +113,9 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
temp = (u64) ref_clk * mfn_abs;
do_div(temp, mfd + 1);
if (mfn < 0)
- temp = -temp;
- temp = (ref_clk * mfi) + temp;
+ temp = (ref_clk * mfi) - temp;
+ else
+ temp = (ref_clk * mfi) + temp;
return temp;
}
diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c
index c3ba67e0b8..6addfed696 100644
--- a/arch/arm/mach-imx/iim.c
+++ b/arch/arm/mach-imx/iim.c
@@ -196,7 +196,7 @@ int imx_iim_read(unsigned int banknum, int offset, void *buf, int count)
if (!imx_iim)
return -ENODEV;
- if (banknum > IIM_NUM_BANKS)
+ if (banknum >= IIM_NUM_BANKS)
return -EINVAL;
bank = iim->bank[banknum];
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 3cfeebbe93..2534d75429 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -23,14 +23,6 @@
#define MX25_BOOTROM_HAB_MAGIC 0x3c95cac6
#define MX25_DRYICE_GPR 0x3c
-void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
- unsigned additional)
-{
- writel(upper, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
- writel(lower, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
- writel(additional, MX25_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
-}
-
/* IIM fuse definitions */
#define IIM_BANK0_BASE (MX25_IIM_BASE_ADDR + 0x800)
#define IIM_BANK1_BASE (MX25_IIM_BASE_ADDR + 0xc00)
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 46fe38856f..0a4200b3f4 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -4,6 +4,7 @@
#include <linux/compiler.h>
#include <linux/types.h>
#include <bootsource.h>
+#include <mach/imx_cpu_types.h>
u64 imx_uid(void);
@@ -42,16 +43,6 @@ void imx6_cpu_lowlevel_init(void);
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-#define IMX_CPU_IMX1 1
-#define IMX_CPU_IMX21 21
-#define IMX_CPU_IMX25 25
-#define IMX_CPU_IMX27 27
-#define IMX_CPU_IMX31 31
-#define IMX_CPU_IMX35 35
-#define IMX_CPU_IMX51 51
-#define IMX_CPU_IMX53 53
-#define IMX_CPU_IMX6 6
-
extern unsigned int __imx_cpu_type;
#ifdef CONFIG_ARCH_IMX1
diff --git a/arch/arm/mach-imx/include/mach/imx-pll.h b/arch/arm/mach-imx/include/mach/imx-pll.h
index df7e73efea..0ccf41bcaa 100644
--- a/arch/arm/mach-imx/include/mach/imx-pll.h
+++ b/arch/arm/mach-imx/include/mach/imx-pll.h
@@ -15,4 +15,12 @@
#define IMX_PLL_MFN(x) (((x) & 0x3ff) << 0)
#define IMX_PLL_BRMO (1 << 31)
+/* Assuming 24MHz input clock */
+#define MPCTL_PARAM_532 ((1 << 31) | \
+ IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+#define MPCTL_PARAM_399 \
+ (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define PPCTL_PARAM_300 \
+ (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
+
#endif /* __INCLUDE_ASM_ARCH_IMX_PLL_H*/
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 52e209b4de..48bf64386a 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -150,11 +150,26 @@
#define MX35_CCM_CGR3 0x38
#define MX35_CCM_CGR0_CSPI1_SHIFT 10
+#define MX35_CCM_CGR0_CSPI2_SHIFT 12
+#define MX35_CCM_CGR0_EPIT1_SHIFT 20
+#define MX35_CCM_CGR0_EPIT2_SHIFT 22
+#define MX35_CCM_CGR0_ESDHC1_SHIFT 26
+#define MX35_CCM_CGR0_ESDHC2_SHIFT 28
+#define MX35_CCM_CGR0_ESDHC3_SHIFT 30
#define MX35_CCM_CGR1_FEC_SHIFT 0
+#define MX35_CCM_CGR1_GPIO1_SHIFT 2
+#define MX35_CCM_CGR1_GPIO2_SHIFT 4
+#define MX35_CCM_CGR1_GPIO3_SHIFT 6
#define MX35_CCM_CGR1_I2C1_SHIFT 10
-#define MX35_CCM_CGR1_SDHC1_SHIFT 26
+#define MX35_CCM_CGR1_I2C2_SHIFT 12
+#define MX35_CCM_CGR1_I2C3_SHIFT 14
+#define MX35_CCM_CGR1_IOMUX_SHIFT 16
+#define MX35_CCM_CGR1_KPP_SHIFT 20
+#define MX35_CCM_CGR2_UART1_SHIFT 16
#define MX35_CCM_CGR2_UART2_SHIFT 18
+#define MX35_CCM_CGR2_UART3_SHIFT 20
#define MX35_CCM_CGR2_USB_SHIFT 22
+#define MX35_CCM_CGR2_WDOG_SHIFT 24
#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25
#define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
index 9cd7723ce9..d45c94370d 100644
--- a/arch/arm/mach-imx/include/mach/imx53-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx53-regs.h
@@ -1,8 +1,13 @@
#ifndef __MACH_IMX53_REGS_H
#define __MACH_IMX53_REGS_H
+#include <linux/sizes.h>
+
#define MX53_IROM_BASE_ADDR 0x0
+#define MX53_IRAM_BASE_ADDR 0xF8000000
+#define MX53_IRAM_SIZE SZ_128K
+
#define MX53_SATA_BASE_ADDR 0x10000000
#define MX53_IPU_BASE_ADDR 0x18000000
diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
new file mode 100644
index 0000000000..781ab9fe74
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h
@@ -0,0 +1,14 @@
+#ifndef __MACH_IMX_CPU_TYPES_H
+#define __MACH_IMX_CPU_TYPES_H
+
+#define IMX_CPU_IMX1 1
+#define IMX_CPU_IMX21 21
+#define IMX_CPU_IMX25 25
+#define IMX_CPU_IMX27 27
+#define IMX_CPU_IMX31 31
+#define IMX_CPU_IMX35 35
+#define IMX_CPU_IMX51 51
+#define IMX_CPU_IMX53 53
+#define IMX_CPU_IMX6 6
+
+#endif /* __MACH_IMX_CPU_TYPES_H */
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h
index 258ccee034..c814c15912 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx31.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx31.h
@@ -573,10 +573,7 @@ enum iomux_pins {
#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
@@ -640,37 +637,6 @@ enum iomux_pins {
#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
diff --git a/arch/arm/mach-imx/include/mach/weim.h b/arch/arm/mach-imx/include/mach/weim.h
index 3fbbb6ba8e..22d9c76d61 100644
--- a/arch/arm/mach-imx/include/mach/weim.h
+++ b/arch/arm/mach-imx/include/mach/weim.h
@@ -12,9 +12,6 @@ void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
unsigned additional);
-void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
- unsigned additional);
-
void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower);
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-18 05:13:02 +0000