diff options
Diffstat (limited to 'arch/arm/mach-omap')
61 files changed, 118 insertions, 5045 deletions
diff --git a/arch/arm/mach-omap/am33xx_bbu_emmc.c b/arch/arm/mach-omap/am33xx_bbu_emmc.c index 29e13de778..3cae31d34c 100644 --- a/arch/arm/mach-omap/am33xx_bbu_emmc.c +++ b/arch/arm/mach-omap/am33xx_bbu_emmc.c @@ -18,7 +18,7 @@ #include <fs.h> #include <fcntl.h> #include <filetype.h> -#include <mach/bbu.h> +#include <mach/omap/bbu.h> #define PART_TABLE_SIZE 66 #define PART_TABLE_OFFSET 0x1BE @@ -42,16 +42,15 @@ static int emmc_mlo_handler(struct bbu_handler *handler, struct bbu_data *data) fd = open(handler->devicefile, O_RDWR); if (fd < 0) { - pr_err("could not open %s: %s\n", handler->devicefile, - errno_str()); + pr_err("could not open %s: %m\n", handler->devicefile); return fd; } /* save the partition table */ ret = pread(fd, part_table, PART_TABLE_SIZE, PART_TABLE_OFFSET); if (ret < 0) { - pr_err("could not read partition table from fd %s: %s\n", - handler->devicefile, errno_str()); + pr_err("could not read partition table from fd %s: %m\n", + handler->devicefile); goto error; } @@ -59,8 +58,8 @@ static int emmc_mlo_handler(struct bbu_handler *handler, struct bbu_data *data) for (i = 0; i < 4; i++) { ret = pwrite(fd, image, size, i * 0x20000); if (ret < 0) { - pr_err("could not write MLO %i/4 to fd %s: %s\n", - i + 1, handler->devicefile, errno_str()); + pr_err("could not write MLO %i/4 to fd %s: %m\n", + i + 1, handler->devicefile); goto error_save_part_table; } } @@ -69,8 +68,8 @@ error_save_part_table: /* write the partition table back */ ret = pwrite(fd, part_table, PART_TABLE_SIZE, PART_TABLE_OFFSET); if (ret < 0) - pr_err("could not write partition table to fd %s: %s\n", - handler->devicefile, errno_str()); + pr_err("could not write partition table to fd %s: %m\n", + handler->devicefile); error: close(fd); diff --git a/arch/arm/mach-omap/am33xx_bbu_nand.c b/arch/arm/mach-omap/am33xx_bbu_nand.c index 8c487c8ebb..40e382780a 100644 --- a/arch/arm/mach-omap/am33xx_bbu_nand.c +++ b/arch/arm/mach-omap/am33xx_bbu_nand.c @@ -24,7 +24,7 @@ #include <filetype.h> #include <linux/mtd/mtd.h> #include <mtd/mtd-peb.h> -#include <mach/bbu.h> +#include <mach/omap/bbu.h> struct nand_bbu_handler { struct bbu_handler bbu_handler; @@ -213,7 +213,7 @@ static int nand_update_handler_complete(struct bbu_handler *handler, buf = xzalloc(mtd->erasesize); memcpy(buf, data->image, data->len); - + for (i = 0; i < 4; i++) { if (mtd_peb_is_bad(mtd, i)) { pr_info("PEB%d is bad, skipping\n", i); diff --git a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c index 7d2ef1f0f2..2c58c9ae69 100644 --- a/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c +++ b/arch/arm/mach-omap/am33xx_bbu_spi_mlo.c @@ -20,7 +20,7 @@ #include <fs.h> #include <fcntl.h> #include <linux/stat.h> -#include <mach/bbu.h> +#include <mach/omap/bbu.h> /* * AM35xx, AM33xx chips use big endian MLO for SPI NOR flash @@ -51,7 +51,7 @@ static int spi_nor_mlo_handler(struct bbu_handler *handler, ret = stat(data->devicefile, &s); if (ret) { - printf("could not open %s: %s", data->devicefile, errno_str()); + printf("could not open %s: %m", data->devicefile); return ret; } @@ -66,14 +66,14 @@ static int spi_nor_mlo_handler(struct bbu_handler *handler, dstfd = open(data->devicefile, O_WRONLY); if (dstfd < 0) { - printf("could not open %s: %s", data->devicefile, errno_str()); + printf("could not open %s: %m", data->devicefile); ret = dstfd; goto out; } ret = erase(dstfd, ERASE_SIZE_ALL, 0); if (ret < 0) { - printf("could not erase %s: %s", data->devicefile, errno_str()); + printf("could not erase %s: %m", data->devicefile); goto out1; } diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c index a5ac6f68c0..4ba10491be 100644 --- a/arch/arm/mach-omap/am33xx_clock.c +++ b/arch/arm/mach-omap/am33xx_clock.c @@ -14,8 +14,8 @@ */ #include <common.h> #include <asm/io.h> -#include <mach/am33xx-clock.h> -#include <mach/am33xx-generic.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/am33xx-generic.h> #include <linux/math64.h> #define PRCM_MOD_EN 0x2 @@ -169,6 +169,11 @@ void am33xx_enable_per_clocks(void) __raw_writel(PRCM_MOD_EN, CM_WKUP_ADC_TSC_CLKCTRL); while (__raw_readl(CM_WKUP_ADC_TSC_CLKCTRL) != PRCM_MOD_EN); + if (IS_ENABLED(CONFIG_HW_RANDOM_OMAP)) { + __raw_writel(PRCM_MOD_EN, CM_PER_RNG_CLKCTRL); + while ((__raw_readl(CM_PER_RNG_CLKCTRL) & 0x30000) != 0x0); + } + clkdcoldo = __raw_readl(CM_CLKDCOLDO_DPLL_PER); clkdcoldo = clkdcoldo | 0x100; __raw_writel(clkdcoldo, CM_CLKDCOLDO_DPLL_PER); diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c index bfe5b3dc73..850fbceaec 100644 --- a/arch/arm/mach-omap/am33xx_generic.c +++ b/arch/arm/mach-omap/am33xx_generic.c @@ -21,13 +21,13 @@ #include <net.h> #include <restart.h> #include <asm/barebox-arm.h> -#include <mach/am33xx-silicon.h> -#include <mach/am33xx-clock.h> -#include <mach/emif4.h> -#include <mach/generic.h> -#include <mach/sys_info.h> -#include <mach/am33xx-generic.h> -#include <mach/gpmc.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/am33xx-clock.h> +#include <mach/omap/emif4.h> +#include <mach/omap/generic.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/gpmc.h> #include <reset_source.h> static void __noreturn am33xx_restart_soc(struct restart_handler *rst) @@ -153,8 +153,7 @@ static int am33xx_bootsource(void) default: src = BOOTSOURCE_UNKNOWN; } - bootsource_set(src); - bootsource_set_instance(instance); + bootsource_set_raw(src, instance); return 0; } @@ -420,7 +419,7 @@ void am33xx_select_rmii2_crs_dv(void) int am33xx_of_register_bootdevice(void) { - struct device_d *dev; + struct device *dev; switch (bootsource_get()) { case BOOTSOURCE_MMC: diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c index cc96ced18e..3192e332c6 100644 --- a/arch/arm/mach-omap/am33xx_mux.c +++ b/arch/arm/mach-omap/am33xx_mux.c @@ -15,8 +15,8 @@ #include <common.h> #include <config.h> #include <asm/io.h> -#include <mach/am33xx-mux.h> -#include <mach/am33xx-silicon.h> +#include <mach/omap/am33xx-mux.h> +#include <mach/omap/am33xx-silicon.h> #define MUX_CFG(value, offset) \ __raw_writel(value, (AM33XX_CTRL_BASE + offset)); diff --git a/arch/arm/mach-omap/am33xx_scrm.c b/arch/arm/mach-omap/am33xx_scrm.c index e10e80ce31..431e72fdda 100644 --- a/arch/arm/mach-omap/am33xx_scrm.c +++ b/arch/arm/mach-omap/am33xx_scrm.c @@ -20,10 +20,10 @@ #include <of.h> #include <asm/barebox-arm.h> #include <asm/memory.h> -#include <mach/am33xx-silicon.h> -#include <mach/emif4.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/emif4.h> -static int am33xx_scrm_probe(struct device_d *dev) +static int am33xx_scrm_probe(struct device *dev) { return arm_add_mem_device("ram0", 0x80000000, emif4_sdram_size(IOMEM(AM33XX_EMIF4_BASE))); @@ -36,8 +36,9 @@ static __maybe_unused struct of_device_id am33xx_scrm_dt_ids[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, am33xx_scrm_dt_ids); -static struct driver_d am33xx_scrm_driver = { +static struct driver am33xx_scrm_driver = { .name = "am33xx-scrm", .probe = am33xx_scrm_probe, .of_compatible = DRV_OF_COMPAT(am33xx_scrm_dt_ids), diff --git a/arch/arm/mach-omap/am3xxx.c b/arch/arm/mach-omap/am3xxx.c index 60a6e4b825..faf230a027 100644 --- a/arch/arm/mach-omap/am3xxx.c +++ b/arch/arm/mach-omap/am3xxx.c @@ -2,7 +2,7 @@ #include <common.h> #include <io.h> -#include <mach/am3xxx-silicon.h> +#include <mach/omap/am3xxx-silicon.h> /* UART Defines */ #define UART_SYSCFG_OFFSET 0x54 diff --git a/arch/arm/mach-omap/boot_order.c b/arch/arm/mach-omap/boot_order.c index 4b74fdba66..4fed99743f 100644 --- a/arch/arm/mach-omap/boot_order.c +++ b/arch/arm/mach-omap/boot_order.c @@ -15,7 +15,7 @@ #include <common.h> #include <command.h> #include <complete.h> -#include <mach/omap4-silicon.h> +#include <mach/omap/omap4-silicon.h> struct bootsrc { const char *name; diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c index c4ddc951fe..1cfba5af71 100644 --- a/arch/arm/mach-omap/devices-gpmc-nand.c +++ b/arch/arm/mach-omap/devices-gpmc-nand.c @@ -24,8 +24,8 @@ #include <clock.h> #include <io.h> -#include <mach/gpmc.h> -#include <mach/gpmc_nand.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/gpmc_nand.h> #define GPMC_CONF1_VALx8 0x00000800 #define GPMC_CONF1_VALx16 0x00001800 diff --git a/arch/arm/mach-omap/emif4.c b/arch/arm/mach-omap/emif4.c index b5a53e8c63..db16d6c760 100644 --- a/arch/arm/mach-omap/emif4.c +++ b/arch/arm/mach-omap/emif4.c @@ -11,7 +11,7 @@ #include <common.h> #include <io.h> -#include <mach/emif4.h> +#include <mach/omap/emif4.h> /* * AM35xx configuration values diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c index 07eeae1ace..1cee845012 100644 --- a/arch/arm/mach-omap/gpmc.c +++ b/arch/arm/mach-omap/gpmc.c @@ -24,13 +24,13 @@ #include <init.h> #include <io.h> #include <errno.h> -#include <mach/omap3-silicon.h> -#include <mach/omap4-silicon.h> -#include <mach/am33xx-silicon.h> -#include <mach/gpmc.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/generic.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/generic.h> /** * @brief Do a Generic initialization of GPMC. if you choose otherwise, diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h deleted file mode 100644 index b0293db990..0000000000 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef _AM33XX_CLOCKS_H_ -#define _AM33XX_CLOCKS_H_ - -#include "am33xx-silicon.h" - -/* Put the pll config values over here */ - -/* MAIN PLL Fdll = 1 GHZ, */ -#define MPUPLL_M_500 500 /* 125 * n */ -#define MPUPLL_M_550 550 /* 125 * n */ -#define MPUPLL_M_600 600 /* 125 * n */ -#define MPUPLL_M_720 720 /* 125 * n */ -#define MPUPLL_M_800 800 -#define MPUPLL_M_1000 1000 - -#define MPUPLL_M2 1 - -/* Core PLL Fdll = 1 GHZ, */ -#define COREPLL_M 1000 /* 125 * n */ - -#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ -#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ -#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ - -/* - * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll - * frequency needs to be set to 960 MHZ. Hence, - * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below - */ -#define PERPLL_M 960 -#define PERPLL_M2 5 - -/* DDR Freq is 266 MHZ for now*/ -/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ -#define DDRPLL_M_200 200 -#define DDRPLL_M_266 266 -#define DDRPLL_M_303 303 -#define DDRPLL_M_400 400 -#define DDRPLL_N (OSC - 1) -#define DDRPLL_M2 1 - -/* PRCM */ -/* Module Offsets */ -#define CM_PER (AM33XX_PRM_BASE + 0x0) -#define CM_WKUP (AM33XX_PRM_BASE + 0x400) -#define CM_DPLL (AM33XX_PRM_BASE + 0x500) -#define CM_DEVICE (AM33XX_PRM_BASE + 0x0700) -#define CM_CEFUSE (AM33XX_PRM_BASE + 0x0A00) -#define PRM_DEVICE (AM33XX_PRM_BASE + 0x0F00) -/* Register Offsets */ -/* Core PLL ADPLLS */ -#define CM_CLKSEL_DPLL_CORE (CM_WKUP + 0x68) -#define CM_CLKMODE_DPLL_CORE (CM_WKUP + 0x90) - -/* Core HSDIV */ -#define CM_DIV_M4_DPLL_CORE (CM_WKUP + 0x80) -#define CM_DIV_M5_DPLL_CORE (CM_WKUP + 0x84) -#define CM_DIV_M6_DPLL_CORE (CM_WKUP + 0xD8) -#define CM_IDLEST_DPLL_CORE (CM_WKUP + 0x5c) - -/* Peripheral PLL */ -#define CM_CLKSEL_DPLL_PER (CM_WKUP + 0x9c) -#define CM_CLKMODE_DPLL_PER (CM_WKUP + 0x8c) -#define CM_DIV_M2_DPLL_PER (CM_WKUP + 0xAC) -#define CM_IDLEST_DPLL_PER (CM_WKUP + 0x70) -#define CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x7C) /* for USB_PHY clock */ - -/* Display PLL */ -#define CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x54) -#define CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x98) -#define CM_DIV_M2_DPLL_DISP (CM_WKUP + 0xA4) - -/* DDR PLL */ -#define CM_CLKSEL_DPLL_DDR (CM_WKUP + 0x40) -#define CM_CLKMODE_DPLL_DDR (CM_WKUP + 0x94) -#define CM_DIV_M2_DPLL_DDR (CM_WKUP + 0xA0) -#define CM_IDLEST_DPLL_DDR (CM_WKUP + 0x34) - -/* MPU PLL */ -#define CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x2c) -#define CM_CLKMODE_DPLL_MPU (CM_WKUP + 0x88) -#define CM_DIV_M2_DPLL_MPU (CM_WKUP + 0xA8) -#define CM_IDLEST_DPLL_MPU (CM_WKUP + 0x20) - -/* TIMER Clock Source Select */ -#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x8) - -/* Interconnect clocks */ -#define CM_PER_L4LS_CLKCTRL (CM_PER + 0x60) /* EMIF */ -#define CM_PER_L4FW_CLKCTRL (CM_PER + 0x64) /* EMIF FW */ -#define CM_PER_L3_CLKCTRL (CM_PER + 0xE0) /* OCMC RAM */ -#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0xDC) -#define CM_PER_L4HS_CLKCTRL (CM_PER + 0x120) -#define CM_WKUP_L4WKUP_CLKCTRL (CM_WKUP + 0x0c)/* UART0 */ - -/* Domain Wake UP */ -#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0) /* UART0 */ -#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x0) /* TIMER2 */ -#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x0c) /* EMIF */ -#define CM_PER_L4FW_CLKSTCTRL (CM_PER + 0x08) /* EMIF FW */ -#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x4) -#define CM_PER_L4HS_CLKSTCTRL (CM_PER + 0x011c) -#define CM_CEFUSE_CLKSTCTRL (CM_CEFUSE + 0x0) - -/* Module Enable Registers */ -#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x80) /* Timer2 */ -#define CM_WKUP_UART0_CLKCTRL (CM_WKUP + 0xB4)/* UART0 */ -#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x4) /* Control Module */ -#define CM_PER_EMIF_CLKCTRL (CM_PER + 0x28) /* EMIF */ -#define CM_PER_EMIF_FW_CLKCTRL (CM_PER + 0xD0) /* EMIF FW */ -#define CM_PER_GPMC_CLKCTRL (CM_PER + 0x30) /* GPMC */ -#define CM_PER_ELM_CLKCTRL (CM_PER + 0x40) /* ELM */ -#define CM_PER_SPI0_CLKCTRL (CM_PER + 0x4c) /* SPI0 */ -#define CM_PER_SPI1_CLKCTRL (CM_PER + 0x50) /* SPI1 */ -#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0xB8) /* I2C0 */ -#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x14) /* Ethernet */ -#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144)/* Ethernet */ -#define CM_PER_OCMCRAM_CLKCTRL (CM_PER + 0x2C) /* OCMC RAM */ -#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0xAC) /* GPIO1 */ -#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0xB0) /* GPIO2 */ -#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0xB4) /* GPIO3 */ -#define CM_PER_UART1_CLKCTRL (CM_PER + 0x6C) /* UART1 */ -#define CM_PER_UART2_CLKCTRL (CM_PER + 0x70) /* UART2 */ -#define CM_PER_UART3_CLKCTRL (CM_PER + 0x74) /* UART3 */ -#define CM_PER_UART4_CLKCTRL (CM_PER + 0x78) /* UART4 */ -#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */ -#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */ -#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x8) /* GPIO0 */ -#define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0xbc)/* TSCADC */ - -#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x3C) -#define CM_PER_MMC1_CLKCTRL (CM_PER + 0xF4) -#define CM_PER_MMC2_CLKCTRL (CM_PER + 0xF8) -#define CM_PER_USB0_CLKCTRL (CM_PER + 0x1c) /* USB */ - -/* PRCM */ -#define CM_DPLL_OFFSET (AM33XX_PRM_BASE + 0x0300) - -#define CM_ALWON_WDTIMER_CLKCTRL (AM33XX_PRM_BASE + 0x158C) -#define CM_ALWON_SPI_CLKCTRL (AM33XX_PRM_BASE + 0x1590) -#define CM_ALWON_CONTROL_CLKCTRL (AM33XX_PRM_BASE + 0x15C4) - -#define CM_ALWON_L3_SLOW_CLKSTCTRL (AM33XX_PRM_BASE + 0x1400) - -#define CM_ALWON_GPIO_0_CLKCTRL (AM33XX_PRM_BASE + 0x155c) -#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (AM33XX_PRM_BASE + 0x155c) - -/* Ethernet */ -#define CM_ETHERNET_CLKSTCTRL (AM33XX_PRM_BASE + 0x1404) -#define CM_ALWON_ETHERNET_0_CLKCTRL (AM33XX_PRM_BASE + 0x15D4) -#define CM_ALWON_ETHERNET_1_CLKCTRL (AM33XX_PRM_BASE + 0x15D8) - -/* UARTs */ -#define CM_ALWON_UART_0_CLKCTRL (AM33XX_PRM_BASE + 0x1550) -#define CM_ALWON_UART_1_CLKCTRL (AM33XX_PRM_BASE + 0x1554) -#define CM_ALWON_UART_2_CLKCTRL (AM33XX_PRM_BASE + 0x1558) - -/* I2C */ -/* Note: In ti814x I2C0 and I2C2 have common clk control */ -#define CM_ALWON_I2C_0_CLKCTRL (AM33XX_PRM_BASE + 0x1564) - -/* EMIF4 PRCM Defintion */ -#define CM_DEFAULT_L3_FAST_CLKSTCTRL (AM33XX_PRM_BASE + 0x0508) -#define CM_DEFAULT_EMIF_0_CLKCTRL (AM33XX_PRM_BASE + 0x0520) -#define CM_DEFAULT_EMIF_1_CLKCTRL (AM33XX_PRM_BASE + 0x0524) -#define CM_DEFAULT_DMM_CLKCTRL (AM33XX_PRM_BASE + 0x0528) -#define CM_DEFAULT_FW_CLKCTRL (AM33XX_PRM_BASE + 0x052C) - -/* ALWON PRCM */ -#define CM_ALWON_OCMC_0_CLKSTCTRL CM_PER_L3_CLKSTCTRL -#define CM_ALWON_OCMC_0_CLKCTRL CM_PER_OCMCRAM_CLKCTRL - -#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL - -void am33xx_pll_init(int mpupll_M, int ddrpll_M); -void am33xx_enable_ddr_clocks(void); -int am33xx_get_osc_clock(void); - -#endif /* endif _AM33XX_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/am33xx-generic.h b/arch/arm/mach-omap/include/mach/am33xx-generic.h deleted file mode 100644 index e146bf0909..0000000000 --- a/arch/arm/mach-omap/include/mach/am33xx-generic.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_AM33XX_GENERIC_H -#define __MACH_AM33XX_GENERIC_H - -#include <string.h> -#include <mach/generic.h> -#include <mach/am33xx-silicon.h> - -int am33xx_register_ethaddr(int eth_id, int mac_id); - -u32 am33xx_get_cpu_rev(void); - -static inline void am33xx_save_bootinfo(uint32_t *info) -{ - unsigned long i = (unsigned long)info; - uint32_t *scratch = (void *)AM33XX_SRAM_SCRATCH_SPACE; - - if (i & 0x3) - return; - if (i < AM33XX_SRAM0_START) - return; - if (i > AM33XX_SRAM0_START + AM33XX_SRAM0_SIZE) - return; - - memcpy(scratch, info, 3 * sizeof(uint32_t)); -} - -u32 am33xx_running_in_flash(void); -u32 am33xx_running_in_sram(void); -u32 am33xx_running_in_sdram(void); - -void am33xx_enable_per_clocks(void); -int am33xx_init(void); -int am33xx_devices_init(void); -void am33xx_select_rmii2_crs_dv(void); -int am33xx_of_register_bootdevice(void); - -#endif /* __MACH_AM33XX_GENERIC_H */ diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h b/arch/arm/mach-omap/include/mach/am33xx-mux.h deleted file mode 100644 index af9f14dd5b..0000000000 --- a/arch/arm/mach-omap/include/mach/am33xx-mux.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __AM33XX_MUX_H__ -#define __AM33XX_MUX_H__ - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 6) -#define RXACTIVE (0x1 << 5) -#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) val - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -/* TODO replace with defines */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; - int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; - int rsvd1; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int pmic_power_en; - int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; - int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; - int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; - int ddr_a0; - int ddr_a1; - int ddr_a2; - int ddr_a3; - int ddr_a4; - int ddr_a5; - int ddr_a6; - int ddr_a7; - int ddr_a8; - int ddr_a9; - int ddr_a10; - int ddr_a11; - int ddr_a12; - int ddr_a13; - int ddr_a14; - int ddr_a15; - int ddr_odt; - int ddr_d0; - int ddr_d1; - int ddr_d2; - int ddr_d3; - int ddr_d4; - int ddr_d5; - int ddr_d6; - int ddr_d7; - int ddr_d8; - int ddr_d9; - int ddr_d10; - int ddr_d11; - int ddr_d12; - int ddr_d13; - int ddr_d14; - int ddr_d15; - int ddr_dqm0; - int ddr_dqm1; - int ddr_dqs0; - int ddr_dqsn0; - int ddr_dqs1; - int ddr_dqsn1; - int ddr_vref; - int ddr_vtp; - int ddr_strben0; - int ddr_strben1; - int ain7; - int ain6; - int ain5; - int ain4; - int ain3; - int ain2; - int ain1; - int ain0; - int vrefp; - int vrefn; -}; - -struct module_pin_mux { - short reg_offset; - unsigned char val; -}; - -#define PAD_CTRL_BASE 0x800 -#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ - (PAD_CTRL_BASE))->x) - -extern void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux); - -/* Standard mux settings */ -extern void am33xx_enable_mii1_pin_mux(void); -extern void am33xx_enable_rmii1_pin_mux(void); -extern void am33xx_enable_rmii2_pin_mux(void); -extern void am33xx_enable_i2c0_pin_mux(void); -extern void am33xx_enable_i2c1_pin_mux(void); -extern void am33xx_enable_i2c2_pin_mux(void); -extern void am33xx_enable_uart0_pin_mux(void); -extern void am33xx_enable_uart1_pin_mux(void); -extern void am33xx_enable_uart2_pin_mux(void); -extern void am33xx_enable_mmc0_pin_mux(void); -extern void am33xx_enable_spi0_pin_mux(void); -extern void am33xx_enable_nand_pin_mux(void); - -#endif /*__AM33XX_MUX_H__ */ diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h deleted file mode 100644 index 74b0b7638e..0000000000 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * This file contains the address info for various AM33XX modules. - * - * Copyright (C) 2012 Teresa Gámez <t.gamez@phytec.de>, - * Phytec Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_AM33XX_H -#define __ASM_ARCH_AM33XX_H - -#include <linux/sizes.h> - -/** AM335x Internal Bus Base addresses */ -#define AM33XX_L4_WKUP_BASE 0x44C00000 -#define AM33XX_L4_PER_BASE 0x48000000 -#define AM33XX_L4_FAST_BASE 0x4A000000 - -/* the device numbering is the same as in the TRM memory map (SPRUH73G) */ - -/* UART */ -#define AM33XX_UART0_BASE (AM33XX_L4_WKUP_BASE + 0x209000) -#define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000) -#define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000) - -/* GPIO */ -#define AM33XX_GPIO0_BASE (AM33XX_L4_WKUP_BASE + 0x207000 + 0x100) -#define AM33XX_GPIO1_BASE (AM33XX_L4_PER_BASE + 0x4C000 + 0x100) -#define AM33XX_GPIO2_BASE (AM33XX_L4_PER_BASE + 0x1AC000 + 0x100) -#define AM33XX_GPIO3_BASE (AM33XX_L4_PER_BASE + 0x1AE000 + 0x100) - -#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000 -#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000 - -/* I2C */ -#define AM33XX_I2C0_BASE (AM33XX_L4_WKUP_BASE + 0x20B000) -#define AM33XX_I2C1_BASE (AM33XX_L4_PER_BASE + 0x02A000) -#define AM33XX_I2C2_BASE (AM33XX_L4_PER_BASE + 0x19C000) - -/* GPMC */ -#define AM33XX_GPMC_BASE 0x50000000 - -/* MMC */ -#define AM33XX_MMCHS0_BASE (AM33XX_L4_PER_BASE + 0x60000) -#define AM33XX_MMC1_BASE (AM33XX_L4_PER_BASE + 0x1D8000) -#define AM33XX_MMCHS2_BASE 0x47810000 - -/* SPI */ -#define AM33XX_MCSPI0_BASE (AM33XX_L4_PER_BASE + 0x30000) -#define AM33XX_MCSPI1_BASE (AM33XX_L4_PER_BASE + 0x1A0000) - -/* DTMTimer0 */ -#define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000) -/* DMTIimer2 */ -#define AM33XX_DMTIMER2_BASE (AM33XX_L4_PER_BASE + 0x40000) -#define AM33XX_CM_DPLL (AM33XX_L4_WKUP_BASE + 0x200500) - -/* PRM */ -#define AM33XX_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000) - -#define AM33XX_PRM_RSTCTRL (AM33XX_PRM_BASE + 0x0f00) -#define AM33XX_PRM_RSTCTRL_RESET 0x1 -#define AM33XX_PRM_RSTTIME (AM33XX_PRM_BASE + 0x0f04) -#define AM33XX_PRM_RSTST (AM33XX_PRM_BASE + 0x0f08) - -/* CTRL */ -#define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000) -#define AM33XX_IDCODE_REG (AM33XX_CTRL_BASE + 0x600) -#define AM33XX_CTRL_STATUS (AM33XX_CTRL_BASE + 0x40) - -/* Watchdog Timer */ -#define AM33XX_WDT_BASE 0x44E35000 - -/* EMIF Base address */ -#define AM33XX_EMIF4_BASE 0x4c000000 - -#define AM33XX_DMM_BASE 0x4E000000 - -#define AM335X_CPSW_BASE 0x4A100000 -#define AM335X_CPSW_MDIO_BASE 0x4A101000 - -/*DMM & EMIF4 MMR Declaration*/ -#define AM33XX_DMM_LISA_MAP__0 (AM33XX_DMM_BASE + 0x40) -#define AM33XX_DMM_LISA_MAP__1 (AM33XX_DMM_BASE + 0x44) -#define AM33XX_DMM_LISA_MAP__2 (AM33XX_DMM_BASE + 0x48) -#define AM33XX_DMM_LISA_MAP__3 (AM33XX_DMM_BASE + 0x4C) -#define AM33XX_DMM_PAT_BASE_ADDR (AM33XX_DMM_BASE + 0x460) - -#define AM33XX_VTP0_CTRL_REG 0x44E10E0C -#define AM33XX_VTP1_CTRL_REG 0x48140E10 - -/* OCMC */ -#define AM33XX_SRAM0_START 0x402f0400 -#define AM33XX_SRAM0_SIZE (SZ_128K - SZ_1K) -#define AM33XX_SRAM_SCRATCH_SPACE 0x4030b800 /* start of public stack */ -#define AM33XX_SRAM_GPMC_STACK_SIZE (0x40) - -/* DDR offsets */ -#define AM33XX_DDR_PHY_BASE_ADDR 0x44E12000 -#define AM33XX_CONTROL_BASE_ADDR 0x44E10000 - -#define AM33XX_DDR_IO_CTRL (AM33XX_CONTROL_BASE_ADDR + 0x0E04) -#define AM33XX_DDR_CKE_CTRL (AM33XX_CONTROL_BASE_ADDR + 0x131C) -#define AM33XX_DDR_CMD0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1404) -#define AM33XX_DDR_CMD1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1408) -#define AM33XX_DDR_CMD2_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x140C) -#define AM33XX_DDR_DATA0_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1440) -#define AM33XX_DDR_DATA1_IOCTRL (AM33XX_CONTROL_BASE_ADDR + 0x1444) - -#define AM33XX_CMD0_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x01C) -#define AM33XX_CMD0_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x020) -#define AM33XX_CMD0_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x024) -#define AM33XX_CMD0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x028) -#define AM33XX_CMD0_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x02C) - -#define AM33XX_CMD1_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x050) -#define AM33XX_CMD1_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x054) -#define AM33XX_CMD1_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x058) -#define AM33XX_CMD1_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x05C) -#define AM33XX_CMD1_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x060) - -#define AM33XX_CMD2_CTRL_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x084) -#define AM33XX_CMD2_CTRL_SLAVE_FORCE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x088) -#define AM33XX_CMD2_CTRL_SLAVE_DELAY_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x08C) -#define AM33XX_CMD2_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x090) -#define AM33XX_CMD2_INVERT_CLKOUT_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x094) - -#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0C8) -#define AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0CC) -#define AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0DC) - -#define AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0E0) -#define AM33XX_DATA0_WRLVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F0) - -#define AM33XX_DATA0_WRLVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F4) -#define AM33XX_DATA0_WRLVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F8) -#define AM33XX_DATA0_GATELVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0FC) - -#define AM33XX_DATA0_GATELVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x100) -#define AM33XX_DATA0_GATELVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x104) -#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x108) - -#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x10C) -#define AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x120) - -#define AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x124) -#define AM33XX_DATA0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x138) - -#define AM33XX_DATA0_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x134) - -#define AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x16C) -#define AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x180) - -#define AM33XX_DATA1_WRLVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x19C) -#define AM33XX_DATA1_GATELVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1A8) - -#define AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1AC) -#define AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1C4) - -#define AM33XX_DATA1_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1D8) - -/* Ethernet MAC ID from EFuse */ -#define AM33XX_MAC_ID0_LO (AM33XX_CTRL_BASE + 0x630) -#define AM33XX_MAC_ID0_HI (AM33XX_CTRL_BASE + 0x634) -#define AM33XX_MAC_ID1_LO (AM33XX_CTRL_BASE + 0x638) -#define AM33XX_MAC_ID1_HI (AM33XX_CTRL_BASE + 0x63c) -#define AM33XX_MAC_MII_SEL (AM33XX_CTRL_BASE + 0x650) - -#define AM33XX_EFUSE_SMA (AM33XX_CTRL_BASE + 0x7fc) - -struct am33xx_cmd_control { - u32 slave_ratio0; - u32 dll_lock_diff0; - u32 invert_clkout0; - u32 slave_ratio1; - u32 dll_lock_diff1; - u32 invert_clkout1; - u32 slave_ratio2; - u32 dll_lock_diff2; - u32 invert_clkout2; -}; - -struct am33xx_emif_regs { - u32 emif_read_latency; - u32 emif_tim1; - u32 emif_tim2; - u32 emif_tim3; - u32 ocp_config; - u32 sdram_config; - u32 sdram_config2; - u32 zq_config; - u32 sdram_ref_ctrl; -}; - -struct am33xx_ddr_data { - u32 rd_slave_ratio0; - u32 wr_dqs_slave_ratio0; - u32 wrlvl_init_ratio0; - u32 gatelvl_init_ratio0; - u32 fifo_we_slave_ratio0; - u32 wr_slave_ratio0; - u32 use_rank0_delay; - u32 dll_lock_diff0; -}; - -void am33xx_uart_soft_reset(void __iomem *uart_base); -void am33xx_config_vtp(void); -void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl); -void am33xx_config_io_ctrl(int ioctrl); -void am33xx_config_sdram(const struct am33xx_emif_regs *regs); -void am33xx_config_ddr_data(const struct am33xx_ddr_data *data, int macronr); -void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl, - const struct am33xx_emif_regs *emif_regs, - const struct am33xx_ddr_data *ddr_data); -void am335x_barebox_entry(void *boarddata); - -#endif diff --git a/arch/arm/mach-omap/include/mach/am3xxx-silicon.h b/arch/arm/mach-omap/include/mach/am3xxx-silicon.h deleted file mode 100644 index dba3d634d5..0000000000 --- a/arch/arm/mach-omap/include/mach/am3xxx-silicon.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_ARCH_AM33XX_H -#define __ASM_ARCH_AM33XX_H - -void am3xxx_uart_soft_reset(void __iomem *uart_base); - -#endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/mach-omap/include/mach/bbu.h b/arch/arm/mach-omap/include/mach/bbu.h deleted file mode 100644 index 5ca7ec43cc..0000000000 --- a/arch/arm/mach-omap/include/mach/bbu.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_BBU_H -#define __MACH_BBU_H - -#include <bbu.h> - -#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO -int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile); -#else -static inline int am33xx_bbu_spi_nor_mlo_register_handler(const char *name, char *devicefile) -{ - return 0; -} -#endif - -static inline int am33xx_bbu_spi_nor_register_handler(const char *name, char *devicefile) -{ - return bbu_register_std_file_update(name, 0, devicefile, filetype_arm_barebox); -} - -#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_NAND -int am33xx_bbu_nand_xloadslots_register_handler(const char *name, - char **devicefile, - int num_devicefiles); -int am33xx_bbu_nand_slots_register_handler(const char *name, char **devicefile, - int num_devicefiles); -int am33xx_bbu_nand_register_handler(const char *device); -#else -static inline int am33xx_bbu_nand_xloadslots_register_handler(const char *name, - char **devicefile, - int num_devicefiles) -{ - return 0; -} - -static inline int am33xx_bbu_nand_slots_register_handler(const char *name, - char **devicefile, - int num_devicefiles) -{ - return 0; -} - -static inline int am33xx_bbu_nand_register_handler(const char *device) -{ - return 0; -} -#endif - -#ifdef CONFIG_BAREBOX_UPDATE_AM33XX_EMMC -int am33xx_bbu_emmc_mlo_register_handler(const char *name, char *devicefile); -int am33xx_bbu_emmc_register_handler(const char *name, char *devicefile); -#else -static inline int am33xx_bbu_emmc_mlo_register_handler(const char *name, - char *devicefile) -{ - return 0; -} - -static inline int am33xx_bbu_emmc_register_handler(const char *name, - char *devicefile) -{ - return 0; -} -#endif - - -#endif diff --git a/arch/arm/mach-omap/include/mach/clocks.h b/arch/arm/mach-omap/include/mach/clocks.h deleted file mode 100644 index e44d98b914..0000000000 --- a/arch/arm/mach-omap/include/mach/clocks.h +++ /dev/null @@ -1,37 +0,0 @@ -/** - * @file - * @brief Generic Clock wrapper header. - * - * This includes each of the architecture Clock definitions under it. - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __OMAP_CLOCKS_H_ -#define __OMAP_CLOCKS_H_ - -#define LDELAY 12000000 - -/* Standard defines for Various clocks */ -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#endif /* __OMAP_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h b/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h deleted file mode 100644 index 16a0201328..0000000000 --- a/arch/arm/mach-omap/include/mach/cm-regbits-34xx.h +++ /dev/null @@ -1,799 +0,0 @@ -#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H -#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H - -/* - * OMAP3430 Clock Management register bits - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/* Bits shared between registers */ - -/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ -#define OMAP3430ES2_EN_MMC3_MASK (1 << 30) -#define OMAP3430ES2_EN_MMC3_SHIFT 30 -#define OMAP3430_EN_MSPRO_MASK (1 << 23) -#define OMAP3430_EN_MSPRO_SHIFT 23 -#define OMAP3430_EN_HDQ_MASK (1 << 22) -#define OMAP3430_EN_HDQ_SHIFT 22 -#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) -#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 -#define OMAP3430ES1_EN_D2D_MASK (1 << 3) -#define OMAP3430ES1_EN_D2D_SHIFT 3 -#define OMAP3430_EN_SSI_MASK (1 << 0) -#define OMAP3430_EN_SSI_SHIFT 0 - -/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ -#define OMAP3430ES2_EN_USBTLL_SHIFT 2 -#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) - -/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ -#define OMAP3430_EN_WDT2_MASK (1 << 5) -#define OMAP3430_EN_WDT2_SHIFT 5 - -/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ -#define OMAP3430_EN_CAM_MASK (1 << 0) -#define OMAP3430_EN_CAM_SHIFT 0 - -/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ -#define OMAP3430_EN_WDT3_MASK (1 << 12) -#define OMAP3430_EN_WDT3_SHIFT 12 - -/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ -#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) - - -/* Bits specific to each register */ - -/* CM_FCLKEN_IVA2 */ -#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) -#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 - -/* CM_CLKEN_PLL_IVA2 */ -#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 -#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_IVA2_DPLL_SHIFT 0 -#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_IVA2 */ -#define OMAP3430_ST_IVA2_MASK (1 << 0) - -/* CM_IDLEST_PLL_IVA2 */ -#define OMAP3430_ST_IVA2_CLK_SHIFT 0 -#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL_IVA2 */ -#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 -#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL_IVA2 */ -#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) -#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 -#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 -#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL2_PLL_IVA2 */ -#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* CM_CLKSTCTRL_IVA2 */ -#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 -#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) - -/* CM_CLKSTST_IVA2 */ -#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 -#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) - -/* CM_REVISION specific bits */ - -/* CM_SYSCONFIG specific bits */ - -/* CM_CLKEN_PLL_MPU */ -#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 -#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_MPU_DPLL_SHIFT 0 -#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_MPU */ -#define OMAP3430_ST_MPU_MASK (1 << 0) - -/* CM_IDLEST_PLL_MPU */ -#define OMAP3430_ST_MPU_CLK_SHIFT 0 -#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL_MPU */ -#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 -#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL_MPU */ -#define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) -#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 -#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 -#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL2_PLL_MPU */ -#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* CM_CLKSTCTRL_MPU */ -#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 -#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) - -/* CM_CLKSTST_MPU */ -#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 -#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) - -/* CM_FCLKEN1_CORE specific bits */ -#define OMAP3430_EN_MODEM_MASK (1 << 31) -#define OMAP3430_EN_MODEM_SHIFT 31 - -/* CM_ICLKEN1_CORE specific bits */ -#define OMAP3430_EN_ICR_MASK (1 << 29) -#define OMAP3430_EN_ICR_SHIFT 29 -#define OMAP3430_EN_AES2_MASK (1 << 28) -#define OMAP3430_EN_AES2_SHIFT 28 -#define OMAP3430_EN_SHA12_MASK (1 << 27) -#define OMAP3430_EN_SHA12_SHIFT 27 -#define OMAP3430_EN_DES2_MASK (1 << 26) -#define OMAP3430_EN_DES2_SHIFT 26 -#define OMAP3430ES1_EN_FAC_MASK (1 << 8) -#define OMAP3430ES1_EN_FAC_SHIFT 8 -#define OMAP3430_EN_MAILBOXES_MASK (1 << 7) -#define OMAP3430_EN_MAILBOXES_SHIFT 7 -#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) -#define OMAP3430_EN_OMAPCTRL_SHIFT 6 -#define OMAP3430_EN_SAD2D_MASK (1 << 3) -#define OMAP3430_EN_SAD2D_SHIFT 3 -#define OMAP3430_EN_SDRC_MASK (1 << 1) -#define OMAP3430_EN_SDRC_SHIFT 1 - -/* AM35XX specific CM_ICLKEN1_CORE bits */ -#define AM35XX_EN_IPSS_MASK (1 << 4) -#define AM35XX_EN_IPSS_SHIFT 4 -#define AM35XX_EN_UART4_MASK (1 << 23) -#define AM35XX_EN_UART4_SHIFT 23 - -/* CM_ICLKEN2_CORE */ -#define OMAP3430_EN_PKA_MASK (1 << 4) -#define OMAP3430_EN_PKA_SHIFT 4 -#define OMAP3430_EN_AES1_MASK (1 << 3) -#define OMAP3430_EN_AES1_SHIFT 3 -#define OMAP3430_EN_RNG_MASK (1 << 2) -#define OMAP3430_EN_RNG_SHIFT 2 -#define OMAP3430_EN_SHA11_MASK (1 << 1) -#define OMAP3430_EN_SHA11_SHIFT 1 -#define OMAP3430_EN_DES1_MASK (1 << 0) -#define OMAP3430_EN_DES1_SHIFT 0 - -/* CM_ICLKEN3_CORE */ -#define OMAP3430_EN_MAD2D_SHIFT 3 -#define OMAP3430_EN_MAD2D_MASK (1 << 3) - -/* CM_FCLKEN3_CORE specific bits */ -#define OMAP3430ES2_EN_TS_SHIFT 1 -#define OMAP3430ES2_EN_TS_MASK (1 << 1) -#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 -#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) - -/* CM_IDLEST1_CORE specific bits */ -#define OMAP3430ES2_ST_MMC3_SHIFT 30 -#define OMAP3430ES2_ST_MMC3_MASK (1 << 30) -#define OMAP3430_ST_ICR_SHIFT 29 -#define OMAP3430_ST_ICR_MASK (1 << 29) -#define OMAP3430_ST_AES2_SHIFT 28 -#define OMAP3430_ST_AES2_MASK (1 << 28) -#define OMAP3430_ST_SHA12_SHIFT 27 -#define OMAP3430_ST_SHA12_MASK (1 << 27) -#define OMAP3430_ST_DES2_SHIFT 26 -#define OMAP3430_ST_DES2_MASK (1 << 26) -#define OMAP3430_ST_MSPRO_SHIFT 23 -#define OMAP3430_ST_MSPRO_MASK (1 << 23) -#define OMAP3430_ST_HDQ_SHIFT 22 -#define OMAP3430_ST_HDQ_MASK (1 << 22) -#define OMAP3430ES1_ST_FAC_SHIFT 8 -#define OMAP3430ES1_ST_FAC_MASK (1 << 8) -#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 -#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) -#define OMAP3430_ST_MAILBOXES_SHIFT 7 -#define OMAP3430_ST_MAILBOXES_MASK (1 << 7) -#define OMAP3430_ST_OMAPCTRL_SHIFT 6 -#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) -#define OMAP3430_ST_SDMA_SHIFT 2 -#define OMAP3430_ST_SDMA_MASK (1 << 2) -#define OMAP3430_ST_SDRC_SHIFT 1 -#define OMAP3430_ST_SDRC_MASK (1 << 1) -#define OMAP3430_ST_SSI_STDBY_SHIFT 0 -#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) - -/* AM35xx specific CM_IDLEST1_CORE bits */ -#define AM35XX_ST_IPSS_SHIFT 5 -#define AM35XX_ST_IPSS_MASK (1 << 5) - -/* CM_IDLEST2_CORE */ -#define OMAP3430_ST_PKA_SHIFT 4 -#define OMAP3430_ST_PKA_MASK (1 << 4) -#define OMAP3430_ST_AES1_SHIFT 3 -#define OMAP3430_ST_AES1_MASK (1 << 3) -#define OMAP3430_ST_RNG_SHIFT 2 -#define OMAP3430_ST_RNG_MASK (1 << 2) -#define OMAP3430_ST_SHA11_SHIFT 1 -#define OMAP3430_ST_SHA11_MASK (1 << 1) -#define OMAP3430_ST_DES1_SHIFT 0 -#define OMAP3430_ST_DES1_MASK (1 << 0) - -/* CM_IDLEST3_CORE */ -#define OMAP3430ES2_ST_USBTLL_SHIFT 2 -#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) -#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 -#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) - -/* CM_AUTOIDLE1_CORE */ -#define OMAP3430_AUTO_MODEM_MASK (1 << 31) -#define OMAP3430_AUTO_MODEM_SHIFT 31 -#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) -#define OMAP3430ES2_AUTO_MMC3_SHIFT 30 -#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) -#define OMAP3430ES2_AUTO_ICR_SHIFT 29 -#define OMAP3430_AUTO_AES2_MASK (1 << 28) -#define OMAP3430_AUTO_AES2_SHIFT 28 -#define OMAP3430_AUTO_SHA12_MASK (1 << 27) -#define OMAP3430_AUTO_SHA12_SHIFT 27 -#define OMAP3430_AUTO_DES2_MASK (1 << 26) -#define OMAP3430_AUTO_DES2_SHIFT 26 -#define OMAP3430_AUTO_MMC2_MASK (1 << 25) -#define OMAP3430_AUTO_MMC2_SHIFT 25 -#define OMAP3430_AUTO_MMC1_MASK (1 << 24) -#define OMAP3430_AUTO_MMC1_SHIFT 24 -#define OMAP3430_AUTO_MSPRO_MASK (1 << 23) -#define OMAP3430_AUTO_MSPRO_SHIFT 23 -#define OMAP3430_AUTO_HDQ_MASK (1 << 22) -#define OMAP3430_AUTO_HDQ_SHIFT 22 -#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) -#define OMAP3430_AUTO_MCSPI4_SHIFT 21 -#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) -#define OMAP3430_AUTO_MCSPI3_SHIFT 20 -#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) -#define OMAP3430_AUTO_MCSPI2_SHIFT 19 -#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) -#define OMAP3430_AUTO_MCSPI1_SHIFT 18 -#define OMAP3430_AUTO_I2C3_MASK (1 << 17) -#define OMAP3430_AUTO_I2C3_SHIFT 17 -#define OMAP3430_AUTO_I2C2_MASK (1 << 16) -#define OMAP3430_AUTO_I2C2_SHIFT 16 -#define OMAP3430_AUTO_I2C1_MASK (1 << 15) -#define OMAP3430_AUTO_I2C1_SHIFT 15 -#define OMAP3430_AUTO_UART2_MASK (1 << 14) -#define OMAP3430_AUTO_UART2_SHIFT 14 -#define OMAP3430_AUTO_UART1_MASK (1 << 13) -#define OMAP3430_AUTO_UART1_SHIFT 13 -#define OMAP3430_AUTO_GPT11_MASK (1 << 12) -#define OMAP3430_AUTO_GPT11_SHIFT 12 -#define OMAP3430_AUTO_GPT10_MASK (1 << 11) -#define OMAP3430_AUTO_GPT10_SHIFT 11 -#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) -#define OMAP3430_AUTO_MCBSP5_SHIFT 10 -#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) -#define OMAP3430_AUTO_MCBSP1_SHIFT 9 -#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) -#define OMAP3430ES1_AUTO_FAC_SHIFT 8 -#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) -#define OMAP3430_AUTO_MAILBOXES_SHIFT 7 -#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) -#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 -#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) -#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 -#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) -#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 -#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) -#define OMAP3430ES1_AUTO_D2D_SHIFT 3 -#define OMAP3430_AUTO_SAD2D_MASK (1 << 3) -#define OMAP3430_AUTO_SAD2D_SHIFT 3 -#define OMAP3430_AUTO_SSI_MASK (1 << 0) -#define OMAP3430_AUTO_SSI_SHIFT 0 - -/* CM_AUTOIDLE2_CORE */ -#define OMAP3430_AUTO_PKA_MASK (1 << 4) -#define OMAP3430_AUTO_PKA_SHIFT 4 -#define OMAP3430_AUTO_AES1_MASK (1 << 3) -#define OMAP3430_AUTO_AES1_SHIFT 3 -#define OMAP3430_AUTO_RNG_MASK (1 << 2) -#define OMAP3430_AUTO_RNG_SHIFT 2 -#define OMAP3430_AUTO_SHA11_MASK (1 << 1) -#define OMAP3430_AUTO_SHA11_SHIFT 1 -#define OMAP3430_AUTO_DES1_MASK (1 << 0) -#define OMAP3430_AUTO_DES1_SHIFT 0 - -/* CM_AUTOIDLE3_CORE */ -#define OMAP3430ES2_AUTO_USBHOST (1 << 0) -#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 -#define OMAP3430ES2_AUTO_USBTLL (1 << 2) -#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 -#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) -#define OMAP3430_AUTO_MAD2D_SHIFT 3 -#define OMAP3430_AUTO_MAD2D_MASK (1 << 3) - -/* CM_CLKSEL_CORE */ -#define OMAP3430_CLKSEL_SSI_SHIFT 8 -#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) -#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT11_SHIFT 7 -#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT10_SHIFT 6 -#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 -#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) -#define OMAP3430_CLKSEL_L4_SHIFT 2 -#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) -#define OMAP3430_CLKSEL_L3_SHIFT 0 -#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) -#define OMAP3630_CLKSEL_96M_SHIFT 12 -#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) - -/* CM_CLKSTCTRL_CORE */ -#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 -#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) -#define OMAP3430_CLKTRCTRL_L4_SHIFT 2 -#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) -#define OMAP3430_CLKTRCTRL_L3_SHIFT 0 -#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) - -/* CM_CLKSTST_CORE */ -#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 -#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) -#define OMAP3430_CLKACTIVITY_L4_SHIFT 1 -#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) -#define OMAP3430_CLKACTIVITY_L3_SHIFT 0 -#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) - -/* CM_FCLKEN_GFX */ -#define OMAP3430ES1_EN_3D_MASK (1 << 2) -#define OMAP3430ES1_EN_3D_SHIFT 2 -#define OMAP3430ES1_EN_2D_MASK (1 << 1) -#define OMAP3430ES1_EN_2D_SHIFT 1 - -/* CM_ICLKEN_GFX specific bits */ - -/* CM_IDLEST_GFX specific bits */ - -/* CM_CLKSEL_GFX specific bits */ - -/* CM_SLEEPDEP_GFX specific bits */ - -/* CM_CLKSTCTRL_GFX */ -#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 -#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) - -/* CM_CLKSTST_GFX */ -#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 -#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) - -/* CM_FCLKEN_SGX */ -#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 -#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) - -/* CM_IDLEST_SGX */ -#define OMAP3430ES2_ST_SGX_SHIFT 1 -#define OMAP3430ES2_ST_SGX_MASK (1 << 1) - -/* CM_ICLKEN_SGX */ -#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 -#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) - -/* CM_CLKSEL_SGX */ -#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 -#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) - -/* CM_CLKSTCTRL_SGX */ -#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 -#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) - -/* CM_CLKSTST_SGX */ -#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 -#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) - -/* CM_FCLKEN_WKUP specific bits */ -#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 -#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) - -/* CM_ICLKEN_WKUP specific bits */ -#define OMAP3430_EN_WDT1_MASK (1 << 4) -#define OMAP3430_EN_WDT1_SHIFT 4 -#define OMAP3430_EN_32KSYNC_MASK (1 << 2) -#define OMAP3430_EN_32KSYNC_SHIFT 2 - -/* CM_IDLEST_WKUP specific bits */ -#define OMAP3430ES2_ST_USIMOCP_SHIFT 9 -#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) -#define OMAP3430_ST_WDT2_SHIFT 5 -#define OMAP3430_ST_WDT2_MASK (1 << 5) -#define OMAP3430_ST_WDT1_SHIFT 4 -#define OMAP3430_ST_WDT1_MASK (1 << 4) -#define OMAP3430_ST_32KSYNC_SHIFT 2 -#define OMAP3430_ST_32KSYNC_MASK (1 << 2) - -/* CM_AUTOIDLE_WKUP */ -#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) -#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 -#define OMAP3430_AUTO_WDT2_MASK (1 << 5) -#define OMAP3430_AUTO_WDT2_SHIFT 5 -#define OMAP3430_AUTO_WDT1_MASK (1 << 4) -#define OMAP3430_AUTO_WDT1_SHIFT 4 -#define OMAP3430_AUTO_GPIO1_MASK (1 << 3) -#define OMAP3430_AUTO_GPIO1_SHIFT 3 -#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) -#define OMAP3430_AUTO_32KSYNC_SHIFT 2 -#define OMAP3430_AUTO_GPT12_MASK (1 << 1) -#define OMAP3430_AUTO_GPT12_SHIFT 1 -#define OMAP3430_AUTO_GPT1_MASK (1 << 0) -#define OMAP3430_AUTO_GPT1_SHIFT 0 - -/* CM_CLKSEL_WKUP */ -#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) -#define OMAP3430_CLKSEL_RM_SHIFT 1 -#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) -#define OMAP3430_CLKSEL_GPT1_SHIFT 0 -#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) - -/* CM_CLKEN_PLL */ -#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 -#define OMAP3430_PWRDN_CAM_SHIFT 30 -#define OMAP3430_PWRDN_DSS1_SHIFT 29 -#define OMAP3430_PWRDN_TV_SHIFT 28 -#define OMAP3430_PWRDN_96M_SHIFT 27 -#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 -#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) -#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 -#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) -#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 -#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) -#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 -#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) -#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 -#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 -#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_CORE_DPLL_SHIFT 0 -#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) - -/* CM_CLKEN2_PLL */ -#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 -#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 -#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) -#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 -#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_CKGEN */ -#define OMAP3430_ST_54M_CLK_MASK (1 << 5) -#define OMAP3430_ST_12M_CLK_MASK (1 << 4) -#define OMAP3430_ST_48M_CLK_MASK (1 << 3) -#define OMAP3430_ST_96M_CLK_MASK (1 << 2) -#define OMAP3430_ST_PERIPH_CLK_SHIFT 1 -#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) -#define OMAP3430_ST_CORE_CLK_SHIFT 0 -#define OMAP3430_ST_CORE_CLK_MASK (1 << 0) - -/* CM_IDLEST2_CKGEN */ -#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 -#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) -#define OMAP3430ES2_ST_120M_CLK_SHIFT 1 -#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) -#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 -#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL */ -#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 -#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) -#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 -#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) - -/* CM_AUTOIDLE2_PLL */ -#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 -#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL */ -/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) -#define OMAP3430_CORE_DPLL_MULT_SHIFT 16 -#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) -#define OMAP3430_CORE_DPLL_DIV_SHIFT 8 -#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) -#define OMAP3430_SOURCE_96M_SHIFT 6 -#define OMAP3430_SOURCE_96M_MASK (1 << 6) -#define OMAP3430_SOURCE_54M_SHIFT 5 -#define OMAP3430_SOURCE_54M_MASK (1 << 5) -#define OMAP3430_SOURCE_48M_SHIFT 3 -#define OMAP3430_SOURCE_48M_MASK (1 << 3) - -/* CM_CLKSEL2_PLL */ -#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 -#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) -#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 -#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 -#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) -#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 -#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) - -/* CM_CLKSEL3_PLL */ -#define OMAP3430_DIV_96M_SHIFT 0 -#define OMAP3430_DIV_96M_MASK (0x1f << 0) -#define OMAP3630_DIV_96M_MASK (0x3f << 0) - -/* CM_CLKSEL4_PLL */ -#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 -#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 -#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL5_PLL */ -#define OMAP3430ES2_DIV_120M_SHIFT 0 -#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) - -/* CM_CLKOUT_CTRL */ -#define OMAP3430_CLKOUT2_EN_SHIFT 7 -#define OMAP3430_CLKOUT2_EN_MASK (1 << 7) -#define OMAP3430_CLKOUT2_DIV_SHIFT 3 -#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) -#define OMAP3430_CLKOUT2SOURCE_SHIFT 0 -#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) - -/* CM_FCLKEN_DSS */ -#define OMAP3430_EN_TV_MASK (1 << 2) -#define OMAP3430_EN_TV_SHIFT 2 -#define OMAP3430_EN_DSS2_MASK (1 << 1) -#define OMAP3430_EN_DSS2_SHIFT 1 -#define OMAP3430_EN_DSS1_MASK (1 << 0) -#define OMAP3430_EN_DSS1_SHIFT 0 - -/* CM_ICLKEN_DSS */ -#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) -#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 - -/* CM_IDLEST_DSS */ -#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) -#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 -#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) -#define OMAP3430ES1_ST_DSS_SHIFT 0 -#define OMAP3430ES1_ST_DSS_MASK (1 << 0) - -/* CM_AUTOIDLE_DSS */ -#define OMAP3430_AUTO_DSS_MASK (1 << 0) -#define OMAP3430_AUTO_DSS_SHIFT 0 - -/* CM_CLKSEL_DSS */ -#define OMAP3430_CLKSEL_TV_SHIFT 8 -#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) -#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) -#define OMAP3430_CLKSEL_DSS1_SHIFT 0 -#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) -#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) - -/* CM_SLEEPDEP_DSS specific bits */ - -/* CM_CLKSTCTRL_DSS */ -#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 -#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) - -/* CM_CLKSTST_DSS */ -#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 -#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) - -/* CM_FCLKEN_CAM specific bits */ -#define OMAP3430_EN_CSI2_MASK (1 << 1) -#define OMAP3430_EN_CSI2_SHIFT 1 - -/* CM_ICLKEN_CAM specific bits */ - -/* CM_IDLEST_CAM */ -#define OMAP3430_ST_CAM_MASK (1 << 0) - -/* CM_AUTOIDLE_CAM */ -#define OMAP3430_AUTO_CAM_MASK (1 << 0) -#define OMAP3430_AUTO_CAM_SHIFT 0 - -/* CM_CLKSEL_CAM */ -#define OMAP3430_CLKSEL_CAM_SHIFT 0 -#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) -#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) - -/* CM_SLEEPDEP_CAM specific bits */ - -/* CM_CLKSTCTRL_CAM */ -#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 -#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) - -/* CM_CLKSTST_CAM */ -#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 -#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) - -/* CM_FCLKEN_PER specific bits */ - -/* CM_ICLKEN_PER specific bits */ - -/* CM_IDLEST_PER */ -#define OMAP3430_ST_WDT3_SHIFT 12 -#define OMAP3430_ST_WDT3_MASK (1 << 12) -#define OMAP3430_ST_MCBSP4_SHIFT 2 -#define OMAP3430_ST_MCBSP4_MASK (1 << 2) -#define OMAP3430_ST_MCBSP3_SHIFT 1 -#define OMAP3430_ST_MCBSP3_MASK (1 << 1) -#define OMAP3430_ST_MCBSP2_SHIFT 0 -#define OMAP3430_ST_MCBSP2_MASK (1 << 0) - -/* CM_AUTOIDLE_PER */ -#define OMAP3430_AUTO_GPIO6_MASK (1 << 17) -#define OMAP3430_AUTO_GPIO6_SHIFT 17 -#define OMAP3430_AUTO_GPIO5_MASK (1 << 16) -#define OMAP3430_AUTO_GPIO5_SHIFT 16 -#define OMAP3430_AUTO_GPIO4_MASK (1 << 15) -#define OMAP3430_AUTO_GPIO4_SHIFT 15 -#define OMAP3430_AUTO_GPIO3_MASK (1 << 14) -#define OMAP3430_AUTO_GPIO3_SHIFT 14 -#define OMAP3430_AUTO_GPIO2_MASK (1 << 13) -#define OMAP3430_AUTO_GPIO2_SHIFT 13 -#define OMAP3430_AUTO_WDT3_MASK (1 << 12) -#define OMAP3430_AUTO_WDT3_SHIFT 12 -#define OMAP3430_AUTO_UART3_MASK (1 << 11) -#define OMAP3430_AUTO_UART3_SHIFT 11 -#define OMAP3430_AUTO_GPT9_MASK (1 << 10) -#define OMAP3430_AUTO_GPT9_SHIFT 10 -#define OMAP3430_AUTO_GPT8_MASK (1 << 9) -#define OMAP3430_AUTO_GPT8_SHIFT 9 -#define OMAP3430_AUTO_GPT7_MASK (1 << 8) -#define OMAP3430_AUTO_GPT7_SHIFT 8 -#define OMAP3430_AUTO_GPT6_MASK (1 << 7) -#define OMAP3430_AUTO_GPT6_SHIFT 7 -#define OMAP3430_AUTO_GPT5_MASK (1 << 6) -#define OMAP3430_AUTO_GPT5_SHIFT 6 -#define OMAP3430_AUTO_GPT4_MASK (1 << 5) -#define OMAP3430_AUTO_GPT4_SHIFT 5 -#define OMAP3430_AUTO_GPT3_MASK (1 << 4) -#define OMAP3430_AUTO_GPT3_SHIFT 4 -#define OMAP3430_AUTO_GPT2_MASK (1 << 3) -#define OMAP3430_AUTO_GPT2_SHIFT 3 -#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) -#define OMAP3430_AUTO_MCBSP4_SHIFT 2 -#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) -#define OMAP3430_AUTO_MCBSP3_SHIFT 1 -#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) -#define OMAP3430_AUTO_MCBSP2_SHIFT 0 - -/* CM_CLKSEL_PER */ -#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT9_SHIFT 7 -#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT8_SHIFT 6 -#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) -#define OMAP3430_CLKSEL_GPT7_SHIFT 5 -#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) -#define OMAP3430_CLKSEL_GPT6_SHIFT 4 -#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) -#define OMAP3430_CLKSEL_GPT5_SHIFT 3 -#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) -#define OMAP3430_CLKSEL_GPT4_SHIFT 2 -#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) -#define OMAP3430_CLKSEL_GPT3_SHIFT 1 -#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) -#define OMAP3430_CLKSEL_GPT2_SHIFT 0 - -/* CM_SLEEPDEP_PER specific bits */ -#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) - -/* CM_CLKSTCTRL_PER */ -#define OMAP3430_CLKTRCTRL_PER_SHIFT 0 -#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) - -/* CM_CLKSTST_PER */ -#define OMAP3430_CLKACTIVITY_PER_SHIFT 0 -#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) - -/* CM_CLKSEL1_EMU */ -#define OMAP3430_DIV_DPLL4_SHIFT 24 -#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) -#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) -#define OMAP3430_DIV_DPLL3_SHIFT 16 -#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) -#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 -#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) -#define OMAP3430_CLKSEL_PCLK_SHIFT 8 -#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) -#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 -#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) -#define OMAP3430_CLKSEL_ATCLK_SHIFT 4 -#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) -#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 -#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) -#define OMAP3430_MUX_CTRL_SHIFT 0 -#define OMAP3430_MUX_CTRL_MASK (0x3 << 0) - -/* CM_CLKSTCTRL_EMU */ -#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 -#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) - -/* CM_CLKSTST_EMU */ -#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 -#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) - -/* CM_CLKSEL2_EMU specific bits */ -#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) -#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL3_EMU specific bits */ -#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 -#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) -#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 -#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* CM_POLCTRL */ -#define OMAP3430_CLKOUT2_POL_MASK (1 << 0) - -/* CM_IDLEST_NEON */ -#define OMAP3430_ST_NEON_MASK (1 << 0) - -/* CM_CLKSTCTRL_NEON */ -#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 -#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) - -/* CM_FCLKEN_USBHOST */ -#define OMAP3430ES2_EN_USBHOST2_SHIFT 1 -#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) -#define OMAP3430ES2_EN_USBHOST1_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) - -/* CM_ICLKEN_USBHOST */ -#define OMAP3430ES2_EN_USBHOST_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) - -/* CM_IDLEST_USBHOST */ -#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) -#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 -#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) - -/* CM_AUTOIDLE_USBHOST */ -#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 -#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) - -/* CM_SLEEPDEP_USBHOST */ -#define OMAP3430ES2_EN_MPU_SHIFT 1 -#define OMAP3430ES2_EN_MPU_MASK (1 << 1) -#define OMAP3430ES2_EN_IVA2_SHIFT 2 -#define OMAP3430ES2_EN_IVA2_MASK (1 << 2) - -/* CM_CLKSTCTRL_USBHOST */ -#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 -#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) - -/* CM_CLKSTST_USBHOST */ -#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 -#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) - -#endif diff --git a/arch/arm/mach-omap/include/mach/control.h b/arch/arm/mach-omap/include/mach/control.h deleted file mode 100644 index 1cc4cd4ae4..0000000000 --- a/arch/arm/mach-omap/include/mach/control.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * @file - * @brief This file contains the Control register defines - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP_CONTROL_H -#define __ASM_ARCH_OMAP_CONTROL_H - -/** - * Control register defintion which unwraps to the real register - * offset + base address - */ -#define OMAP3_CONTROL_REG(REGNAME) (OMAP3_CTRL_BASE + CONTROL_##REGNAME) - -#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (0x534) -#define CONTROL_SCRATCHPAD_BASE (0x910) -#define CONTROL_SCRATCHPAD_ROM_BASE (0x860) -#define CONTROL_STATUS (0x2f0) -#define CONTROL_SYSCONFIG (0x010) -#define CONTROL_DEVCONF0 (0x274) -#define CONTROL_DEVCONF1 (0x2D8) -#define CONTROL_IVA2_BOOTMOD (0x404) -#define CONTROL_IVA2_BOOTADDR (0x400) -#define CONTROL_PBIAS_1 (0x520) -#define CONTROL_GENERAL_PURPOSE_STATUS (0x2F4) -#define CONTROL_MEM_DFTRW0 (0x278) -#define CONTROL_MEM_DFTRW1 (0x27C) -#define CONTROL_MSUSPENDMUX_0 (0x290) -#define CONTROL_MSUSPENDMUX_1 (0x294) -#define CONTROL_MSUSPENDMUX_2 (0x298) -#define CONTROL_MSUSPENDMUX_3 (0x29C) -#define CONTROL_MSUSPENDMUX_4 (0x2A0) -#define CONTROL_MSUSPENDMUX_5 (0x2A4) -#define CONTROL_SEC_CTRL (0x2B0) -#define CONTROL_CSIRXFE (0x2DC) -#define CONTROL_DEBOBS_0 (0x420) -#define CONTROL_DEBOBS_1 (0x424) -#define CONTROL_DEBOBS_2 (0x428) -#define CONTROL_DEBOBS_3 (0x42C) -#define CONTROL_DEBOBS_4 (0x430) -#define CONTROL_DEBOBS_5 (0x434) -#define CONTROL_DEBOBS_6 (0x438) -#define CONTROL_DEBOBS_7 (0x43C) -#define CONTROL_DEBOBS_8 (0x440) -#define CONTROL_PROG_IO0 (0x444) -#define CONTROL_PROG_IO1 (0x448) -#define CONTROL_DSS_DPLL_SPREADING (0x450) -#define CONTROL_CORE_DPLL_SPREADING (0x454) -#define CONTROL_PER_DPLL_SPREADING (0x458) -#define CONTROL_USBHOST_DPLL_SPREADING (0x45C) -#define CONTROL_TEMP_SENSOR (0x524) -#define CONTROL_SRAMLDO4 (0x528) -#define CONTROL_SRAMLDO5 (0x52C) -#define CONTROL_CSI (0x530) -#define CONTROL_SCALABLE_OMAP_OCP (0x534) -#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) - -/** Provide the Regoffset, Value */ -#define MUX_VAL(OFFSET,VALUE)\ - writew((VALUE), OMAP3_CTRL_BASE + (OFFSET)) - -/** - * macro for Padconfig Registers @see - * include/mach-arm/arch-omap/omap3-mux.h - */ -#define CP(X) (CONTROL_PADCONF_##X) - -#endif /* __ASM_ARCH_OMAP_CONTROL_H */ diff --git a/arch/arm/mach-omap/include/mach/cpsw.h b/arch/arm/mach-omap/include/mach/cpsw.h deleted file mode 100644 index 5474667a01..0000000000 --- a/arch/arm/mach-omap/include/mach/cpsw.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * CPSW Ethernet Switch Driver - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CPSW_H_ -#define _CPSW_H_ - -struct cpsw_slave_data { - int phy_id; - int phy_if; -}; - -struct cpsw_platform_data { - struct cpsw_slave_data *slave_data; - int num_slaves; -}; - -#endif /* _CPSW_H_ */ diff --git a/arch/arm/mach-omap/include/mach/debug_ll.h b/arch/arm/mach-omap/include/mach/debug_ll.h deleted file mode 100644 index 25ddd485be..0000000000 --- a/arch/arm/mach-omap/include/mach/debug_ll.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2011 - * Author: Jan Weitzel <j.weitzel@phytec.de> - * based on arch/arm/mach-versatile/include/mach/debug_ll.h - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MACH_DEBUG_LL_H__ -#define __MACH_DEBUG_LL_H__ - -#include <io.h> -#include <mach/omap3-silicon.h> -#include <mach/omap4-silicon.h> -#include <mach/am33xx-silicon.h> - -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LCR_BKSE 0x80 /* Bank select enable */ -#define LSR (5 << 2) -#define THR (0 << 2) -#define DLL (0 << 2) -#define IER (1 << 2) -#define DLM (1 << 2) -#define FCR (2 << 2) -#define LCR (3 << 2) -#define MCR (4 << 2) -#define MDR (8 << 2) - -static inline void omap_uart_lowlevel_init(void __iomem *base) -{ - writeb(0x00, base + LCR); - writeb(0x00, base + IER); - writeb(0x07, base + MDR); - writeb(LCR_BKSE, base + LCR); - writeb(26, base + DLL); /* 115200 */ - writeb(0, base + DLM); - writeb(0x03, base + LCR); - writeb(0x03, base + MCR); - writeb(0x07, base + FCR); - writeb(0x00, base + MDR); -} - -#ifdef CONFIG_DEBUG_LL - -#ifdef CONFIG_DEBUG_OMAP3_UART -#define OMAP_DEBUG_SOC OMAP3 -#elif defined CONFIG_DEBUG_OMAP4_UART -#define OMAP_DEBUG_SOC OMAP44XX -#elif defined CONFIG_DEBUG_AM33XX_UART -#define OMAP_DEBUG_SOC AM33XX -#else -#error "unknown OMAP debug uart soc type" -#endif - -#define __OMAP_UART_BASE(soc, num) soc##_UART##num##_BASE -#define OMAP_UART_BASE(soc, num) __OMAP_UART_BASE(soc, num) - -static inline void PUTC_LL(char c) -{ - void __iomem *base = (void *)OMAP_UART_BASE(OMAP_DEBUG_SOC, - CONFIG_DEBUG_OMAP_UART_PORT); - - /* Wait until there is space in the FIFO */ - while ((readb(base + LSR) & LSR_THRE) == 0); - /* Send the character */ - writeb(c, base + THR); - /* Wait to make sure it hits the line, in case we die too soon. */ - while ((readb(base + LSR) & LSR_THRE) == 0); -} -#endif - -#endif diff --git a/arch/arm/mach-omap/include/mach/devices.h b/arch/arm/mach-omap/include/mach/devices.h deleted file mode 100644 index 06fd2a8dd3..0000000000 --- a/arch/arm/mach-omap/include/mach/devices.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_OMAP_DEVICES_H -#define __MACH_OMAP_DEVICES_H - -#include <mach/omap_hsmmc.h> -#include <video/omap-fb.h> - -void omap_add_ram0(resource_size_t size); - -void omap_add_sram0(resource_size_t base, resource_size_t size); - -struct device_d *omap_add_uart(int id, unsigned long base); - -struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata); - -#endif /* __MACH_OMAP_DEVICES_H */ diff --git a/arch/arm/mach-omap/include/mach/ehci.h b/arch/arm/mach-omap/include/mach/ehci.h deleted file mode 100644 index cccb9ad364..0000000000 --- a/arch/arm/mach-omap/include/mach/ehci.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de> - * - * This file is released under the GPLv2 - * - */ - -#ifndef __OMAP_EHCI_H -#define __OMAP_EHCI_H - -/* TLL Register Set */ -#define OMAP_USBTLL_REVISION (0x00) -#define OMAP_USBTLL_SYSCONFIG (0x10) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) - -#define OMAP_USBTLL_SYSSTATUS (0x14) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) - -#define OMAP_USBTLL_IRQSTATUS (0x18) -#define OMAP_USBTLL_IRQENABLE (0x1C) - -#define OMAP_TLL_SHARED_CONF (0x30) -#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) -#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) -#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) -#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) -#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) - -#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) -#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) -#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) -#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) -#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) -#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) - -#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) -#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) -#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) -#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) -#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) -#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) -#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) -#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) -#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) - -#define OMAP_TLL_CHANNEL_COUNT 3 -#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1) -#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2) -#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4) - -/* UHH Register Set */ -#define OMAP_UHH_REVISION (0x00) -#define OMAP_UHH_SYSCONFIG (0x10) -#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) -#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) - -#define OMAP_UHH_SYSSTATUS (0x14) -#define OMAP_UHH_HOSTCONFIG (0x40) -#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) -#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) -#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) -#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) -#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) -#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) -#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) -#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) -#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) -#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) -#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) - -#define OMAP_UHH_DEBUG_CSR (0x44) - -/* EHCI Register Set */ -#define EHCI_INSNREG05_ULPI (0xA4) -#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 -#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 -#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 -#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 -#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8 -#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0 - -#define OMAP3_HS_USB_PORTS 3 - -enum ehci_hcd_omap_mode { - EHCI_HCD_OMAP_MODE_UNKNOWN, - EHCI_HCD_OMAP_MODE_PHY, - EHCI_HCD_OMAP_MODE_TLL, -}; - -struct omap_hcd { - enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS]; - unsigned phy_reset:1; - - /* have to be valid if phy_reset is true and portx is in phy mode */ - int reset_gpio_port[OMAP3_HS_USB_PORTS]; -}; - -void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask); -int ehci_omap_init(struct omap_hcd *omap); - -#endif /* __OMAP_EHCI_H */ diff --git a/arch/arm/mach-omap/include/mach/emac_defs.h b/arch/arm/mach-omap/include/mach/emac_defs.h deleted file mode 100644 index 568de6a12a..0000000000 --- a/arch/arm/mach-omap/include/mach/emac_defs.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * ---------------------------------------------------------------------------- - - * Modifications: - * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. - * - */ - -#ifndef _AM3517_EMAC_H_ -#define _AM3517_EMAC_H_ - -#define EMAC_BASE_ADDR 0x5C010000 -#define EMAC_WRAPPER_BASE_ADDR 0x5C000000 -#define EMAC_WRAPPER_RAM_ADDR 0x5C020000 -#define EMAC_MDIO_BASE_ADDR 0x5C030000 -#define EMAC_HW_RAM_ADDR 0x01E20000 - -#define EMAC_MDIO_BUS_FREQ 166000000 /* 166 MHZ check */ -#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 2.0 MHz */ - -#endif /* _AM3517_EMAC_H_ */ diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h deleted file mode 100644 index 00702e60e8..0000000000 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Auther: - * Vaibhav Hiremath <hvaibhav@ti.com> - * - * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _EMIF_H_ -#define _EMIF_H_ - -#define EMIF4_MOD_ID_REV 0x0 -#define EMIF4_STATUS 0x04 -#define EMIF4_SDRAM_CONFIG 0x08 -#define EMIF4_SDRAM_CONFIG2 0x0c -#define EMIF4_SDRAM_REF_CTRL 0x10 -#define EMIF4_SDRAM_REF_CTRL_SHADOW 0x14 -#define EMIF4_SDRAM_TIM_1 0x18 -#define EMIF4_SDRAM_TIM_1_SHADOW 0x1c -#define EMIF4_SDRAM_TIM_2 0x20 -#define EMIF4_SDRAM_TIM_2_SHADOW 0x24 -#define EMIF4_SDRAM_TIM_3 0x28 -#define EMIF4_SDRAM_TIM_3_SHADOW 0x2c -#define EMIF4_POWER_MANAGEMENT_CTRL 0x38 -#define EMIF4_POWER_MANAGEMENT_CTRL_SHADOW 0x3c -#define EMIF4_OCP_CONFIG 0x54 -#define EMIF4_ZQ_CONFIG 0xc8 -#define EMIF4_DDR_PHY_CTRL_1 0xe4 -#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xe8 -#define EMIF4_DDR_PHY_CTRL_2 0xec -#define EMIF4_IODFT_TLGC 0x60 - -unsigned long emif4_sdram_size(const void __iomem *emif4); - -void am35xx_emif4_init(const void __iomem *emif4); - -#endif /* endif _EMIF_H_ */ diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h deleted file mode 100644 index 8b2b7a4f0c..0000000000 --- a/arch/arm/mach-omap/include/mach/generic.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MACH_GENERIC_H -#define _MACH_GENERIC_H - -/* I2C controller revisions */ -#define OMAP_I2C_OMAP1_REV_2 0x20 - -/* I2C controller revisions present on specific hardware */ -#define OMAP_I2C_REV_ON_2430 0x00000036 -#define OMAP_I2C_REV_ON_3430_3530 0x0000003C -#define OMAP_I2C_REV_ON_3630 0x00000040 -#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002 - -extern unsigned int __omap_cpu_type; - -#define OMAP_CPU_OMAP3 3 -#define OMAP_CPU_OMAP4 4 -#define OMAP_CPU_AM33XX 33 - -#ifdef CONFIG_ARCH_OMAP3 -# ifdef omap_cpu_type -# undef omap_cpu_type -# define omap_cpu_type __omap_cpu_type -# else -# define omap_cpu_type OMAP_CPU_OMAP3 -# endif -# define cpu_is_omap3() (omap_cpu_type == OMAP_CPU_OMAP3) -#else -# define cpu_is_omap3() (0) -#endif - -#ifdef CONFIG_ARCH_OMAP4 -# ifdef omap_cpu_type -# undef omap_cpu_type -# define omap_cpu_type __omap_cpu_type -# else -# define omap_cpu_type OMAP_CPU_OMAP4 -# endif -# define cpu_is_omap4() (omap_cpu_type == OMAP_CPU_OMAP4) -#else -# define cpu_is_omap4() (0) -#endif - -#ifdef CONFIG_ARCH_AM33XX -# ifdef omap_cpu_type -# undef omap_cpu_type -# define omap_cpu_type __omap_cpu_type -# else -# define omap_cpu_type OMAP_CPU_AM33XX -# endif -# define cpu_is_am33xx() (omap_cpu_type == OMAP_CPU_AM33XX) -#else -# define cpu_is_am33xx() (0) -#endif - -struct omap_barebox_part { - unsigned int nand_offset; - unsigned int nand_size; - unsigned int nand_bkup_offset; - unsigned int nand_bkup_size; - unsigned int nor_offset; - unsigned int nor_size; -}; - -#ifdef CONFIG_SHELL_NONE -int omap_set_barebox_part(struct omap_barebox_part *part); -int omap_set_mmc_dev(const char *mmcdev); -#else -static inline int omap_set_barebox_part(struct omap_barebox_part *part) -{ - return 0; -} -static inline int omap_set_mmc_dev(const char *mmcdev) -{ - return 0; -} -#endif - -void __noreturn omap_start_barebox(void *barebox); - -void omap_watchdog_disable(const void __iomem *wdt); - -void omap_set_bootmmc_devname(const char *devname); -const char *omap_get_bootmmc_devname(void); - -#endif diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h deleted file mode 100644 index d4eac79717..0000000000 --- a/arch/arm/mach-omap/include/mach/gpmc.h +++ /dev/null @@ -1,165 +0,0 @@ -/** - * @file - * @brief This file contains the GPMC's generic definitions - * - * OMAP's General Purpose Memory Controller(GPMC) provides features - * allowing us to communicate with memory devices such as NOR, NAND, - * OneNAND, SRAM etc.. This file defines certain generic parameters - * allowing us to configure the same painlessly. - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -extern void __iomem *omap_gpmc_base; - -/** GPMC Reg Wrapper */ -#define GPMC_REG(REGNAME) (omap_gpmc_base + GPMC_##REGNAME) - -#define GPMC_SYS_CONFIG (0x10) -#define GPMC_SYS_STATUS (0x14) -#define GPMC_IRQSTATUS (0x18) -#define GPMC_IRQ_ENABLE (0x1C) -#define GPMC_TIMEOUT_CONTROL (0x40) -#define GPMC_CFG (0x50) -#define GPMC_STATUS (0x54) -#define GPMC_PREFETCH_CONFIG1 (0x1E0) -#define GPMC_PREFETCH_CONFIG2 (0x1E4) -#define GPMC_PREFETCH_CONTROL (0x1EC) -#define GPMC_PREFETCH_STATUS (0x1f0) -#define GPMC_ECC_CONFIG (0x1F4) -#define GPMC_ECC_CONTROL (0x1F8) -#define GPMC_ECC_SIZE_CONFIG (0x1FC) -#define GPMC_ECC1_RESULT (0x200) -#define GPMC_ECC2_RESULT (0x204) -#define GPMC_ECC3_RESULT (0x208) -#define GPMC_ECC4_RESULT (0x20C) -#define GPMC_ECC5_RESULT (0x210) -#define GPMC_ECC6_RESULT (0x214) -#define GPMC_ECC7_RESULT (0x218) -#define GPMC_ECC8_RESULT (0x21C) -#define GPMC_ECC9_RESULT (0x220) -#define GPMC_ECC_BCH_RESULT_0 0x240 - -#define GPMC_CONFIG1_0 (0x60) -#define GPMC_CONFIG1_1 (0x90) -#define GPMC_CONFIG1_2 (0xC0) -#define GPMC_CONFIG1_3 (0xF0) -#define GPMC_CONFIG1_4 (0x120) -#define GPMC_CONFIG1_5 (0x150) -#define GPMC_CONFIG1_6 (0x180) -#define GPMC_CONFIG1_7 (0x1B0) -#define GPMC_CONFIG2_0 (0x64) -#define GPMC_CONFIG2_1 (0x94) -#define GPMC_CONFIG2_2 (0xC4) -#define GPMC_CONFIG2_3 (0xF4) -#define GPMC_CONFIG2_4 (0x124) -#define GPMC_CONFIG2_5 (0x154) -#define GPMC_CONFIG2_6 (0x184) -#define GPMC_CONFIG2_7 (0x1B4) -#define GPMC_CONFIG3_0 (0x68) -#define GPMC_CONFIG3_1 (0x98) -#define GPMC_CONFIG3_2 (0xC8) -#define GPMC_CONFIG3_3 (0xF8) -#define GPMC_CONFIG3_4 (0x128) -#define GPMC_CONFIG3_5 (0x158) -#define GPMC_CONFIG3_6 (0x188) -#define GPMC_CONFIG3_7 (0x1B8) -#define GPMC_CONFIG4_0 (0x6C) -#define GPMC_CONFIG4_1 (0x9C) -#define GPMC_CONFIG4_2 (0xCC) -#define GPMC_CONFIG4_3 (0xFC) -#define GPMC_CONFIG4_4 (0x12C) -#define GPMC_CONFIG4_5 (0x15C) -#define GPMC_CONFIG4_6 (0x18C) -#define GPMC_CONFIG4_7 (0x1BC) -#define GPMC_CONFIG5_0 (0x70) -#define GPMC_CONFIG5_1 (0xA0) -#define GPMC_CONFIG5_2 (0xD0) -#define GPMC_CONFIG5_3 (0x100) -#define GPMC_CONFIG5_4 (0x130) -#define GPMC_CONFIG5_5 (0x160) -#define GPMC_CONFIG5_6 (0x190) -#define GPMC_CONFIG5_7 (0x1C0) -#define GPMC_CONFIG6_0 (0x74) -#define GPMC_CONFIG6_1 (0xA4) -#define GPMC_CONFIG6_2 (0xD4) -#define GPMC_CONFIG6_3 (0x104) -#define GPMC_CONFIG6_4 (0x134) -#define GPMC_CONFIG6_5 (0x164) -#define GPMC_CONFIG6_6 (0x194) -#define GPMC_CONFIG6_7 (0x1C4) -#define GPMC_CONFIG7_0 (0x78) -#define GPMC_CONFIG7_1 (0xA8) -#define GPMC_CONFIG7_2 (0xD8) -#define GPMC_CONFIG7_3 (0x108) -#define GPMC_CONFIG7_4 (0x138) -#define GPMC_CONFIG7_5 (0x168) -#define GPMC_CONFIG7_6 (0x198) -#define GPMC_CONFIG7_7 (0x1C8) - -#define GPMC_NUM_CS 8 -#define GPMC_CONFIG_CS_SIZE (GPMC_CONFIG1_1 - GPMC_CONFIG1_0) -#define GPMC_CONFIG_REG_OFF (GPMC_CONFIG2_0 - GPMC_CONFIG1_0) - -#define GPMC_CS_NAND_COMMAND (0x1C) -#define GPMC_CS_NAND_ADDRESS (0x20) -#define GPMC_CS_NAND_DATA (0x24) - -#define GPMC_SIZE_128M 0x08 -#define GPMC_SIZE_64M 0x0C -#define GPMC_SIZE_32M 0x0E -#define GPMC_SIZE_16M 0x0F - -#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 -#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) -#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) -#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) - -int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, - unsigned int u32_count, int is_write); -int gpmc_prefetch_reset(int cs); - -#define NAND_WP_BIT 0x00000010 - -#ifndef __ASSEMBLY__ - -/** Generic GPMC configuration structure to be used to configure a - * chip select - */ -struct gpmc_config { - unsigned int cfg[6]; - unsigned int base; - unsigned char size; -}; - -/** Generic configuration - will reset all the cs configs. */ -void gpmc_generic_init(unsigned int cfg); - -/** Configuration for a specific chip select */ -void gpmc_cs_config(char cs, struct gpmc_config *config); - -#endif - -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h deleted file mode 100644 index f172b576eb..0000000000 --- a/arch/arm/mach-omap/include/mach/gpmc_nand.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @file - * @brief This file contains exported structure for NAND - * - * OMAP's General Purpose Memory Controller (GPMC) has a NAND controller - * embedded. this file provides the platform data structure required to - * hook on to it. - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz - * include/asm-arm/arch-omap/nand.h - * - * Copyright (C) 2006 Micron Technology Inc. - * Author: Shahrom Sharif-Kashani - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_OMAP_NAND_GPMC_H -#define __ASM_OMAP_NAND_GPMC_H - -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/nand_ecc.h> - -enum gpmc_ecc_mode { - OMAP_ECC_SOFT, - OMAP_ECC_HAMMING_CODE_HW_ROMCODE, - OMAP_ECC_BCH8_CODE_HW, - OMAP_ECC_BCH8_CODE_HW_ROMCODE, - OMAP_ECC_BCH16_CODE_HW, -}; - -/** omap nand platform data structure */ -struct gpmc_nand_platform_data { - /** Chip select you want to use */ - int cs; - struct mtd_partition *parts; - int nr_parts; - /** If there are any special setups you'd want to do */ - int (*nand_setup) (struct gpmc_nand_platform_data *); - - /** ecc mode to use */ - enum gpmc_ecc_mode ecc_mode; - /** setup any special options */ - unsigned int options; - /** set up device access as 8,16 as per GPMC config */ - char device_width; - /** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */ - char wait_mon_pin; - - /* if you like a custom oob use this. */ - struct nand_ecclayout *oob; - /** gpmc config for nand */ - struct gpmc_config *nand_cfg; - - struct device_node *of_node; - struct device_node *elm_of_node; -}; - -int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata); - -extern struct gpmc_config omap3_nand_cfg; -extern struct gpmc_config omap4_nand_cfg; -extern struct gpmc_config am33xx_nand_cfg; - -#endif /* __ASM_OMAP_NAND_GPMC_H */ diff --git a/arch/arm/mach-omap/include/mach/intc.h b/arch/arm/mach-omap/include/mach/intc.h deleted file mode 100644 index 6c53528db2..0000000000 --- a/arch/arm/mach-omap/include/mach/intc.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * @brief This file contains the Interrupt controller register defines - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP_INTC_H -#define __ASM_ARCH_OMAP_INTC_H - -/** Interrupt Controller Register wrapper */ -#define INTC_REG(REGNAME) (OMAP_INTC_BASE + INTC_##REGNAME) - -#define INTC_MIR_0 (0x084) -#define INTC_MIR_1 (0x0A4) -#define INTC_MIR_2 (0x0C4) -#define INTC_MIR_SET_0 (0x08C) -#define INTC_MIR_SET_1 (0x0AC) -#define INTC_MIR_SET_2 (0x0CC) -#define INTC_MIR_CLEAR_0 (0x094) -#define INTC_MIR_CLEAR_1 (0x0B4) -#define INTC_MIR_CLEAR_2 (0x0D4) -#define INTC_PS_SYSCONFIG (0x010) -#define INTC_PS_PROTECTION (0x04C) -#define INTC_PS_IDLE (0x050) -#define INTC_PS_THRESHOLD (0x068) -#define INTC_PS_PENDING_IRQ0 (0x098) -#define INTC_PS_PENDING_IRQ1 (0x0B8) -#define INTC_PS_PENDING_IRQ2 (0x0D8) - -#endif /* __ASM_ARCH_OMAP_INTC_H */ diff --git a/arch/arm/mach-omap/include/mach/mcspi.h b/arch/arm/mach-omap/include/mach/mcspi.h deleted file mode 100644 index febb08db2a..0000000000 --- a/arch/arm/mach-omap/include/mach/mcspi.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __OMAP_MCSPI_H -#define __OMAP_MCSPI_H - -#define OMAP3_MCSPI1_BASE 0x48098000 -#define OMAP3_MCSPI2_BASE 0x4809A000 -#define OMAP3_MCSPI3_BASE 0x480B8000 -#define OMAP3_MCSPI4_BASE 0x480BA000 - -int mcspi_devices_init(void); - -#endif /* __OMAP_MCSPI_H */ diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h deleted file mode 100644 index 849964ab3e..0000000000 --- a/arch/arm/mach-omap/include/mach/omap3-clock.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * @file - * @brief Contains the PRM and CM definitions - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _OMAP343X_CLOCKS_H_ -#define _OMAP343X_CLOCKS_H_ - -/** CM Clock Regs Wrapper */ -#define OMAP3_CM_REG(REGNAME) (OMAP3_CM_BASE + CM_##REGNAME) - -#define CM_FCLKEN_IVA2 0X0000 -#define CM_CLKEN_PLL_IVA2 0X0004 -#define CM_IDLEST_PLL_IVA2 0X0024 -#define CM_CLKSEL1_PLL_IVA2 0X0040 -#define CM_CLKSEL2_PLL_IVA2 0X0044 -#define CM_CLKEN_PLL_MPU 0X0904 -#define CM_IDLEST_PLL_MPU 0X0924 -#define CM_CLKSEL1_PLL_MPU 0X0940 -#define CM_CLKSEL2_PLL_MPU 0X0944 -#define CM_FCLKEN1_CORE 0X0A00 -#define CM_FCLKEN3_CORE 0X0A08 -#define CM_ICLKEN1_CORE 0X0A10 -#define CM_ICLKEN2_CORE 0X0A14 -#define CM_ICLKEN3_CORE 0X0A18 -#define CM_AIDLE3_CORE 0X0A38 -#define CM_CLKSEL_CORE 0X0A40 -#define CM_FCLKEN_GFX 0X0B00 -#define CM_ICLKEN_GFX 0X0B10 -#define CM_CLKSEL_GFX 0X0B40 -#define CM_FCLKEN_WKUP 0X0C00 -#define CM_ICLKEN_WKUP 0X0C10 -#define CM_CLKSEL_WKUP 0X0C40 -#define CM_IDLEST_WKUP 0X0C20 -#define CM_CLKEN_PLL 0X0D00 -#define CM_CLKEN2_PLL 0X0D04 -#define CM_IDLEST_CKGEN 0X0D20 -#define CM_CLKSEL1_PLL 0X0D40 -#define CM_CLKSEL2_PLL 0X0D44 -#define CM_CLKSEL3_PLL 0X0D48 -#define CM_CLKSEL4_PLL 0X0D4C -#define CM_CLKSEL5_PLL 0X0D50 -#define CM_FCLKEN_DSS 0X0E00 -#define CM_ICLKEN_DSS 0X0E10 -#define CM_CLKSEL_DSS 0X0E40 -#define CM_FCLKEN_CAM 0X0F00 -#define CM_ICLKEN_CAM 0X0F10 -#define CM_CLKSEL_CAM 0X0f40 -#define CM_FCLKEN_PER 0X1000 -#define CM_ICLKEN_PER 0X1010 -#define CM_IDLEST_PER 0X1020 -#define CM_AUTOIDLE_PER 0X1030 -#define CM_CLKSEL_PER 0X1040 -#define CM_CLKSEL1_EMU 0X1140 -#define CM_FCLKEN_USBH 0x1400 -#define CM_ICLKEN_USBH 0x1410 -#define CM_AIDLE_USBH 0x1430 -#define CM_SLEEPD_USBH 0x1444 -#define CM_CLKSTCTRL_USBH 0x1448 - -/** PRM Clock Regs */ -#define OMAP3_PRM_REG(REGNAME) (OMAP3_PRM_BASE + PRM_##REGNAME) -#define PRM_CLKSEL 0x0D40 -#define PRM_RSTCTRL 0x1250 -#define PRM_CLKSRC_CTRL 0x1270 - -/*************** Clock Values */ -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* - * Bit positions indicating current SYSCLK divider - */ -#define SYSCLK_DIV_1 (1 << 6) -#define SYSCLK_DIV_2 (1 << 7) - -/* The following configurations are OPP and SysClk value independant - * and hence are defined here. - */ - -/* CORE DPLL */ -#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -#define CORE_FUSB_DIV 2 /* 41.5MHz: */ -#define CORE_L4_DIV 2 /* 83MHz : L4 */ -#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV_34X 3 /* 96MHz : CM_CLKSEL_GFX (OMAP34XX) */ -#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX (OMAP36XX) */ -#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ -#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) - -#define MAX_SIL_INDEX 1 - -#ifndef __ASSEMBLY__ -void prcm_init(void); -/* Used to index into DPLL parameter tables -See TRM for further details */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -struct dpll_param_per_36x { - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m2div; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap3-devices.h b/arch/arm/mach-omap/include/mach/omap3-devices.h deleted file mode 100644 index 5d7bc8bf1e..0000000000 --- a/arch/arm/mach-omap/include/mach/omap3-devices.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_OMAP3_DEVICES_H -#define __MACH_OMAP3_DEVICES_H - -#include <driver.h> -#include <linux/sizes.h> -#include <mach/omap3-silicon.h> -#include <mach/devices.h> -#include <mach/mcspi.h> -#include <mach/omap_hsmmc.h> - - -static inline void omap3_add_sram0(void) -{ - return omap_add_sram0(OMAP3_SRAM_BASE, 64 * SZ_1K); -} - -/* the device numbering is the same as in the device tree */ - -static inline struct device_d *omap3_add_spi(int id, resource_size_t start) -{ - return add_generic_device("omap3_spi", id, NULL, start, SZ_4K, - IORESOURCE_MEM, NULL); -} - -static inline struct device_d *omap3_add_spi1(void) -{ - return omap3_add_spi(1, OMAP3_MCSPI1_BASE); -} - -static inline struct device_d *omap3_add_spi2(void) -{ - return omap3_add_spi(2, OMAP3_MCSPI2_BASE); -} - -static inline struct device_d *omap3_add_spi3(void) -{ - return omap3_add_spi(3, OMAP3_MCSPI3_BASE); -} - -static inline struct device_d *omap3_add_spi4(void) -{ - return omap3_add_spi(4, OMAP3_MCSPI4_BASE); -} - -static inline struct device_d *omap3_add_uart1(void) -{ - return omap_add_uart(0, OMAP3_UART1_BASE); -} - -static inline struct device_d *omap3_add_uart2(void) -{ - return omap_add_uart(1, OMAP3_UART2_BASE); -} - -static inline struct device_d *omap3_add_uart3(void) -{ - return omap_add_uart(2, OMAP3_UART3_BASE); -} - -static inline struct device_d *omap3_add_mmc1(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap3-hsmmc", 0, NULL, - OMAP3_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap3_add_mmc2(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap3-hsmmc", 1, NULL, - OMAP3_MMC2_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap3_add_mmc3(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap3-hsmmc", 2, NULL, - OMAP3_MMC3_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap3_add_i2c1(void *pdata) -{ - return add_generic_device("i2c-omap3", 0, NULL, OMAP3_I2C1_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap3_add_i2c2(void *pdata) -{ - return add_generic_device("i2c-omap3", 1, NULL, OMAP3_I2C2_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap3_add_i2c3(void *pdata) -{ - return add_generic_device("i2c-omap3", 2, NULL, OMAP3_I2C3_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap3_add_ehci(void *pdata) -{ - return add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP3_EHCI_BASE, - OMAP3_EHCI_BASE + 0x10, pdata); -} - -#endif /* __MACH_OMAP3_DEVICES_H */ diff --git a/arch/arm/mach-omap/include/mach/omap3-generic.h b/arch/arm/mach-omap/include/mach/omap3-generic.h deleted file mode 100644 index 6304ac7bb8..0000000000 --- a/arch/arm/mach-omap/include/mach/omap3-generic.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_OMAP3_GENERIC_H -#define __MACH_OMAP3_GENERIC_H - -#include <linux/sizes.h> -#include <linux/string.h> -#include <mach/generic.h> -#include <mach/omap3-silicon.h> - -static inline void omap3_save_bootinfo(uint32_t *info) -{ - unsigned long i = (unsigned long)info; - - if (i & 0x3) - return; - if (i < OMAP3_SRAM_BASE) - return; - if (i > OMAP3_SRAM_BASE + SZ_64K) - return; - - memcpy((void *)OMAP3_SRAM_SCRATCH_SPACE, info, 3 * sizeof(uint32_t)); -} - -u32 omap3_running_in_flash(void); -u32 omap3_running_in_sram(void); -u32 omap3_running_in_sdram(void); - -int omap3_init(void); -int omap3_devices_init(void); - -void *omap3_xload_boot_usb(void); - -#endif /* __MACH_OMAP3_GENERIC_H */ diff --git a/arch/arm/mach-omap/include/mach/omap3-mux.h b/arch/arm/mach-omap/include/mach/omap3-mux.h deleted file mode 100644 index a679e25567..0000000000 --- a/arch/arm/mach-omap/include/mach/omap3-mux.h +++ /dev/null @@ -1,463 +0,0 @@ -/** - * @file - * @brief Mux Configuration Register defines for OMAP3 - * - * This file defines the various Pin Mux registers - * @see include/asm-arm/arch-omap/control.h - * The @ref MUX_VAL macro uses the defines from this file - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _ASM_ARCH_OMAP3_MUX_H_ -#define _ASM_ARCH_OMAP3_MUX_H_ - -/** - * Pin Mux Enable Defines - * - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0-7 - Mode 0-7 - * - * @see MUX_VAL - */ -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -/* - * To get the actual address the offset has to added - * with OMAP_CTRL_BASE to get the actual address - */ - -/* SDRC */ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -/* GPMC */ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_NCS0 0x00AE -#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_NCS6 0x00BA -#define CONTROL_PADCONF_GPMC_NCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_NOE 0x00C2 -#define CONTROL_PADCONF_GPMC_NWE 0x00C4 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_NWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/* DSS */ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/* CAMERA */ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/* Audio Interface */ -#define CONTROL_PADCONF_MCBSP2_FSX 0x013C -#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E -#define CONTROL_PADCONF_MCBSP2_DR 0x0140 -#define CONTROL_PADCONF_MCBSP2_DX 0x0142 -#define CONTROL_PADCONF_ -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/* WirelesS LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/* Bluetooth */ -#define CONTROL_PADCONF_MCBSP3_DX 0x016C -#define CONTROL_PADCONF_MCBSP3_DR 0x016E -#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/* Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_MCBSP4_DR 0x0186 -#define CONTROL_PADCONF_MCBSP4_DX 0x0188 -#define CONTROL_PADCONF_MCBSP4_FSX 0x018A -#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C -#define CONTROL_PADCONF_MCBSP1_FSR 0x018E -#define CONTROL_PADCONF_MCBSP1_DX 0x0190 -#define CONTROL_PADCONF_MCBSP1_DR 0x0192 -#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 -#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 -#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 -/* Serial Interface */ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE -#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC -#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE -/* Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA -/* Die to die */ -#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 -#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 -#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 -#define CONTROL_PADCONF_D2D_MCAD3 0x01EA -#define CONTROL_PADCONF_D2D_MCAD4 0x01EC -#define CONTROL_PADCONF_D2D_MCAD5 0x01EE -#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 -#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 -#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 -#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 -#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 -#define CONTROL_PADCONF_D2D_MCAD11 0x01FA -#define CONTROL_PADCONF_D2D_MCAD12 0x01FC -#define CONTROL_PADCONF_D2D_MCAD13 0x01FE -#define CONTROL_PADCONF_D2D_MCAD14 0x0200 -#define CONTROL_PADCONF_D2D_MCAD15 0x0202 -#define CONTROL_PADCONF_D2D_MCAD16 0x0204 -#define CONTROL_PADCONF_D2D_MCAD17 0x0206 -#define CONTROL_PADCONF_D2D_MCAD18 0x0208 -#define CONTROL_PADCONF_D2D_MCAD19 0x020A -#define CONTROL_PADCONF_D2D_MCAD20 0x020C -#define CONTROL_PADCONF_D2D_MCAD21 0x020E -#define CONTROL_PADCONF_D2D_MCAD22 0x0210 -#define CONTROL_PADCONF_D2D_MCAD23 0x0212 -#define CONTROL_PADCONF_D2D_MCAD24 0x0214 -#define CONTROL_PADCONF_D2D_MCAD25 0x0216 -#define CONTROL_PADCONF_D2D_MCAD26 0x0218 -#define CONTROL_PADCONF_D2D_MCAD27 0x021A -#define CONTROL_PADCONF_D2D_MCAD28 0x021C -#define CONTROL_PADCONF_D2D_MCAD29 0x021E -#define CONTROL_PADCONF_D2D_MCAD30 0x0220 -#define CONTROL_PADCONF_D2D_MCAD31 0x0222 -#define CONTROL_PADCONF_D2D_MCAD32 0x0224 -#define CONTROL_PADCONF_D2D_MCAD33 0x0226 -#define CONTROL_PADCONF_D2D_MCAD34 0x0228 -#define CONTROL_PADCONF_D2D_MCAD35 0x022A -#define CONTROL_PADCONF_D2D_MCAD36 0x022C -#define CONTROL_PADCONF_D2D_CLK26MI 0x022E -#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 -#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 -#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 -#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 -#define CONTROL_PADCONF_D2D_SPINT 0x0238 -#define CONTROL_PADCONF_D2D_FRINT 0x023A -#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C -#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E -#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 -#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 -#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 -#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 -#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 -#define CONTROL_PADCONF_D2D_N3GTMS 0x024A -#define CONTROL_PADCONF_D2D_N3GTCK 0x024C -#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E -#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 -#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C -#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 -#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 -#define CONTROL_PADCONF_D2D_MWRITE 0x0256 -#define CONTROL_PADCONF_D2D_SWRITE 0x0258 -#define CONTROL_PADCONF_D2D_MREAD 0x025A -#define CONTROL_PADCONF_D2D_SREAD 0x025C -#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E -#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 -#define CONTROL_PADCONF_SDRC_CKE0 0x0262 -#define CONTROL_PADCONF_SDRC_CKE1 0x0264 - -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 - -/* AM/DM37xx specific */ -#define CONTROL_PADCONF_GPIO127 0x0A54 -#define CONTROL_PADCONF_GPIO126 0x0A56 -#define CONTROL_PADCONF_GPIO128 0x0A58 -#define CONTROL_PADCONF_GPIO129 0x0A5A - -#endif diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h deleted file mode 100644 index b4de045652..0000000000 --- a/arch/arm/mach-omap/include/mach/omap3-silicon.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - * @file - * @brief This file contains the processor specific definitions of - * the TI OMAP34XX. For more info on OMAP34XX, - * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf - * - * OMAP34XX base address defines go here. - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap3-silicon.h - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP3_H -#define __ASM_ARCH_OMAP3_H - -/* PLEASE PLACE ONLY BASE DEFINES HERE */ - -/** OMAP Internal Bus Base addresses */ -#define OMAP3_L4_CORE_BASE 0x48000000 -#define OMAP3_INTC_BASE 0x48200000 -#define OMAP3_L4_WKUP_BASE 0x48300000 -#define OMAP3_L4_PER_BASE 0x49000000 -#define OMAP3_L4_EMU_BASE 0x54000000 -#define OMAP3_SGX_BASE 0x50000000 -#define OMAP3_IVA_BASE 0x5C000000 -#define OMAP3_SMX_APE_BASE 0x68000000 -#define OMAP3_SMS_BASE 0x6C000000 -#define OMAP3_SDRC_BASE 0x6D000000 -#define OMAP3_GPMC_BASE 0x6E000000 - -/** Peripheral Base Addresses */ -#define OMAP3_CTRL_BASE (OMAP3_L4_CORE_BASE + 0x02000) -#define OMAP3_CM_BASE (OMAP3_L4_CORE_BASE + 0x04000) -#define OMAP3_PRM_BASE (OMAP3_L4_WKUP_BASE + 0x06000) - -#define OMAP3_UART1_BASE (OMAP3_L4_CORE_BASE + 0x6A000) -#define OMAP3_UART2_BASE (OMAP3_L4_CORE_BASE + 0x6C000) -#define OMAP3_UART3_BASE (OMAP3_L4_PER_BASE + 0x20000) - -#define OMAP3_I2C1_BASE (OMAP3_L4_CORE_BASE + 0x70000) -#define OMAP3_I2C2_BASE (OMAP3_L4_CORE_BASE + 0x72000) -#define OMAP3_I2C3_BASE (OMAP3_L4_CORE_BASE + 0x60000) - -#define OMAP3_GPTIMER1_BASE (OMAP3_L4_WKUP_BASE + 0x18000) -#define OMAP3_GPTIMER2_BASE (OMAP3_L4_PER_BASE + 0x32000) -#define OMAP3_GPTIMER3_BASE (OMAP3_L4_PER_BASE + 0x34000) -#define OMAP3_GPTIMER4_BASE (OMAP3_L4_PER_BASE + 0x36000) -#define OMAP3_GPTIMER5_BASE (OMAP3_L4_PER_BASE + 0x38000) -#define OMAP3_GPTIMER6_BASE (OMAP3_L4_PER_BASE + 0x3A000) -#define OMAP3_GPTIMER7_BASE (OMAP3_L4_PER_BASE + 0x3C000) -#define OMAP3_GPTIMER8_BASE (OMAP3_L4_PER_BASE + 0x3E000) -#define OMAP3_GPTIMER9_BASE (OMAP3_L4_PER_BASE + 0x40000) -#define OMAP3_GPTIMER10_BASE (OMAP3_L4_CORE_BASE + 0x86000) -#define OMAP3_GPTIMER11_BASE (OMAP3_L4_CORE_BASE + 0x88000) - -#define OMAP3_WDTIMER2_BASE (OMAP3_L4_WKUP_BASE + 0x14000) -#define OMAP3_WDTIMER3_BASE (OMAP3_L4_PER_BASE + 0x30000) - -#define OMAP3_32KTIMER_BASE (OMAP3_L4_WKUP_BASE + 0x20000) - -#define OMAP3_MMC1_BASE (OMAP3_L4_CORE_BASE + 0x9C000) -#define OMAP3_MMC2_BASE (OMAP3_L4_CORE_BASE + 0xB4000) -#define OMAP3_MMC3_BASE (OMAP3_L4_CORE_BASE + 0xAD000) - -#define OMAP3_MUSB0_BASE (OMAP3_L4_CORE_BASE + 0xAB000) - -#define OMAP3_GPIO1_BASE (OMAP3_L4_WKUP_BASE + 0x10000) -#define OMAP3_GPIO2_BASE (OMAP3_L4_PER_BASE + 0x50000) -#define OMAP3_GPIO3_BASE (OMAP3_L4_PER_BASE + 0x52000) -#define OMAP3_GPIO4_BASE (OMAP3_L4_PER_BASE + 0x54000) -#define OMAP3_GPIO5_BASE (OMAP3_L4_PER_BASE + 0x56000) -#define OMAP3_GPIO6_BASE (OMAP3_L4_PER_BASE + 0x58000) - -/** MPU WDT Definition */ -#define OMAP3_MPU_WDTIMER_BASE OMAP3_WDTIMER2_BASE - -#define OMAP3_HSUSB_OTG_BASE (OMAP3_L4_CORE_BASE + 0xAB000) -#define OMAP3_USBTLL_BASE (OMAP3_L4_CORE_BASE + 0x62000) -#define OMAP3_UHH_CONFIG_BASE (OMAP3_L4_CORE_BASE + 0x64000) -#define OMAP3_OHCI_BASE (OMAP3_L4_CORE_BASE + 0x64400) -#define OMAP3_EHCI_BASE (OMAP3_L4_CORE_BASE + 0x64800) - -/** Interrupt Vector base address */ -#define OMAP3_SRAM_BASE 0x40200000 -#define OMAP3_SRAM_SCRATCH_SPACE 0x4020f000 /* start of public stack */ -#define OMAP3_SRAM_INTVECT 0x4020F800 -#define OMAP3_SRAM_INTVECT_COPYSIZE 0x64 - -/** Gives the silicon revision */ -#define OMAP3_TAP_BASE (OMAP3_L4_WKUP_BASE + 0xA000) -#define OMAP3_IDCODE_REG (OMAP3_TAP_BASE + 0x204) -#define OMAP3_DIE_ID_0 (OMAP3_TAP_BASE + 0x218) -#define OMAP3_DIE_ID_1 (OMAP3_TAP_BASE + 0x21c) -#define OMAP3_DIE_ID_2 (OMAP3_TAP_BASE + 0x220) -#define OMAP3_DIE_ID_3 (OMAP3_TAP_BASE + 0x224) - -/** Masks to extract information from ID code register */ -#define IDCODE_HAWKEYE_MASK 0x0FFFF000 -#define IDCODE_VERSION_MASK 0xF0000000 - - #define get_hawkeye(v) (((v) & IDCODE_HAWKEYE_MASK) >> 12) - #define get_version(v) (((v) & IDCODE_VERSION_MASK) >> 28) - -#define HAWKEYE_ES1 0x0B6D6000 -#define HAWKEYE_ES2 0x0B7AE000 -#define HAWKEYE_ES2_1 0x1B7AE000 - -#define DEVICE_MASK ((0x1 << 8)|(0x1 << 9)|(0x1 << 10)) - -#define OMAP_SDRC_CS0 0x80000000 -#define OMAP_SDRC_CS1 0xA0000000 - -/* PRM */ -#define OMAP3_PRM_RSTCTRL_RESET 0x04 - -/* - * ROM code API related flags - */ -#define OMAP3_GP_ROMCODE_API_L2_INVAL 1 -#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3 - -/* If Architecture specific init functions are present */ -#ifndef __ASSEMBLY__ -void omap3_core_init(void); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_OMAP3_H */ diff --git a/arch/arm/mach-omap/include/mach/omap3-smx.h b/arch/arm/mach-omap/include/mach/omap3-smx.h deleted file mode 100644 index fb444b8cf3..0000000000 --- a/arch/arm/mach-omap/include/mach/omap3-smx.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file - * @brief This file contains the SMX specific register definitions - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * include/asm-arm/arch-omap/omap34xx.h - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP_SMX_H -#define __ASM_ARCH_OMAP_SMX_H - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x12C00) -#define PM_IVA2_BASE_ADDR_ARM (OMAP3_SMX_APE_BASE + 0x14000) - -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -/* IVA2 */ -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -/* SMS */ -#define SMS_SYSCONFIG (OMAP3_SMS_BASE + 0x10) -#define SMS_RG_ATT0 (OMAP3_SMS_BASE + 0x48) -#define SMS_CLASS_ARB0 (OMAP3_SMS_BASE + 0xD0) -#define BURSTCOMPLETE_GROUP7 (0x1 << 31) - -#endif /* __ASM_ARCH_OMAP_SMX_H */ diff --git a/arch/arm/mach-omap/include/mach/omap4-clock.h b/arch/arm/mach-omap/include/mach/omap4-clock.h deleted file mode 100644 index 6bbb10e83d..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4-clock.h +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_OMAP4_CLOCK_H -#define __MACH_OMAP4_CLOCK_H - -/* PRCM */ -#define CM_SYS_CLKSEL 0x4a306110 - -#define CM_SYS_CLKSEL_19M2 0x4 -#define CM_SYS_CLKSEL_38M4 0x7 - -/* PRM.CKGEN module registers */ -#define CM_ABE_PLL_REF_CLKSEL 0x4a30610c - - -/* PRM.WKUP_CM module registers */ -#define CM_WKUP_CLKSTCTRL 0x4a307800 -#define CM_WKUP_L4WKUP_CLKCTRL 0x4a307820 -#define CM_WKUP_WDT1_CLKCTRL 0x4a307828 -#define CM_WKUP_WDT2_CLKCTRL 0x4a307830 -#define CM_WKUP_GPIO1_CLKCTRL 0x4a307838 -#define CM_WKUP_TIMER1_CLKCTRL 0x4a307840 -#define CM_WKUP_TIMER12_CLKCTRL 0x4a307848 -#define CM_WKUP_SYNCTIMER_CLKCTRL 0x4a307850 -#define CM_WKUP_USIM_CLKCTRL 0x4a307858 -#define CM_WKUP_SARRAM_CLKCTRL 0x4a307860 -#define CM_WKUP_KEYBOARD_CLKCTRL 0x4a307878 -#define CM_WKUP_RTC_CLKCTRL 0x4a307880 -#define CM_WKUP_BANDGAP_CLKCTRL 0x4a307888 - -/* CM1.CKGEN module registers */ -#define CM_CLKSEL_CORE 0x4a004100 -#define CM_CLKSEL_ABE 0x4a004108 -#define CM_DLL_CTRL 0x4a004110 -#define CM_CLKMODE_DPLL_CORE 0x4a004120 -#define CM_IDLEST_DPLL_CORE 0x4a004124 -#define CM_AUTOIDLE_DPLL_CORE 0x4a004128 -#define CM_CLKSEL_DPLL_CORE 0x4a00412c -#define CM_DIV_M2_DPLL_CORE 0x4a004130 -#define CM_DIV_M3_DPLL_CORE 0x4a004134 -#define CM_DIV_M4_DPLL_CORE 0x4a004138 -#define CM_DIV_M5_DPLL_CORE 0x4a00413c -#define CM_DIV_M6_DPLL_CORE 0x4a004140 -#define CM_DIV_M7_DPLL_CORE 0x4a004144 -#define CM_SSC_DELTAMSTEP_DPLL_CORE 0x4a004148 -#define CM_SSC_MODFREQDIV_DPLL_CORE 0x4a00414c -#define CM_EMU_OVERRIDE_DPLL_CORE 0x4a004150 -#define CM_CLKMODE_DPLL_MPU 0x4a004160 -#define CM_IDLEST_DPLL_MPU 0x4a004164 -#define CM_AUTOIDLE_DPLL_MPU 0x4a004168 -#define CM_CLKSEL_DPLL_MPU 0x4a00416c -#define CM_DIV_M2_DPLL_MPU 0x4a004170 -#define CM_SSC_DELTAMSTEP_DPLL_MPU 0x4a004188 -#define CM_SSC_MODFREQDIV_DPLL_MPU 0x4a00418c -#define CM_BYPCLK_DPLL_MPU 0x4a00419c -#define CM_CLKMODE_DPLL_IVA 0x4a0041a0 -#define CM_IDLEST_DPLL_IVA 0x4a0041a4 -#define CM_AUTOIDLE_DPLL_IVA 0x4a0041a8 -#define CM_CLKSEL_DPLL_IVA 0x4a0041ac -#define CM_DIV_M4_DPLL_IVA 0x4a0041b8 -#define CM_DIV_M5_DPLL_IVA 0x4a0041bc -#define CM_SSC_DELTAMSTEP_DPLL_IVA 0x4a0041c8 -#define CM_SSC_MODFREQDIV_DPLL_IVA 0x4a0041cc -#define CM_BYPCLK_DPLL_IVA 0x4a0041dc -#define CM_CLKMODE_DPLL_ABE 0x4a0041e0 -#define CM_IDLEST_DPLL_ABE 0x4a0041e4 -#define CM_AUTOIDLE_DPLL_ABE 0x4a0041e8 -#define CM_CLKSEL_DPLL_ABE 0x4a0041ec -#define CM_DIV_M2_DPLL_ABE 0x4a0041f0 -#define CM_DIV_M3_DPLL_ABE 0x4a0041f4 -#define CM_SSC_DELTAMSTEP_DPLL_ABE 0x4a004208 -#define CM_SSC_MODFREQDIV_DPLL_ABE 0x4a00420c -#define CM_CLKMODE_DPLL_DDRPHY 0x4a004220 -#define CM_IDLEST_DPLL_DDRPHY 0x4a004224 -#define CM_AUTOIDLE_DPLL_DDRPHY 0x4a004228 -#define CM_CLKSEL_DPLL_DDRPHY 0x4a00422c -#define CM_DIV_M2_DPLL_DDRPHY 0x4a004230 -#define CM_DIV_M4_DPLL_DDRPHY 0x4a004238 -#define CM_DIV_M5_DPLL_DDRPHY 0x4a00423c -#define CM_DIV_M6_DPLL_DDRPHY 0x4a004240 -#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY 0x4a004248 - -/* CM1.ABE register offsets */ -#define CM1_ABE_CLKSTCTRL 0x4a004500 -#define CM1_ABE_L4ABE_CLKCTRL 0x4a004520 -#define CM1_ABE_AESS_CLKCTRL 0x4a004528 -#define CM1_ABE_PDM_CLKCTRL 0x4a004530 -#define CM1_ABE_DMIC_CLKCTRL 0x4a004538 -#define CM1_ABE_MCASP_CLKCTRL 0x4a004540 -#define CM1_ABE_MCBSP1_CLKCTRL 0x4a004548 -#define CM1_ABE_MCBSP2_CLKCTRL 0x4a004550 -#define CM1_ABE_MCBSP3_CLKCTRL 0x4a004558 -#define CM1_ABE_SLIMBUS_CLKCTRL 0x4a004560 -#define CM1_ABE_TIMER5_CLKCTRL 0x4a004568 -#define CM1_ABE_TIMER6_CLKCTRL 0x4a004570 -#define CM1_ABE_TIMER7_CLKCTRL 0x4a004578 -#define CM1_ABE_TIMER8_CLKCTRL 0x4a004580 -#define CM1_ABE_WDT3_CLKCTRL 0x4a004588 - -/* CM1.DSP register offsets */ -#define DSP_CLKSTCTRL 0x4a004400 -#define DSP_DSP_CLKCTRL 0x4a004420 - -/* CM2.CKGEN module registers */ -#define CM_CLKSEL_DUCATI_ISS_ROOT 0x4a008100 -#define CM_CLKSEL_USB_60MHz 0x4a008104 -#define CM_SCALE_FCLK 0x4a008108 -#define CM_CORE_DVFS_PERF1 0x4a008110 -#define CM_CORE_DVFS_PERF2 0x4a008114 -#define CM_CORE_DVFS_PERF3 0x4a008118 -#define CM_CORE_DVFS_PERF4 0x4a00811c -#define CM_CORE_DVFS_CURRENT 0x4a008124 -#define CM_IVA_DVFS_PERF_TESLA 0x4a008128 -#define CM_IVA_DVFS_PERF_IVAHD 0x4a00812c -#define CM_IVA_DVFS_PERF_ABE 0x4a008130 -#define CM_IVA_DVFS_CURRENT 0x4a008138 -#define CM_CLKMODE_DPLL_PER 0x4a008140 -#define CM_IDLEST_DPLL_PER 0x4a008144 -#define CM_AUTOIDLE_DPLL_PER 0x4a008148 -#define CM_CLKSEL_DPLL_PER 0x4a00814c -#define CM_DIV_M2_DPLL_PER 0x4a008150 -#define CM_DIV_M3_DPLL_PER 0x4a008154 -#define CM_DIV_M4_DPLL_PER 0x4a008158 -#define CM_DIV_M5_DPLL_PER 0x4a00815c -#define CM_DIV_M6_DPLL_PER 0x4a008160 -#define CM_DIV_M7_DPLL_PER 0x4a008164 -#define CM_SSC_DELTAMSTEP_DPLL_PER 0x4a008168 -#define CM_SSC_MODFREQDIV_DPLL_PER 0x4a00816c -#define CM_EMU_OVERRIDE_DPLL_PER 0x4a008170 -#define CM_CLKMODE_DPLL_USB 0x4a008180 -#define CM_IDLEST_DPLL_USB 0x4a008184 -#define CM_AUTOIDLE_DPLL_USB 0x4a008188 -#define CM_CLKSEL_DPLL_USB 0x4a00818c -#define CM_DIV_M2_DPLL_USB 0x4a008190 -#define CM_SSC_DELTAMSTEP_DPLL_USB 0x4a0081a8 -#define CM_SSC_MODFREQDIV_DPLL_USB 0x4a0081ac -#define CM_CLKDCOLDO_DPLL_USB 0x4a0081b4 -#define CM_CLKMODE_DPLL_UNIPRO 0x4a0081c0 -#define CM_IDLEST_DPLL_UNIPRO 0x4a0081c4 -#define CM_AUTOIDLE_DPLL_UNIPRO 0x4a0081c8 -#define CM_CLKSEL_DPLL_UNIPRO 0x4a0081cc -#define CM_DIV_M2_DPLL_UNIPRO 0x4a0081d0 -#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO 0x4a0081e8 -#define CM_SSC_MODFREQDIV_DPLL_UNIPRO 0x4a0081ec - -/* CM2.CORE module registers */ -#define CM_L3_1_CLKSTCTRL 0x4a008700 -#define CM_L3_1_DYNAMICDEP 0x4a008708 -#define CM_L3_1_L3_1_CLKCTRL 0x4a008720 -#define CM_L3_2_CLKSTCTRL 0x4a008800 -#define CM_L3_2_DYNAMICDEP 0x4a008808 -#define CM_L3_2_L3_2_CLKCTRL 0x4a008820 -#define CM_L3_2_GPMC_CLKCTRL 0x4a008828 -#define CM_L3_2_OCMC_RAM_CLKCTRL 0x4a008830 -#define CM_DUCATI_CLKSTCTRL 0x4a008900 -#define CM_DUCATI_STATICDEP 0x4a008904 -#define CM_DUCATI_DYNAMICDEP 0x4a008908 -#define CM_DUCATI_DUCATI_CLKCTRL 0x4a008920 -#define CM_SDMA_CLKSTCTRL 0x4a008a00 -#define CM_SDMA_STATICDEP 0x4a008a04 -#define CM_SDMA_DYNAMICDEP 0x4a008a08 -#define CM_SDMA_SDMA_CLKCTRL 0x4a008a20 -#define CM_MEMIF_CLKSTCTRL 0x4a008b00 -#define CM_MEMIF_DMM_CLKCTRL 0x4a008b20 -#define CM_MEMIF_EMIF_FW_CLKCTRL 0x4a008b28 -#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30 -#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38 -#define CM_MEMIF_DLL_CLKCTRL 0x4a008b40 -#define CM_MEMIF_EMIF_H1_CLKCTRL 0x4a008b50 -#define CM_MEMIF_EMIF_H2_CLKCTRL 0x4a008b58 -#define CM_MEMIF_DLL_H_CLKCTRL 0x4a008b60 -#define CM_D2D_CLKSTCTRL 0x4a008c00 -#define CM_D2D_STATICDEP 0x4a008c04 -#define CM_D2D_DYNAMICDEP 0x4a008c08 -#define CM_D2D_SAD2D_CLKCTRL 0x4a008c20 -#define CM_D2D_MODEM_ICR_CLKCTRL 0x4a008c28 -#define CM_D2D_SAD2D_FW_CLKCTRL 0x4a008c30 -#define CM_L4CFG_CLKSTCTRL 0x4a008d00 -#define CM_L4CFG_DYNAMICDEP 0x4a008d08 -#define CM_L4CFG_L4_CFG_CLKCTRL 0x4a008d20 -#define CM_L4CFG_HW_SEM_CLKCTRL 0x4a008d28 -#define CM_L4CFG_MAILBOX_CLKCTRL 0x4a008d30 -#define CM_L4CFG_SAR_ROM_CLKCTRL 0x4a008d38 -#define CM_L3INSTR_CLKSTCTRL 0x4a008e00 -#define CM_L3INSTR_L3_3_CLKCTRL 0x4a008e20 -#define CM_L3INSTR_L3_INSTR_CLKCTRL 0x4a008e28 -#define CM_L3INSTR_OCP_WP1_CLKCTRL 0x4a008e40 - -/* CM2.L4PER register offsets */ -#define CM_L4PER_CLKSTCTRL 0x4a009400 -#define CM_L4PER_DYNAMICDEP 0x4a009408 -#define CM_L4PER_ADC_CLKCTRL 0x4a009420 -#define CM_L4PER_DMTIMER10_CLKCTRL 0x4a009428 -#define CM_L4PER_DMTIMER11_CLKCTRL 0x4a009430 -#define CM_L4PER_DMTIMER2_CLKCTRL 0x4a009438 -#define CM_L4PER_DMTIMER3_CLKCTRL 0x4a009440 -#define CM_L4PER_DMTIMER4_CLKCTRL 0x4a009448 -#define CM_L4PER_DMTIMER9_CLKCTRL 0x4a009450 -#define CM_L4PER_ELM_CLKCTRL 0x4a009458 -#define CM_L4PER_GPIO2_CLKCTRL 0x4a009460 -#define CM_L4PER_GPIO3_CLKCTRL 0x4a009468 -#define CM_L4PER_GPIO4_CLKCTRL 0x4a009470 -#define CM_L4PER_GPIO5_CLKCTRL 0x4a009478 -#define CM_L4PER_GPIO6_CLKCTRL 0x4a009480 -#define CM_L4PER_HDQ1W_CLKCTRL 0x4a009488 -#define CM_L4PER_HECC1_CLKCTRL 0x4a009490 -#define CM_L4PER_HECC2_CLKCTRL 0x4a009498 -#define CM_L4PER_I2C1_CLKCTRL 0x4a0094a0 -#define CM_L4PER_I2C2_CLKCTRL 0x4a0094a8 -#define CM_L4PER_I2C3_CLKCTRL 0x4a0094b0 -#define CM_L4PER_I2C4_CLKCTRL 0x4a0094b8 -#define CM_L4PER_L4PER_CLKCTRL 0x4a0094c0 -#define CM_L4PER_MCASP2_CLKCTRL 0x4a0094d0 -#define CM_L4PER_MCASP3_CLKCTRL 0x4a0094d8 -#define CM_L4PER_MCBSP4_CLKCTRL 0x4a0094e0 -#define CM_L4PER_MGATE_CLKCTRL 0x4a0094e8 -#define CM_L4PER_MCSPI1_CLKCTRL 0x4a0094f0 -#define CM_L4PER_MCSPI2_CLKCTRL 0x4a0094f8 -#define CM_L4PER_MCSPI3_CLKCTRL 0x4a009500 -#define CM_L4PER_MCSPI4_CLKCTRL 0x4a009508 -#define CM_L4PER_MMCSD3_CLKCTRL 0x4a009520 -#define CM_L4PER_MMCSD4_CLKCTRL 0x4a009528 -#define CM_L4PER_MSPROHG_CLKCTRL 0x4a009530 -#define CM_L4PER_SLIMBUS2_CLKCTRL 0x4a009538 -#define CM_L4PER_UART1_CLKCTRL 0x4a009540 -#define CM_L4PER_UART2_CLKCTRL 0x4a009548 -#define CM_L4PER_UART3_CLKCTRL 0x4a009550 -#define CM_L4PER_UART4_CLKCTRL 0x4a009558 -#define CM_L4PER_MMCSD5_CLKCTRL 0x4a009560 -#define CM_L4PER_I2C5_CLKCTRL 0x4a009568 -#define CM_L4SEC_CLKSTCTRL 0x4a009580 -#define CM_L4SEC_STATICDEP 0x4a009584 -#define CM_L4SEC_DYNAMICDEP 0x4a009588 -#define CM_L4SEC_AES1_CLKCTRL 0x4a0095a0 -#define CM_L4SEC_AES2_CLKCTRL 0x4a0095a8 -#define CM_L4SEC_DES3DES_CLKCTRL 0x4a0095b0 -#define CM_L4SEC_PKAEIP29_CLKCTRL 0x4a0095b8 -#define CM_L4SEC_RNG_CLKCTRL 0x4a0095c0 -#define CM_L4SEC_SHA2MD51_CLKCTRL 0x4a0095c8 -#define CM_L4SEC_CRYPTODMA_CLKCTRL 0x4a0095d8 - -/* CM2.IVAHD */ -#define IVAHD_CLKSTCTRL 0x4a008f00 -#define IVAHD_IVAHD_CLKCTRL 0x4a008f20 -#define IVAHD_SL2_CLKCTRL 0x4a008f28 - -/* CM2.L3INIT */ -#define CM_L3INIT_HSMMC1_CLKCTRL 0x4a009328 -#define CM_L3INIT_HSMMC2_CLKCTRL 0x4a009330 -#define CM_L3INIT_HSI_CLKCTRL 0x4a009338 -#define CM_L3INIT_UNIPRO1_CLKCTRL 0x4a009340 -#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4a009358 -#define CM_L3INIT_HSUSBOTG_CLKCTRL 0x4a009360 -#define CM_L3INIT_HSUSBTLL_CLKCTRL 0x4a009368 -#define CM_L3INIT_P1500_CLKCTRL 0x4a009378 -#define CM_L3INIT_FSUSB_CLKCTRL 0x4a0093d0 -#define CM_L3INIT_USBPHY_CLKCTRL 0x4a0093e0 - -/* CM2.CAM */ -#define CM_CAM_CLKSTCTRL 0x4a009000 -#define CM_CAM_ISS_CLKCTRL 0x4a009020 -#define CM_CAM_FDIF_CLKCTRL 0x4a009028 - -/* CM2.DSS */ -#define CM_DSS_CLKSTCTRL 0x4a009100 -#define CM_DSS_DSS_CLKCTRL 0x4a009120 -#define CM_DSS_DEISS_CLKCTRL 0x4a009128 - -/* CM2.SGX */ -#define CM_SGX_CLKSTCTRL 0x4a009200 -#define CM_SGX_SGX_CLKCTRL 0x4a009220 - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_MN_POWER_BYPASS 4 -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m7; -}; - -#define OMAP4_MPU_DPLL_PARAM_19M2 {0x34, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_19M2_MPU600 {0x7d, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1000 {0x69, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_38M4 {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_38M4_MPU600 {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_38M4_MPU1000 {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */ -#define OMAP4_MPU_DPLL_PARAM_19M2_MPU920 {0x30, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1200 {0x7d, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_MPU_DPLL_PARAM_19M2_MPU1500 {0x4e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00} - -#define OMAP4_IVA_DPLL_PARAM_19M2 {0x61, 0x01, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00} -#define OMAP4_IVA_DPLL_PARAM_38M4 {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00} - -#define OMAP4_PER_DPLL_PARAM_19M2 {0x28, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05} -#define OMAP4_PER_DPLL_PARAM_38M4 {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05} - -#define OMAP4_ABE_DPLL_PARAM_19M2 {0x80, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00} -#define OMAP4_ABE_DPLL_PARAM_38M4 {0x40, 0x18, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00} - -#define OMAP4_USB_DPLL_PARAM_19M2 {0x32, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0} -#define OMAP4_USB_DPLL_PARAM_38M4 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0} - -#define OMAP4_CORE_DPLL_PARAM_19M2_DDR200 {0x7d, 0x02, 0x02, 0x05, 0x08, 0x04, 0x06, 0x06} -#define OMAP4_CORE_DPLL_PARAM_19M2_DDR333 {0x410, 0x09, 0x03, 0x0c, 0x14, 0x0a, 0x0f, 0x0c} -#define OMAP4_CORE_DPLL_PARAM_19M2_DDR400 {0x7d, 0x02, 0x01, 0x05, 0x08, 0x04, 0x06, 0x06} -#define OMAP4_CORE_DPLL_PARAM_38M4_DDR200 {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x06} -#define OMAP4_CORE_DPLL_PARAM_38M4_DDR400 {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x06} - -void omap4_configure_mpu_dpll(const struct dpll_param *dpll_param); -void omap4_configure_iva_dpll(const struct dpll_param *dpll_param); -void omap4_configure_per_dpll(const struct dpll_param *dpll_param); -void omap4_configure_abe_dpll(const struct dpll_param *dpll_param); -void omap4_configure_usb_dpll(const struct dpll_param *dpll_param); -void omap4_configure_core_dpll_no_lock(const struct dpll_param *param); -void omap4_lock_core_dpll(void); -void omap4_lock_core_dpll_shadow(const struct dpll_param *param); -void omap4_enable_gpio1_wup_clocks(void); -void omap4_enable_gpio_clocks(void); -void omap4_enable_all_clocks(void); -void omap4_do_scale_tps62361(u32 reg, u32 volt_mv); - -#endif /* __MACH_OMAP4_CLOCK_H */ diff --git a/arch/arm/mach-omap/include/mach/omap4-devices.h b/arch/arm/mach-omap/include/mach/omap4-devices.h deleted file mode 100644 index 22a1eb79fc..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4-devices.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_OMAP4_DEVICES_H -#define __MACH_OMAP4_DEVICES_H - -#include <driver.h> -#include <linux/sizes.h> -#include <mach/devices.h> -#include <mach/omap4-silicon.h> -#include <mach/mcspi.h> -#include <mach/omap_hsmmc.h> - -static inline void omap44xx_add_sram0(void) -{ - return omap_add_sram0(OMAP44XX_SRAM_BASE, 48 * SZ_1K); -} - -static inline struct device_d *omap44xx_add_uart1(void) -{ - return omap_add_uart(0, OMAP44XX_UART1_BASE); -} - -static inline struct device_d *omap44xx_add_uart2(void) -{ - return omap_add_uart(1, OMAP44XX_UART2_BASE); -} - -static inline struct device_d *omap44xx_add_uart3(void) -{ - return omap_add_uart(2, OMAP44XX_UART3_BASE); -} - -static inline struct device_d *omap44xx_add_mmc1(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap4-hsmmc", 0, NULL, - OMAP44XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_mmc2(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap4-hsmmc", 1, NULL, - OMAP44XX_MMC2_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_mmc3(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap4-hsmmc", 2, NULL, - OMAP44XX_MMC3_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_mmc4(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap4-hsmmc", 3, NULL, - OMAP44XX_MMC4_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_mmc5(struct omap_hsmmc_platform_data *pdata) -{ - return add_generic_device("omap4-hsmmc", 4, NULL, - OMAP44XX_MMC5_BASE, SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_i2c1(void *pdata) -{ - return add_generic_device("i2c-omap4", 0, NULL, OMAP44XX_I2C1_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_i2c2(void *pdata) -{ - return add_generic_device("i2c-omap4", 1, NULL, OMAP44XX_I2C2_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_i2c3(void *pdata) -{ - return add_generic_device("i2c-omap4", 2, NULL, OMAP44XX_I2C3_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_i2c4(void *pdata) -{ - return add_generic_device("i2c-omap4", 3, NULL, OMAP44XX_I2C4_BASE, - SZ_4K, IORESOURCE_MEM, pdata); -} - -static inline struct device_d *omap44xx_add_ehci(void *pdata) -{ - return add_usb_ehci_device(DEVICE_ID_DYNAMIC, OMAP44XX_EHCI_BASE, - OMAP44XX_EHCI_BASE + 0x10, pdata); -} - -#endif /* __MACH_OMAP4_DEVICES_H */ diff --git a/arch/arm/mach-omap/include/mach/omap4-generic.h b/arch/arm/mach-omap/include/mach/omap4-generic.h deleted file mode 100644 index b6a72cfc55..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4-generic.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_OMAP4_GENERIC_H -#define __MACH_OMAP4_GENERIC_H - -#include <linux/sizes.h> -#include <mach/generic.h> -#include <mach/omap4-silicon.h> - -static inline void omap4_save_bootinfo(uint32_t *info) -{ - unsigned long i = (unsigned long)info; - - if (i & 0x3) - return; - if (i < OMAP44XX_SRAM_BASE) - return; - if (i > OMAP44XX_SRAM_BASE + SZ_64K) - return; - - memcpy((void *)OMAP44XX_SRAM_SCRATCH_SPACE, info, 3 * sizeof(uint32_t)); -} - -int omap4_init(void); -int omap4_devices_init(void); - -#endif /* __MACH_OMAP4_GENERIC_H */ diff --git a/arch/arm/mach-omap/include/mach/omap4-mux.h b/arch/arm/mach-omap/include/mach/omap4-mux.h deleted file mode 100644 index 8ef9ae0847..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4-mux.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef _MUX_OMAP4_H_ -#define _MUX_OMAP4_H_ - -#include <asm/types.h> - -struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - -#define WAKEUP_EN (1 << 14) -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define GPMC_AD0 0x0040 -#define GPMC_AD1 0x0042 -#define GPMC_AD2 0x0044 -#define GPMC_AD3 0x0046 -#define GPMC_AD4 0x0048 -#define GPMC_AD5 0x004A -#define GPMC_AD6 0x004C -#define GPMC_AD7 0x004E -#define GPMC_AD8 0x0050 -#define GPMC_AD9 0x0052 -#define GPMC_AD10 0x0054 -#define GPMC_AD11 0x0056 -#define GPMC_AD12 0x0058 -#define GPMC_AD13 0x005A -#define GPMC_AD14 0x005C -#define GPMC_AD15 0x005E -#define GPMC_A16 0x0060 -#define GPMC_A17 0x0062 -#define GPMC_A18 0x0064 -#define GPMC_A19 0x0066 -#define GPMC_A20 0x0068 -#define GPMC_A21 0x006A -#define GPMC_A22 0x006C -#define GPMC_A23 0x006E -#define GPMC_A24 0x0070 -#define GPMC_A25 0x0072 -#define GPMC_NCS0 0x0074 -#define GPMC_NCS1 0x0076 -#define GPMC_NCS2 0x0078 -#define GPMC_NCS3 0x007A -#define GPMC_NWP 0x007C -#define GPMC_CLK 0x007E -#define GPMC_NADV_ALE 0x0080 -#define GPMC_NOE 0x0082 -#define GPMC_NWE 0x0084 -#define GPMC_NBE0_CLE 0x0086 -#define GPMC_NBE1 0x0088 -#define GPMC_WAIT0 0x008A -#define GPMC_WAIT1 0x008C -#define C2C_DATA11 0x008E -#define GPMC_WAIT2 0x008E -#define C2C_DATA12 0x0090 -#define GPMC_NCS4 0x0090 -#define C2C_DATA13 0x0092 -#define GPMC_NCS5 0x0092 -#define C2C_DATA14 0x0094 -#define GPMC_NCS6 0x0094 -#define C2C_DATA15 0x0096 -#define GPMC_NCS7 0x0096 -#define HDMI_HPD 0x0098 -#define GPIO63 0x0098 -#define HDMI_CEC 0x009A -#define GPIO64 0x009A -#define HDMI_DDC_SCL 0x009C -#define GPIO65 0x009C -#define HDMI_DDC_SDA 0x009E -#define GPIO66 0x009E -#define CSI21_DX0 0x00A0 -#define CSI21_DY0 0x00A2 -#define CSI21_DX1 0x00A4 -#define CSI21_DY1 0x00A6 -#define CSI21_DX2 0x00A8 -#define CSI21_DY2 0x00AA -#define CSI21_DX3 0x00AC -#define CSI21_DY3 0x00AE -#define CSI21_DX4 0x00B0 -#define CSI21_DY4 0x00B2 -#define CSI22_DX0 0x00B4 -#define CSI22_DY0 0x00B6 -#define CSI22_DX1 0x00B8 -#define CSI22_DY1 0x00BA -#define CAM_SHUTTER 0x00BC -#define CAM_STROBE 0x00BE -#define CAM_GLOBALRESET 0x00C0 -#define USBB1_ULPITLL_CLK 0x00C2 -#define USBB1_ULPITLL_STP 0x00C4 -#define USBB1_ULPITLL_DIR 0x00C6 -#define USBB1_ULPITLL_NXT 0x00C8 -#define USBB1_ULPITLL_DAT0 0x00CA -#define USBB1_ULPITLL_DAT1 0x00CC -#define USBB1_ULPITLL_DAT2 0x00CE -#define USBB1_ULPITLL_DAT3 0x00D0 -#define USBB1_ULPITLL_DAT4 0x00D2 -#define USBB1_ULPITLL_DAT5 0x00D4 -#define USBB1_ULPITLL_DAT6 0x00D6 -#define USBB1_ULPITLL_DAT7 0x00D8 -#define USBB1_HSIC_DATA 0x00DA -#define USBB1_HSIC_STROBE 0x00DC -#define USBC1_ICUSB_DP 0x00DE -#define USBC1_ICUSB_DM 0x00E0 -#define SDMMC1_CLK 0x00E2 -#define SDMMC1_CMD 0x00E4 -#define SDMMC1_DAT0 0x00E6 -#define SDMMC1_DAT1 0x00E8 -#define SDMMC1_DAT2 0x00EA -#define SDMMC1_DAT3 0x00EC -#define SDMMC1_DAT4 0x00EE -#define SDMMC1_DAT5 0x00F0 -#define SDMMC1_DAT6 0x00F2 -#define SDMMC1_DAT7 0x00F4 -#define ABE_MCBSP2_CLKX 0x00F6 -#define ABE_MCBSP2_DR 0x00F8 -#define ABE_MCBSP2_DX 0x00FA -#define ABE_MCBSP2_FSX 0x00FC -#define ABE_MCBSP1_CLKX 0x00FE -#define ABE_MCBSP1_DR 0x0100 -#define ABE_MCBSP1_DX 0x0102 -#define ABE_MCBSP1_FSX 0x0104 -#define ABE_PDM_UL_DATA 0x0106 -#define ABE_PDM_DL_DATA 0x0108 -#define ABE_PDM_FRAME 0x010A -#define ABE_PDM_LB_CLK 0x010C -#define ABE_CLKS 0x010E -#define ABE_DMIC_CLK1 0x0110 -#define ABE_DMIC_DIN1 0x0112 -#define ABE_DMIC_DIN2 0x0114 -#define ABE_DMIC_DIN3 0x0116 -#define UART2_CTS 0x0118 -#define UART2_RTS 0x011A -#define UART2_RX 0x011C -#define UART2_TX 0x011E -#define HDQ_SIO 0x0120 -#define I2C1_SCL 0x0122 -#define I2C1_SDA 0x0124 -#define I2C2_SCL 0x0126 -#define I2C2_SDA 0x0128 -#define I2C3_SCL 0x012A -#define I2C3_SDA 0x012C -#define I2C4_SCL 0x012E -#define I2C4_SDA 0x0130 -#define MCSPI1_CLK 0x0132 -#define MCSPI1_SOMI 0x0134 -#define MCSPI1_SIMO 0x0136 -#define MCSPI1_CS0 0x0138 -#define MCSPI1_CS1 0x013A -#define MCSPI1_CS2 0x013C -#define MCSPI1_CS3 0x013E -#define UART3_CTS_RCTX 0x0140 -#define UART3_RTS_SD 0x0142 -#define UART3_RX_IRRX 0x0144 -#define UART3_TX_IRTX 0x0146 -#define SDMMC5_CLK 0x0148 -#define SDMMC5_CMD 0x014A -#define SDMMC5_DAT0 0x014C -#define SDMMC5_DAT1 0x014E -#define SDMMC5_DAT2 0x0150 -#define SDMMC5_DAT3 0x0152 -#define MCSPI4_CLK 0x0154 -#define MCSPI4_SIMO 0x0156 -#define MCSPI4_SOMI 0x0158 -#define MCSPI4_CS0 0x015A -#define UART4_RX 0x015C -#define UART4_TX 0x015E -#define USBB2_ULPITLL_CLK 0x0160 -#define USBB2_ULPITLL_STP 0x0162 -#define USBB2_ULPITLL_DIR 0x0164 -#define USBB2_ULPITLL_NXT 0x0166 -#define USBB2_ULPITLL_DAT0 0x0168 -#define USBB2_ULPITLL_DAT1 0x016A -#define USBB2_ULPITLL_DAT2 0x016C -#define USBB2_ULPITLL_DAT3 0x016E -#define USBB2_ULPITLL_DAT4 0x0170 -#define USBB2_ULPITLL_DAT5 0x0172 -#define USBB2_ULPITLL_DAT6 0x0174 -#define USBB2_ULPITLL_DAT7 0x0176 -#define USBB2_HSIC_DATA 0x0178 -#define USBB2_HSIC_STROBE 0x017A -#define UNIPRO_TX0 0x017C -#define KPD_COL3 0x017C -#define UNIPRO_TY0 0x017E -#define KPD_COL4 0x017E -#define UNIPRO_TX1 0x0180 -#define KPD_COL5 0x0180 -#define UNIPRO_TY1 0x0182 -#define KPD_COL0 0x0182 -#define UNIPRO_TX2 0x0184 -#define KPD_COL1 0x0184 -#define UNIPRO_TY2 0x0186 -#define KPD_COL2 0x0186 -#define UNIPRO_RX0 0x0188 -#define KPD_ROW3 0x0188 -#define UNIPRO_RY0 0x018A -#define KPD_ROW4 0x018A -#define UNIPRO_RX1 0x018C -#define KPD_ROW5 0x018C -#define UNIPRO_RY1 0x018E -#define KPD_ROW0 0x018E -#define UNIPRO_RX2 0x0190 -#define KPD_ROW1 0x0190 -#define UNIPRO_RY2 0x0192 -#define KPD_ROW2 0x0192 -#define USBA0_OTG_CE 0x0194 -#define USBA0_OTG_DP 0x0196 -#define USBA0_OTG_DM 0x0198 -#define FREF_CLK1_OUT 0x019A -#define FREF_CLK2_OUT 0x019C -#define SYS_NIRQ1 0x019E -#define SYS_NIRQ2 0x01A0 -#define SYS_BOOT0 0x01A2 -#define SYS_BOOT1 0x01A4 -#define SYS_BOOT2 0x01A6 -#define SYS_BOOT3 0x01A8 -#define SYS_BOOT4 0x01AA -#define SYS_BOOT5 0x01AC -#define DPM_EMU0 0x01AE -#define DPM_EMU1 0x01B0 -#define DPM_EMU2 0x01B2 -#define DPM_EMU3 0x01B4 -#define DPM_EMU4 0x01B6 -#define DPM_EMU5 0x01B8 -#define DPM_EMU6 0x01BA -#define DPM_EMU7 0x01BC -#define DPM_EMU8 0x01BE -#define DPM_EMU9 0x01C0 -#define DPM_EMU10 0x01C2 -#define DPM_EMU11 0x01C4 -#define DPM_EMU12 0x01C6 -#define DPM_EMU13 0x01C8 -#define DPM_EMU14 0x01CA -#define DPM_EMU15 0x01CC -#define DPM_EMU16 0x01CE -#define DPM_EMU17 0x01D0 -#define DPM_EMU18 0x01D2 -#define DPM_EMU19 0x01D4 -#define CSI22_DX2 0x01D6 -#define CSI22_DY2 0x01F4 -#define WAKEUPEVENT_0 0x01D8 -#define WAKEUPEVENT_1 0x01DC -#define WAKEUPEVENT_2 0x01E0 -#define WAKEUPEVENT_3 0x01E4 -#define WAKEUPEVENT_4 0x01E8 -#define WAKEUPEVENT_5 0x01EC -#define WAKEUPEVENT_6 0x01F0 - -#define WKUP_REVISION 0x0000 -#define WKUP_HWINFO 0x0004 -#define WKUP_SYSCONFIG 0x0010 -#define GPIO_WK0 0x0040 -#define GPIO_WK1 0x0042 -#define GPIO_WK2 0x0044 -#define GPIO_WK3 0x0046 -#define GPIO_WK4 0x0048 -#define SR_SCL 0x004A -#define SR_SDA 0x004C -#define FREF_XTAL_IN 0x004E -#define FREF_SLICER_IN 0x0050 -#define FREF_CLK_IOREQ 0x0052 -#define FREF_CLK0_OUT 0x0054 -#define FREF_CLK3_REQ 0x0056 -#define FREF_CLK3_OUT 0x0058 -#define FREF_CLK4_REQ 0x005A -#define FREF_CLK4_OUT 0x005C -#define SYS_32K 0x005E -#define SYS_NRESPWRON 0x0060 -#define SYS_NRESWARM 0x0062 -#define SYS_PWR_REQ 0x0064 -#define SYS_PWRON_RESET_OUT 0x0066 -#define SYS_BOOT6 0x0068 -#define SYS_BOOT7 0x006A -#define JTAG_NTRST 0x006C -#define JTAG_TCK 0x006E -#define JTAG_RTCK 0x0070 -#define JTAG_TMS_TMSC 0x0072 -#define JTAG_TDI 0x0074 -#define JTAG_TDO 0x0076 -#define PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_SPARE_RW 0x0614 -#define CONTROL_SPARE_R 0x0618 -#define CONTROL_SPARE_R_C0 0x061C - -void omap4_do_set_mux(u32 base, struct pad_conf_entry const *array, int size); - -#endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap4-silicon.h b/arch/arm/mach-omap/include/mach/omap4-silicon.h deleted file mode 100644 index b9f6119894..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4-silicon.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Authors: - * Aneesh V <aneesh@ti.com> - * - * Derived from OMAP3 work by - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _OMAP4_H_ -#define _OMAP4_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP44XX_L4_CORE_BASE 0x4A000000 -#define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000 -#define OMAP44XX_L4_WKUP_BASE 0x4A300000 -#define OMAP44XX_L4_PER_BASE 0x48000000 - -#define OMAP44XX_SRAM_BASE 0x40300000 -#define OMAP44XX_SRAM_SCRATCH_SPACE 0x4030c000 /* start of public stack */ - -/* EMIF and DMM registers */ -#define OMAP44XX_EMIF1_BASE 0x4c000000 -#define OMAP44XX_EMIF2_BASE 0x4d000000 - -#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 - - -/* CONTROL */ -#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) -#define OMAP44XX_CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000) -#define OMAP44XX_CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000) - -/* PRM */ -#define OMAP44XX_PRM_VC_VAL_BYPASS (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0) -#define OMAP44XX_PRM_VC_CFG_I2C_MODE (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8) -#define OMAP44XX_PRM_VC_CFG_I2C_CLK (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac) -#define OMAP44XX_PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 -#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 -#define OMAP44XX_PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F -#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 -#define OMAP44XX_PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF -#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_SHIFT 16 -#define OMAP44XX_PRM_VC_VAL_BYPASS_DATA_MASK 0xFF - -/* IRQ */ -#define OMAP44XX_PRM_IRQSTATUS_MPU_A9 (OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010) - -/* UART */ -#define OMAP44XX_UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) -#define OMAP44XX_UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) -#define OMAP44XX_UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) - -/* I2C */ -#define OMAP44XX_I2C1_BASE (OMAP44XX_L4_PER_BASE + 0x070000) -#define OMAP44XX_I2C2_BASE (OMAP44XX_L4_PER_BASE + 0x072000) -#define OMAP44XX_I2C3_BASE (OMAP44XX_L4_PER_BASE + 0x060000) -#define OMAP44XX_I2C4_BASE (OMAP44XX_L4_PER_BASE + 0x350000) - -/* General Purpose Timers */ -#define OMAP44XX_GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) -#define OMAP44XX_GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) -#define OMAP44XX_GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) - -/* Watchdog Timer2 - MPU watchdog */ -#define OMAP44XX_WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) - -#define OMAP44XX_SCRM_BASE 0x4a30a000 -#define OMAP44XX_SCRM_ALTCLKSRC (OMAP44XX_SCRM_BASE + 0x110) -#define OMAP44XX_SCRM_AUXCLK1 (OMAP44XX_SCRM_BASE + 0x314) -#define OMAP44XX_SCRM_AUXCLK3 (OMAP44XX_SCRM_BASE + 0x31c) - -/* 32KTIMER */ -#define OMAP44XX_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000) - -/* MMC */ -#define OMAP44XX_MMC1_BASE (OMAP44XX_L4_PER_BASE + 0x09C000) -#define OMAP44XX_MMC2_BASE (OMAP44XX_L4_PER_BASE + 0x0B4000) -#define OMAP44XX_MMC3_BASE (OMAP44XX_L4_PER_BASE + 0x0AD000) -#define OMAP44XX_MMC4_BASE (OMAP44XX_L4_PER_BASE + 0x0D1000) -#define OMAP44XX_MMC5_BASE (OMAP44XX_L4_PER_BASE + 0x0D5000) - -/* GPIO - * - * Note that, while the GPIO controller is the same as on an OMAP3, - * the base address has an additional offset of 0x100, which you can - * see being added here so that the OMAP_GPIO_* macros you see in - * mach-omap/gpio.c don't need to be adjusted based on the platform. - */ - -#define OMAP44XX_GPIO1_BASE (OMAP44XX_L4_WKUP_BASE + 0x10100) -#define OMAP44XX_GPIO2_BASE (OMAP44XX_L4_PER_BASE + 0x55100) -#define OMAP44XX_GPIO3_BASE (OMAP44XX_L4_PER_BASE + 0x57100) -#define OMAP44XX_GPIO4_BASE (OMAP44XX_L4_PER_BASE + 0x59100) -#define OMAP44XX_GPIO5_BASE (OMAP44XX_L4_PER_BASE + 0x5B100) -#define OMAP44XX_GPIO6_BASE (OMAP44XX_L4_PER_BASE + 0x5D100) - -/* GPMC */ -#define OMAP44XX_GPMC_BASE 0x50000000 - -/* EHCI */ -#define OMAP44XX_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) - -/* DMM */ -#define OMAP44XX_DMM_BASE 0x4E000000 -#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40) -#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20) -#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20 -#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24) - -/* Memory Adapter (4460 onwards) */ -#define OMAP44XX_MA_BASE 0x482AF000 - -/* - * Hardware Register Details - */ - -/* Watchdog Timer */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* GP Timer */ -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* - * PRCM - */ - -/* PRM */ -#define OMAP44XX_PRM_BASE 0x4A306000 -#define OMAP44XX_PRM_DEVICE_BASE (OMAP44XX_PRM_BASE + 0x1B00) - -#define OMAP44XX_PRM_RSTCTRL OMAP44XX_PRM_DEVICE_BASE -#define OMAP44XX_PRM_RSTCTRL_RESET 0x01 - -/* - * SAR (Save & Rescue) memory region - */ -#define OMAP44XX_SAR_RAM_BASE 0x4a326000 -#define OMAP44XX_SAR_CH_ADDRESS (OMAP44XX_SAR_RAM_BASE + 0xA00) -#define OMAP44XX_SAR_CH_START (OMAP44XX_SAR_RAM_BASE + 0xA0C) -#define OMAP44XX_SAR_BOOT_VOID 0x00 -#define OMAP44XX_SAR_BOOT_XIP 0x01 -#define OMAP44XX_SAR_BOOT_XIPWAIT 0x02 -#define OMAP44XX_SAR_BOOT_NAND 0x03 -#define OMAP44XX_SAR_BOOT_ONENAND 0x04 -#define OMAP44XX_SAR_BOOT_MMC1 0x05 -#define OMAP44XX_SAR_BOOT_MMC2_1 0x06 -#define OMAP44XX_SAR_BOOT_MMC2_2 0x07 -#define OMAP44XX_SAR_BOOT_UART 0x43 -#define OMAP44XX_SAR_BOOT_USB_1 0x45 -#define OMAP44XX_SAR_BOOT_USB_ULPI 0x46 -#define OMAP44XX_SAR_BOOT_USB_2 0x47 - -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ -#define NON_SECURE_SRAM_START 0x40304000 -#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_ROM_VECT_BASE 0x4030D000 - -/* - * OMAP4 real hardware: - * TODO: Change this to the IDCODE in the hw regsiter - */ -#define CPU_OMAP4430_ES10 1 -#define CPU_OMAP4430_ES20 2 - -#define CM_DLL_CTRL 0x4a004110 -#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30 -#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38 - -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0 -#define OMAP4430_ES1_0 1 -#define OMAP4430_ES2_0 2 -#define OMAP4430_ES2_1 3 -#define OMAP4430_ES2_2 4 -#define OMAP4430_ES2_3 5 -#define OMAP4460_ES1_0 6 -#define OMAP4460_ES1_1 7 - -#ifndef __ASSEMBLY__ - -struct ddr_regs { - u32 tim1; - u32 tim2; - u32 tim3; - u32 phy_ctrl_1; - u32 ref_ctrl; - u32 config_init; - u32 config_final; - u32 zq_config; - u8 mr1; - u8 mr2; -}; - -struct dpll_param; - -void omap4_ddr_init(const struct ddr_regs *, const struct dpll_param *); -void omap4_power_i2c_send(u32); -unsigned int omap4_revision(void); -int omap4430_scale_vcores(void); -int omap4460_scale_vcores(unsigned vsel0_pin, unsigned volt_mv); -void omap4_set_warmboot_order(u32 *device_list); - -#endif - -#endif diff --git a/arch/arm/mach-omap/include/mach/omap4_rom_usb.h b/arch/arm/mach-omap/include/mach/omap4_rom_usb.h deleted file mode 100644 index bf8bd159ad..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4_rom_usb.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2010 The Android Open Source Project - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _OMAP4_ROM_USB_H_ -#define _OMAP4_ROM_USB_H_ - -/* public api */ -#define PUBLIC_API_BASE_4430 (0x28400) -#define PUBLIC_API_BASE_4460 (0x30400) - -#define PUBLIC_GET_DRIVER_MEM_OFFSET (0x04) -#define PUBLIC_GET_DRIVER_PER_OFFSET (0x08) -#define PUBLIC_GET_DEVICE_MEM_OFFSET (0x80) -#define PUBLIC_GET_DEVICE_PER_OFFSET (0x84) - -#define DEVICE_NULL 0x40 -#define DEVICE_UART1 0x41 -#define DEVICE_UART2 0x42 -#define DEVICE_UART3 0x43 -#define DEVICE_UART4 0x44 -#define DEVICE_USB 0x45 -#define DEVICE_USBEXT 0x46 - -#define XFER_MODE_CPU 0 -#define XFER_MODE_DMA 1 - -#define STATUS_OKAY 0 -#define STATUS_FAILED 1 -#define STATUS_TIMEOUT 2 -#define STATUS_BAD_PARAM 3 -#define STATUS_WAITING 4 -#define STATUS_NO_MEMORY 5 -#define STATUS_INVALID_PTR 6 - -/* Memory ROM interface */ -struct read_desc { - u32 sector_start; - u32 sector_count; - void *destination; -}; - -struct mem_device { - u32 initialized; - u8 device_type; - u8 trials_count; - u32 xip_device; - u16 search_size; - u32 base_address; - u16 hs_toc_mask; - u16 gp_toc_mask; - void *device_data; - u16 *boot_options; -}; - -struct mem_driver { - int (*init)(struct mem_device *md); - int (*read)(struct mem_device *md, struct read_desc *rd); - int (*configure)(struct mem_device *md, void *config); -}; - - -/* Peripheral ROM interface */ -struct per_handle { - void *set_to_null; - void (*callback)(struct per_handle *rh); - void *data; - u32 length; - u16 *options; - u32 xfer_mode; - u32 device_type; - u32 status; - u16 hs_toc_mask; - u16 gp_toc_mask; - u32 config_timeout; -}; - -struct per_driver { - int (*init)(struct per_handle *rh); - int (*read)(struct per_handle *rh); - int (*write)(struct per_handle *rh); - int (*close)(struct per_handle *rh); - int (*config)(struct per_handle *rh, void *x); -}; - -#define USB_SETCONFIGDESC_ATTRIBUTES (0) -#define USB_SETCONFIGDESC_MAXPOWER (1) -#define USB_SETSUSPEND_CALLBACK (2) -struct per_usb_config { - u32 configid; - u32 value; -}; - -#define API(n) ((void *) (*((u32 *) (n)))) -/* ROM API End */ - -struct omap4_usbboot { - struct per_handle dread; - struct per_handle dwrite; - struct per_driver *io; - int ready; -}; - -int omap4_usbboot_open(void); -int omap4_usbboot_ready(void); -void omap4_usbboot_close(void); - -void omap4_usbboot_queue_read(void *data, unsigned len); -int omap4_usbboot_wait_read(void); -int omap4_usbboot_is_read_waiting(void); -int omap4_usbboot_is_read_ok(void); - -void omap4_usbboot_queue_write(void *data, unsigned len); -int omap4_usbboot_wait_write(void); - -int omap4_usbboot_read(void *data, unsigned len); -int omap4_usbboot_write(void *data, unsigned len); -void omap4_usbboot_puts(const char *s); - -#endif diff --git a/arch/arm/mach-omap/include/mach/omap4_twl6030_mmc.h b/arch/arm/mach-omap/include/mach/omap4_twl6030_mmc.h deleted file mode 100644 index 0cde30619b..0000000000 --- a/arch/arm/mach-omap/include/mach/omap4_twl6030_mmc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Copyright (C) 2011 Alexander Aring <a.aring@phytec.de> - */ - -#ifndef __OMAP4_TWL6030_MMC_H__ -#define __OMAP4_TWL6030_MMC_H__ - -/* - * Sets up voltage for mmc slot. - */ -void set_up_mmc_voltage_omap4(void); - -/* __OMAP4_TWL6030_MMC_H__ */ -#endif diff --git a/arch/arm/mach-omap/include/mach/omap_hsmmc.h b/arch/arm/mach-omap/include/mach/omap_hsmmc.h deleted file mode 100644 index 19942df587..0000000000 --- a/arch/arm/mach-omap/include/mach/omap_hsmmc.h +++ /dev/null @@ -1,26 +0,0 @@ -/** - * @file - * @brief This file contains exported structure for OMAP hsmmc - * - * OMAP3 and OMAP4 has a MMC/SD controller embedded. - * This file provides the platform data structure required to - * addapt to platform specialities. - * - * (C) Copyright 2011 - * Phytec Messtechnik GmbH, <www.phytec.de> - * Juergen Kilb <j.kilb@phytec.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_OMAP_HSMMC_H -#define __ASM_OMAP_HSMMC_H - -/** omapmmc platform data structure */ -struct omap_hsmmc_platform_data { - unsigned f_max; /* host interface upper limit */ - char *devname; /* The mci device name, optional */ -}; -#endif /* __ASM_OMAP_HSMMC_H */ diff --git a/arch/arm/mach-omap/include/mach/sdrc.h b/arch/arm/mach-omap/include/mach/sdrc.h deleted file mode 100644 index 1cccbc63e2..0000000000 --- a/arch/arm/mach-omap/include/mach/sdrc.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * @file - * @brief This file contains the SDRC specific register definitions - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _ASM_ARCH_SDRC_H -#define _ASM_ARCH_SDRC_H - -#define OMAP3_SDRC_REG(REGNAME) (OMAP3_SDRC_BASE + OMAP_SDRC_##REGNAME) -#define OMAP_SDRC_SYSCONFIG (0x10) -#define OMAP_SDRC_STATUS (0x14) -#define OMAP_SDRC_CS_CFG (0x40) -#define OMAP_SDRC_SHARING (0x44) -#define OMAP_SDRC_DLLA_CTRL (0x60) -#define OMAP_SDRC_DLLA_STATUS (0x64) -#define OMAP_SDRC_DLLB_CTRL (0x68) -#define OMAP_SDRC_DLLB_STATUS (0x6C) -#define DLLPHASE (0x1 << 1) -#define LOADDLL (0x1 << 2) -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK ((0x1 << 8)|(0x1 << 9)) - -#define OMAP_SDRC_POWER (0x70) -#define WAKEUPPROC (0x1 << 26) - -#define OMAP_SDRC_MCFG_0 (0x80) -#define OMAP_SDRC_MCFG_1 (0xB0) -#define OMAP_SDRC_MR_0 (0x84) -#define OMAP_SDRC_MR_1 (0xB4) -#define OMAP_SDRC_ACTIM_CTRLA_0 (0x9C) -#define OMAP_SDRC_ACTIM_CTRLB_0 (0xA0) -#define OMAP_SDRC_ACTIM_CTRLA_1 (0xC4) -#define OMAP_SDRC_ACTIM_CTRLB_1 (0xC8) -#define OMAP_SDRC_RFR_CTRL_0 (0xA4) -#define OMAP_SDRC_RFR_CTRL_1 (0xD4) -#define OMAP_SDRC_MANUAL_0 (0xA8) -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET (0x1 << 1) -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -#define SDRC_CS0_OSET 0x0 -/* Mirror CS1 regs appear offset 0x30 from CS0 */ -#define SDRC_CS1_OSET 0x30 - -#define SDRC_STACKED 0 -#define SDRC_IP_DDR 1 -#define SDRC_COMBO_DDR 2 -#define SDRC_IP_SDR 3 - - -#define SDRC_B_R_C (0 << 6) /* bank-row-column */ -#define SDRC_B1_R_B0_C (1 << 6) /* bank1-row-bank0-column */ -#define SDRC_R_B_C (2 << 6) /* row-bank-column */ - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -#endif /* _ASM_ARCH_SDRC_H */ diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h deleted file mode 100644 index 57bfb3c680..0000000000 --- a/arch/arm/mach-omap/include/mach/sys_info.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * @file - * @brief This file defines the macros apis which are useful for most OMAP - * platforms. - * - * These are implemented by the System specific code in omapX-generic.c - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_SYS_INFO_H_ -#define __ASM_ARCH_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_1610 0x1610 -#define CPU_1710 0x1710 -#define CPU_2420 0x2420 -#define CPU_2430 0x2430 -#define CPU_3350 0x3350 -#define CPU_3430 0x3430 -#define CPU_3630 0x3630 -#define CPU_AM35XX 0x3500 - -/** - * Define CPU revisions - */ -#define cpu_revision(cpu,rev) (((cpu) << 16) | (rev)) - -#define OMAP34XX_ES1 cpu_revision(CPU_3430, 0) -#define OMAP34XX_ES2 cpu_revision(CPU_3430, 1) -#define OMAP34XX_ES2_1 cpu_revision(CPU_3430, 2) -#define OMAP34XX_ES3 cpu_revision(CPU_3430, 3) -#define OMAP34XX_ES3_1 cpu_revision(CPU_3430, 4) - -#define AM335X_ES1_0 cpu_revision(CPU_3350, 0) -#define AM335X_ES2_0 cpu_revision(CPU_3350, 1) -#define AM335X_ES2_1 cpu_revision(CPU_3350, 2) - -#define OMAP36XX_ES1 cpu_revision(CPU_3630, 0) -#define OMAP36XX_ES1_1 cpu_revision(CPU_3630, 1) -#define OMAP36XX_ES1_2 cpu_revision(CPU_3630, 2) - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/** - * Hawkeye definitions to identify silicon families - */ -#define OMAP_HAWKEYE_34XX 0xB7AE /* OMAP34xx */ -#define OMAP_HAWKEYE_36XX 0xB891 /* OMAP36xx */ -#define OMAP_HAWKEYE_335X 0xB944 /* AM335x */ -#define OMAP_HAWKEYE_AM35XX 0xb868 /* AM35xx */ - -/** These are implemented by the System specific code in omapX-generic.c */ -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_sdr_cs_size(u32 offset); -u32 get_sdr_cs1_base(void); -u32 get_sysboot_value(void); -u32 get_boot_type(void); -u32 get_device_type(void); - -#endif /*__ASM_ARCH_SYS_INFO_H_ */ diff --git a/arch/arm/mach-omap/include/mach/syslib.h b/arch/arm/mach-omap/include/mach/syslib.h deleted file mode 100644 index fe8d71d802..0000000000 --- a/arch/arm/mach-omap/include/mach/syslib.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * @file - * @brief These Apis are OMAP independent support functions - * - * Implemented by arch/arm/mach-omap/syslib.c - * - * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz - * - * (C) Copyright 2004-2008 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_OMAP_SYSLIB_H_ -#define __ASM_ARCH_OMAP_SYSLIB_H_ -#include <io.h> - -/** System Independent functions */ - -/** - * @brief clear & set a value in a bit range for a 32 bit address - * - * @param[in] addr Address to set/read from - * @param[in] start_bit Where to put the value - * @param[in] num_bits number of bits the value should be set - * @param[in] value the value to set - * - * @return void - */ -static inline void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - writel(tmp, addr); -} - -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -void sdelay(unsigned long loops); - -#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */ diff --git a/arch/arm/mach-omap/include/mach/timers.h b/arch/arm/mach-omap/include/mach/timers.h deleted file mode 100644 index 8e4cb929ba..0000000000 --- a/arch/arm/mach-omap/include/mach/timers.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers. - * - * FileName: include/asm-arm/arch-omap/timers.h - * - * Originally from Linux kernel: - * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz - * - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * Nishanth Menon <x0nishan@ti.com> - * - * Copyright (C) 2007 Texas Instruments, <www.ti.com> - * Copyright (C) 2007 Nokia Corporation. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_GPT_H -#define __ASM_ARCH_GPT_H - -/** General Purpose timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ -/* Enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0 << 2) | (0x1 << 1) | (0x1 << 0)) - -#endif /*__ASM_ARCH_GPT_H */ diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index 03b866c28e..f66316a536 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -32,13 +32,13 @@ #include <common.h> #include <io.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> -#include <mach/clocks.h> -#include <mach/omap3-clock.h> -#include <mach/timers.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/clocks.h> +#include <mach/omap/omap3-clock.h> +#include <mach/omap/timers.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> #define S32K_CR (OMAP3_32KTIMER_BASE + 0x10) diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index 69f2d51a62..8230b37619 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -32,17 +32,17 @@ #include <init.h> #include <io.h> #include <restart.h> -#include <mach/omap3-silicon.h> -#include <mach/gpmc.h> -#include <mach/generic.h> -#include <mach/sdrc.h> -#include <mach/control.h> -#include <mach/omap3-smx.h> -#include <mach/clocks.h> -#include <mach/omap3-clock.h> -#include <mach/sys_info.h> -#include <mach/syslib.h> -#include <mach/omap3-generic.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/generic.h> +#include <mach/omap/sdrc.h> +#include <mach/omap/control.h> +#include <mach/omap/omap3-smx.h> +#include <mach/omap/clocks.h> +#include <mach/omap/omap3-clock.h> +#include <mach/omap/sys_info.h> +#include <mach/omap/syslib.h> +#include <mach/omap/omap3-generic.h> #include <reset_source.h> /** @@ -475,8 +475,7 @@ static int omap3_bootsource(void) src = BOOTSOURCE_UNKNOWN; } - bootsource_set(src); - bootsource_set_instance(0); + bootsource_set_raw(src, 0); return 0; } diff --git a/arch/arm/mach-omap/omap3_xload_usb.c b/arch/arm/mach-omap/omap3_xload_usb.c index ac6a434643..01e958da6f 100644 --- a/arch/arm/mach-omap/omap3_xload_usb.c +++ b/arch/arm/mach-omap/omap3_xload_usb.c @@ -19,8 +19,8 @@ #include <common.h> #include <io.h> #include <malloc.h> -#include <mach/omap3-silicon.h> -#include <mach/omap3-generic.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap3-generic.h> static void __iomem *omap3_usb_base = (void __iomem *)OMAP3_MUSB0_BASE; diff --git a/arch/arm/mach-omap/omap4_clock.c b/arch/arm/mach-omap/omap4_clock.c index 6f53c706d6..aa314b70ec 100644 --- a/arch/arm/mach-omap/omap4_clock.c +++ b/arch/arm/mach-omap/omap4_clock.c @@ -2,10 +2,10 @@ #include <common.h> #include <io.h> -#include <mach/syslib.h> -#include <mach/omap4-silicon.h> -#include <mach/clocks.h> -#include <mach/omap4-clock.h> +#include <mach/omap/syslib.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/clocks.h> +#include <mach/omap/omap4-clock.h> #define LDELAY 12000000 diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c index 6d165b7f68..10190b152b 100644 --- a/arch/arm/mach-omap/omap4_generic.c +++ b/arch/arm/mach-omap/omap4_generic.c @@ -5,14 +5,14 @@ #include <init.h> #include <restart.h> #include <io.h> -#include <mach/omap4-clock.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4-mux.h> -#include <mach/syslib.h> -#include <mach/generic.h> -#include <mach/gpmc.h> -#include <mach/omap4_rom_usb.h> -#include <mach/omap4-generic.h> +#include <mach/omap/omap4-clock.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4-mux.h> +#include <mach/omap/syslib.h> +#include <mach/omap/generic.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/omap4_rom_usb.h> +#include <mach/omap/omap4-generic.h> /* * The following several lines are taken from U-Boot to support @@ -498,8 +498,7 @@ static int omap4_bootsource(void) src = BOOTSOURCE_UNKNOWN; } - bootsource_set(src); - bootsource_set_instance(0); + bootsource_set_raw(src, 0); omap_vector_init(); diff --git a/arch/arm/mach-omap/omap4_rom_usb.c b/arch/arm/mach-omap/omap4_rom_usb.c index 0b31240590..01c5565a68 100644 --- a/arch/arm/mach-omap/omap4_rom_usb.c +++ b/arch/arm/mach-omap/omap4_rom_usb.c @@ -31,9 +31,9 @@ */ #include <common.h> -#include <mach/omap4-silicon.h> -#include <mach/omap4_rom_usb.h> -#include <mach/generic.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/omap4_rom_usb.h> +#include <mach/omap/generic.h> #include <init.h> static struct omap4_usbboot omap4_usbboot_data; @@ -46,6 +46,9 @@ int omap4_usbboot_open(void) int n; u32 base; + if (omap4_usbboot_ready()) + return 0; + if (omap4_revision() >= OMAP4460_ES1_0) base = PUBLIC_API_BASE_4460; else @@ -82,7 +85,6 @@ int omap4_usbboot_open(void) omap4_usbboot_puts("USB communications initialized\n"); return 0; } -core_initcall(omap4_usbboot_open); int omap4_usbboot_ready(void){ return omap4_usbboot_data.ready; diff --git a/arch/arm/mach-omap/omap4_twl6030_mmc.c b/arch/arm/mach-omap/omap4_twl6030_mmc.c index 67a9a5d6b5..c5fa0e77aa 100644 --- a/arch/arm/mach-omap/omap4_twl6030_mmc.c +++ b/arch/arm/mach-omap/omap4_twl6030_mmc.c @@ -17,7 +17,7 @@ #include <io.h> #include <mfd/twl6030.h> -#include <mach/omap4_twl6030_mmc.h> +#include <mach/omap/omap4_twl6030_mmc.h> /* MMC voltage */ #define OMAP4_CONTROL_PBIASLITE 0x4A100600 diff --git a/arch/arm/mach-omap/omap_devices.c b/arch/arm/mach-omap/omap_devices.c index beae59f74d..3ade3225df 100644 --- a/arch/arm/mach-omap/omap_devices.c +++ b/arch/arm/mach-omap/omap_devices.c @@ -1,10 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only #include <driver.h> -#include <platform_data/serial-ns16550.h> #include <asm/armlinux.h> -#include <mach/omap3-devices.h> +#include <mach/omap/omap3-devices.h> void omap_add_ram0(resource_size_t size) { @@ -16,15 +15,10 @@ void omap_add_sram0(resource_size_t base, resource_size_t size) add_mem_device("sram0", base, size, IORESOURCE_MEM_WRITEABLE); } -static struct NS16550_plat serial_plat = { - .clock = 48000000, /* 48MHz (APLL96/2) */ - .shift = 2, -}; - -struct device_d *omap_add_uart(int id, unsigned long base) +struct device *omap_add_uart(int id, unsigned long base) { return add_generic_device("omap-uart", id, NULL, base, 1024, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); + IORESOURCE_MEM | IORESOURCE_MEM_8BIT, NULL); } #if defined(CONFIG_DRIVER_VIDEO_OMAP) @@ -42,7 +36,7 @@ static struct resource omapfb_resources[] = { }, }; -struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) +struct device *omap_add_display(struct omapfb_platform_data *o_pdata) { return add_generic_device_res("omap_fb", -1, omapfb_resources, @@ -50,7 +44,7 @@ struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) o_pdata); } #else -struct device_d *omap_add_display(struct omapfb_platform_data *o_pdata) +struct device *omap_add_display(struct omapfb_platform_data *o_pdata) { return NULL; } diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c index 6bb26a6ef0..99e14fb540 100644 --- a/arch/arm/mach-omap/omap_generic.c +++ b/arch/arm/mach-omap/omap_generic.c @@ -22,14 +22,14 @@ #include <malloc.h> #include <libfile.h> #include <linux/stat.h> -#include <mach/gpmc.h> -#include <mach/generic.h> -#include <mach/am33xx-silicon.h> -#include <mach/omap3-silicon.h> -#include <mach/omap4-silicon.h> -#include <mach/am33xx-generic.h> -#include <mach/omap3-generic.h> -#include <mach/omap4-generic.h> +#include <mach/omap/gpmc.h> +#include <mach/omap/generic.h> +#include <mach/omap/am33xx-silicon.h> +#include <mach/omap/omap3-silicon.h> +#include <mach/omap/omap4-silicon.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/omap3-generic.h> +#include <mach/omap/omap4-generic.h> void __iomem *omap_gpmc_base; @@ -113,6 +113,9 @@ static struct image_handler omap_barebox_handler = { static int omap_bootm_barebox(void) { + if (!cpu_is_omap()) + return 0; + return register_image_handler(&omap_barebox_handler); } device_initcall(omap_bootm_barebox); @@ -141,6 +144,9 @@ static int omap_env_init(void) struct cdev *cdev; const char *rootpath; + if (!cpu_is_omap()) + return 0; + if (bootsource_get() != BOOTSOURCE_MMC) return 0; @@ -174,6 +180,7 @@ static int omap_env_init(void) partname); default_environment_path_set(envpath); + free(envpath); out: free(partname); @@ -203,7 +210,7 @@ static int omap_init(void) if (root) { __omap_cpu_type = omap_soc_from_dt(); if (!__omap_cpu_type) - hang(); + return 0; } if (cpu_is_omap3()) diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c index 488f0ab859..f8fad243c6 100644 --- a/arch/arm/mach-omap/syslib.c +++ b/arch/arm/mach-omap/syslib.c @@ -25,7 +25,7 @@ #include <config.h> #include <common.h> #include <io.h> -#include <mach/syslib.h> +#include <mach/omap/syslib.h> /** * @brief simple spin loop diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c index 6a02e2b589..e632b53788 100644 --- a/arch/arm/mach-omap/xload.c +++ b/arch/arm/mach-omap/xload.c @@ -2,7 +2,6 @@ #include <common.h> #include <bootsource.h> -#include <partition.h> #include <nand.h> #include <init.h> #include <driver.h> @@ -14,9 +13,9 @@ #include <malloc.h> #include <filetype.h> #include <xymodem.h> -#include <mach/generic.h> -#include <mach/am33xx-generic.h> -#include <mach/omap3-generic.h> +#include <mach/omap/generic.h> +#include <mach/omap/am33xx-generic.h> +#include <mach/omap/omap3-generic.h> #include <net.h> #include <environment.h> #include <dhcp.h> @@ -356,6 +355,9 @@ int omap_set_barebox_part(struct omap_barebox_part *part) static int omap_set_xload(void) { + if (!cpu_is_omap()) + return 0; + barebox_main = omap_xload; return 0; |