diff options
Diffstat (limited to 'arch/arm/mach-pxa')
| -rw-r--r-- | arch/arm/mach-pxa/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/common.c | 17 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/hardware.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/reset_source.c | 41 | ||||
| -rw-r--r-- | arch/arm/mach-pxa/sleep.S | 81 |
5 files changed, 145 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 6a02a5459c..6ddb6e58e5 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -2,6 +2,8 @@ obj-y += clocksource.o obj-y += common.o obj-y += gpio.o obj-y += devices.o +obj-y += sleep.o obj-$(CONFIG_ARCH_PXA2XX) += mfp-pxa2xx.o obj-$(CONFIG_ARCH_PXA27X) += speed-pxa27x.o +obj-$(CONFIG_RESET_SOURCE) += reset_source.o diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c index 82e81b75d9..0c114ed58e 100644 --- a/arch/arm/mach-pxa/common.c +++ b/arch/arm/mach-pxa/common.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <mach/pxa-regs.h> #include <asm/io.h> #define OSMR3 0x40A0000C @@ -26,8 +27,13 @@ #define OWER_WME (1 << 0) /* Watch-dog Match Enable */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ +extern void pxa_suspend(int mode); + void reset_cpu(ulong addr) { + /* Clear last reset source */ + RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; + /* Initialize the watchdog and let it fire */ writel(OWER_WME, OWER); writel(OSSR_M3, OSSR); @@ -35,3 +41,14 @@ void reset_cpu(ulong addr) while (1); } + +void __noreturn poweroff() +{ + shutdown_barebox(); + + /* Clear last reset source */ + RCSR = RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR; + + pxa_suspend(PWRMODE_DEEPSLEEP); + unreachable(); +} diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index e53085cdde..c5f40d7c08 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -28,4 +28,8 @@ #define cpu_is_pxa27x() (0) #endif +#ifdef __ASSEMBLY__ +#define __REG(x) (x) +#endif + #endif /* !__MACH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/reset_source.c b/arch/arm/mach-pxa/reset_source.c new file mode 100644 index 0000000000..a90584b1a6 --- /dev/null +++ b/arch/arm/mach-pxa/reset_source.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2014 Robert Jarzmik <robert.jarzmik@free.fr> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <init.h> +#include <reset_source.h> +#include <mach/pxa-regs.h> + +static int pxa_detect_reset_source(void) +{ + u32 reg = RCSR; + + /* + * Order is important, as many bits can be set together + */ + if (reg & RCSR_GPR) + reset_source_set(RESET_RST); + else if (reg & RCSR_WDR) + reset_source_set(RESET_WDG); + else if (reg & RCSR_HWR) + reset_source_set(RESET_POR); + else if (reg & RCSR_SMR) + reset_source_set(RESET_WKE); + else + reset_source_set(RESET_UKWN); + + return 0; +} + +device_initcall(pxa_detect_reset_source); diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S new file mode 100644 index 0000000000..881033da21 --- /dev/null +++ b/arch/arm/mach-pxa/sleep.S @@ -0,0 +1,81 @@ +/* + * Low-level PXA250/210 sleep/wakeUp support + * + * Initial SA1110 code: + * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> + * + * Adapted for PXA by Nicolas Pitre: + * Copyright (c) 2002 Monta Vista Software, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <mach/hardware.h> +#include <mach/pxa2xx-regs.h> + +#define MDREFR_KDIV 0x200a4000 // all banks +#define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 +#define UNCACHED_PHYS_0 0 + .text + +#ifdef CONFIG_ARCH_PXA27X +/* + * pxa27x_finish_suspend() + * + * Forces CPU into sleep state. + * + * r0 = value for PWRMODE M field for desired sleep state + */ +ENTRY(pxa_suspend) + @ Put the processor to sleep + @ (also workaround for sighting 28071) + + @ prepare value for sleep mode + mov r1, r0 @ sleep mode + + @ Intel PXA270 Specification Update notes problems sleeping + @ with core operating above 91 MHz + @ (see Errata 50, ...processor does not exit from sleep...) + ldr r6, =CCCR + ldr r8, [r6] @ keep original value for resume + + ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value + mov r0, #0x2 @ prepare value for CLKCFG + + @ align execution to a cache line + b pxa_cpu_do_suspend +#endif + + + .ltorg + .align 5 +pxa_cpu_do_suspend: + + @ All needed values are now in registers. + @ These last instructions should be in cache + + @ initiate the frequency change... + str r7, [r6] + mcr p14, 0, r0, c6, c0, 0 + + @ restore the original cpu speed value for resume + str r8, [r6] + + @ need 6 13-MHz cycles before changing PWRMODE + @ just set frequency to 91-MHz... 6*91/13 = 42 + + mov r0, #42 +10: subs r0, r0, #1 + bne 10b + + @ Do not reorder... + @ Intel PXA270 Specification Update notes problems performing + @ external accesses after SDRAM is put in self-refresh mode + @ (see Errata 39 ...hangs when entering self-refresh mode) + + @ enter sleep mode + mcr p14, 0, r1, c7, c0, 0 @ PWRMODE +20: b 20b @ loop waiting for sleep |