diff options
Diffstat (limited to 'arch/arm/mach-pxa')
34 files changed, 29 insertions, 2370 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 711f8ed8d8..a506c8e892 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -20,7 +20,6 @@ config ARCH_PXA3XX bool select CPU_XSC3 select HAVE_CLK - select CLKDEV_LOOKUP select COMMON_CLK config ARCH_PXA310 diff --git a/arch/arm/mach-pxa/common.c b/arch/arm/mach-pxa/common.c index 5b980cb81b..e0bf1de461 100644 --- a/arch/arm/mach-pxa/common.c +++ b/arch/arm/mach-pxa/common.c @@ -15,7 +15,7 @@ #include <common.h> #include <init.h> #include <restart.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/pxa-regs.h> #include <asm/io.h> #define OSMR3 0x40A0000C diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 16f45273af..b5d098bd91 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -14,38 +14,38 @@ */ #include <common.h> #include <driver.h> -#include <mach/devices.h> -#include <mach/pxafb.h> +#include <mach/pxa/devices.h> +#include <mach/pxa/pxafb.h> -static inline struct device_d *pxa_add_device(char *name, int id, void *base, +static inline struct device *pxa_add_device(char *name, int id, void *base, int size, void *pdata) { return add_generic_device(name, id, NULL, (resource_size_t)base, size, IORESOURCE_MEM, pdata); } -struct device_d *pxa_add_i2c(void *base, int id, +struct device *pxa_add_i2c(void *base, int id, struct i2c_platform_data *pdata) { return pxa_add_device("i2c-pxa", id, base, 0x1000, pdata); } -struct device_d *pxa_add_uart(void *base, int id) +struct device *pxa_add_uart(void *base, int id) { return pxa_add_device("pxa_serial", id, base, 0x1000, NULL); } -struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata) +struct device *pxa_add_fb(void *base, struct pxafb_platform_data *pdata) { return pxa_add_device("pxafb", -1, base, 0x1000, pdata); } -struct device_d *pxa_add_mmc(void *base, int id, void *pdata) +struct device *pxa_add_mmc(void *base, int id, void *pdata) { return pxa_add_device("pxa-mmc", id, base, 0x1000, pdata); } -struct device_d *pxa_add_pwm(void *base, int id) +struct device *pxa_add_pwm(void *base, int id) { return pxa_add_device("pxa_pwm", id, base, 0x10, NULL); } diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c index ebda6bbe2a..130faa404b 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/mach-pxa/gpio.c @@ -14,7 +14,7 @@ #include <errno.h> #include <gpio.h> -#include <mach/gpio.h> +#include <mach/pxa/gpio.h> #include <asm/io.h> int pxa_last_gpio; diff --git a/arch/arm/mach-pxa/include/mach/clock.h b/arch/arm/mach-pxa/include/mach/clock.h deleted file mode 100644 index f86152f7af..0000000000 --- a/arch/arm/mach-pxa/include/mach/clock.h +++ /dev/null @@ -1,19 +0,0 @@ - -/* - * clock.h - definitions of the PXA clock functions - * - * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * This file is released under the GPLv2 - * - */ - -#ifndef __MACH_CLOCK_H -#define __MACH_CLOCK_H - -unsigned long pxa_get_uartclk(void); -unsigned long pxa_get_mmcclk(void); -unsigned long pxa_get_lcdclk(void); -unsigned long pxa_get_pwmclk(void); - -#endif /* !__MACH_CLOCK_H */ diff --git a/arch/arm/mach-pxa/include/mach/devices.h b/arch/arm/mach-pxa/include/mach/devices.h deleted file mode 100644 index 0f2e38dbae..0000000000 --- a/arch/arm/mach-pxa/include/mach/devices.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) 2011 Robert Jarzmik <robert.jarzmik@free.fr> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <i2c/i2c.h> -#include <mach/pxafb.h> - -struct device_d *pxa_add_i2c(void *base, int id, - struct i2c_platform_data *pdata); -struct device_d *pxa_add_uart(void *base, int id); -struct device_d *pxa_add_fb(void *base, struct pxafb_platform_data *pdata); -struct device_d *pxa_add_mmc(void *base, int id, void *pdata); -struct device_d *pxa_add_pwm(void *base, int id); diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h deleted file mode 100644 index e6724e1caf..0000000000 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/gpio.h - * - * PXA GPIO wrappers for arch-neutral GPIO calls - * - * Written by Philipp Zabel <philipp.zabel@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ASM_ARCH_PXA_GPIO_H -#define __ASM_ARCH_PXA_GPIO_H - -#include <mach/hardware.h> - -#define GPIO_REGS_VIRT (0x40E00000) - -#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) - -/* GPIO Pin Level Registers */ -#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) -#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) -#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) -#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) - -/* GPIO Pin Direction Registers */ -#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) -#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) -#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) -#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) - -/* GPIO Pin Output Set Registers */ -#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) -#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) -#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) -#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) - -/* GPIO Pin Output Clear Registers */ -#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) -#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) -#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) -#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) - -/* GPIO Rising Edge Detect Registers */ -#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) -#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) -#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) -#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) - -/* GPIO Falling Edge Detect Registers */ -#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) -#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) -#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) -#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) - -/* GPIO Edge Detect Status Registers */ -#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) -#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) -#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) -#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) - -/* GPIO Alternate Function Select Registers */ -#define GAFR0_L GPIO_REG(0x0054) -#define GAFR0_U GPIO_REG(0x0058) -#define GAFR1_L GPIO_REG(0x005C) -#define GAFR1_U GPIO_REG(0x0060) -#define GAFR2_L GPIO_REG(0x0064) -#define GAFR2_U GPIO_REG(0x0068) -#define GAFR3_L GPIO_REG(0x006C) -#define GAFR3_U GPIO_REG(0x0070) - -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) -#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) -#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) -#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) -#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) -#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) -#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) -#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) - - -#define NR_BUILTIN_GPIO 128 - -#define gpio_to_bank(gpio) ((gpio) >> 5) - -#ifdef CONFIG_CPU_PXA26x -/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, - * as well as their Alternate Function value being '1' for GPIO in GAFRx. - */ -static inline int __gpio_is_inverted(unsigned gpio) -{ - return cpu_is_pxa25x() && gpio > 85; -} -#else -static inline int __gpio_is_inverted(unsigned gpio) { return 0; } -#endif - -/* - * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate - * function of a GPIO, and GPDRx cannot be altered once configured. It - * is attributed as "occupied" here (I know this terminology isn't - * accurate, you are welcome to propose a better one :-) - */ -static inline int __gpio_is_occupied(unsigned gpio) -{ - if (cpu_is_pxa27x() || cpu_is_pxa25x()) { - int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; - int dir = GPDR(gpio) & GPIO_bit(gpio); - - if (__gpio_is_inverted(gpio)) - return af != 1 || dir == 0; - else - return af != 0 || dir != 0; - } else - return GPDR(gpio) & GPIO_bit(gpio); -} -#include <plat/gpio.h> -#endif diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h deleted file mode 100644 index d968a11880..0000000000 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * This file is released under the GPLv2 - * - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#ifdef CONFIG_ARCH_PXA2XX -#define cpu_is_pxa2xx() (1) -#else -#define cpu_is_pxa2xx() (0) -#endif - -#ifdef CONFIG_ARCH_PXA25X -#define cpu_is_pxa25x() (1) -#else -#define cpu_is_pxa25x() (0) -#endif - -#ifdef CONFIG_ARCH_PXA27X -#define cpu_is_pxa27x() (1) -#else -#define cpu_is_pxa27x() (0) -#endif - -#ifdef CONFIG_ARCH_PXA3XX -#define cpu_is_pxa3xx() (1) -# ifdef CONFIG_ARCH_PXA320 -# define cpu_is_pxa320() (1) -# else -# define cpu_is_pxa320() (0) -# endif -# ifdef CONFIG_ARCH_PXA310 -# define cpu_is_pxa310() (1) -# else -# define cpu_is_pxa310() (0) -# endif -#else -#define cpu_is_pxa3xx() (0) -#endif - -#ifdef __ASSEMBLY__ -#define __REG(x) (x) -#else - -void pxa_clear_reset_source(void); - -#endif - -#endif /* !__MACH_HARDWARE_H */ diff --git a/arch/arm/mach-pxa/include/mach/mci_pxa2xx.h b/arch/arm/mach-pxa/include/mach/mci_pxa2xx.h deleted file mode 100644 index e5bc211ea8..0000000000 --- a/arch/arm/mach-pxa/include/mach/mci_pxa2xx.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - -struct mci_host; -struct device_d; - -struct pxamci_platform_data { - int gpio_power; - int gpio_power_invert; - int (*init)(struct mci_host*, struct device_d*); - int (*setpower)(struct mci_host*, int on); -}; diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h deleted file mode 100644 index 5db786a85a..0000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ /dev/null @@ -1,472 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_ARCH_MFP_PXA27X_H -#define __ASM_ARCH_MFP_PXA27X_H - -/* - * NOTE: for those special-function bidirectional GPIOs, as described - * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input - * alternative is preserved, the direction is actually selected by the - * specific controller, and this should work in most cases. - */ - -#include <mach/mfp-pxa2xx.h> - -/* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN - * bit is set, regardless of the GPIO configuration - */ -#define GPIO3_GPIO MFP_CFG_IN(GPIO3, AF0) -#define GPIO4_GPIO MFP_CFG_IN(GPIO4, AF0) - -/* GPIO */ -#define GPIO85_GPIO MFP_CFG_IN(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG_IN(GPIO86, AF0) -#define GPIO87_GPIO MFP_CFG_IN(GPIO87, AF0) -#define GPIO88_GPIO MFP_CFG_IN(GPIO88, AF0) -#define GPIO89_GPIO MFP_CFG_IN(GPIO89, AF0) -#define GPIO90_GPIO MFP_CFG_IN(GPIO90, AF0) -#define GPIO91_GPIO MFP_CFG_IN(GPIO91, AF0) -#define GPIO92_GPIO MFP_CFG_IN(GPIO92, AF0) -#define GPIO93_GPIO MFP_CFG_IN(GPIO93, AF0) -#define GPIO94_GPIO MFP_CFG_IN(GPIO94, AF0) -#define GPIO95_GPIO MFP_CFG_IN(GPIO95, AF0) -#define GPIO96_GPIO MFP_CFG_IN(GPIO96, AF0) -#define GPIO97_GPIO MFP_CFG_IN(GPIO97, AF0) -#define GPIO98_GPIO MFP_CFG_IN(GPIO98, AF0) -#define GPIO99_GPIO MFP_CFG_IN(GPIO99, AF0) -#define GPIO100_GPIO MFP_CFG_IN(GPIO100, AF0) -#define GPIO101_GPIO MFP_CFG_IN(GPIO101, AF0) -#define GPIO102_GPIO MFP_CFG_IN(GPIO102, AF0) -#define GPIO103_GPIO MFP_CFG_IN(GPIO103, AF0) -#define GPIO104_GPIO MFP_CFG_IN(GPIO104, AF0) -#define GPIO105_GPIO MFP_CFG_IN(GPIO105, AF0) -#define GPIO106_GPIO MFP_CFG_IN(GPIO106, AF0) -#define GPIO107_GPIO MFP_CFG_IN(GPIO107, AF0) -#define GPIO108_GPIO MFP_CFG_IN(GPIO108, AF0) -#define GPIO109_GPIO MFP_CFG_IN(GPIO109, AF0) -#define GPIO110_GPIO MFP_CFG_IN(GPIO110, AF0) -#define GPIO111_GPIO MFP_CFG_IN(GPIO111, AF0) -#define GPIO112_GPIO MFP_CFG_IN(GPIO112, AF0) -#define GPIO113_GPIO MFP_CFG_IN(GPIO113, AF0) -#define GPIO114_GPIO MFP_CFG_IN(GPIO114, AF0) -#define GPIO115_GPIO MFP_CFG_IN(GPIO115, AF0) -#define GPIO116_GPIO MFP_CFG_IN(GPIO116, AF0) -#define GPIO117_GPIO MFP_CFG_IN(GPIO117, AF0) -#define GPIO118_GPIO MFP_CFG_IN(GPIO118, AF0) -#define GPIO119_GPIO MFP_CFG_IN(GPIO119, AF0) -#define GPIO120_GPIO MFP_CFG_IN(GPIO120, AF0) - -/* Crystal and Clock Signals */ -#define GPIO9_HZ_CLK MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW) -#define GPIO10_HZ_CLK MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW) -#define GPIO11_48_MHz MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW) -#define GPIO12_48_MHz MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW) -#define GPIO13_CLK_EXT MFP_CFG_IN(GPIO13, AF1) - -/* OS Timer Signals */ -#define GPIO11_EXT_SYNC_0 MFP_CFG_IN(GPIO11, AF1) -#define GPIO12_EXT_SYNC_1 MFP_CFG_IN(GPIO12, AF1) -#define GPIO9_CHOUT_0 MFP_CFG_OUT(GPIO9, AF3, DRIVE_LOW) -#define GPIO10_CHOUT_1 MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW) -#define GPIO11_CHOUT_0 MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW) -#define GPIO12_CHOUT_1 MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW) - -/* SDRAM and Static Memory I/O Signals */ -#define GPIO20_nSDCS_2 MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH) -#define GPIO21_nSDCS_3 MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH) -#define GPIO15_nCS_1 MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH) -#define GPIO78_nCS_2 MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH) -#define GPIO79_nCS_3 MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH) -#define GPIO80_nCS_4 MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH) -#define GPIO33_nCS_5 MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH) - -/* Miscellaneous I/O and DMA Signals */ -#define GPIO21_DVAL_0 MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH) -#define GPIO116_DVAL_0 MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH) -#define GPIO33_DVAL_1 MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH) -#define GPIO96_DVAL_1 MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH) -#define GPIO18_RDY MFP_CFG_IN(GPIO18, AF1) -#define GPIO20_DREQ_0 MFP_CFG_IN(GPIO20, AF1) -#define GPIO115_DREQ_0 MFP_CFG_IN(GPIO115, AF1) -#define GPIO80_DREQ_1 MFP_CFG_IN(GPIO80, AF1) -#define GPIO97_DREQ_1 MFP_CFG_IN(GPIO97, AF2) -#define GPIO85_DREQ_2 MFP_CFG_IN(GPIO85, AF2) -#define GPIO100_DREQ_2 MFP_CFG_IN(GPIO100, AF2) - -/* Alternate Bus Master Mode I/O Signals */ -#define GPIO20_MBREQ MFP_CFG_IN(GPIO20, AF2) -#define GPIO80_MBREQ MFP_CFG_IN(GPIO80, AF2) -#define GPIO96_MBREQ MFP_CFG_IN(GPIO96, AF2) -#define GPIO115_MBREQ MFP_CFG_IN(GPIO115, AF3) -#define GPIO21_MBGNT MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW) -#define GPIO33_MBGNT MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW) -#define GPIO97_MBGNT MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW) -#define GPIO116_MBGNT MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW) - -/* PC CARD */ -#define GPIO15_nPCE_1 MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH) -#define GPIO85_nPCE_1 MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH) -#define GPIO86_nPCE_1 MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH) -#define GPIO102_nPCE_1 MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH) -#define GPIO54_nPCE_2 MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH) -#define GPIO78_nPCE_2 MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH) -#define GPIO87_nPCE_2 MFP_CFG_IN(GPIO87, AF1) -#define GPIO55_nPREG MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH) -#define GPIO50_nPIOR MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH) -#define GPIO51_nPIOW MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH) -#define GPIO49_nPWE MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH) -#define GPIO48_nPOE MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH) -#define GPIO57_nIOIS16 MFP_CFG_IN(GPIO57, AF1) -#define GPIO56_nPWAIT MFP_CFG_IN(GPIO56, AF1) -#define GPIO79_PSKTSEL MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH) -#define GPIO104_PSKTSEL MFP_CFG_OUT(GPIO104, AF1, DRIVE_HIGH) - -/* I2C */ -#define GPIO117_I2C_SCL MFP_CFG_IN(GPIO117, AF1) -#define GPIO118_I2C_SDA MFP_CFG_IN(GPIO118, AF1) - -/* FFUART */ -#define GPIO9_FFUART_CTS MFP_CFG_IN(GPIO9, AF3) -#define GPIO26_FFUART_CTS MFP_CFG_IN(GPIO26, AF3) -#define GPIO35_FFUART_CTS MFP_CFG_IN(GPIO35, AF1) -#define GPIO100_FFUART_CTS MFP_CFG_IN(GPIO100, AF3) -#define GPIO10_FFUART_DCD MFP_CFG_IN(GPIO10, AF1) -#define GPIO36_FFUART_DCD MFP_CFG_IN(GPIO36, AF1) -#define GPIO33_FFUART_DSR MFP_CFG_IN(GPIO33, AF2) -#define GPIO37_FFUART_DSR MFP_CFG_IN(GPIO37, AF1) -#define GPIO38_FFUART_RI MFP_CFG_IN(GPIO38, AF1) -#define GPIO89_FFUART_RI MFP_CFG_IN(GPIO89, AF3) -#define GPIO19_FFUART_RXD MFP_CFG_IN(GPIO19, AF3) -#define GPIO33_FFUART_RXD MFP_CFG_IN(GPIO33, AF1) -#define GPIO34_FFUART_RXD MFP_CFG_IN(GPIO34, AF1) -#define GPIO41_FFUART_RXD MFP_CFG_IN(GPIO41, AF1) -#define GPIO53_FFUART_RXD MFP_CFG_IN(GPIO53, AF1) -#define GPIO85_FFUART_RXD MFP_CFG_IN(GPIO85, AF1) -#define GPIO96_FFUART_RXD MFP_CFG_IN(GPIO96, AF3) -#define GPIO102_FFUART_RXD MFP_CFG_IN(GPIO102, AF3) -#define GPIO16_FFUART_TXD MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH) -#define GPIO37_FFUART_TXD MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH) -#define GPIO39_FFUART_TXD MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH) -#define GPIO83_FFUART_TXD MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH) -#define GPIO99_FFUART_TXD MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH) -#define GPIO27_FFUART_RTS MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH) -#define GPIO41_FFUART_RTS MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH) -#define GPIO83_FFUART_RTS MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH) -#define GPIO98_FFUART_RTS MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH) -#define GPIO40_FFUART_DTR MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH) -#define GPIO82_FFUART_DTR MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH) - -/* BTUART */ -#define GPIO44_BTUART_CTS MFP_CFG_IN(GPIO44, AF1) -#define GPIO42_BTUART_RXD MFP_CFG_IN(GPIO42, AF1) -#define GPIO45_BTUART_RTS MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH) -#define GPIO43_BTUART_TXD MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH) - -/* STUART */ -#define GPIO46_STUART_RXD MFP_CFG_IN(GPIO46, AF2) -#define GPIO47_STUART_TXD MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH) - -/* FICP */ -#define GPIO42_FICP_RXD MFP_CFG_IN(GPIO42, AF2) -#define GPIO46_FICP_RXD MFP_CFG_IN(GPIO46, AF1) -#define GPIO43_FICP_TXD MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH) -#define GPIO47_FICP_TXD MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH) - -/* PWM 0/1/2/3 */ -#define GPIO11_PWM2_OUT MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW) -#define GPIO12_PWM3_OUT MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW) -#define GPIO16_PWM0_OUT MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW) -#define GPIO17_PWM1_OUT MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW) -#define GPIO38_PWM1_OUT MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW) -#define GPIO46_PWM2_OUT MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW) -#define GPIO47_PWM3_OUT MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW) -#define GPIO79_PWM2_OUT MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW) -#define GPIO80_PWM3_OUT MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW) -#define GPIO115_PWM1_OUT MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW) - -/* AC97 */ -#define GPIO31_AC97_SYNC MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW) -#define GPIO94_AC97_SYNC MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW) -#define GPIO30_AC97_SDATA_OUT MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW) -#define GPIO93_AC97_SDATA_OUT MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW) -#define GPIO45_AC97_SYSCLK MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW) -#define GPIO89_AC97_SYSCLK MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW) -#define GPIO98_AC97_SYSCLK MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW) -#define GPIO95_AC97_nRESET MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW) -#define GPIO113_AC97_nRESET MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW) -#define GPIO28_AC97_BITCLK MFP_CFG_IN(GPIO28, AF1) -#define GPIO29_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO29, AF1) -#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2) -#define GPIO99_AC97_SDATA_IN_1 MFP_CFG_IN(GPIO99, AF2) - -/* I2S */ -#define GPIO28_I2S_BITCLK_IN MFP_CFG_IN(GPIO28, AF2) -#define GPIO28_I2S_BITCLK_OUT MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW) -#define GPIO29_I2S_SDATA_IN MFP_CFG_IN(GPIO29, AF2) -#define GPIO30_I2S_SDATA_OUT MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW) -#define GPIO31_I2S_SYNC MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW) -#define GPIO113_I2S_SYSCLK MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW) - -/* SSP 1 */ -#define GPIO23_SSP1_SCLK MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW) -#define GPIO29_SSP1_SCLK MFP_CFG_IN(GPIO29, AF3) -#define GPIO27_SSP1_SYSCLK MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW) -#define GPIO53_SSP1_SYSCLK MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW) -#define GPIO24_SSP1_SFRM MFP_CFG_IN(GPIO24, AF2) -#define GPIO28_SSP1_SFRM MFP_CFG_IN(GPIO28, AF3) -#define GPIO25_SSP1_TXD MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW) -#define GPIO57_SSP1_TXD MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW) -#define GPIO26_SSP1_RXD MFP_CFG_IN(GPIO26, AF1) -#define GPIO27_SSP1_SCLKEN MFP_CFG_IN(GPIO27, AF2) - -/* SSP 2 */ -#define GPIO19_SSP2_SCLK MFP_CFG_IN(GPIO19, AF1) -#define GPIO22_SSP2_SCLK MFP_CFG_IN(GPIO22, AF3) -#define GPIO29_SSP2_SCLK MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW) -#define GPIO36_SSP2_SCLK MFP_CFG_IN(GPIO36, AF2) -#define GPIO50_SSP2_SCLK MFP_CFG_IN(GPIO50, AF3) -#define GPIO22_SSP2_SYSCLK MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW) -#define GPIO14_SSP2_SFRM MFP_CFG_IN(GPIO14, AF2) -#define GPIO37_SSP2_SFRM MFP_CFG_IN(GPIO37, AF2) -#define GPIO87_SSP2_SFRM MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW) -#define GPIO88_SSP2_SFRM MFP_CFG_IN(GPIO88, AF3) -#define GPIO13_SSP2_TXD MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW) -#define GPIO38_SSP2_TXD MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW) -#define GPIO87_SSP2_TXD MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW) -#define GPIO89_SSP2_TXD MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW) -#define GPIO11_SSP2_RXD MFP_CFG_IN(GPIO11, AF2) -#define GPIO29_SSP2_RXD MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW) -#define GPIO40_SSP2_RXD MFP_CFG_IN(GPIO40, AF1) -#define GPIO86_SSP2_RXD MFP_CFG_IN(GPIO86, AF1) -#define GPIO88_SSP2_RXD MFP_CFG_IN(GPIO88, AF2) -#define GPIO22_SSP2_EXTCLK MFP_CFG_IN(GPIO22, AF1) -#define GPIO27_SSP2_EXTCLK MFP_CFG_IN(GPIO27, AF1) -#define GPIO22_SSP2_SCLKEN MFP_CFG_IN(GPIO22, AF2) -#define GPIO23_SSP2_SCLKEN MFP_CFG_IN(GPIO23, AF2) - -/* SSP 3 */ -#define GPIO34_SSP3_SCLK MFP_CFG_IN(GPIO34, AF3) -#define GPIO40_SSP3_SCLK MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW) -#define GPIO52_SSP3_SCLK MFP_CFG_IN(GPIO52, AF2) -#define GPIO84_SSP3_SCLK MFP_CFG_IN(GPIO84, AF1) -#define GPIO45_SSP3_SYSCLK MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW) -#define GPIO35_SSP3_SFRM MFP_CFG_IN(GPIO35, AF3) -#define GPIO39_SSP3_SFRM MFP_CFG_IN(GPIO39, AF3) -#define GPIO83_SSP3_SFRM MFP_CFG_IN(GPIO83, AF1) -#define GPIO35_SSP3_TXD MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW) -#define GPIO38_SSP3_TXD MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW) -#define GPIO81_SSP3_TXD MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW) -#define GPIO41_SSP3_RXD MFP_CFG_IN(GPIO41, AF3) -#define GPIO82_SSP3_RXD MFP_CFG_IN(GPIO82, AF1) -#define GPIO89_SSP3_RXD MFP_CFG_IN(GPIO89, AF1) - -/* MMC */ -#define GPIO32_MMC_CLK MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW) -#define GPIO92_MMC_DAT_0 MFP_CFG_IN(GPIO92, AF1) -#define GPIO109_MMC_DAT_1 MFP_CFG_IN(GPIO109, AF1) -#define GPIO110_MMC_DAT_2 MFP_CFG_IN(GPIO110, AF1) -#define GPIO111_MMC_DAT_3 MFP_CFG_IN(GPIO111, AF1) -#define GPIO112_MMC_CMD MFP_CFG_IN(GPIO112, AF1) - -/* LCD */ -#define GPIO58_LCD_LDD_0 MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW) -#define GPIO59_LCD_LDD_1 MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW) -#define GPIO60_LCD_LDD_2 MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW) -#define GPIO61_LCD_LDD_3 MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW) -#define GPIO62_LCD_LDD_4 MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW) -#define GPIO63_LCD_LDD_5 MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW) -#define GPIO64_LCD_LDD_6 MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW) -#define GPIO65_LCD_LDD_7 MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW) -#define GPIO66_LCD_LDD_8 MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW) -#define GPIO67_LCD_LDD_9 MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW) -#define GPIO68_LCD_LDD_10 MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW) -#define GPIO69_LCD_LDD_11 MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW) -#define GPIO70_LCD_LDD_12 MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW) -#define GPIO71_LCD_LDD_13 MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW) -#define GPIO72_LCD_LDD_14 MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW) -#define GPIO73_LCD_LDD_15 MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW) -#define GPIO86_LCD_LDD_16 MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW) -#define GPIO87_LCD_LDD_17 MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW) -#define GPIO74_LCD_FCLK MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW) -#define GPIO75_LCD_LCLK MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW) -#define GPIO76_LCD_PCLK MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW) -#define GPIO77_LCD_BIAS MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW) -#define GPIO14_LCD_VSYNC MFP_CFG_IN(GPIO14, AF1) -#define GPIO19_LCD_CS MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW) - -/* Keypad */ -#define GPIO93_KP_DKIN_0 MFP_CFG_IN(GPIO93, AF1) -#define GPIO94_KP_DKIN_1 MFP_CFG_IN(GPIO94, AF1) -#define GPIO95_KP_DKIN_2 MFP_CFG_IN(GPIO95, AF1) -#define GPIO96_KP_DKIN_3 MFP_CFG_IN(GPIO96, AF1) -#define GPIO97_KP_DKIN_4 MFP_CFG_IN(GPIO97, AF1) -#define GPIO98_KP_DKIN_5 MFP_CFG_IN(GPIO98, AF1) -#define GPIO99_KP_DKIN_6 MFP_CFG_IN(GPIO99, AF1) -#define GPIO13_KP_KDIN_7 MFP_CFG_IN(GPIO13, AF2) -#define GPIO100_KP_MKIN_0 MFP_CFG_IN(GPIO100, AF1) -#define GPIO101_KP_MKIN_1 MFP_CFG_IN(GPIO101, AF1) -#define GPIO102_KP_MKIN_2 MFP_CFG_IN(GPIO102, AF1) -#define GPIO34_KP_MKIN_3 MFP_CFG_IN(GPIO34, AF2) -#define GPIO37_KP_MKIN_3 MFP_CFG_IN(GPIO37, AF3) -#define GPIO97_KP_MKIN_3 MFP_CFG_IN(GPIO97, AF3) -#define GPIO98_KP_MKIN_4 MFP_CFG_IN(GPIO98, AF3) -#define GPIO38_KP_MKIN_4 MFP_CFG_IN(GPIO38, AF2) -#define GPIO39_KP_MKIN_4 MFP_CFG_IN(GPIO39, AF1) -#define GPIO16_KP_MKIN_5 MFP_CFG_IN(GPIO16, AF1) -#define GPIO90_KP_MKIN_5 MFP_CFG_IN(GPIO90, AF1) -#define GPIO99_KP_MKIN_5 MFP_CFG_IN(GPIO99, AF3) -#define GPIO17_KP_MKIN_6 MFP_CFG_IN(GPIO17, AF1) -#define GPIO91_KP_MKIN_6 MFP_CFG_IN(GPIO91, AF1) -#define GPIO95_KP_MKIN_6 MFP_CFG_IN(GPIO95, AF3) -#define GPIO13_KP_MKIN_7 MFP_CFG_IN(GPIO13, AF3) -#define GPIO36_KP_MKIN_7 MFP_CFG_IN(GPIO36, AF3) -#define GPIO103_KP_MKOUT_0 MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH) -#define GPIO104_KP_MKOUT_1 MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH) -#define GPIO105_KP_MKOUT_2 MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH) -#define GPIO106_KP_MKOUT_3 MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH) -#define GPIO107_KP_MKOUT_4 MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH) -#define GPIO108_KP_MKOUT_5 MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH) -#define GPIO35_KP_MKOUT_6 MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH) -#define GPIO22_KP_MKOUT_7 MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH) -#define GPIO40_KP_MKOUT_6 MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH) -#define GPIO41_KP_MKOUT_7 MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH) -#define GPIO96_KP_MKOUT_6 MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH) - -/* USB P3 */ -#define GPIO10_USB_P3_5 MFP_CFG_IN(GPIO10, AF3) -#define GPIO11_USB_P3_1 MFP_CFG_IN(GPIO11, AF3) -#define GPIO30_USB_P3_2 MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW) -#define GPIO31_USB_P3_6 MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW) -#define GPIO56_USB_P3_4 MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW) -#define GPIO86_USB_P3_5 MFP_CFG_IN(GPIO86, AF3) -#define GPIO87_USB_P3_1 MFP_CFG_IN(GPIO87, AF3) -#define GPIO90_USB_P3_5 MFP_CFG_IN(GPIO90, AF2) -#define GPIO91_USB_P3_1 MFP_CFG_IN(GPIO91, AF2) -#define GPIO113_USB_P3_3 MFP_CFG_IN(GPIO113, AF3) - -/* USB P2 */ -#define GPIO34_USB_P2_2 MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW) -#define GPIO35_USB_P2_1 MFP_CFG_IN(GPIO35, AF2) -#define GPIO36_USB_P2_4 MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW) -#define GPIO37_USB_P2_8 MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW) -#define GPIO38_USB_P2_3 MFP_CFG_IN(GPIO38, AF3) -#define GPIO39_USB_P2_6 MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW) -#define GPIO40_USB_P2_5 MFP_CFG_IN(GPIO40, AF3) -#define GPIO41_USB_P2_7 MFP_CFG_IN(GPIO41, AF2) -#define GPIO53_USB_P2_3 MFP_CFG_IN(GPIO53, AF2) - -/* USB Host Port 1/2 */ -#define GPIO88_USBH1_PWR MFP_CFG_IN(GPIO88, AF1) -#define GPIO89_USBH1_PEN MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW) -#define GPIO119_USBH2_PWR MFP_CFG_IN(GPIO119, AF1) -#define GPIO120_USBH2_PEN MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW) - -/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */ -#define GPIO115_CIF_DD_3 MFP_CFG_IN(GPIO115, AF2) -#define GPIO116_CIF_DD_2 MFP_CFG_IN(GPIO116, AF1) -#define GPIO12_CIF_DD_7 MFP_CFG_IN(GPIO12, AF2) -#define GPIO17_CIF_DD_6 MFP_CFG_IN(GPIO17, AF2) -#define GPIO23_CIF_MCLK MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW) -#define GPIO24_CIF_FV MFP_CFG_IN(GPIO24, AF1) -#define GPIO25_CIF_LV MFP_CFG_IN(GPIO25, AF1) -#define GPIO26_CIF_PCLK MFP_CFG_IN(GPIO26, AF2) -#define GPIO27_CIF_DD_0 MFP_CFG_IN(GPIO27, AF3) -#define GPIO42_CIF_MCLK MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW) -#define GPIO43_CIF_FV MFP_CFG_IN(GPIO43, AF3) -#define GPIO44_CIF_LV MFP_CFG_IN(GPIO44, AF3) -#define GPIO45_CIF_PCLK MFP_CFG_IN(GPIO45, AF3) -#define GPIO47_CIF_DD_0 MFP_CFG_IN(GPIO47, AF1) -#define GPIO48_CIF_DD_5 MFP_CFG_IN(GPIO48, AF1) -#define GPIO50_CIF_DD_3 MFP_CFG_IN(GPIO50, AF1) -#define GPIO51_CIF_DD_2 MFP_CFG_IN(GPIO51, AF1) -#define GPIO52_CIF_DD_4 MFP_CFG_IN(GPIO52, AF1) -#define GPIO53_CIF_MCLK MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW) -#define GPIO54_CIF_PCLK MFP_CFG_IN(GPIO54, AF3) -#define GPIO55_CIF_DD_1 MFP_CFG_IN(GPIO55, AF1) -#define GPIO81_CIF_DD_0 MFP_CFG_IN(GPIO81, AF2) -#define GPIO82_CIF_DD_5 MFP_CFG_IN(GPIO82, AF3) -#define GPIO83_CIF_DD_4 MFP_CFG_IN(GPIO83, AF3) -#define GPIO84_CIF_FV MFP_CFG_IN(GPIO84, AF3) -#define GPIO85_CIF_LV MFP_CFG_IN(GPIO85, AF3) -#define GPIO90_CIF_DD_4 MFP_CFG_IN(GPIO90, AF3) -#define GPIO91_CIF_DD_5 MFP_CFG_IN(GPIO91, AF3) -#define GPIO93_CIF_DD_6 MFP_CFG_IN(GPIO93, AF2) -#define GPIO94_CIF_DD_5 MFP_CFG_IN(GPIO94, AF2) -#define GPIO95_CIF_DD_4 MFP_CFG_IN(GPIO95, AF2) -#define GPIO98_CIF_DD_0 MFP_CFG_IN(GPIO98, AF2) -#define GPIO103_CIF_DD_3 MFP_CFG_IN(GPIO103, AF1) -#define GPIO104_CIF_DD_2 MFP_CFG_IN(GPIO104, AF1) -#define GPIO105_CIF_DD_1 MFP_CFG_IN(GPIO105, AF1) -#define GPIO106_CIF_DD_9 MFP_CFG_IN(GPIO106, AF1) -#define GPIO107_CIF_DD_8 MFP_CFG_IN(GPIO107, AF1) -#define GPIO108_CIF_DD_7 MFP_CFG_IN(GPIO108, AF1) -#define GPIO114_CIF_DD_1 MFP_CFG_IN(GPIO114, AF1) - -/* Universal Subscriber ID Interface */ -#define GPIO114_UVS0 MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW) -#define GPIO115_nUVS1 MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW) -#define GPIO116_nUVS2 MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW) -#define GPIO14_UCLK MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW) -#define GPIO91_UCLK MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW) -#define GPIO19_nURST MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW) -#define GPIO90_nURST MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW) -#define GPIO116_UDET MFP_CFG_IN(GPIO116, AF3) -#define GPIO114_UEN MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW) -#define GPIO115_UEN MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW) - -/* Mobile Scalable Link (MSL) Interface */ -#define GPIO81_BB_OB_DAT_0 MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW) -#define GPIO48_BB_OB_DAT_1 MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW) -#define GPIO50_BB_OB_DAT_2 MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW) -#define GPIO51_BB_OB_DAT_3 MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW) -#define GPIO52_BB_OB_CLK MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW) -#define GPIO53_BB_OB_STB MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW) -#define GPIO54_BB_OB_WAIT MFP_CFG_IN(GPIO54, AF2) -#define GPIO82_BB_IB_DAT_0 MFP_CFG_IN(GPIO82, AF2) -#define GPIO55_BB_IB_DAT_1 MFP_CFG_IN(GPIO55, AF2) -#define GPIO56_BB_IB_DAT_2 MFP_CFG_IN(GPIO56, AF2) -#define GPIO57_BB_IB_DAT_3 MFP_CFG_IN(GPIO57, AF2) -#define GPIO83_BB_IB_CLK MFP_CFG_IN(GPIO83, AF2) -#define GPIO84_BB_IB_STB MFP_CFG_IN(GPIO84, AF2) -#define GPIO85_BB_IB_WAIT MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW) - -/* Memory Stick Host Controller */ -#define GPIO92_MSBS MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW) -#define GPIO109_MSSDIO MFP_CFG_IN(GPIO109, AF2) -#define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) -#define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) - -/* commonly used pin configurations */ -#define GPIOxx_LCD_16BPP \ - GPIO58_LCD_LDD_0, \ - GPIO59_LCD_LDD_1, \ - GPIO60_LCD_LDD_2, \ - GPIO61_LCD_LDD_3, \ - GPIO62_LCD_LDD_4, \ - GPIO63_LCD_LDD_5, \ - GPIO64_LCD_LDD_6, \ - GPIO65_LCD_LDD_7, \ - GPIO66_LCD_LDD_8, \ - GPIO67_LCD_LDD_9, \ - GPIO68_LCD_LDD_10, \ - GPIO69_LCD_LDD_11, \ - GPIO70_LCD_LDD_12, \ - GPIO71_LCD_LDD_13, \ - GPIO72_LCD_LDD_14, \ - GPIO73_LCD_LDD_15 - -#define GPIOxx_LCD_DSTN_16BPP \ - GPIOxx_LCD_16BPP, \ - GPIO74_LCD_FCLK, \ - GPIO75_LCD_LCLK, \ - GPIO76_LCD_PCLK - -#define GPIOxx_LCD_TFT_16BPP \ - GPIOxx_LCD_16BPP, \ - GPIO74_LCD_FCLK, \ - GPIO75_LCD_LCLK, \ - GPIO76_LCD_PCLK, \ - GPIO77_LCD_BIAS - -extern int keypad_set_wake(unsigned int on); -#endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h deleted file mode 100644 index b01f6188d4..0000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_ARCH_MFP_PXA2XX_H -#define __ASM_ARCH_MFP_PXA2XX_H - -#include <plat/mfp.h> - -/* - * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: - * - * MFP_PIN(x) - * MFP_AFx - * MFP_LPM_DRIVE_{LOW, HIGH} - * MFP_LPM_EDGE_x - * - * other MFP_x bit definitions will be ignored - * - * and adds the below two bits specifically for pxa2xx: - * - * bit 23 - Input/Output (PXA2xx specific) - * bit 24 - Wakeup Enable(PXA2xx specific) - */ - -#define MFP_DIR_IN (0x0 << 23) -#define MFP_DIR_OUT (0x1 << 23) -#define MFP_DIR_MASK (0x1 << 23) -#define MFP_DIR(x) (((x) >> 23) & 0x1) - -#define MFP_LPM_CAN_WAKEUP (0x1 << 24) -#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) -#define WAKEUP_ON_EDGE_FALL (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL) -#define WAKEUP_ON_EDGE_BOTH (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH) - -/* specifically for enabling wakeup on keypad GPIOs */ -#define WAKEUP_ON_LEVEL_HIGH (MFP_LPM_CAN_WAKEUP) - -#define MFP_CFG_IN(pin, af) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN)) - -/* NOTE: pins configured as output _must_ provide a low power state, - * and this state should help to minimize the power dissipation. - */ -#define MFP_CFG_OUT(pin, af, state) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) - -/* Common configurations for pxa25x and pxa27x - * - * Note: pins configured as GPIO are always initialized to input - * so not to cause any side effect - */ -#define GPIO0_GPIO MFP_CFG_IN(GPIO0, AF0) -#define GPIO1_GPIO MFP_CFG_IN(GPIO1, AF0) -#define GPIO9_GPIO MFP_CFG_IN(GPIO9, AF0) -#define GPIO10_GPIO MFP_CFG_IN(GPIO10, AF0) -#define GPIO11_GPIO MFP_CFG_IN(GPIO11, AF0) -#define GPIO12_GPIO MFP_CFG_IN(GPIO12, AF0) -#define GPIO13_GPIO MFP_CFG_IN(GPIO13, AF0) -#define GPIO14_GPIO MFP_CFG_IN(GPIO14, AF0) -#define GPIO15_GPIO MFP_CFG_IN(GPIO15, AF0) -#define GPIO16_GPIO MFP_CFG_IN(GPIO16, AF0) -#define GPIO17_GPIO MFP_CFG_IN(GPIO17, AF0) -#define GPIO18_GPIO MFP_CFG_IN(GPIO18, AF0) -#define GPIO19_GPIO MFP_CFG_IN(GPIO19, AF0) -#define GPIO20_GPIO MFP_CFG_IN(GPIO20, AF0) -#define GPIO21_GPIO MFP_CFG_IN(GPIO21, AF0) -#define GPIO22_GPIO MFP_CFG_IN(GPIO22, AF0) -#define GPIO23_GPIO MFP_CFG_IN(GPIO23, AF0) -#define GPIO24_GPIO MFP_CFG_IN(GPIO24, AF0) -#define GPIO25_GPIO MFP_CFG_IN(GPIO25, AF0) -#define GPIO26_GPIO MFP_CFG_IN(GPIO26, AF0) -#define GPIO27_GPIO MFP_CFG_IN(GPIO27, AF0) -#define GPIO28_GPIO MFP_CFG_IN(GPIO28, AF0) -#define GPIO29_GPIO MFP_CFG_IN(GPIO29, AF0) -#define GPIO30_GPIO MFP_CFG_IN(GPIO30, AF0) -#define GPIO31_GPIO MFP_CFG_IN(GPIO31, AF0) -#define GPIO32_GPIO MFP_CFG_IN(GPIO32, AF0) -#define GPIO33_GPIO MFP_CFG_IN(GPIO33, AF0) -#define GPIO34_GPIO MFP_CFG_IN(GPIO34, AF0) -#define GPIO35_GPIO MFP_CFG_IN(GPIO35, AF0) -#define GPIO36_GPIO MFP_CFG_IN(GPIO36, AF0) -#define GPIO37_GPIO MFP_CFG_IN(GPIO37, AF0) -#define GPIO38_GPIO MFP_CFG_IN(GPIO38, AF0) -#define GPIO39_GPIO MFP_CFG_IN(GPIO39, AF0) -#define GPIO40_GPIO MFP_CFG_IN(GPIO40, AF0) -#define GPIO41_GPIO MFP_CFG_IN(GPIO41, AF0) -#define GPIO42_GPIO MFP_CFG_IN(GPIO42, AF0) -#define GPIO43_GPIO MFP_CFG_IN(GPIO43, AF0) -#define GPIO44_GPIO MFP_CFG_IN(GPIO44, AF0) -#define GPIO45_GPIO MFP_CFG_IN(GPIO45, AF0) -#define GPIO46_GPIO MFP_CFG_IN(GPIO46, AF0) -#define GPIO47_GPIO MFP_CFG_IN(GPIO47, AF0) -#define GPIO48_GPIO MFP_CFG_IN(GPIO48, AF0) -#define GPIO49_GPIO MFP_CFG_IN(GPIO49, AF0) -#define GPIO50_GPIO MFP_CFG_IN(GPIO50, AF0) -#define GPIO51_GPIO MFP_CFG_IN(GPIO51, AF0) -#define GPIO52_GPIO MFP_CFG_IN(GPIO52, AF0) -#define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0) -#define GPIO54_GPIO MFP_CFG_IN(GPIO54, AF0) -#define GPIO55_GPIO MFP_CFG_IN(GPIO55, AF0) -#define GPIO56_GPIO MFP_CFG_IN(GPIO56, AF0) -#define GPIO57_GPIO MFP_CFG_IN(GPIO57, AF0) -#define GPIO58_GPIO MFP_CFG_IN(GPIO58, AF0) -#define GPIO59_GPIO MFP_CFG_IN(GPIO59, AF0) -#define GPIO60_GPIO MFP_CFG_IN(GPIO60, AF0) -#define GPIO61_GPIO MFP_CFG_IN(GPIO61, AF0) -#define GPIO62_GPIO MFP_CFG_IN(GPIO62, AF0) -#define GPIO63_GPIO MFP_CFG_IN(GPIO63, AF0) -#define GPIO64_GPIO MFP_CFG_IN(GPIO64, AF0) -#define GPIO65_GPIO MFP_CFG_IN(GPIO65, AF0) -#define GPIO66_GPIO MFP_CFG_IN(GPIO66, AF0) -#define GPIO67_GPIO MFP_CFG_IN(GPIO67, AF0) -#define GPIO68_GPIO MFP_CFG_IN(GPIO68, AF0) -#define GPIO69_GPIO MFP_CFG_IN(GPIO69, AF0) -#define GPIO70_GPIO MFP_CFG_IN(GPIO70, AF0) -#define GPIO71_GPIO MFP_CFG_IN(GPIO71, AF0) -#define GPIO72_GPIO MFP_CFG_IN(GPIO72, AF0) -#define GPIO73_GPIO MFP_CFG_IN(GPIO73, AF0) -#define GPIO74_GPIO MFP_CFG_IN(GPIO74, AF0) -#define GPIO75_GPIO MFP_CFG_IN(GPIO75, AF0) -#define GPIO76_GPIO MFP_CFG_IN(GPIO76, AF0) -#define GPIO77_GPIO MFP_CFG_IN(GPIO77, AF0) -#define GPIO78_GPIO MFP_CFG_IN(GPIO78, AF0) -#define GPIO79_GPIO MFP_CFG_IN(GPIO79, AF0) -#define GPIO80_GPIO MFP_CFG_IN(GPIO80, AF0) -#define GPIO81_GPIO MFP_CFG_IN(GPIO81, AF0) -#define GPIO82_GPIO MFP_CFG_IN(GPIO82, AF0) -#define GPIO83_GPIO MFP_CFG_IN(GPIO83, AF0) -#define GPIO84_GPIO MFP_CFG_IN(GPIO84, AF0) - -extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num); -extern void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm); -extern int gpio_set_wake(unsigned int gpio, unsigned int on); -#endif /* __ASM_ARCH_MFP_PXA2XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h deleted file mode 100644 index 00eb724709..0000000000 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_ARCH_MFP_PXA3XX_H -#define __ASM_ARCH_MFP_PXA3XX_H - -#include <plat/mfp.h> - -#define MFPR_BASE (0x40e10000) - -/* NOTE: usage of these two functions is not recommended, - * use pxa3xx_mfp_config() instead. - */ -static inline unsigned long pxa3xx_mfp_read(int mfp) -{ - return mfp_read(mfp); -} - -static inline void pxa3xx_mfp_write(int mfp, unsigned long val) -{ - mfp_write(mfp, val); -} - -static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) -{ - mfp_config(mfp_cfg, num); -} -#endif /* __ASM_ARCH_MFP_PXA3XX_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h deleted file mode 100644 index 271e249ae3..0000000000 --- a/arch/arm/mach-pxa/include/mach/mfp.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/mfp.h - * - * Multi-Function Pin Definitions - * - * Copyright (C) 2007 Marvell International Ltd. - * - * 2007-8-21: eric miao <eric.miao@marvell.com> - * initial version - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_MFP_H -#define __ASM_ARCH_MFP_H - -#include <plat/mfp.h> - -#endif /* __ASM_ARCH_MFP_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h deleted file mode 100644 index 9bcb5efb7f..0000000000 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (c) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * Copyright (C) 2010 by Marc Kleine-Budde <mkl@pengutronix.de> - * - * This file is released under the GPLv2 - * - */ - -#ifndef __MACH_PXA_REGS_H -#define __MACH_PXA_REGS_H - -#ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)(x))) -# define __REG16(x) (*(volatile u16 *)(x)) -# define __REG2(x, y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -#else -# define __REG(x) (x) -# define __REG16(x) (x) -# define __REG2(x, y) ((x) + (y)) -#endif - -#ifdef CONFIG_ARCH_PXA2XX -# include <mach/pxa2xx-regs.h> -#endif - -#if defined(CONFIG_ARCH_PXA27X) -# include <mach/pxa27x-regs.h> -#elif defined(CONFIG_ARCH_PXA3XX) -# include <mach/pxa3xx-regs.h> -#elif defined(CONFIG_ARCH_PXA25X) -# include <mach/pxa25x-regs.h> -#else -# error "unknown PXA soc type" -#endif - -#endif /* !__MACH_PXA_REGS_H */ diff --git a/arch/arm/mach-pxa/include/mach/pxa25x-regs.h b/arch/arm/mach-pxa/include/mach/pxa25x-regs.h deleted file mode 100644 index f9cbe50007..0000000000 --- a/arch/arm/mach-pxa/include/mach/pxa25x-regs.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_PXA25X_REGS -#define __MACH_PXA25X_REGS - -/* this file intentionally left blank */ - -#endif /* !__MACH_PXA25X_REGS */ diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-regs.h b/arch/arm/mach-pxa/include/mach/pxa27x-regs.h deleted file mode 100644 index a97538d012..0000000000 --- a/arch/arm/mach-pxa/include/mach/pxa27x-regs.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MACH_PXA27X_REGS -#define __MACH_PXA27X_REGS - -/* this file intentionally left blank */ - -#endif /* !__MACH_PXA27X_REGS */ diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h deleted file mode 100644 index dc7704eda2..0000000000 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h - * - * Taken from pxa-regs.h by Russell King - * - * Author: Nicolas Pitre - * Copyright: MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __PXA2XX_REGS_H -#define __PXA2XX_REGS_H - -#include <mach/hardware.h> - -/* - * PXA Chip selects - */ -#define PXA_CS0_PHYS 0x00000000 -#define PXA_CS1_PHYS 0x04000000 -#define PXA_CS2_PHYS 0x08000000 -#define PXA_CS3_PHYS 0x0C000000 -#define PXA_CS4_PHYS 0x10000000 -#define PXA_CS5_PHYS 0x14000000 - -/* - * Memory controller - */ -#define MDCNFG_OFFSET 0x00000000 -#define MDREFR_OFFSET 0x00000004 -#define MSC0_OFFSET 0x00000008 -#define MSC1_OFFSET 0x0000000C -#define MSC2_OFFSET 0x00000010 -#define MECR_OFFSET 0x00000014 -#define SXCNFG_OFFSET 0x0000001C -#define FLYCNFG_OFFSET 0x00000020 -#define MCMEM0_OFFSET 0x00000028 -#define MCMEM1_OFFSET 0x0000002C -#define MCATT0_OFFSET 0x00000030 -#define MCATT1_OFFSET 0x00000034 -#define MCIO0_OFFSET 0x00000038 -#define MCIO1_OFFSET 0x0000003C -#define MDMRS_OFFSET 0x00000040 - -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define FLYCNFG __REG(0x48000020) /* Flycnfg Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ - -/* - * More handy macros for PCMCIA - * - * Arg is socket number - */ -#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ -#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ -#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ - -/* MECR register defines */ -#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ -#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ - -#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ -#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ -#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ -#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ -#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ -#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ -#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ -#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ -#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ -#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ -#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ -#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ -#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ -#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ -#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ -#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ -#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ - -/* - * Power Manager - */ - -#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ -#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ -#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ -#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ -#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ -#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ - -#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ -#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ -#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ -#define PCMD(x) __REG2(0x40F00080, (x)<<2) -#define PCMD0 __REG(0x40F00080 + 0 * 4) -#define PCMD1 __REG(0x40F00080 + 1 * 4) -#define PCMD2 __REG(0x40F00080 + 2 * 4) -#define PCMD3 __REG(0x40F00080 + 3 * 4) -#define PCMD4 __REG(0x40F00080 + 4 * 4) -#define PCMD5 __REG(0x40F00080 + 5 * 4) -#define PCMD6 __REG(0x40F00080 + 6 * 4) -#define PCMD7 __REG(0x40F00080 + 7 * 4) -#define PCMD8 __REG(0x40F00080 + 8 * 4) -#define PCMD9 __REG(0x40F00080 + 9 * 4) -#define PCMD10 __REG(0x40F00080 + 10 * 4) -#define PCMD11 __REG(0x40F00080 + 11 * 4) -#define PCMD12 __REG(0x40F00080 + 12 * 4) -#define PCMD13 __REG(0x40F00080 + 13 * 4) -#define PCMD14 __REG(0x40F00080 + 14 * 4) -#define PCMD15 __REG(0x40F00080 + 15 * 4) -#define PCMD16 __REG(0x40F00080 + 16 * 4) -#define PCMD17 __REG(0x40F00080 + 17 * 4) -#define PCMD18 __REG(0x40F00080 + 18 * 4) -#define PCMD19 __REG(0x40F00080 + 19 * 4) -#define PCMD20 __REG(0x40F00080 + 20 * 4) -#define PCMD21 __REG(0x40F00080 + 21 * 4) -#define PCMD22 __REG(0x40F00080 + 22 * 4) -#define PCMD23 __REG(0x40F00080 + 23 * 4) -#define PCMD24 __REG(0x40F00080 + 24 * 4) -#define PCMD25 __REG(0x40F00080 + 25 * 4) -#define PCMD26 __REG(0x40F00080 + 26 * 4) -#define PCMD27 __REG(0x40F00080 + 27 * 4) -#define PCMD28 __REG(0x40F00080 + 28 * 4) -#define PCMD29 __REG(0x40F00080 + 29 * 4) -#define PCMD30 __REG(0x40F00080 + 30 * 4) -#define PCMD31 __REG(0x40F00080 + 31 * 4) - -#define PCMD_MBC (1<<12) -#define PCMD_DCE (1<<11) -#define PCMD_LC (1<<10) -/* FIXME: PCMD_SQC need be checked. */ -#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, - bit 9 should be 0 all day. */ -#define PVCR_VCSA (0x1<<14) -#define PVCR_CommandDelay (0xf80) -#define PCFR_PI2C_EN (0x1 << 6) - -#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ -#define PSSR_RDH (1 << 5) /* Read Disable Hold */ -#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ -#define PSSR_STS (1 << 3) /* Standby Mode Status */ -#define PSSR_VFS (1 << 2) /* VDD Fault Status */ -#define PSSR_BFS (1 << 1) /* Battery Fault Status */ -#define PSSR_SSS (1 << 0) /* Software Sleep Status */ - -#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ - -#define PCFR_RO (1 << 15) /* RDH Override */ -#define PCFR_PO (1 << 14) /* PH Override */ -#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ -#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ -#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ -#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ -#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ -#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ -#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ -#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ -#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ -#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ - -#define RCSR_GPR (1 << 3) /* GPIO Reset */ -#define RCSR_SMR (1 << 2) /* Sleep Mode */ -#define RCSR_WDR (1 << 1) /* Watchdog Reset */ -#define RCSR_HWR (1 << 0) /* Hardware Reset */ - -#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO(0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO(1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO(2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO(3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO(4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO(5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO(6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO(7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO(8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO(9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO(10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO(11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO(12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO(13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO(14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO(15) /* GPIO [15] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ - -/* - * PXA2xx specific Core clock definitions - */ -#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ -#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ -#define CKEN __REG(0x41300004) /* Clock Enable Register */ -#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define CCCR_CPDIS (1 << 31) -#define CCCR_PPDIS (1 << 30) -#define CCCR_LCD26 (1 << 27) -#define CCCR_PLL_EARLY (1 << 26) -#define CCCR_A (1 << 25) - -#define CKEN_AC97CONF (1 << 31) /* AC97 Controller Configuration */ -#define CKEN_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN_USB (1 << 11) /* USB Unit Clock Enable */ -#define CKEN_ASSP (1 << 10) /* ASSP (1 << SSP3) Clock Enable */ -#define CKEN_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN_NSSP (1 << 9) /* NSSP (1 << SSP2) Clock Enable */ -#define CKEN_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN_HWUART (1 << 4) /* HWUART Unit Clock Enable */ -#define CKEN_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ -#define CKEN_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ -#define CKEN_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -/* PWRMODE register M field values */ - -#define PWRMODE_IDLE 0x1 -#define PWRMODE_STANDBY 0x2 -#define PWRMODE_SLEEP 0x3 -#define PWRMODE_DEEPSLEEP 0x7 - -#endif diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h deleted file mode 100644 index 373711d92f..0000000000 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h - * - * PXA3xx specific register definitions - * - * Copyright (C) 2007 Marvell International Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_PXA3XX_REGS -#define __MACH_PXA3XX_REGS - -#include <mach/hardware.h> - -/* - * Oscillator Configuration Register (OSCC) - */ -#define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ - -#define OSCC_PEN (1 << 11) /* 13MHz POUT */ - - -/* - * Service Power Management Unit (MPMU) - */ -#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ -#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ -#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ -#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ -#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ -#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ -#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ -#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ -#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) - -/* - * Slave Power Management Unit - */ -#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ -#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ -#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ -#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ -#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ -#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ -#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ -#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ -#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ -#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ -#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ -#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ -#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ -#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ - -/* - * Application Subsystem Configuration bits. - */ -#define ASCR_RDH (1 << 31) -#define ASCR_D1S (1 << 2) -#define ASCR_D2S (1 << 1) -#define ASCR_D3S (1 << 0) - -/* - * Application Reset Status bits. - */ -#define ARSR_GPR (1 << 3) -#define ARSR_LPMR (1 << 2) -#define ARSR_WDT (1 << 1) -#define ARSR_HWR (1 << 0) - -/* - * Application Subsystem Wake-Up bits. - */ -#define ADXER_WRTC (1 << 31) /* RTC */ -#define ADXER_WOST (1 << 30) /* OS Timer */ -#define ADXER_WTSI (1 << 29) /* Touchscreen */ -#define ADXER_WUSBH (1 << 28) /* USB host */ -#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ -#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ -#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ -#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ -#define ADXER_WKP (1 << 21) /* Keypad */ -#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ -#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ -#define ADXER_WOTG (1 << 16) /* USBOTG input */ -#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ -#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ -#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ -#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ -#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ -#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ -#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ -#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ -#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ -#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ -#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ -#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ -#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ -#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ -#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ -#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ - -/* - * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. - */ -#define ADXR_L2 (1 << 8) -#define ADXR_R5 (1 << 5) -#define ADXR_R4 (1 << 4) -#define ADXR_R3 (1 << 3) -#define ADXR_R2 (1 << 2) -#define ADXR_R1 (1 << 1) -#define ADXR_R0 (1 << 0) - -/* - * Values for PWRMODE CP15 register - */ -#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ -#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ -#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ -#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ -#define PXA3xx_PM_S0D0C1 0x01 - -/* - * Application Subsystem Clock - */ -#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ -#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ -#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ -#define CKENB __REG(0x41340010) /* B Clock Enable Register */ -#define CKENC __REG(0x41340024) /* C Clock Enable Register */ -#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ - -#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ -#define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */ -#define ACCR_D0CS (1 << 26) /* D0 Mode Clock Select */ -#define ACCR_PCCE (1 << 11) /* Power Mode Change Clock Enable */ -#define ACCR_DDR_D0CS (1 << 7) /* DDR SDRAM clock frequency in D0CS (PXA31x only) */ - -#define ACCR_SMCFS_MASK (0x7 << 23) /* Static Memory Controller Frequency Select */ -#define ACCR_SFLFS_MASK (0x3 << 18) /* Frequency Select for Internal Memory Controller */ -#define ACCR_XSPCLK_MASK (0x3 << 16) /* Core Frequency during Frequency Change */ -#define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */ -#define ACCR_DMCFS_MASK (0x3 << 12) /* Dynamic Memory Controller Clock Frequency Select */ -#define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */ -#define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */ - -#define ACCR_SMCFS(x) (((x) & 0x7) << 23) -#define ACCR_SFLFS(x) (((x) & 0x3) << 18) -#define ACCR_XSPCLK(x) (((x) & 0x3) << 16) -#define ACCR_HSS(x) (((x) & 0x3) << 14) -#define ACCR_DMCFS(x) (((x) & 0x3) << 12) -#define ACCR_XN(x) (((x) & 0x7) << 8) -#define ACCR_XL(x) ((x) & 0x1f) - -/* - * Clock Enable Bit - */ -#define CKEN_LCD 1 /* < LCD Clock Enable */ -#define CKEN_USBH 2 /* < USB host clock enable */ -#define CKEN_CAMERA 3 /* < Camera interface clock enable */ -#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ -#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ -#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ -#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ -#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ -#define CKEN_BOOT 11 /* < Boot rom clock enable */ -#define CKEN_MMC1 12 /* < MMC1 Clock enable */ -#define CKEN_MMC2 13 /* < MMC2 clock enable */ -#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ -#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ -#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ -#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ -#define CKEN_TPM 19 /* < TPM clock enable */ -#define CKEN_UDC 20 /* < UDC clock enable */ -#define CKEN_BTUART 21 /* < BTUART clock enable */ -#define CKEN_FFUART 22 /* < FFUART clock enable */ -#define CKEN_STUART 23 /* < STUART clock enable */ -#define CKEN_AC97 24 /* < AC97 clock enable */ -#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ -#define CKEN_SSP1 26 /* < SSP1 clock enable */ -#define CKEN_SSP2 27 /* < SSP2 clock enable */ -#define CKEN_SSP3 28 /* < SSP3 clock enable */ -#define CKEN_SSP4 29 /* < SSP4 clock enable */ -#define CKEN_MSL0 30 /* < MSL0 clock enable */ -#define CKEN_PWM0 32 /* < PWM[0] clock enable */ -#define CKEN_PWM1 33 /* < PWM[1] clock enable */ -#define CKEN_I2C 36 /* < I2C clock enable */ -#define CKEN_INTC 38 /* < Interrupt controller clock enable */ -#define CKEN_GPIO 39 /* < GPIO clock enable */ -#define CKEN_1WIRE 40 /* < 1-wire clock enable */ -#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ -#define CKEN_MINI_IM 48 /* < Mini-IM */ -#define CKEN_MINI_LCD 49 /* < Mini LCD */ - -#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ -#define CKEN_MVED 43 /* < MVED clock enable */ - -/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ -#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */ -#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */ - -/* - * Static Memory Controller - */ -#define MSC0 __REG(0x4a000008) /* Static Memory Control 0 */ -#define MSC1 __REG(0x4a00000c) /* Static Memory Control 1 */ -#define MECR __REG(0x4a000014) /* Expansion Memory Configuration */ -#define SXCNFG __REG(0x4a00001c) /* Synchronous Static Memory Control */ -#define MCMEM0 __REG(0x4a000028) /* Expansion Memory Timing */ -#define MCATT0 __REG(0x4a000030) /* Expansion Memory Timing */ -#define MCIO0 __REG(0x4a000038) /* Expansion Memory Timing */ -#define MEMCLKCFG __REG(0x4a000068) /* Clock configuration */ -#define CSADRCFG0 __REG(0x4a000080) /* CS0 address configuration */ -#define CSADRCFG1 __REG(0x4a000084) /* CS1 address configuration */ -#define CSADRCFG2 __REG(0x4a000088) /* CS2 address configuration */ -#define CSADRCFG3 __REG(0x4a00008c) /* CS3 address configuration */ -#define CSADRCFGP __REG(0x4a000090) /* CSP address configuration */ -#define CSMSADRCFG __REG(0x4a0000a0) /* CSP address configuration */ - -#endif /* !__MACH_PXA3XX_REGS */ diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h deleted file mode 100644 index 44ac3237a3..0000000000 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This structure describes the machine which we are running on. - */ -#ifndef _PXAFB_ -#define _PXAFB_ - -#include <fb.h> - -/* - * Supported LCD connections - * - * bits 0 - 3: for LCD panel type: - * - * STN - for passive matrix - * DSTN - for dual scan passive matrix - * TFT - for active matrix - * - * bits 4 - 9 : for bus width - * bits 10-17 : for AC Bias Pin Frequency - * bit 18 : for output enable polarity - * bit 19 : for pixel clock edge - * bit 20 : for output pixel format when base is RGBT16 - */ -#define LCD_CONN_TYPE(_x) ((_x) & 0x0f) -#define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f) - -#define LCD_TYPE_MASK 0xf -#define LCD_TYPE_UNKNOWN 0 -#define LCD_TYPE_MONO_STN 1 -#define LCD_TYPE_MONO_DSTN 2 -#define LCD_TYPE_COLOR_STN 3 -#define LCD_TYPE_COLOR_DSTN 4 -#define LCD_TYPE_COLOR_TFT 5 -#define LCD_TYPE_SMART_PANEL 6 -#define LCD_TYPE_MAX 7 - -#define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN) -#define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN) -#define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) -#define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) -#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) -#define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) -#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) -#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) -#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) -#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL) -#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL) - -#define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10) -#define LCD_BIAS_ACTIVE_HIGH (0 << 18) -#define LCD_BIAS_ACTIVE_LOW (1 << 18) -#define LCD_PCLK_EDGE_RISE (0 << 19) -#define LCD_PCLK_EDGE_FALL (1 << 19) -#define LCD_ALTERNATE_MAPPING (1 << 20) - -struct pxafb_videomode { - struct fb_videomode mode; - u8 bpp; -}; - -/** - * Define relevant framebuffer information - */ -struct pxafb_platform_data { - struct pxafb_videomode *mode; - unsigned int lcd_conn; - - /** force a memory area to be used, else NULL for dynamic allocation */ - void *framebuffer; - - void (*lcd_power)(int); - void (*backlight_power)(int); -}; - -/** - * @file - * @brief PXA related framebuffer declarations - */ -#endif diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h deleted file mode 100644 index 91760b2678..0000000000 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_MACH_REGS_INTC_H -#define __ASM_MACH_REGS_INTC_H - -#include <mach/hardware.h> - -/* - * Interrupt Controller - */ - -#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ -#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ -#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ -#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ -#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ -#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ -#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */ -#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */ -#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */ -#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ -#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ - -#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \ - : (x < 64 ? (0x94 + ((x - 32) << 2)) \ - : (0x128 + ((x - 64) << 2))))) - -#endif /* __ASM_MACH_REGS_INTC_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h deleted file mode 100644 index 4d473f23ae..0000000000 --- a/arch/arm/mach-pxa/include/mach/regs-lcd.h +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_ARCH_REGS_LCD_H -#define __ASM_ARCH_REGS_LCD_H - -/* - * LCD Controller Registers and Bits Definitions - */ -#define LCCR0 (0x000) /* LCD Controller Control Register 0 */ -#define LCCR1 (0x004) /* LCD Controller Control Register 1 */ -#define LCCR2 (0x008) /* LCD Controller Control Register 2 */ -#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */ -#define LCCR4 (0x010) /* LCD Controller Control Register 4 */ -#define LCCR5 (0x014) /* LCD Controller Control Register 5 */ -#define LCSR (0x038) /* LCD Controller Status Register 0 */ -#define LCSR1 (0x034) /* LCD Controller Status Register 1 */ -#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR (0x040) /* TMED RGB Seed Register */ -#define TMEDCR (0x044) /* TMED Control Register */ - -#define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */ -#define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */ -#define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */ -#define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */ -#define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */ -#define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */ -#define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */ - -#define OVL1C1 (0x050) /* Overlay 1 Control Register 1 */ -#define OVL1C2 (0x060) /* Overlay 1 Control Register 2 */ -#define OVL2C1 (0x070) /* Overlay 2 Control Register 1 */ -#define OVL2C2 (0x080) /* Overlay 2 Control Register 2 */ - -#define CMDCR (0x100) /* Command Control Register */ -#define PRSR (0x104) /* Panel Read Status Register */ - -#define LCCR3_BPP(x) ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0)) - -#define LCCR3_PDFOR_0 (0 << 30) -#define LCCR3_PDFOR_1 (1 << 30) -#define LCCR3_PDFOR_2 (2 << 30) -#define LCCR3_PDFOR_3 (3 << 30) - -#define LCCR4_PAL_FOR_0 (0 << 15) -#define LCCR4_PAL_FOR_1 (1 << 15) -#define LCCR4_PAL_FOR_2 (2 << 15) -#define LCCR4_PAL_FOR_3 (3 << 15) -#define LCCR4_PAL_FOR_MASK (3 << 15) - -#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FDADR2 (0x220) /* DMA Channel 2 Frame Descriptor Address Register */ -#define FDADR3 (0x230) /* DMA Channel 3 Frame Descriptor Address Register */ -#define FDADR4 (0x240) /* DMA Channel 4 Frame Descriptor Address Register */ -#define FDADR5 (0x250) /* DMA Channel 5 Frame Descriptor Address Register */ -#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */ - -#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ -#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ - -#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ -#define LCCR0_SFM (1 << 4) /* Start of frame mask */ -#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ -#define LCCR0_EFM (1 << 6) /* End of Frame mask */ -#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */ -#define LCCR0_DIS (1 << 10) /* LCD Disable */ -#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ -#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ -#define LCCR0_PDD_S 12 -#define LCCR0_BM (1 << 20) /* Branch mask */ -#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ -#define LCCR0_LCDT (1 << 22) /* LCD panel type */ -#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ -#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ -#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ -#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ - -#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << 0) /* Pixels Per Line - 1 */ -#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << 10) /* Horizontal Synchronization */ -#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << 16) /* End-of-Line pixel clock Wait - 1 */ -#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << 24) /* Beginning-of-Line pixel clock */ - -#define LCCR2_DisHght(Line) (((Line) - 1) << 0) /* Line Per Panel - 1 */ -#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << 10) /* Vertical Synchronization pulse - 1 */ -#define LCCR2_EndFrmDel(Tln) ((Tln) << 16) /* End-of-Frame line clock Wait */ -#define LCCR2_BegFrmDel(Tln) ((Tln) << 24) /* Beginning-of-Frame line clock */ - -#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ -#define LCCR3_API_S 16 -#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ -#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ -#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ - -#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ - -#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ -#define LCCR3_PixClkDiv(Div) ((Div) << 0) /* Pixel Clock Divisor */ - -#define LCCR3_Acb(Acb) ((Acb) << 8) /* AC Bias */ - -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */ - -#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */ -#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */ - -#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */ -#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */ -#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */ -#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */ - -#define LCSR_LDD (1 << 0) /* LCD Disable Done */ -#define LCSR_SOF (1 << 1) /* Start of frame */ -#define LCSR_BER (1 << 2) /* Bus error */ -#define LCSR_ABC (1 << 3) /* AC Bias count */ -#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ -#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ -#define LCSR_OU (1 << 6) /* output FIFO underrun */ -#define LCSR_QD (1 << 7) /* quick disable */ -#define LCSR_EOF (1 << 8) /* end of frame */ -#define LCSR_BS (1 << 9) /* branch status */ -#define LCSR_SINT (1 << 10) /* subsequent interrupt */ -#define LCSR_RD_ST (1 << 11) /* read status */ -#define LCSR_CMD_INT (1 << 12) /* command interrupt */ - -#define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */ -#define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */ -#define LCSR1_EOF(x) (1 << ((x) + 7)) /* End of Frame Status */ -#define LCSR1_SOF(x) (1 << ((x) - 1)) /* Start of Frame Status */ - -#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ -#define LDCMD_EOFINT (1 << 21) /* End of Frame Interrupt */ - -/* overlay control registers */ -#define OVLxC1_PPL(x) ((((x) - 1) & 0x3ff) << 0) /* Pixels Per Line */ -#define OVLxC1_LPO(x) ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */ -#define OVLxC1_BPP(x) (((x) & 0xf) << 20) /* Bits Per Pixel */ -#define OVLxC1_OEN (1 << 31) /* Enable bit for Overlay */ -#define OVLxC2_XPOS(x) (((x) & 0x3ff) << 0) /* Horizontal Position */ -#define OVLxC2_YPOS(x) (((x) & 0x3ff) << 10) /* Vertical Position */ -#define OVL2C2_PFOR(x) (((x) & 0x7) << 20) /* Pixel Format */ - -/* smartpanel related */ -#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */ -#define PRSR_A0 (1 << 8) /* Read Data Source */ -#define PRSR_ST_OK (1 << 9) /* Status OK */ -#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */ - -#define SMART_CMD_A0 (0x1 << 8) -#define SMART_CMD_READ_STATUS_REG (0x0 << 9) -#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0) -#define SMART_CMD_WRITE_COMMAND (0x1 << 9) -#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0) -#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0) -#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9) -#define SMART_CMD_NOOP (0x4 << 9) -#define SMART_CMD_INTERRUPT (0x5 << 9) - -#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff)) -#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff)) - -/* SMART_DELAY() is introduced for software controlled delay primitive which - * can be inserted between command sequences, unused command 0x6 is used here - * and delay ranges from 0ms ~ 255ms - */ -#define SMART_CMD_DELAY (0x6 << 9) -#define SMART_DELAY(ms) (SMART_CMD_DELAY | ((ms) & 0xff)) -#endif /* __ASM_ARCH_REGS_LCD_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h deleted file mode 100644 index aefdee44f8..0000000000 --- a/arch/arm/mach-pxa/include/mach/regs-ost.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ASM_MACH_REGS_OST_H -#define __ASM_MACH_REGS_OST_H - -#include <mach/hardware.h> - -/* - * OS Timer & Match Registers - */ - -#define OSMR0 __REG(0x40A00000) /* */ -#define OSMR1 __REG(0x40A00004) /* */ -#define OSMR2 __REG(0x40A00008) /* */ -#define OSMR3 __REG(0x40A0000C) /* */ -#define OSMR4 __REG(0x40A00080) /* */ -#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ -#define OMCR4 __REG(0x40A000C0) /* */ -#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ -#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ -#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ - -#define OSSR_M3 (1 << 3) /* Match status channel 3 */ -#define OSSR_M2 (1 << 2) /* Match status channel 2 */ -#define OSSR_M1 (1 << 1) /* Match status channel 1 */ -#define OSSR_M0 (1 << 0) /* Match status channel 0 */ - -#define OWER_WME (1 << 0) /* Watchdog Match Enable */ - -#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ -#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ -#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ -#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ - -#endif /* __ASM_MACH_REGS_OST_H */ diff --git a/arch/arm/mach-pxa/include/mach/regs-pwm.h b/arch/arm/mach-pxa/include/mach/regs-pwm.h deleted file mode 100644 index 9fdcbb64ae..0000000000 --- a/arch/arm/mach-pxa/include/mach/regs-pwm.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __ASM_MACH_REGS_PWM_H -#define __ASM_MACH_REGS_PWM_H - -#include <mach/hardware.h> - -/* - * Pulse modulator registers - */ -#define PWM0 0x40B00000 -#define PWM1 0x40C00000 -#define PWM0slave 0x40B00010 -#define PWM1slave 0x40C00010 - -#endif diff --git a/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h b/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h deleted file mode 100644 index 1ddfa7b797..0000000000 --- a/arch/arm/mach-pxa/include/mach/udc_pxa2xx.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * arch/arm/mach-pxa/include/mach/udc_pxa2xx.h - * - * This supports machine-specific differences in how the PXA2xx - * USB Device Controller (UDC) is wired. - * - * It is set in linux/arch/arm/mach-pxa/<machine>.c or in - * linux/arch/mach-ixp4xx/<machine>.c and used in - * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c - */ - -struct pxa2xx_udc_mach_info { - int (*udc_is_connected)(void); /* do we see host? */ - void (*udc_command)(int cmd); -#define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */ -#define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */ - - /* Boards following the design guidelines in the developer's manual, - * with on-chip GPIOs not Lubbock's weird hardware, can have a sane - * VBUS IRQ and omit the methods above. Store the GPIO number - * here. Note that sometimes the signals go through inverters... - */ - bool gpio_pullup_inverted; - int gpio_pullup; /* high == pullup activated */ -}; - diff --git a/arch/arm/mach-pxa/include/plat/gpio.h b/arch/arm/mach-pxa/include/plat/gpio.h deleted file mode 100644 index 35f90715e0..0000000000 --- a/arch/arm/mach-pxa/include/plat/gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef __PLAT_GPIO_H -#define __PLAT_GPIO_H - -#include <mach/gpio.h> - -/* - * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with - * one set of registers. The register offsets are organized below: - * - * GPLR GPDR GPSR GPCR GRER GFER GEDR - * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 - * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C - * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 - * - * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 - * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C - * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 - * - * NOTE: - * BANK 3 is only available on PXA27x and later processors. - * BANK 4 and 5 are only available on PXA935 - */ - -#define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - -/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). - * Those cases currently cause holes in the GPIO number space, the - * actual number of the last GPIO is recorded by 'pxa_last_gpio'. - */ -extern int pxa_last_gpio; - -extern int pxa_init_gpio(int start, int end); - -#endif /* __PLAT_GPIO_H */ diff --git a/arch/arm/mach-pxa/include/plat/mfp.h b/arch/arm/mach-pxa/include/plat/mfp.h deleted file mode 100644 index aedb956cd3..0000000000 --- a/arch/arm/mach-pxa/include/plat/mfp.h +++ /dev/null @@ -1,469 +0,0 @@ -/* - * arch/arm/plat-pxa/include/plat/mfp.h - * - * Common Multi-Function Pin Definitions - * - * Copyright (C) 2007 Marvell International Ltd. - * - * 2007-8-21: eric miao <eric.miao@marvell.com> - * initial version - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_PLAT_MFP_H -#define __ASM_PLAT_MFP_H - -#define mfp_to_gpio(m) ((m) % 256) - -/* list of all the configurable MFP pins */ -enum { - MFP_PIN_INVALID = -1, - - MFP_PIN_GPIO0 = 0, - MFP_PIN_GPIO1, - MFP_PIN_GPIO2, - MFP_PIN_GPIO3, - MFP_PIN_GPIO4, - MFP_PIN_GPIO5, - MFP_PIN_GPIO6, - MFP_PIN_GPIO7, - MFP_PIN_GPIO8, - MFP_PIN_GPIO9, - MFP_PIN_GPIO10, - MFP_PIN_GPIO11, - MFP_PIN_GPIO12, - MFP_PIN_GPIO13, - MFP_PIN_GPIO14, - MFP_PIN_GPIO15, - MFP_PIN_GPIO16, - MFP_PIN_GPIO17, - MFP_PIN_GPIO18, - MFP_PIN_GPIO19, - MFP_PIN_GPIO20, - MFP_PIN_GPIO21, - MFP_PIN_GPIO22, - MFP_PIN_GPIO23, - MFP_PIN_GPIO24, - MFP_PIN_GPIO25, - MFP_PIN_GPIO26, - MFP_PIN_GPIO27, - MFP_PIN_GPIO28, - MFP_PIN_GPIO29, - MFP_PIN_GPIO30, - MFP_PIN_GPIO31, - MFP_PIN_GPIO32, - MFP_PIN_GPIO33, - MFP_PIN_GPIO34, - MFP_PIN_GPIO35, - MFP_PIN_GPIO36, - MFP_PIN_GPIO37, - MFP_PIN_GPIO38, - MFP_PIN_GPIO39, - MFP_PIN_GPIO40, - MFP_PIN_GPIO41, - MFP_PIN_GPIO42, - MFP_PIN_GPIO43, - MFP_PIN_GPIO44, - MFP_PIN_GPIO45, - MFP_PIN_GPIO46, - MFP_PIN_GPIO47, - MFP_PIN_GPIO48, - MFP_PIN_GPIO49, - MFP_PIN_GPIO50, - MFP_PIN_GPIO51, - MFP_PIN_GPIO52, - MFP_PIN_GPIO53, - MFP_PIN_GPIO54, - MFP_PIN_GPIO55, - MFP_PIN_GPIO56, - MFP_PIN_GPIO57, - MFP_PIN_GPIO58, - MFP_PIN_GPIO59, - MFP_PIN_GPIO60, - MFP_PIN_GPIO61, - MFP_PIN_GPIO62, - MFP_PIN_GPIO63, - MFP_PIN_GPIO64, - MFP_PIN_GPIO65, - MFP_PIN_GPIO66, - MFP_PIN_GPIO67, - MFP_PIN_GPIO68, - MFP_PIN_GPIO69, - MFP_PIN_GPIO70, - MFP_PIN_GPIO71, - MFP_PIN_GPIO72, - MFP_PIN_GPIO73, - MFP_PIN_GPIO74, - MFP_PIN_GPIO75, - MFP_PIN_GPIO76, - MFP_PIN_GPIO77, - MFP_PIN_GPIO78, - MFP_PIN_GPIO79, - MFP_PIN_GPIO80, - MFP_PIN_GPIO81, - MFP_PIN_GPIO82, - MFP_PIN_GPIO83, - MFP_PIN_GPIO84, - MFP_PIN_GPIO85, - MFP_PIN_GPIO86, - MFP_PIN_GPIO87, - MFP_PIN_GPIO88, - MFP_PIN_GPIO89, - MFP_PIN_GPIO90, - MFP_PIN_GPIO91, - MFP_PIN_GPIO92, - MFP_PIN_GPIO93, - MFP_PIN_GPIO94, - MFP_PIN_GPIO95, - MFP_PIN_GPIO96, - MFP_PIN_GPIO97, - MFP_PIN_GPIO98, - MFP_PIN_GPIO99, - MFP_PIN_GPIO100, - MFP_PIN_GPIO101, - MFP_PIN_GPIO102, - MFP_PIN_GPIO103, - MFP_PIN_GPIO104, - MFP_PIN_GPIO105, - MFP_PIN_GPIO106, - MFP_PIN_GPIO107, - MFP_PIN_GPIO108, - MFP_PIN_GPIO109, - MFP_PIN_GPIO110, - MFP_PIN_GPIO111, - MFP_PIN_GPIO112, - MFP_PIN_GPIO113, - MFP_PIN_GPIO114, - MFP_PIN_GPIO115, - MFP_PIN_GPIO116, - MFP_PIN_GPIO117, - MFP_PIN_GPIO118, - MFP_PIN_GPIO119, - MFP_PIN_GPIO120, - MFP_PIN_GPIO121, - MFP_PIN_GPIO122, - MFP_PIN_GPIO123, - MFP_PIN_GPIO124, - MFP_PIN_GPIO125, - MFP_PIN_GPIO126, - MFP_PIN_GPIO127, - - MFP_PIN_GPIO128, - MFP_PIN_GPIO129, - MFP_PIN_GPIO130, - MFP_PIN_GPIO131, - MFP_PIN_GPIO132, - MFP_PIN_GPIO133, - MFP_PIN_GPIO134, - MFP_PIN_GPIO135, - MFP_PIN_GPIO136, - MFP_PIN_GPIO137, - MFP_PIN_GPIO138, - MFP_PIN_GPIO139, - MFP_PIN_GPIO140, - MFP_PIN_GPIO141, - MFP_PIN_GPIO142, - MFP_PIN_GPIO143, - MFP_PIN_GPIO144, - MFP_PIN_GPIO145, - MFP_PIN_GPIO146, - MFP_PIN_GPIO147, - MFP_PIN_GPIO148, - MFP_PIN_GPIO149, - MFP_PIN_GPIO150, - MFP_PIN_GPIO151, - MFP_PIN_GPIO152, - MFP_PIN_GPIO153, - MFP_PIN_GPIO154, - MFP_PIN_GPIO155, - MFP_PIN_GPIO156, - MFP_PIN_GPIO157, - MFP_PIN_GPIO158, - MFP_PIN_GPIO159, - MFP_PIN_GPIO160, - MFP_PIN_GPIO161, - MFP_PIN_GPIO162, - MFP_PIN_GPIO163, - MFP_PIN_GPIO164, - MFP_PIN_GPIO165, - MFP_PIN_GPIO166, - MFP_PIN_GPIO167, - MFP_PIN_GPIO168, - MFP_PIN_GPIO169, - MFP_PIN_GPIO170, - MFP_PIN_GPIO171, - MFP_PIN_GPIO172, - MFP_PIN_GPIO173, - MFP_PIN_GPIO174, - MFP_PIN_GPIO175, - MFP_PIN_GPIO176, - MFP_PIN_GPIO177, - MFP_PIN_GPIO178, - MFP_PIN_GPIO179, - MFP_PIN_GPIO180, - MFP_PIN_GPIO181, - MFP_PIN_GPIO182, - MFP_PIN_GPIO183, - MFP_PIN_GPIO184, - MFP_PIN_GPIO185, - MFP_PIN_GPIO186, - MFP_PIN_GPIO187, - MFP_PIN_GPIO188, - MFP_PIN_GPIO189, - MFP_PIN_GPIO190, - MFP_PIN_GPIO191, - - MFP_PIN_GPIO255 = 255, - - MFP_PIN_GPIO0_2, - MFP_PIN_GPIO1_2, - MFP_PIN_GPIO2_2, - MFP_PIN_GPIO3_2, - MFP_PIN_GPIO4_2, - MFP_PIN_GPIO5_2, - MFP_PIN_GPIO6_2, - MFP_PIN_GPIO7_2, - MFP_PIN_GPIO8_2, - MFP_PIN_GPIO9_2, - MFP_PIN_GPIO10_2, - MFP_PIN_GPIO11_2, - MFP_PIN_GPIO12_2, - MFP_PIN_GPIO13_2, - MFP_PIN_GPIO14_2, - MFP_PIN_GPIO15_2, - MFP_PIN_GPIO16_2, - MFP_PIN_GPIO17_2, - - MFP_PIN_ULPI_STP, - MFP_PIN_ULPI_NXT, - MFP_PIN_ULPI_DIR, - - MFP_PIN_nXCVREN, - MFP_PIN_DF_CLE_nOE, - MFP_PIN_DF_nADV1_ALE, - MFP_PIN_DF_SCLK_E, - MFP_PIN_DF_SCLK_S, - MFP_PIN_nBE0, - MFP_PIN_nBE1, - MFP_PIN_DF_nADV2_ALE, - MFP_PIN_DF_INT_RnB, - MFP_PIN_DF_nCS0, - MFP_PIN_DF_nCS1, - MFP_PIN_nLUA, - MFP_PIN_nLLA, - MFP_PIN_DF_nWE, - MFP_PIN_DF_ALE_nWE, - MFP_PIN_DF_nRE_nOE, - MFP_PIN_DF_ADDR0, - MFP_PIN_DF_ADDR1, - MFP_PIN_DF_ADDR2, - MFP_PIN_DF_ADDR3, - MFP_PIN_DF_IO0, - MFP_PIN_DF_IO1, - MFP_PIN_DF_IO2, - MFP_PIN_DF_IO3, - MFP_PIN_DF_IO4, - MFP_PIN_DF_IO5, - MFP_PIN_DF_IO6, - MFP_PIN_DF_IO7, - MFP_PIN_DF_IO8, - MFP_PIN_DF_IO9, - MFP_PIN_DF_IO10, - MFP_PIN_DF_IO11, - MFP_PIN_DF_IO12, - MFP_PIN_DF_IO13, - MFP_PIN_DF_IO14, - MFP_PIN_DF_IO15, - MFP_PIN_DF_nCS0_SM_nCS2, - MFP_PIN_DF_nCS1_SM_nCS3, - MFP_PIN_SM_nCS0, - MFP_PIN_SM_nCS1, - MFP_PIN_DF_WEn, - MFP_PIN_DF_REn, - MFP_PIN_DF_CLE_SM_OEn, - MFP_PIN_DF_ALE_SM_WEn, - MFP_PIN_DF_RDY0, - MFP_PIN_DF_RDY1, - - MFP_PIN_SM_SCLK, - MFP_PIN_SM_BE0, - MFP_PIN_SM_BE1, - MFP_PIN_SM_ADV, - MFP_PIN_SM_ADVMUX, - MFP_PIN_SM_RDY, - - MFP_PIN_MMC1_DAT7, - MFP_PIN_MMC1_DAT6, - MFP_PIN_MMC1_DAT5, - MFP_PIN_MMC1_DAT4, - MFP_PIN_MMC1_DAT3, - MFP_PIN_MMC1_DAT2, - MFP_PIN_MMC1_DAT1, - MFP_PIN_MMC1_DAT0, - MFP_PIN_MMC1_CMD, - MFP_PIN_MMC1_CLK, - MFP_PIN_MMC1_CD, - MFP_PIN_MMC1_WP, - - /* additional pins on PXA930 */ - MFP_PIN_GSIM_UIO, - MFP_PIN_GSIM_UCLK, - MFP_PIN_GSIM_UDET, - MFP_PIN_GSIM_nURST, - MFP_PIN_PMIC_INT, - MFP_PIN_RDY, - - MFP_PIN_MAX, -}; - -/* - * a possible MFP configuration is represented by a 32-bit integer - * - * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) - * bit 10..12 - Alternate Function Selection - * bit 13..15 - Drive Strength - * bit 16..18 - Low Power Mode State - * bit 19..20 - Low Power Mode Edge Detection - * bit 21..22 - Run Mode Pull State - * - * to facilitate the definition, the following macros are provided - * - * MFP_CFG_DEFAULT - default MFP configuration value, with - * alternate function = 0, - * drive strength = fast 3mA (MFP_DS03X) - * low power mode = default - * edge detection = none - * - * MFP_CFG - default MFPR value with alternate function - * MFP_CFG_DRV - default MFPR value with alternate function and - * pin drive strength - * MFP_CFG_LPM - default MFPR value with alternate function and - * low power mode - * MFP_CFG_X - default MFPR value with alternate function, - * pin drive strength and low power mode - */ - -typedef unsigned long mfp_cfg_t; - -#define MFP_PIN(x) ((x) & 0x3ff) - -#define MFP_AF0 (0x0 << 10) -#define MFP_AF1 (0x1 << 10) -#define MFP_AF2 (0x2 << 10) -#define MFP_AF3 (0x3 << 10) -#define MFP_AF4 (0x4 << 10) -#define MFP_AF5 (0x5 << 10) -#define MFP_AF6 (0x6 << 10) -#define MFP_AF7 (0x7 << 10) -#define MFP_AF_MASK (0x7 << 10) -#define MFP_AF(x) (((x) >> 10) & 0x7) - -#define MFP_DS01X (0x0 << 13) -#define MFP_DS02X (0x1 << 13) -#define MFP_DS03X (0x2 << 13) -#define MFP_DS04X (0x3 << 13) -#define MFP_DS06X (0x4 << 13) -#define MFP_DS08X (0x5 << 13) -#define MFP_DS10X (0x6 << 13) -#define MFP_DS13X (0x7 << 13) -#define MFP_DS_MASK (0x7 << 13) -#define MFP_DS(x) (((x) >> 13) & 0x7) - -#define MFP_LPM_DEFAULT (0x0 << 16) -#define MFP_LPM_DRIVE_LOW (0x1 << 16) -#define MFP_LPM_DRIVE_HIGH (0x2 << 16) -#define MFP_LPM_PULL_LOW (0x3 << 16) -#define MFP_LPM_PULL_HIGH (0x4 << 16) -#define MFP_LPM_FLOAT (0x5 << 16) -#define MFP_LPM_INPUT (0x6 << 16) -#define MFP_LPM_STATE_MASK (0x7 << 16) -#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) - -#define MFP_LPM_EDGE_NONE (0x0 << 19) -#define MFP_LPM_EDGE_RISE (0x1 << 19) -#define MFP_LPM_EDGE_FALL (0x2 << 19) -#define MFP_LPM_EDGE_BOTH (0x3 << 19) -#define MFP_LPM_EDGE_MASK (0x3 << 19) -#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) - -#define MFP_PULL_NONE (0x0 << 21) -#define MFP_PULL_LOW (0x1 << 21) -#define MFP_PULL_HIGH (0x2 << 21) -#define MFP_PULL_BOTH (0x3 << 21) -#define MFP_PULL_FLOAT (0x4 << 21) -#define MFP_PULL_MASK (0x7 << 21) -#define MFP_PULL(x) (((x) >> 21) & 0x7) - -#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ - MFP_LPM_EDGE_NONE | MFP_PULL_NONE) - -#define MFP_CFG(pin, af) \ - ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) - -#define MFP_CFG_DRV(pin, af, drv) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) - -#define MFP_CFG_LPM(pin, af, lpm) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) - -#define MFP_CFG_X(pin, af, drv, lpm) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) - -#if defined(CONFIG_ARCH_PXA3XX) -/* - * each MFP pin will have a MFPR register, since the offset of the - * register varies between processors, the processor specific code - * should initialize the pin offsets by mfp_init() - * - * mfp_init_base() - accepts a virtual base for all MFPR registers and - * initialize the MFP table to a default state - * - * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which - * represents a range of MFP pins from "start" to "end", with the offset - * begining at "offset", to define a single pin, let "end" = -1. - * - * use - * - * MFP_ADDR_X() to define a range of pins - * MFP_ADDR() to define a single pin - * MFP_ADDR_END to signal the end of pin offset definitions - */ -struct mfp_addr_map { - unsigned int start; - unsigned int end; - unsigned long offset; -}; - -#define MFP_ADDR_X(start, end, offset) \ - { MFP_PIN_##start, MFP_PIN_##end, offset } - -#define MFP_ADDR(pin, offset) \ - { MFP_PIN_##pin, -1, offset } - -#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } - -void __init mfp_init_base(void __iomem *mfpr_base); -void __init mfp_init_addr(struct mfp_addr_map *map); - -/* - * mfp_{read, write}() - for direct read/write access to the MFPR register - * mfp_config() - for configuring a group of MFPR registers - * mfp_config_lpm() - configuring all low power MFPR registers for suspend - * mfp_config_run() - configuring all run time MFPR registers after resume - */ -unsigned long mfp_read(int mfp); -void mfp_write(int mfp, unsigned long mfpr_val); -void mfp_config(unsigned long *mfp_cfgs, int num); -void mfp_config_run(void); -void mfp_config_lpm(void); -void mfp_init(void); -#endif /* CONFIG_ARCH_PXA3XX */ - -#endif /* __ASM_PLAT_MFP_H */ diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 2456cef936..aca46c45b3 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -17,10 +17,10 @@ #include <errno.h> #include <init.h> -#include <mach/gpio.h> -#include <mach/hardware.h> -#include <mach/mfp-pxa2xx.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/gpio.h> +#include <mach/pxa/hardware.h> +#include <mach/pxa/mfp-pxa2xx.h> +#include <mach/pxa/pxa-regs.h> #define PGSR(x) __REG2(0x40F00020, (x) << 2) #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index df4922453d..7f9e5113b8 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -16,9 +16,9 @@ #include <common.h> #include <init.h> #include <io.h> -#include <mach/hardware.h> -#include <mach/mfp-pxa3xx.h> -#include <plat/mfp.h> +#include <mach/pxa/hardware.h> +#include <mach/pxa/mfp-pxa3xx.h> +#include <mach/pxa/mfp.h> #define MFPR_SIZE (PAGE_SIZE) diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index e28378e6db..496ceb39d5 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c @@ -16,8 +16,8 @@ #include <init.h> #include <poweroff.h> #include <reset_source.h> -#include <mach/hardware.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/hardware.h> +#include <mach/pxa/pxa-regs.h> extern void pxa_suspend(int mode); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index ccfd952b5e..ec49983962 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -16,8 +16,8 @@ #include <init.h> #include <poweroff.h> #include <reset_source.h> -#include <mach/hardware.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/hardware.h> +#include <mach/pxa/pxa-regs.h> extern void pxa3xx_suspend(int mode); diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 1c678158c9..3d12dc54de 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S @@ -13,8 +13,8 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/pxa2xx-regs.h> +#include <mach/pxa/hardware.h> +#include <mach/pxa/pxa2xx-regs.h> #define MDREFR_KDIV 0x200a4000 // all banks #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0 diff --git a/arch/arm/mach-pxa/speed-pxa25x.c b/arch/arm/mach-pxa/speed-pxa25x.c index 69143431e4..de3d5c251c 100644 --- a/arch/arm/mach-pxa/speed-pxa25x.c +++ b/arch/arm/mach-pxa/speed-pxa25x.c @@ -8,8 +8,8 @@ */ #include <common.h> -#include <mach/clock.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/clock.h> +#include <mach/pxa/pxa-regs.h> /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 diff --git a/arch/arm/mach-pxa/speed-pxa27x.c b/arch/arm/mach-pxa/speed-pxa27x.c index 1de034c677..5441dc3d70 100644 --- a/arch/arm/mach-pxa/speed-pxa27x.c +++ b/arch/arm/mach-pxa/speed-pxa27x.c @@ -8,8 +8,8 @@ */ #include <common.h> -#include <mach/clock.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/clock.h> +#include <mach/pxa/pxa-regs.h> /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 diff --git a/arch/arm/mach-pxa/speed-pxa3xx.c b/arch/arm/mach-pxa/speed-pxa3xx.c index b24b7a8fc3..2579966f41 100644 --- a/arch/arm/mach-pxa/speed-pxa3xx.c +++ b/arch/arm/mach-pxa/speed-pxa3xx.c @@ -11,8 +11,8 @@ #include <init.h> #include <linux/clk.h> #include <linux/clkdev.h> -#include <mach/clock.h> -#include <mach/pxa-regs.h> +#include <mach/pxa/clock.h> +#include <mach/pxa/pxa-regs.h> /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 |