diff options
Diffstat (limited to 'arch/arm/mach-s3c24xx')
| -rw-r--r-- | arch/arm/mach-s3c24xx/generic.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/lowlevel-init.S | 10 |
2 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-s3c24xx/generic.c index 4613e59760..dddd0187c3 100644 --- a/arch/arm/mach-s3c24xx/generic.c +++ b/arch/arm/mach-s3c24xx/generic.c @@ -240,7 +240,7 @@ EXPORT_SYMBOL(reset_cpu); /** -@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in U-Boot-v2 +@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox @section s3c24xx_boards Boards using S3C24xx Processors @@ -274,20 +274,20 @@ All S3C24xx common headers are located here. /** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms -@par U-Boot-v2 Map +@par barebox Map -The location of the U-Boot-v2 itself depends on the available amount of +The location of the barebox itself depends on the available amount of installed SDRAM memory: -- 0x30fc.0000 Start of U-Boot-v2 when 16MiB SDRAM is available -- 0x31fc.0000 Start of U-Boot-v2 when 32MiB SDRAM is available -- 0x33fc.0000 Start of U-Boot-v2 when 64MiB SDRAM is available +- 0x30fc.0000 Start of barebox when 16MiB SDRAM is available +- 0x31fc.0000 Start of barebox when 32MiB SDRAM is available +- 0x33fc.0000 Start of barebox when 64MiB SDRAM is available Adjust the CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to the available memory. @note The RAM based filesystem and the stack resides always below the -U-Boot-v2 start address. +barebox start address. @li @subpage dev_s3c24xx_wd_handling @li @subpage dev_s3c24xx_pll_handling diff --git a/arch/arm/mach-s3c24xx/lowlevel-init.S b/arch/arm/mach-s3c24xx/lowlevel-init.S index fd6b0f396d..e8004e588c 100644 --- a/arch/arm/mach-s3c24xx/lowlevel-init.S +++ b/arch/arm/mach-s3c24xx/lowlevel-init.S @@ -223,7 +223,7 @@ SDRAMDATA: @page dev_s3c24xx_sdram_handling SDRAM controller initialisation The SDRAM controller is very simple and its initialisation requires only a -few steps. U-Boot-v2 provides a generic routine to do this step. +few steps. barebox provides a generic routine to do this step. Enable CONFIG_S3C24XX_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able to call the generic s3c24x0_sdram_init() assembler function from within the @@ -292,14 +292,14 @@ machine specific board_init_lowlevel() assembler function. an initialized stack pointer. @note Basicly this routine runs from inside the internal SRAM. After load of -the whole U-Boot-v2 image from the NAND flash memory into the SDRAM it adjusts +the whole barebox image from the NAND flash memory into the SDRAM it adjusts the link register to the final SDRAM adress and returns. @note In the NAND boot mode, ECC is not checked. So, the first x KBytes used -by U-Boot-v2 should have no bit error. +by barebox should have no bit error. -Due to the fact the code to load the whole U-Boot-v2 from NAND must fit into -the first 4kiB of the U-Boot-v2 image, the shrinked NAND driver is very +Due to the fact the code to load the whole barebox from NAND must fit into +the first 4kiB of the barebox image, the shrinked NAND driver is very minimalistic. Setup the NAND access timing is done in a safe manner, what means: Slowest possible values are used. If you want to increase the speed you should define the BOARD_DEFAULT_NAND_TIMING to a valid setting into the |