diff options
Diffstat (limited to 'arch/arm/mach-samsung')
-rw-r--r-- | arch/arm/mach-samsung/generic.c | 28 | ||||
-rw-r--r-- | arch/arm/mach-samsung/include/mach/s3c-busctl.h | 32 | ||||
-rw-r--r-- | arch/arm/mach-samsung/include/mach/s3c-generic.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-samsung/include/mach/s3c-iomap.h | 39 | ||||
-rw-r--r-- | arch/arm/mach-samsung/lowlevel-init.S | 4 | ||||
-rw-r--r-- | arch/arm/mach-samsung/s3c24xx-clocks.c | 9 |
6 files changed, 72 insertions, 43 deletions
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c index 4a0c87b0dc..cbe03217c4 100644 --- a/arch/arm/mach-samsung/generic.c +++ b/arch/arm/mach-samsung/generic.c @@ -27,55 +27,63 @@ #include <init.h> #include <clock.h> #include <io.h> +#include <sizes.h> #include <mach/s3c-iomap.h> #include <mach/s3c-generic.h> +#include <mach/s3c-busctl.h> /** * Calculate the amount of connected and available memory * @return Memory size in bytes */ -uint32_t s3c24x0_get_memory_size(void) +uint32_t s3c24xx_get_memory_size(void) { uint32_t reg, size; /* * detect the current memory size */ - reg = readl(BANKSIZE); + reg = readl(S3C_BANKSIZE); switch (reg & 0x7) { case 0: - size = 32 * 1024 * 1024; + size = SZ_32M; break; case 1: - size = 64 * 1024 * 1024; + size = SZ_64M; break; case 2: - size = 128 * 1024 * 1024; + size = SZ_128M; break; case 4: - size = 2 * 1024 * 1024; + size = SZ_2M; break; case 5: - size = 4 * 1024 * 1024; + size = SZ_4M; break; case 6: - size = 8 * 1024 * 1024; + size = SZ_8M; break; default: - size = 16 * 1024 * 1024; + size = SZ_16M; break; } /* * Is bank7 also configured for SDRAM usage? */ - if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15)) + if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15)) size <<= 1; /* also count this bank */ return size; } +void s3c24xx_disable_second_sdram_bank(void) +{ + writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7); + writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable its clock */ +} + #define S3C_WTCON (S3C_WATCHDOG_BASE) #define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04) #define S3C_WTCNT (S3C_WATCHDOG_BASE + 0x08) diff --git a/arch/arm/mach-samsung/include/mach/s3c-busctl.h b/arch/arm/mach-samsung/include/mach/s3c-busctl.h new file mode 100644 index 0000000000..4bcf0a7013 --- /dev/null +++ b/arch/arm/mach-samsung/include/mach/s3c-busctl.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2011 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_S3C_BUSCTL_H +# define __MACH_S3C_BUSCTL_H + +#define S3C_BWSCON (S3C_MEMCTL_BASE) +#define S3C_BANKCON0 (S3C_MEMCTL_BASE + 0x04) +#define S3C_BANKCON1 (S3C_MEMCTL_BASE + 0x08) +#define S3C_BANKCON2 (S3C_MEMCTL_BASE + 0x0c) +#define S3C_BANKCON3 (S3C_MEMCTL_BASE + 0x10) +#define S3C_BANKCON4 (S3C_MEMCTL_BASE + 0x14) +#define S3C_BANKCON5 (S3C_MEMCTL_BASE + 0x18) +#define S3C_BANKCON6 (S3C_MEMCTL_BASE + 0x1c) +#define S3C_BANKCON7 (S3C_MEMCTL_BASE + 0x20) +#define S3C_REFRESH (S3C_MEMCTL_BASE + 0x24) +#define S3C_BANKSIZE (S3C_MEMCTL_BASE + 0x28) +#define S3C_MRSRB6 (S3C_MEMCTL_BASE + 0x2c) +#define S3C_MRSRB7 (S3C_MEMCTL_BASE + 0x30) + +#endif /* __MACH_S3C_BUSCTL_H */ diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h index 33f025d894..4ea3dd7ea4 100644 --- a/arch/arm/mach-samsung/include/mach/s3c-generic.h +++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h @@ -30,4 +30,5 @@ uint32_t s3c_get_fclk(void); uint32_t s3c_get_hclk(void); uint32_t s3c_get_pclk(void); uint32_t s3c_get_uclk(void); -uint32_t s3c24x0_get_memory_size(void); +uint32_t s3c24xx_get_memory_size(void); +void s3c24xx_disable_second_sdram_bank(void); diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h index 7c45c53c64..4f713bed87 100644 --- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h +++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h @@ -19,9 +19,7 @@ */ /* S3C2410 device base addresses */ -#define S3C24X0_SDRAM_BASE 0x30000000 -#define S3C24X0_SDRAM_END 0x40000000 -#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C_MEMCTL_BASE 0x48000000 #define S3C2410_USB_HOST_BASE 0x49000000 #define S3C2410_INTERRUPT_BASE 0x4A000000 #define S3C2410_DMA_BASE 0x4B000000 @@ -40,6 +38,17 @@ #define S3C2410_SPI_BASE 0x59000000 #define S3C2410_SDI_BASE 0x5A000000 +/* external IO space */ +#define S3C_CS0_BASE 0x00000000 +#define S3C_CS1_BASE 0x08000000 +#define S3C_CS2_BASE 0x10000000 +#define S3C_CS3_BASE 0x18000000 +#define S3C_CS4_BASE 0x20000000 +#define S3C_CS5_BASE 0x28000000 +#define S3C_CS6_BASE 0x30000000 + +#define S3C_SDRAM_BASE S3C_CS6_BASE +#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000) /* * if we are booting from NAND, its internal SRAM occures at @@ -59,21 +68,6 @@ #define S3C_UART3_BASE (S3C_UART_BASE + 0x8000) #define S3C_UART3_SIZE 0x4000 -/* CS configuration (direct access) */ -#define BWSCON (S3C24X0_MEMCTL_BASE) -#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04) -#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08) -#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c) -#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10) -#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14) -#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18) -#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c) -#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20) -#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24) -#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28) -#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c) -#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30) - /* GPIO registers (direct access) */ #define GPACON (S3C24X0_GPIO_BASE) #define GPADAT (S3C24X0_GPIO_BASE + 0x04) @@ -133,12 +127,3 @@ # define DSC0 (S3C24X0_GPIO_BASE + 0xc4) # define DSC1 (S3C24X0_GPIO_BASE + 0xc8) #endif - -/* external IO space */ -#define CS0_BASE 0x00000000 -#define CS1_BASE 0x08000000 -#define CS2_BASE 0x10000000 -#define CS3_BASE 0x18000000 -#define CS4_BASE 0x20000000 -#define CS5_BASE 0x28000000 -#define CS6_BASE 0x30000000 diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-init.S index 93ea3ceb62..31c619609f 100644 --- a/arch/arm/mach-samsung/lowlevel-init.S +++ b/arch/arm/mach-samsung/lowlevel-init.S @@ -192,7 +192,7 @@ With m = MDIV + 8, p = PDIV + 2 and s = SDIV. s3c24x0_sdram_init: adr r0, SDRAMDATA /* get the current relative address of the table */ - mov r1, #S3C24X0_MEMCTL_BASE + mov r1, #S3C_MEMCTL_BASE mov r2, #6 /* we *know* it contains 6 entries */ ldr r3, [r0], #4 /* write BSWCON first */ @@ -255,7 +255,7 @@ s3c24x0_nand_boot: * In the case of NOR boot we are running from the same address space. * Detect this case to handle it correctly. */ - mov r1, #S3C24X0_MEMCTL_BASE + mov r1, #S3C_MEMCTL_BASE ldr r3, [r1] and r3, r3, #0x6 cmp r3, #0x0 /* check for NAND case */ diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c index beacc763b4..a99d1b9d18 100644 --- a/arch/arm/mach-samsung/s3c24xx-clocks.c +++ b/arch/arm/mach-samsung/s3c24xx-clocks.c @@ -21,6 +21,7 @@ #include <mach/s3c-iomap.h> #include <mach/s3c-generic.h> #include <mach/s3c-clocks.h> +#include <mach/s3c-busctl.h> /** * Calculate the current M-PLL clock. @@ -127,9 +128,11 @@ int s3c24xx_dump_clocks(void) printf("fclk: %7d kHz\n", s3c_get_fclk() / 1000); printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000); printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000); - printf("SDRAM1: CL%d@%dMHz\n", ((readl(BANKCON6) & 0xc) >> 2) + 2, s3c_get_hclk() / 1000000); - if ((readl(BANKCON7) & (0x3 << 15)) == (0x3 << 15)) - printf("SDRAM2: CL%d@%dMHz\n", ((readl(BANKCON7) & 0xc) >> 2) + 2, + printf("SDRAM1: CL%d@%dMHz\n", ((readl(S3C_BANKCON6) & 0xc) >> 2) + 2, + s3c_get_hclk() / 1000000); + if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15)) + printf("SDRAM2: CL%d@%dMHz\n", + ((readl(S3C_BANKCON7) & 0xc) >> 2) + 2, s3c_get_hclk() / 1000000); return 0; } |