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-rw-r--r--arch/arm/mach-stm32mp/include/mach/bbu.h14
-rw-r--r--arch/arm/mach-stm32mp/include/mach/bootsource.h33
-rw-r--r--arch/arm/mach-stm32mp/include/mach/bsec.h41
-rw-r--r--arch/arm/mach-stm32mp/include/mach/debug_ll.h28
-rw-r--r--arch/arm/mach-stm32mp/include/mach/revision.h32
-rw-r--r--arch/arm/mach-stm32mp/include/mach/smc.h28
-rw-r--r--arch/arm/mach-stm32mp/include/mach/stm32.h35
7 files changed, 0 insertions, 211 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/bbu.h b/arch/arm/mach-stm32mp/include/mach/bbu.h
deleted file mode 100644
index 8b9504400e..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/bbu.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef MACH_STM32MP_BBU_H_
-#define MACH_STM32MP_BBU_H_
-
-#include <bbu.h>
-
-static inline int stm32mp_bbu_mmc_register_handler(const char *name,
- const char *devicefile,
- unsigned long flags)
-{
- return bbu_register_std_file_update(name, flags, devicefile,
- filetype_stm32_image_v1);
-}
-
-#endif /* MACH_STM32MP_BBU_H_ */
diff --git a/arch/arm/mach-stm32mp/include/mach/bootsource.h b/arch/arm/mach-stm32mp/include/mach/bootsource.h
deleted file mode 100644
index 1b6f562ac3..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/bootsource.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef __MACH_STM32_BOOTSOURCE_H__
-#define __MACH_STM32_BOOTSOURCE_H__
-
-enum stm32mp_boot_device {
- STM32MP_BOOT_FLASH_SD = 0x10, /* .. 0x13 */
- STM32MP_BOOT_FLASH_EMMC = 0x20, /* .. 0x23 */
- STM32MP_BOOT_FLASH_NAND = 0x30,
- STM32MP_BOOT_FLASH_NAND_FMC = 0x31,
- STM32MP_BOOT_FLASH_NOR = 0x40,
- STM32MP_BOOT_FLASH_NOR_QSPI = 0x41,
- STM32MP_BOOT_SERIAL_UART = 0x50, /* .. 0x58 */
- STM32MP_BOOT_SERIAL_USB = 0x60,
- STM32MP_BOOT_SERIAL_USB_OTG = 0x62,
-};
-
-enum stm32mp_forced_boot_mode {
- STM32MP_BOOT_NORMAL = 0x00,
- STM32MP_BOOT_FASTBOOT = 0x01,
- STM32MP_BOOT_RECOVERY = 0x02,
- STM32MP_BOOT_STM32PROG = 0x03,
- STM32MP_BOOT_UMS_MMC0 = 0x10,
- STM32MP_BOOT_UMS_MMC1 = 0x11,
- STM32MP_BOOT_UMS_MMC2 = 0x12,
-};
-
-enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void);
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h
deleted file mode 100644
index 559faaa2ba..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/bsec.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef __MACH_STM32_BSEC_H__
-#define __MACH_STM32_BSEC_H__
-
-#include <mach/smc.h>
-
-/* Return status */
-enum bsec_smc {
- BSEC_SMC_OK = 0,
- BSEC_SMC_ERROR = -1,
- BSEC_SMC_DISTURBED = -2,
- BSEC_SMC_INVALID_PARAM = -3,
- BSEC_SMC_PROG_FAIL = -4,
- BSEC_SMC_LOCK_FAIL = -5,
- BSEC_SMC_WRITE_FAIL = -6,
- BSEC_SMC_SHADOW_FAIL = -7,
- BSEC_SMC_TIMEOUT = -8,
-};
-
-/* Service for BSEC */
-enum bsec_field {
- BSEC_SMC_READ_SHADOW = 1,
- BSEC_SMC_PROG_OTP = 2,
- BSEC_SMC_WRITE_SHADOW = 3,
- BSEC_SMC_READ_OTP = 4,
- BSEC_SMC_READ_ALL = 5,
- BSEC_SMC_WRITE_ALL = 6,
-};
-
-static inline enum bsec_smc bsec_read_field(enum bsec_field field, unsigned *val)
-{
- return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW,
- field, 0, val);
-}
-
-static inline enum bsec_smc bsec_write_field(enum bsec_field field, unsigned val)
-{
- return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW,
- field, val, NULL);
-}
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/debug_ll.h b/arch/arm/mach-stm32mp/include/mach/debug_ll.h
deleted file mode 100644
index 99fedb91fe..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/debug_ll.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __MACH_STM32MP1_DEBUG_LL_H
-#define __MACH_STM32MP1_DEBUG_LL_H
-
-#include <io.h>
-#include <mach/stm32.h>
-
-#define DEBUG_LL_UART_ADDR STM32_UART4_BASE
-
-#define CR1_OFFSET 0x00
-#define CR3_OFFSET 0x08
-#define BRR_OFFSET 0x0c
-#define ISR_OFFSET 0x1c
-#define ICR_OFFSET 0x20
-#define RDR_OFFSET 0x24
-#define TDR_OFFSET 0x28
-
-#define USART_ISR_TXE BIT(7)
-
-static inline void PUTC_LL(int c)
-{
- void __iomem *base = IOMEM(DEBUG_LL_UART_ADDR);
-
- writel(c, base + TDR_OFFSET);
-
- while ((readl(base + ISR_OFFSET) & USART_ISR_TXE) == 0);
-}
-
-#endif /* __MACH_STM32MP1_DEBUG_LL_H */
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
deleted file mode 100644
index 387201421d..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/revision.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef __MACH_CPUTYPE_H__
-#define __MACH_CPUTYPE_H__
-
-/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
-#define CPU_STM32MP157Cxx 0x05000000
-#define CPU_STM32MP157Axx 0x05000001
-#define CPU_STM32MP153Cxx 0x05000024
-#define CPU_STM32MP153Axx 0x05000025
-#define CPU_STM32MP151Cxx 0x0500002E
-#define CPU_STM32MP151Axx 0x0500002F
-
-/* silicon revisions */
-#define CPU_REV_A 0x1000
-#define CPU_REV_B 0x2000
-
-int stm32mp_silicon_revision(void);
-int stm32mp_cputype(void);
-int stm32mp_package(void);
-
-#define cpu_is_stm32mp157c() (stm32mp_cputype() == CPU_STM32MP157Cxx)
-#define cpu_is_stm32mp157a() (stm32mp_cputype() == CPU_STM32MP157Axx)
-#define cpu_is_stm32mp153c() (stm32mp_cputype() == CPU_STM32MP153Cxx)
-#define cpu_is_stm32mp153a() (stm32mp_cputype() == CPU_STM32MP153Axx)
-#define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx)
-#define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx)
-
-#endif /* __MACH_CPUTYPE_H__ */
diff --git a/arch/arm/mach-stm32mp/include/mach/smc.h b/arch/arm/mach-stm32mp/include/mach/smc.h
deleted file mode 100644
index 6b8e62bd53..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/smc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __MACH_STM32_SMC_H__
-#define __MACH_STM32_SMC_H__
-
-#include <linux/arm-smccc.h>
-
-/* Secure Service access from Non-secure */
-#define STM32_SMC_RCC 0x82001000
-#define STM32_SMC_PWR 0x82001001
-#define STM32_SMC_RTC 0x82001002
-#define STM32_SMC_BSEC 0x82001003
-
-/* Register access service use for RCC/RTC/PWR */
-#define STM32_SMC_REG_WRITE 0x1
-#define STM32_SMC_REG_SET 0x2
-#define STM32_SMC_REG_CLEAR 0x3
-
-static inline int stm32mp_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *val)
-{
- struct arm_smccc_res res;
-
- arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res);
- if (val)
- *val = res.a1;
-
- return (int)res.a0;
-}
-
-#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
deleted file mode 100644
index f9bdb788b9..0000000000
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- */
-
-#ifndef _MACH_STM32_H_
-#define _MACH_STM32_H_
-
-/*
- * Peripheral memory map
- */
-#define STM32_RCC_BASE 0x50000000
-#define STM32_PWR_BASE 0x50001000
-#define STM32_DBGMCU_BASE 0x50081000
-#define STM32_BSEC_BASE 0x5C005000
-#define STM32_TZC_BASE 0x5C006000
-#define STM32_ETZPC_BASE 0x5C007000
-#define STM32_TAMP_BASE 0x5C00A000
-
-#define STM32_USART1_BASE 0x5C000000
-#define STM32_USART2_BASE 0x4000E000
-#define STM32_USART3_BASE 0x4000F000
-#define STM32_UART4_BASE 0x40010000
-#define STM32_UART5_BASE 0x40011000
-#define STM32_USART6_BASE 0x44003000
-#define STM32_UART7_BASE 0x40018000
-#define STM32_UART8_BASE 0x40019000
-
-#define STM32_SYSRAM_BASE 0x2FFC0000
-#define STM32_SYSRAM_SIZE SZ_256K
-
-#define STM32_DDR_BASE 0xC0000000
-#define STM32_DDR_SIZE SZ_1G
-
-#endif /* _MACH_STM32_H_ */