diff options
Diffstat (limited to 'arch/arm/mach-stm32mp/init.c')
-rw-r--r-- | arch/arm/mach-stm32mp/init.c | 233 |
1 files changed, 119 insertions, 114 deletions
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c index 7bad989a60..2eb8b6beec 100644 --- a/arch/arm/mach-stm32mp/init.c +++ b/arch/arm/mach-stm32mp/init.c @@ -8,31 +8,12 @@ #include <common.h> #include <init.h> -#include <mach/stm32.h> -#include <mach/bsec.h> -#include <mach/revision.h> -#include <mach/bootsource.h> +#include <mach/stm32mp/stm32.h> +#include <mach/stm32mp/bsec.h> +#include <mach/stm32mp/revision.h> +#include <mach/stm32mp/bootsource.h> #include <bootsource.h> - -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* BSEC OTP index */ -#define BSEC_OTP_RPN 1 -#define BSEC_OTP_PKG 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) +#include <dt-bindings/pinctrl/stm32-pinfunc.h> /* Package = bit 27:29 of OTP16 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm @@ -61,12 +42,9 @@ /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) -/* secure access */ -#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) -#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) /* non secure access */ -#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) -#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) +#define STM32MP13_TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) +#define STM32MP15_TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 @@ -75,16 +53,12 @@ #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) #define TAMP_BOOT_DEBUG_ON BIT(16) +#define FIXUP_CPU_MASK(num, mhz) (((num) << 16) | (mhz)) +#define FIXUP_CPU_NUM(mask) ((mask) >> 16) +#define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL) -static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode; -enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void) -{ - return __stm32mp_forced_boot_mode; -} - -static void setup_boot_mode(void) +static void setup_boot_mode(u32 boot_ctx) { - u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); u32 boot_mode = (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; @@ -117,143 +91,174 @@ static void setup_boot_mode(void) break; } - __stm32mp_forced_boot_mode = boot_ctx & TAMP_BOOT_FORCED_MASK; + pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d\n", + boot_ctx, boot_mode, instance); - pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d forced=0x%x\n", - boot_ctx, boot_mode, instance, __stm32mp_forced_boot_mode); - - bootsource_set(src); - bootsource_set_instance(instance); - - /* clear TAMP for next reboot */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, - STM32MP_BOOT_NORMAL); + bootsource_set_raw(src, instance); } -static int __stm32mp_cputype; -int stm32mp_cputype(void) +static int get_cpu_package(u32 *pkg) { - return __stm32mp_cputype; -} + int ret = bsec_read_field(BSEC_OTP_PKG, pkg); + if (ret) + return ret; -static int __stm32mp_silicon_revision; -int stm32mp_silicon_revision(void) -{ - return __stm32mp_silicon_revision; + *pkg = (*pkg >> PKG_SHIFT) & PKG_MASK; + return 0; } -static int __stm32mp_package; -int stm32mp_package(void) +static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx) { - return __stm32mp_package; -} + unsigned long ctx = (unsigned long)_ctx; + struct device_node *cpus_node, *np, *tmp; -static inline u32 read_idc(void) -{ - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - return readl(IOMEM(DBGMCU_IDC)); -} + cpus_node = of_find_node_by_name_address(root, "cpus"); + if (!cpus_node) + return 0; -/* Get Device Part Number (RPN) from OTP */ -static u32 get_cpu_rpn(u32 *rpn) -{ - int ret = bsec_read_field(BSEC_OTP_RPN, rpn); - if (ret) - return ret; + for_each_child_of_node_safe(cpus_node, tmp, np) { + u32 cpu_index; - *rpn = (*rpn >> RPN_SHIFT) & RPN_MASK; - return 0; -} + if (of_property_read_u32(np, "reg", &cpu_index)) + continue; -static u32 get_cpu_revision(void) -{ - return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; + if (cpu_index >= FIXUP_CPU_NUM(ctx)) { + of_delete_node(np); + continue; + } + + of_property_write_u32(np, "clock-frequency", FIXUP_CPU_HZ(ctx)); + } + + return 0; } -static u32 get_cpu_type(u32 *type) +static int fixup_pinctrl(struct device_node *root, const char *compat, u32 pkg) { - u32 id; - int ret = get_cpu_rpn(type); - if (ret) - return ret; + struct device_node *np = of_find_compatible_node(root, NULL, compat); + if (!np) + return -ENODEV; - id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; - *type |= id << 16; - return 0; + return of_property_write_u32(np, "st,package", pkg); } -static int get_cpu_package(u32 *pkg) +static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg) { - int ret = bsec_read_field(BSEC_OTP_PKG, pkg); + unsigned long pkg = (unsigned long)_pkg; + int ret; + + ret = fixup_pinctrl(root, "st,stm32mp157-pinctrl", pkg); if (ret) return ret; - *pkg = (*pkg >> PKG_SHIFT) & PKG_MASK; - return 0; + return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg); } -static int setup_cpu_type(void) +static int stm32mp15_setup_cpu_type(void) { - const char *cputypestr; - const char *cpupkgstr; + unsigned long cpufixupctx = 0, pkgfixupctx = 0; + int cputype, package; - get_cpu_type(&__stm32mp_cputype); - switch (__stm32mp_cputype) { + __stm32mp15_get_cpu_type(&cputype); + switch (cputype) { + case CPU_STM32MP157Fxx: + cpufixupctx = FIXUP_CPU_MASK(2, 800); + break; + case CPU_STM32MP157Dxx: + cpufixupctx = FIXUP_CPU_MASK(2, 800); + break; case CPU_STM32MP157Cxx: - cputypestr = "157C"; + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP157Axx: - cputypestr = "157A"; + cpufixupctx = FIXUP_CPU_MASK(2, 650); + break; + case CPU_STM32MP153Fxx: + cpufixupctx = FIXUP_CPU_MASK(2, 800); + break; + case CPU_STM32MP153Dxx: + cpufixupctx = FIXUP_CPU_MASK(2, 800); break; case CPU_STM32MP153Cxx: - cputypestr = "153C"; + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP153Axx: - cputypestr = "153A"; + cpufixupctx = FIXUP_CPU_MASK(2, 650); break; case CPU_STM32MP151Cxx: - cputypestr = "151C"; + cpufixupctx = FIXUP_CPU_MASK(1, 650); break; case CPU_STM32MP151Axx: - cputypestr = "151A"; + cpufixupctx = FIXUP_CPU_MASK(1, 650); + break; + case CPU_STM32MP151Fxx: + cpufixupctx = FIXUP_CPU_MASK(1, 800); + break; + case CPU_STM32MP151Dxx: + cpufixupctx = FIXUP_CPU_MASK(1, 800); break; default: - cputypestr = "????"; break; } - get_cpu_package(&__stm32mp_package ); - switch (__stm32mp_package) { + get_cpu_package(&package); + switch (package) { case PKG_AA_LBGA448: - cpupkgstr = "AA"; + pkgfixupctx = STM32MP_PKG_AA; break; case PKG_AB_LBGA354: - cpupkgstr = "AB"; + pkgfixupctx = STM32MP_PKG_AB; break; case PKG_AC_TFBGA361: - cpupkgstr = "AC"; + pkgfixupctx = STM32MP_PKG_AC; break; case PKG_AD_TFBGA257: - cpupkgstr = "AD"; + pkgfixupctx = STM32MP_PKG_AD; break; default: - cpupkgstr = "??"; break; } - __stm32mp_silicon_revision = get_cpu_revision(); + pr_debug("cputype = 0x%x, package = 0x%x\n", cputype, package); + + if (cpufixupctx) + of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx); + if (pkgfixupctx) + of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx); - pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n", - __stm32mp_cputype, __stm32mp_package, __stm32mp_silicon_revision); - pr_info("detected STM32MP%s%s Rev.%c\n", cputypestr, cpupkgstr, - (__stm32mp_silicon_revision >> 12) + 'A' - 1); return 0; } +static int __st32mp_soc; + +int stm32mp_soc(void) +{ + return __st32mp_soc; +} + static int stm32mp_init(void) { - setup_cpu_type(); - setup_boot_mode(); + u32 boot_ctx; + + if (of_machine_is_compatible("st,stm32mp135")) + __st32mp_soc = 32135; + else if (of_machine_is_compatible("st,stm32mp151")) + __st32mp_soc = 32151; + else if (of_machine_is_compatible("st,stm32mp153")) + __st32mp_soc = 32153; + else if (of_machine_is_compatible("st,stm32mp157")) + __st32mp_soc = 32157; + else + return 0; + + if (__st32mp_soc == 32135) { + boot_ctx = readl(STM32MP13_TAMP_BOOT_CONTEXT); + } else { + stm32mp15_setup_cpu_type(); + boot_ctx = readl(STM32MP15_TAMP_BOOT_CONTEXT); + } + + setup_boot_mode(boot_ctx); return 0; } |