diff options
Diffstat (limited to 'arch/arm')
129 files changed, 931 insertions, 532 deletions
diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c index 2069ab3764..14b33dc691 100644 --- a/arch/arm/boards/animeo_ip/init.c +++ b/arch/arm/boards/animeo_ip/init.c @@ -8,7 +8,6 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <fec.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <partition.h> diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c index 6f82f5ee26..52f7e86fbe 100644 --- a/arch/arm/boards/archosg9/board.c +++ b/arch/arm/boards/archosg9/board.c @@ -13,7 +13,6 @@ #include <common.h> #include <clock.h> #include <init.h> -#include <ns16550.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <mach/omap4-silicon.h> diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c index 6cb170192a..b9e4914376 100644 --- a/arch/arm/boards/at91sam9261ek/init.c +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -34,7 +34,7 @@ #include <mach/io.h> #include <mach/iomux.h> #include <mach/at91sam9_smc.h> -#include <dm9000.h> +#include <platform_data/eth-dm9000.h> #include <gpio_keys.h> #include <readkey.h> #include <led.h> diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c index 26d08ae659..2ed58c1995 100644 --- a/arch/arm/boards/at91sam9n12ek/init.c +++ b/arch/arm/boards/at91sam9n12ek/init.c @@ -18,7 +18,6 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <fec.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <partition.h> diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c index e0c11a11e1..1ef35803f7 100644 --- a/arch/arm/boards/at91sam9x5ek/init.c +++ b/arch/arm/boards/at91sam9x5ek/init.c @@ -18,7 +18,6 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <fec.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <partition.h> diff --git a/arch/arm/boards/beagle/board.c b/arch/arm/boards/beagle/board.c index 4ac9517dbe..460f42ac2d 100644 --- a/arch/arm/boards/beagle/board.c +++ b/arch/arm/boards/beagle/board.c @@ -23,7 +23,6 @@ #include <io.h> #include <bbu.h> #include <filetype.h> -#include <ns16550.h> #include <envfs.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 40cf76dc5a..71a51e1927 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -20,7 +20,7 @@ #include <init.h> #include <environment.h> #include <mach/imx51-regs.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <partition.h> diff --git a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c index 6e83570c55..947db7cff6 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c +++ b/arch/arm/boards/crystalfontz-cfa10036/cfa10036.c @@ -19,7 +19,6 @@ #include <environment.h> #include <envfs.h> #include <errno.h> -#include <fec.h> #include <gpio.h> #include <init.h> #include <mci.h> diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c index 96c7fbe4bf..043a93461b 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/board.c +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -26,7 +26,6 @@ #include <linux/sizes.h> #include <init.h> #include <gpio.h> -#include <fec.h> #include <of.h> #include <linux/micrel_phy.h> diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c index feca909c27..321c383ffc 100644 --- a/arch/arm/boards/dss11/init.c +++ b/arch/arm/boards/dss11/init.c @@ -17,7 +17,6 @@ #include <mci.h> #include <init.h> #include <environment.h> -#include <fec.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <partition.h> diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c index 0fb93d23dc..99c69548bd 100644 --- a/arch/arm/boards/edb93xx/edb93xx.c +++ b/arch/arm/boards/edb93xx/edb93xx.c @@ -27,7 +27,7 @@ #include <malloc.h> #include <generated/mach-types.h> #include <mach/ep93xx-regs.h> -#include <net/ep93xx_eth.h> +#include <platform_data/eth-ep93xx.h> #include "edb93xx.h" #define DEVCFG_U1EN (1 << 18) @@ -123,7 +123,7 @@ static int edb93xx_console_init(void) else shortname = "unknown"; - board = asprintf("Cirrus Logic %s", shortname); + board = basprintf("Cirrus Logic %s", shortname); barebox_set_model(board); free(board); barebox_set_hostname(shortname); diff --git a/arch/arm/boards/embedsky-e9/board.c b/arch/arm/boards/embedsky-e9/board.c index 23bfec1b77..0f47677bb0 100644 --- a/arch/arm/boards/embedsky-e9/board.c +++ b/arch/arm/boards/embedsky-e9/board.c @@ -22,7 +22,6 @@ #include <init.h> #include <environment.h> #include <mach/imx6-regs.h> -#include <fec.h> #include <gpio.h> #include <asm/armlinux.h> #include <generated/mach-types.h> @@ -70,8 +69,8 @@ static int e9_devices_init(void) armlinux_set_architecture(3980); - environment_path = asprintf("/chosen/environment-mmc%d", - bootsource_get_instance()); + environment_path = basprintf("/chosen/environment-mmc%d", + bootsource_get_instance()); ret = of_device_enable_path(environment_path); diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c index 22bf7409a2..90451911e4 100644 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -36,7 +36,7 @@ #include <mach/imx-nand.h> #include <mach/imxfb.h> #include <mach/iim.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <nand.h> #include <mach/iomux-mx25.h> #include <i2c/i2c.h> diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index 31422e64a0..f27dcd6f44 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2009 Eric Benard, Eukrea Electromatique * Based on pcm038.c which is : - * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,7 +22,6 @@ #include <init.h> #include <environment.h> #include <mach/imx27-regs.h> -#include <fec.h> #include <notifier.h> #include <gpio.h> #include <asm/armlinux.h> @@ -39,7 +38,7 @@ #include <mach/imx-pll.h> #include <mach/weim.h> #include <mach/imxfb.h> -#include <ns16550.h> +#include <platform_data/serial-ns16550.h> #include <asm/mmu.h> #include <i2c/i2c.h> #include <mfd/lp3972.h> diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 7b3993d506..9c4ea13d8e 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -27,7 +27,7 @@ #include <environment.h> #include <errno.h> #include <fcntl.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <fs.h> #include <init.h> #include <nand.h> diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c index 75f325001b..fc57f6c157 100644 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c @@ -20,7 +20,7 @@ #include <init.h> #include <environment.h> #include <mach/imx51-regs.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <gpio.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c index 5f0e7bda63..8afe9ace51 100644 --- a/arch/arm/boards/freescale-mx21-ads/imx21ads.c +++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.c @@ -1,8 +1,8 @@ /* * Copyright (C) 2009 Ivo Clarysse - * + * * Based on imx27ads.c, - * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c index 6348692cb1..dd8048851b 100644 --- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c +++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c @@ -139,7 +139,7 @@ static int mx23_evk_console_init(void) add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192, IORESOURCE_MEM, NULL); - + return 0; } diff --git a/arch/arm/boards/freescale-mx25-3ds/3stack.c b/arch/arm/boards/freescale-mx25-3ds/3stack.c index 6d0e38205a..36ad591cc0 100644 --- a/arch/arm/boards/freescale-mx25-3ds/3stack.c +++ b/arch/arm/boards/freescale-mx25-3ds/3stack.c @@ -30,7 +30,7 @@ #include <partition.h> #include <generated/mach-types.h> #include <mach/imx-nand.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <nand.h> #include <mach/iomux-mx25.h> #include <mach/generic.h> diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.c b/arch/arm/boards/freescale-mx27-ads/imx27ads.c index 9fb1760602..9818a55137 100644 --- a/arch/arm/boards/freescale-mx27-ads/imx27ads.c +++ b/arch/arm/boards/freescale-mx27-ads/imx27ads.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,7 +21,7 @@ #include <mach/imx27-regs.h> #include <asm/armlinux.h> #include <io.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <gpio.h> #include <mach/weim.h> #include <partition.h> diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c index fc1237588f..9e5d612bda 100644 --- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c @@ -17,7 +17,7 @@ #include <common.h> #include <environment.h> #include <errno.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <gpio.h> #include <init.h> #include <mci.h> diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.c b/arch/arm/boards/freescale-mx35-3ds/3stack.c index cca0fe49eb..caeb3f75e8 100644 --- a/arch/arm/boards/freescale-mx35-3ds/3stack.c +++ b/arch/arm/boards/freescale-mx35-3ds/3stack.c @@ -25,7 +25,7 @@ #include <environment.h> #include <errno.h> #include <fcntl.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <fs.h> #include <init.h> #include <nand.h> diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c index c4acb8ee16..915748528d 100644 --- a/arch/arm/boards/freescale-mx51-babbage/board.c +++ b/arch/arm/boards/freescale-mx51-babbage/board.c @@ -20,7 +20,6 @@ #include <init.h> #include <environment.h> #include <mach/imx51-regs.h> -#include <fec.h> #include <gpio.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c index 196d20a45d..354702dea1 100644 --- a/arch/arm/boards/freescale-mx53-smd/board.c +++ b/arch/arm/boards/freescale-mx53-smd/board.c @@ -17,7 +17,7 @@ #include <common.h> #include <environment.h> #include <fcntl.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <fs.h> #include <init.h> #include <nand.h> diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index d40f99bb93..63fa58886c 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -18,7 +18,6 @@ #include <init.h> #include <environment.h> #include <mach/imx6-regs.h> -#include <fec.h> #include <gpio.h> #include <mach/bbu.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/freescale-mx6-sabresd/board.c b/arch/arm/boards/freescale-mx6-sabresd/board.c index 734adde070..595b1eae0b 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/board.c +++ b/arch/arm/boards/freescale-mx6-sabresd/board.c @@ -19,7 +19,6 @@ #include <init.h> #include <environment.h> #include <mach/imx6-regs.h> -#include <fec.h> #include <gpio.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/friendlyarm-mini2440/mini2440.c b/arch/arm/boards/friendlyarm-mini2440/mini2440.c index b59c8367f3..7f59cb99b2 100644 --- a/arch/arm/boards/friendlyarm-mini2440/mini2440.c +++ b/arch/arm/boards/friendlyarm-mini2440/mini2440.c @@ -21,7 +21,7 @@ #include <init.h> #include <generated/mach-types.h> #include <partition.h> -#include <dm9000.h> +#include <platform_data/eth-dm9000.h> #include <nand.h> #include <mci.h> #include <fb.h> diff --git a/arch/arm/boards/friendlyarm-mini6410/mini6410.c b/arch/arm/boards/friendlyarm-mini6410/mini6410.c index a372db5471..a85b1bd920 100644 --- a/arch/arm/boards/friendlyarm-mini6410/mini6410.c +++ b/arch/arm/boards/friendlyarm-mini6410/mini6410.c @@ -14,7 +14,7 @@ #include <common.h> #include <driver.h> #include <init.h> -#include <dm9000.h> +#include <platform_data/eth-dm9000.h> #include <gpio.h> #include <generated/mach-types.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/friendlyarm-tiny210/tiny210.c b/arch/arm/boards/friendlyarm-tiny210/tiny210.c index d84b3128ad..b40dc98c5b 100644 --- a/arch/arm/boards/friendlyarm-tiny210/tiny210.c +++ b/arch/arm/boards/friendlyarm-tiny210/tiny210.c @@ -29,7 +29,6 @@ #include <init.h> #include <linux/sizes.h> #include <generated/mach-types.h> -#include <dm9000.h> #include <gpio.h> #include <led.h> #include <io.h> diff --git a/arch/arm/boards/friendlyarm-tiny6410/development-board.c b/arch/arm/boards/friendlyarm-tiny6410/development-board.c index 773a423ea0..5dd05e4cc8 100644 --- a/arch/arm/boards/friendlyarm-tiny6410/development-board.c +++ b/arch/arm/boards/friendlyarm-tiny6410/development-board.c @@ -23,7 +23,7 @@ #include <driver.h> #include <init.h> #include <gpio.h> -#include <dm9000.h> +#include <platform_data/eth-dm9000.h> #include <mach/devices-s3c64xx.h> #include <mach/s3c-generic.h> #include <mach/iomux.h> diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c index 90f16272fd..6ec74eb49b 100644 --- a/arch/arm/boards/guf-cupid/board.c +++ b/arch/arm/boards/guf-cupid/board.c @@ -33,7 +33,7 @@ #include <nand.h> #include <generated/mach-types.h> #include <mach/imx-nand.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <fb.h> #include <asm/mmu.h> #include <mach/weim.h> diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index f40f0d1591..176d77e7b3 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -18,7 +18,7 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <notifier.h> #include <partition.h> #include <gpio.h> diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c index ad47ee2558..43c195254e 100644 --- a/arch/arm/boards/guf-vincell/board.c +++ b/arch/arm/boards/guf-vincell/board.c @@ -40,7 +40,8 @@ static void vincell_fec_reset(void) static int vincell_devices_init(void) { - if (!of_machine_is_compatible("guf,imx53-vincell")) + if (!of_machine_is_compatible("guf,imx53-vincell") && + !of_machine_is_compatible("guf,imx53-vincell-lt")) return 0; writel(0, MX53_M4IF_BASE_ADDR + 0xc); diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index d67607b717..ec0826297b 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -18,7 +18,7 @@ #include <environment.h> #include <errno.h> #include <mci.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <linux/sizes.h> #include <io.h> #include <net.h> diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c index f5ebe46a2b..913df68cc9 100644 --- a/arch/arm/boards/karo-tx51/tx51.c +++ b/arch/arm/boards/karo-tx51/tx51.c @@ -19,7 +19,7 @@ #include <init.h> #include <environment.h> #include <mach/imx51-regs.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <gpio.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c index 9e65a839ad..99aa9e74f5 100644 --- a/arch/arm/boards/karo-tx53/board.c +++ b/arch/arm/boards/karo-tx53/board.c @@ -16,7 +16,7 @@ #include <bootsource.h> #include <environment.h> #include <fcntl.h> -#include <fec.h> +#include <platform_data/eth-fec.h> #include <fs.h> #include <init.h> #include <nand.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg new file mode 100644 index 0000000000..455aab92ca --- /dev/null +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -0,0 +1,183 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +wm 32 0x020e00a4 0x00000016 +wm 32 0x020e00c4 0x00000011 +wm 32 0x020e03b8 0x0000f079 +wm 32 0x020e03d8 0x0000f079 +wm 32 0x020e0898 0x00000000 +wm 32 0x020e089c 0x00000000 +wm 32 0x020e0248 0x00000012 +wm 32 0x020e02c8 0x00000015 +wm 32 0x020e06b0 0x000030b0 +wm 32 0x020e00a0 0x00000015 +wm 32 0x020e03b4 0x000030b0 +wm 32 0x020e024c 0x00000005 +wm 32 0x020e061c 0x000030b0 +wm 32 0x020c402c 0x006336c1 +wm 32 0x020c4034 0x00012093 +wm 32 0x020c4038 0x00012090 +wm 32 0x020c80e0 0x00002001 +set_bits 32 0x020c4068 0x00000030 +set_bits 32 0x020c406c 0x00000c00 +set_bits 32 0x020c4070 0x000000c0 +set_bits 32 0x020c4078 0xff000000 +set_bits 32 0x020c407c 0x0f000000 +set_bits 32 0x020c4080 0x000003fc +wm 32 0x020c80a0 0x00082029 +wm 32 0x020c80b0 0x0007a120 +wm 32 0x020c80c0 0x000f4240 +wm 32 0x020e0004 0x48640005 +wm 32 0x020e0010 0xf00000cf +wm 32 0x020e0018 0x77177717 +wm 32 0x020e001c 0x77177717 +wm 32 0x020e02a8 0x00000001 +wm 32 0x020e02ac 0x00000001 +wm 32 0x020e0920 0x00000003 +wm 32 0x020e02c0 0x00000001 +wm 32 0x020e02c4 0x00000001 +wm 32 0x020e091c 0x00000003 +wm 32 0x020e02ec 0x00000000 +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 +wm 32 0x020e052c 0x00020200 +wm 32 0x020e0530 0x00020200 +wm 32 0x020e0534 0x00020200 +wm 32 0x020e0538 0x00020200 +wm 32 0x020e053c 0x00020200 +wm 32 0x020e0540 0x00020200 +wm 32 0x020e0544 0x00020200 +wm 32 0x020e0548 0x00020200 +wm 32 0x020e054c 0x00020200 +wm 32 0x020e0550 0x00020200 +wm 32 0x020e0554 0x00020200 +wm 32 0x020e0558 0x00020200 +wm 32 0x020e055c 0x00020200 +wm 32 0x020e0560 0x00020200 +wm 32 0x020e0564 0x00020200 +wm 32 0x020e0568 0x00020200 +wm 32 0x020e056c 0x00020030 +wm 32 0x020e0578 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e0594 0x00020030 +wm 32 0x020e057c 0x00020030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e0580 0x00000000 +wm 32 0x020e0584 0x00000000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0798 0x000c0000 +wm 32 0x020e0768 0x00002000 +wm 32 0x020e0770 0x00000000 +wm 32 0x020e0754 0x00000200 +wm 32 0x020e075c 0x00000200 +wm 32 0x020e0760 0x00000200 +wm 32 0x020e0764 0x00000200 +wm 32 0x020e076c 0x00000200 +wm 32 0x020e0778 0x00000200 +wm 32 0x020e077c 0x00000200 +wm 32 0x020e0780 0x00000200 +wm 32 0x021b001c 0x04008010 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0800 0xa1390001 +wm 32 0x021b080c 0x001e001e +wm 32 0x021b0810 0x001e001e +wm 32 0x021b480c 0x001e001e +wm 32 0x021b4810 0x001e001e +wm 32 0x021b083c 0x43430349 +wm 32 0x021b0840 0x03330334 +wm 32 0x021b483c 0x434b0351 +wm 32 0x021b4840 0x033d030e +wm 32 0x021b0848 0x40404040 +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4848 0x40404040 +wm 32 0x021b4850 0x40404040 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0018 0x00000742 +check 32 while_all_bits_clear 0x021b0018 0x00000002 +wm 32 0x021b001c 0x00008000 +check 32 while_any_bit_clear 0x021b001c 0x00004000 +wm 32 0x021b0000 0x841a0000 +check 32 while_any_bit_clear 0x021b0018 0x40000000 +wm 32 0x021b000c 0x898f78f4 +wm 32 0x021b0010 0xff328e64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x008f1023 +wm 32 0x021b0008 0x24444040 +wm 32 0x021b0004 0x00020076 +wm 32 0x021b0040 0x00000047 +wm 32 0x021b001c 0x09308030 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00488032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b0020 0x0000c000 +wm 32 0x021b001c 0x00008020 +wm 32 0x021b0818 0x00022222 +wm 32 0x021b4818 0x00022222 +wm 32 0x021b0890 0x00000003 +set_bits 32 0x021b0400 0x02000000 +wm 32 0x021b0404 0x00000001 +wm 32 0x021b001c 0x04008010 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0800 0xa1390001 +check 32 while_all_bits_clear 0x021b0800 0x00010000 +wm 32 0x021b0800 0xa1380000 +wm 32 0x021b001c 0x00048033 +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +wm 32 0x021b001c 0x04008050 +wm 32 0x021b0860 0x00000030 +wm 32 0x021b4860 0x00000030 +check 32 while_all_bits_clear 0x021b0860 0x0000001f +check 32 while_all_bits_clear 0x021b4860 0x0000001f +wm 32 0x021b001c 0x04008050 +wm 32 0x021b0864 0x00000030 +check 32 while_all_bits_clear 0x021b0864 0x0000001f +wm 32 0x021b001c 0x04008050 +wm 32 0x021b4864 0x00000030 +check 32 while_all_bits_clear 0x021b4864 0x0000001f +wm 32 0x021b001c 0x00008033 +wm 32 0x021b0800 0xa138002b +wm 32 0x021b0020 0x00001800 +wm 32 0x021b0404 0x00001000 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b001c 0x00000000 +check 32 while_all_bits_clear 0x021b001c 0x00004000 diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c index 1aa24c5842..459c44b845 100644 --- a/arch/arm/boards/karo-tx6x/lowlevel.c +++ b/arch/arm/boards/karo-tx6x/lowlevel.c @@ -77,3 +77,23 @@ ENTRY_FUNCTION(start_imx6q_tx6x_1g, r0, r1, r2) imx6q_barebox_entry(fdt); } + +BAREBOX_IMD_TAG_STRING(tx6x_mx6_memsize_2G, IMD_TYPE_PARAMETER, "memsize=2048", 0); + +ENTRY_FUNCTION(start_imx6q_tx6x_2g, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + IMD_USED(tx6x_mx6_memsize_2G); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = __dtb_imx6q_tx6q_start - get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c index 6f517d8926..c2a0db7bd8 100644 --- a/arch/arm/boards/lubbock/board.c +++ b/arch/arm/boards/lubbock/board.c @@ -33,7 +33,7 @@ #include <mach/udc_pxa2xx.h> #include <mach/mci_pxa2xx.h> -#include <net/smc91111.h> +#include <platform_data/eth-smc91111.h> #include <asm/armlinux.h> #include <asm/io.h> #include <asm/mmu.h> diff --git a/arch/arm/boards/mainstone/board.c b/arch/arm/boards/mainstone/board.c index c339bb9315..0e48e79967 100644 --- a/arch/arm/boards/mainstone/board.c +++ b/arch/arm/boards/mainstone/board.c @@ -33,7 +33,7 @@ #include <mach/udc_pxa2xx.h> #include <mach/mci_pxa2xx.h> -#include <net/smc91111.h> +#include <platform_data/eth-smc91111.h> #include <asm/armlinux.h> #include <asm/io.h> #include <asm/mmu.h> diff --git a/arch/arm/boards/mmccpu/init.c b/arch/arm/boards/mmccpu/init.c index 8979b818b0..747c4b2742 100644 --- a/arch/arm/boards/mmccpu/init.c +++ b/arch/arm/boards/mmccpu/init.c @@ -18,7 +18,6 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <fec.h> #include <gpio.h> #include <asm/armlinux.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c index 1b1cb79212..2fd0dee194 100644 --- a/arch/arm/boards/omap343xdsp/board.c +++ b/arch/arm/boards/omap343xdsp/board.c @@ -20,7 +20,6 @@ #include <init.h> #include <driver.h> #include <io.h> -#include <ns16550.h> #include <asm/armlinux.h> #include <mach/omap3-silicon.h> #include <mach/omap3-devices.h> diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c index 0fe69b61a7..eefb540fc1 100644 --- a/arch/arm/boards/omap3evm/board.c +++ b/arch/arm/boards/omap3evm/board.c @@ -44,7 +44,6 @@ #include <driver.h> #include <io.h> #include <linux/sizes.h> -#include <ns16550.h> #include <asm/armlinux.h> #include <mach/omap3-silicon.h> #include <mach/omap3-mux.h> diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c index f7a3a0fa28..acba689623 100644 --- a/arch/arm/boards/panda/board.c +++ b/arch/arm/boards/panda/board.c @@ -4,7 +4,6 @@ #include <driver.h> #include <io.h> #include <gpio.h> -#include <ns16550.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <mach/omap4-silicon.h> diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c index 0481113c65..b0fee46d3b 100644 --- a/arch/arm/boards/phytec-phycard-imx27/pca100.c +++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,7 +19,6 @@ #include <init.h> #include <environment.h> #include <mach/imx27-regs.h> -#include <fec.h> #include <gpio.h> #include <linux/sizes.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c index 1c2e7f7429..930f3b9c7c 100644 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c @@ -44,7 +44,6 @@ #include <errno.h> #include <init.h> #include <nand.h> -#include <ns16550.h> #include <partition.h> #include <linux/sizes.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c index 78890ba5a9..c0e4448a00 100644 --- a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c +++ b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c @@ -20,7 +20,6 @@ #include <driver.h> #include <io.h> #include <gpio.h> -#include <ns16550.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <mach/omap4-silicon.h> diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.c b/arch/arm/boards/phytec-phycore-imx27/pcm038.c index 01f6a55ad0..f1f808116c 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pcm038.c +++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm970.c b/arch/arm/boards/phytec-phycore-imx27/pcm970.c index 73df2ad2a8..13bb7c1cf5 100644 --- a/arch/arm/boards/phytec-phycore-imx27/pcm970.c +++ b/arch/arm/boards/phytec-phycore-imx27/pcm970.c @@ -15,7 +15,7 @@ #include <gpio.h> #include <init.h> #include <io.h> -#include <platform_ide.h> +#include <platform_data/ide.h> #include <linux/sizes.h> #include <mach/imx27-regs.h> #include <mach/iomux-mx27.h> diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.c b/arch/arm/boards/phytec-phycore-imx31/pcm037.c index a1ffb2e73e..39e7838be0 100644 --- a/arch/arm/boards/phytec-phycore-imx31/pcm037.c +++ b/arch/arm/boards/phytec-phycore-imx31/pcm037.c @@ -31,7 +31,7 @@ #include <asm/sections.h> #include <mach/weim.h> #include <io.h> -#include <smc911x.h> +#include <platform_data/eth-smc911x.h> #include <asm/mmu.h> #include <partition.h> #include <generated/mach-types.h> diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.c b/arch/arm/boards/phytec-phycore-imx35/pcm043.c index e31c79d15f..b83698b90a 100644 --- a/arch/arm/boards/phytec-phycore-imx35/pcm043.c +++ b/arch/arm/boards/phytec-phycore-imx35/pcm043.c @@ -34,7 +34,6 @@ #include <nand.h> #include <generated/mach-types.h> #include <mach/imx-nand.h> -#include <fec.h> #include <fb.h> #include <led.h> #include <bootsource.h> diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c index 6495a6f6ab..807cdd677d 100644 --- a/arch/arm/boards/phytec-phycore-omap4460/board.c +++ b/arch/arm/boards/phytec-phycore-omap4460/board.c @@ -20,7 +20,6 @@ #include <driver.h> #include <gpio.h> #include <io.h> -#include <ns16550.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <mach/omap4-silicon.h> diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c index 73e75eb491..33e83c5a8e 100644 --- a/arch/arm/boards/phytec-som-am335x/lowlevel.c +++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c @@ -125,6 +125,7 @@ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_1024mb, am335x_phytec_phycore_som_mlo, PHYCORE_IM8G16D3FBBG15EI_1024MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K256M16TW107IT_512MB); PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K128M16JT_256MB); +PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_1024mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K512M16HA125IT_1024MB); PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som); PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi); PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_eeprom_sdram, am335x_phytec_phycore_som_no_eeprom); diff --git a/arch/arm/boards/phytec-som-am335x/ram-timings.h b/arch/arm/boards/phytec-som-am335x/ram-timings.h index 884874caf7..9576d265e5 100644 --- a/arch/arm/boards/phytec-som-am335x/ram-timings.h +++ b/arch/arm/boards/phytec-som-am335x/ram-timings.h @@ -32,6 +32,7 @@ enum { PHYCORE_IM8G16D3FBBG15EI_1024MB, PHYCORE_R2_MT41K256M16TW107IT_512MB, PHYCORE_R2_MT41K128M16JT_256MB, + PHYCORE_R2_MT41K512M16HA125IT_1024MB, PHYCARD_NT5CB128M16BP_256MB, }; @@ -232,6 +233,25 @@ struct am335x_sdram_timings physom_timings[] = { .wr_slave_ratio0 = 0x73, }, }, + + /* 1024MB R2 */ + [PHYCORE_R2_MT41K512M16HA125IT_1024MB] = { + .regs = { + .emif_read_latency = 0x7, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x268F7FDA, + .emif_tim3 = 0x501F88BF, + .sdram_config = 0x61C053B2, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x00000C30, + }, + .data = { + .rd_slave_ratio0 = 0x38, + .wr_dqs_slave_ratio0 = 0x4d, + .fifo_we_slave_ratio0 = 0x9d, + .wr_slave_ratio0 = 0x82, + }, + }, }; #endif diff --git a/arch/arm/boards/phytec-som-imx6/Makefile b/arch/arm/boards/phytec-som-imx6/Makefile index c61e9cddcf..2f9c4a8a8f 100644 --- a/arch/arm/boards/phytec-som-imx6/Makefile +++ b/arch/arm/boards/phytec-som-imx6/Makefile @@ -1,4 +1,4 @@ obj-y += board.o lwl-y += lowlevel.o bbenv-y += defaultenv-physom-imx6 -bbenv-y += defaultenv-physom-imx6-mira +bbenv-y += defaultenv-physom-imx6-phycore diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c index 85ad8cb5e2..930ad74d74 100644 --- a/arch/arm/boards/phytec-som-imx6/board.c +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -29,7 +29,8 @@ #include <init.h> #include <of.h> #include <mach/bbu.h> -#include <fec.h> +#include <platform_data/eth-fec.h> + #include <globalvar.h> #include <linux/micrel_phy.h> @@ -113,7 +114,8 @@ static int physom_imx6_devices_init(void) } else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") - || of_machine_is_compatible("phytec,imx6dl-pcm058-nand")) { + || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") + || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { barebox_set_hostname("phyCORE-i.MX6"); default_environment_path = "/chosen/environment-spinor"; @@ -124,20 +126,20 @@ static int physom_imx6_devices_init(void) switch (bootsource_get()) { case BOOTSOURCE_MMC: - environment_path = asprintf("/chosen/environment-sd%d", - bootsource_get_instance() + 1); + environment_path = basprintf("/chosen/environment-sd%d", + bootsource_get_instance() + 1); envdev = "MMC"; break; case BOOTSOURCE_NAND: - environment_path = asprintf("/chosen/environment-nand"); + environment_path = basprintf("/chosen/environment-nand"); envdev = "NAND flash"; break; case BOOTSOURCE_SPI: - environment_path = asprintf("/chosen/environment-spinor"); + environment_path = basprintf("/chosen/environment-spinor"); envdev = "SPI NOR flash"; break; default: - environment_path = asprintf(default_environment_path); + environment_path = basprintf(default_environment_path); envdev = default_envdev; break; } @@ -152,15 +154,23 @@ static int physom_imx6_devices_init(void) pr_notice("Using environment in %s\n", envdev); - imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + if (of_machine_is_compatible("phytec,imx6q-pcm058-emmc") + || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { + imx6_bbu_internal_mmc_register_handler("mmc3", + "/dev/mmc3", + BBU_HANDLER_FLAG_DEFAULT); + } else { + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + } defaultenv_append_directory(defaultenv_physom_imx6); /* Overwrite file /env/init/automount */ if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") - || of_machine_is_compatible("phytec,imx6dl-pcm058-nand")) { - defaultenv_append_directory(defaultenv_physom_imx6_mira); + || of_machine_is_compatible("phytec,imx6dl-pcm058-nand") + || of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) { + defaultenv_append_directory(defaultenv_physom_imx6_phycore); } return 0; diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-mira/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount index 3659cf7d39..a059e190e2 100644 --- a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-mira/init/automount +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/automount @@ -12,3 +12,6 @@ automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' mkdir -p /mnt/mmc automount -d /mnt/mmc 'mmc0.probe=1 && [ -e /dev/mmc0.0 ] && mount /dev/mmc0.0 /mnt/mmc' + +mkdir -p /mnt/emmc +automount -d /mnt/emmc 'mmc3.probe=1 && [ -e /dev/mmc3.0 ] && mount /dev/mmc3.0 /mnt/emmc' diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource new file mode 100644 index 0000000000..515613b041 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-phycore/init/bootsource @@ -0,0 +1,19 @@ +#!/bin/sh + +if [ -n "$nv.boot.default" ]; then + exit +fi + +if [ $bootsource = mmc ]; then + if [ $bootsource_instance = 0 ]; then + global.boot.default="mmc emmc nand spi net" + elif [ $bootsource_instance = 3 ]; then + global.boot.default="emmc mmc nand spi net" + fi +elif [ $bootsource = nand ]; then + global.boot.default="nand spi emmc mmc net" +elif [ $bootsource = spi ]; then + global.boot.default="spi nand emmc mmc net" +elif [ $bootsource = net ]; then + global.boot.default="net nand spi emmc mmc" +fi diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg new file mode 100644 index 0000000000..54c9e41d28 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-2gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000047; \ + wm 32 0x021b0000 0x841A0000 + +#include "flash-header-phytec-pcm058.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg new file mode 100644 index 0000000000..f047253084 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-1gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x555A7955 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831A0000 + +#include "flash-header-phytec-pcm058dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h index c7df7907d1..a6e4578cb1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h @@ -44,18 +44,18 @@ wm 32 0x020e0488 0x00000028 wm 32 0x020e048c 0x00000028 wm 32 0x021b0800 0xa1390003 wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x0032003A -wm 32 0x021b0810 0x00350037 -wm 32 0x021b480c 0x00260038 -wm 32 0x021b4810 0x002C0038 -wm 32 0x021b083c 0x42630244 -wm 32 0x021b0840 0x02300238 -wm 32 0x021b483c 0x02540258 -wm 32 0x021b4840 0x0236021e -wm 32 0x021b0848 0x46484446 -wm 32 0x021b4848 0x302d2c35 -wm 32 0x021b0850 0x36342630 -wm 32 0x021b4850 0x3423372d +wm 32 0x021b080c 0x0019001C +wm 32 0x021b0810 0x00140019 +wm 32 0x021b480c 0x00030003 +wm 32 0x021b4810 0x00030010 +wm 32 0x021b083c 0x42140210 +wm 32 0x021b0840 0x02040208 +wm 32 0x021b483c 0x42040208 +wm 32 0x021b4840 0x01680178 +wm 32 0x021b0848 0x40423E3E +wm 32 0x021b4848 0x4242443E +wm 32 0x021b0850 0x2C2C2A30 +wm 32 0x021b4850 0x2E2A3228 wm 32 0x021b081c 0x33333333 wm 32 0x021b0820 0x33333333 wm 32 0x021b0824 0x33333333 diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index eb796e78b8..c732d32a96 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -91,7 +91,10 @@ PHYTEC_ENTRY(start_phytec_pbab01s_256mb_1bank, imx6s_phytec_pbab01, SZ_256M, fal PHYTEC_ENTRY(start_phytec_pbab01s_512mb_1bank, imx6s_phytec_pbab01, SZ_512M, false); PHYTEC_ENTRY(start_phytec_phyboard_alcor_1gib, imx6q_phytec_phyboard_alcor, SZ_1G, false); PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_subra, SZ_512M, false); +PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra, SZ_1G, false); PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true); PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true); diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c index 63f4f19b3f..177355b633 100644 --- a/arch/arm/boards/pm9261/init.c +++ b/arch/arm/boards/pm9261/init.c @@ -35,7 +35,7 @@ #include <mach/iomux.h> #include <mach/io.h> #include <mach/at91sam9_smc.h> -#include <dm9000.h> +#include <platform_data/eth-dm9000.h> #include <linux/w1-gpio.h> #include <w1_mac_address.h> diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c index 2b6b0891f5..e9f8588649 100644 --- a/arch/arm/boards/pm9263/init.c +++ b/arch/arm/boards/pm9263/init.c @@ -20,7 +20,6 @@ #include <net.h> #include <init.h> #include <environment.h> -#include <fec.h> #include <asm/armlinux.h> #include <generated/mach-types.h> #include <partition.h> diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c index 0e17587a74..147fce9952 100644 --- a/arch/arm/boards/raspberry-pi/rpi-common.c +++ b/arch/arm/boards/raspberry-pi/rpi-common.c @@ -201,8 +201,8 @@ static void rpi_get_board_rev(void) if (!rpi_board_rev) goto unknown_rev; - name = asprintf("RaspberryPi %s %s", rpi_models[rpi_board_rev].name, - rpi_model_string); + name = basprintf("RaspberryPi %s %s", + rpi_models[rpi_board_rev].name, rpi_model_string); barebox_set_model(name); free(name); @@ -210,7 +210,7 @@ static void rpi_get_board_rev(void) unknown_rev: rpi_board_rev = 0; - name = asprintf("RaspberryPi %s", rpi_model_string); + name = basprintf("RaspberryPi %s", rpi_model_string); barebox_set_model(name); free(name); } diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index 3af140423f..fda3b1432c 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -26,7 +26,7 @@ #include <partition.h> #include <fs.h> #include <fcntl.h> -#include <dm9000.h> +#include <platform_data/eth-dm9000.h> #include <led.h> #include <mach/iomux-mx1.h> #include <mach/devices-imx1.h> diff --git a/arch/arm/boards/tqma6x/board.c b/arch/arm/boards/tqma6x/board.c index 9c52c8ae7a..8946a27b69 100644 --- a/arch/arm/boards/tqma6x/board.c +++ b/arch/arm/boards/tqma6x/board.c @@ -26,7 +26,6 @@ #include <linux/sizes.h> #include <init.h> #include <gpio.h> -#include <fec.h> #include <of.h> #include <linux/micrel_phy.h> diff --git a/arch/arm/boards/udoo/board.c b/arch/arm/boards/udoo/board.c index f3668fef0b..f0befaf3a9 100644 --- a/arch/arm/boards/udoo/board.c +++ b/arch/arm/boards/udoo/board.c @@ -19,7 +19,6 @@ #include <init.h> #include <environment.h> #include <mach/imx6-regs.h> -#include <fec.h> #include <gpio.h> #include <mach/bbu.h> #include <asm/armlinux.h> diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c index 3166cd4fed..8691a171e1 100644 --- a/arch/arm/boards/versatile/versatilepb.c +++ b/arch/arm/boards/versatile/versatilepb.c @@ -29,7 +29,7 @@ #include <environment.h> #include <partition.h> #include <linux/sizes.h> -#include <net/smc91111.h> +#include <platform_data/eth-smc91111.h> static int vpb_console_init(void) { diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c index 2ff08b7934..bd72cd1992 100644 --- a/arch/arm/boards/zylonite/board.c +++ b/arch/arm/boards/zylonite/board.c @@ -25,7 +25,7 @@ #include <init.h> #include <partition.h> #include <led.h> -#include <net/smc91111.h> +#include <platform_data/eth-smc91111.h> #include <platform_data/mtd-nand-mrvl.h> #include <pwm.h> #include <linux/clk.h> diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 82b3821d91..1b0739c35c 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -54,6 +54,7 @@ CONFIG_CMD_IMD=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_ARM_MMUINFO=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MMC_EXTCSD=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y @@ -101,6 +102,7 @@ CONFIG_CMD_FLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_LED=y +CONFIG_CMD_NANDTEST=y CONFIG_CMD_SPI=y CONFIG_CMD_LED_TRIGGER=y CONFIG_CMD_USBGADGET=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b83c1109ef..813e098145 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -45,10 +45,12 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ imx6dl-phytec-pbab01.dtb.o \ imx6q-phytec-pbab01.dtb.o \ imx6q-phytec-phyboard-alcor.dtb.o \ + imx6q-phytec-phyboard-subra.dtb.o \ imx6dl-phytec-phyboard-subra.dtb.o \ imx6q-phytec-phycore-som-nand.dtb.o \ imx6q-phytec-phycore-som-emmc.dtb.o \ - imx6dl-phytec-phycore-som-nand.dtb.o + imx6dl-phytec-phycore-som-nand.dtb.o \ + imx6dl-phytec-phycore-som-emmc.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o diff --git a/arch/arm/dts/am335x-phytec-phycard-som.dtsi b/arch/arm/dts/am335x-phytec-phycard-som.dtsi index d1dfa86bca..f052f0cc3a 100644 --- a/arch/arm/dts/am335x-phytec-phycard-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycard-som.dtsi @@ -185,42 +185,42 @@ reg = <0x0 0x20000>; }; - partition@1 { + partition@20000 { label = "xload_backup1"; reg = <0x20000 0x20000>; }; - partition@2 { + partition@40000 { label = "xload_backup2"; reg = <0x40000 0x20000>; }; - partition@3 { + partition@60000 { label = "xload_backup3"; reg = <0x60000 0x20000>; }; - partition@4 { + partition@80000 { label = "barebox"; reg = <0x80000 0x80000>; }; - partition@5 { + partition@100000 { label = "bareboxenv"; reg = <0x100000 0x40000>; }; - partition@6 { + partition@140000 { label = "oftree"; reg = <0x140000 0x40000>; }; - partition@7 { + partition@180000 { label = "kernel"; reg = <0x180000 0x800000>; }; - partition@8 { + partition@980000 { label = "root"; reg = <0x980000 0x0>; }; diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi index f3a1d4d45a..e48d545e64 100644 --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi @@ -174,22 +174,22 @@ reg = <0x0 0x20000>; }; - partition@1 { + partition@20000 { label = "barebox"; reg = <0x20000 0x80000>; }; - partition@2 { + partition@a0000 { label = "bareboxenv"; reg = <0xa0000 0x20000>; }; - partition@3 { + partition@c0000 { label = "oftree"; reg = <0xc0000 0x20000>; }; - partition@4 { + partition@e0000 { label = "kernel"; reg = <0xe0000 0x0>; }; @@ -269,42 +269,42 @@ reg = <0x0 0x20000>; }; - partition@1 { + partition@20000 { label = "xload_backup1"; reg = <0x20000 0x20000>; }; - partition@2 { + partition@40000 { label = "xload_backup2"; reg = <0x40000 0x20000>; }; - partition@3 { + partition@60000 { label = "xload_backup3"; reg = <0x60000 0x20000>; }; - partition@4 { + partition@80000 { label = "barebox"; reg = <0x80000 0x80000>; }; - partition@5 { + partition@100000 { label = "bareboxenv"; reg = <0x100000 0x40000>; }; - partition@6 { + partition@140000 { label = "oftree"; reg = <0x140000 0x40000>; }; - partition@7 { + partition@180000 { label = "kernel"; reg = <0x180000 0x800000>; }; - partition@8 { + partition@980000 { label = "root"; /* * Size 0x0 extends partition to diff --git a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi index c60943ccec..6561625686 100644 --- a/arch/arm/dts/am335x-phytec-phyflex-som.dtsi +++ b/arch/arm/dts/am335x-phytec-phyflex-som.dtsi @@ -165,22 +165,22 @@ reg = <0x0 0x20000>; }; - partition@1 { + partition@20000 { label = "barebox"; reg = <0x20000 0x80000>; }; - partition@2 { + partition@a0000 { label = "bareboxenv"; reg = <0xa0000 0x20000>; }; - partition@3 { + partition@c0000 { label = "oftree"; reg = <0xc0000 0x20000>; }; - partition@4 { + partition@e0000 { label = "kernel"; reg = <0xe0000 0x0>; }; @@ -283,42 +283,42 @@ reg = <0x0 0x20000>; }; - partition@1 { + partition@20000 { label = "xload_backup1"; reg = <0x20000 0x20000>; }; - partition@2 { + partition@40000 { label = "xload_backup2"; reg = <0x40000 0x20000>; }; - partition@3 { + partition@60000 { label = "xload_backup3"; reg = <0x60000 0x20000>; }; - partition@4 { + partition@80000 { label = "barebox"; reg = <0x80000 0x80000>; }; - partition@5 { + partition@100000 { label = "bareboxenv"; reg = <0x100000 0x40000>; }; - partition@6 { + partition@140000 { label = "oftree"; reg = <0x140000 0x40000>; }; - partition@7 { + partition@180000 { label = "kernel"; reg = <0x180000 0x800000>; }; - partition@8 { + partition@980000 { label = "root"; reg = <0x980000 0x0>; }; diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts index d661463282..8d79471a30 100644 --- a/arch/arm/dts/imx25-karo-tx25.dts +++ b/arch/arm/dts/imx25-karo-tx25.dts @@ -126,17 +126,17 @@ reg = <0x0 0x80000>; }; - partition@1 { + partition@80000 { label = "environment"; reg = <0x80000 0x80000>; }; - partition@2 { + partition@100000 { label = "kernel"; reg = <0x100000 0x400000>; }; - partition@3 { + partition@500000 { label = "root"; reg = <0x500000 0x7b00000>; }; diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts index 3ea1b5b052..cb02a1dfce 100644 --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts @@ -18,20 +18,20 @@ &nfc { partition@0 { label = "boot"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; - partition@2 { + partition@100000 { label = "kernel"; reg = <0x100000 0x400000>; }; - partition@3 { + partition@500000 { label = "root"; reg = <0x500000 0x7b00000>; }; diff --git a/arch/arm/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/dts/imx27-phytec-phycore-rdk.dts index f602045c7e..fff154cb97 100644 --- a/arch/arm/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/dts/imx27-phytec-phycore-rdk.dts @@ -32,17 +32,17 @@ reg = <0x00000000 0x00080000>; }; - environment_nand: partition@1 { + environment_nand: partition@80000 { label = "env"; reg = <0x00080000 0x00020000>; }; - partition@2 { + partition@a0000 { label = "kernel"; reg = <0x000a0000 0x00400000>; }; - partition@3 { + partition@4a0000 { label = "root"; reg = <0x004a0000 0>; }; @@ -54,17 +54,17 @@ reg = <0x00000000 0x00080000>; }; - environment_nor: partition@1 { + environment_nor: partition@80000 { label = "env"; reg = <0x00080000 0x00020000>; }; - partition@2 { + partition@a0000 { label = "kernel"; reg = <0x000a0000 0x00400000>; }; - partition@3 { + partition@4a0000 { label = "root"; reg = <0x004a0000 0>; }; diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts index f8402ca8fa..bde3031d1b 100644 --- a/arch/arm/dts/imx51-babbage.dts +++ b/arch/arm/dts/imx51-babbage.dts @@ -27,9 +27,9 @@ #address-cells = <1>; #size-cells = <1>; - environment_esdhc1: partition@0 { + environment_esdhc1: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x20000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx51-genesi-efika-sb.dts b/arch/arm/dts/imx51-genesi-efika-sb.dts index 78cb1b7184..5a2c3a1c40 100644 --- a/arch/arm/dts/imx51-genesi-efika-sb.dts +++ b/arch/arm/dts/imx51-genesi-efika-sb.dts @@ -415,9 +415,9 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + partition@e0000 { label = "barebox-environment"; - reg = <0xc0000 0x40000>; + reg = <0xe0000 0x20000>; }; }; @@ -533,9 +533,9 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; }; diff --git a/arch/arm/dts/imx53-ccxmx53.dtsi b/arch/arm/dts/imx53-ccxmx53.dtsi index e4b4e54928..2ed24b65e4 100644 --- a/arch/arm/dts/imx53-ccxmx53.dtsi +++ b/arch/arm/dts/imx53-ccxmx53.dtsi @@ -233,20 +233,20 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; - partition@2 { + partition@100000 { label = "kernel"; reg = <0x100000 0x400000>; }; - partition@3 { + partition@500000 { label = "rootfs"; reg = <0x500000 0x0>; }; diff --git a/arch/arm/dts/imx53-guf-vincell-lt.dts b/arch/arm/dts/imx53-guf-vincell-lt.dts index a577ab262e..bcc378d07f 100644 --- a/arch/arm/dts/imx53-guf-vincell-lt.dts +++ b/arch/arm/dts/imx53-guf-vincell-lt.dts @@ -361,15 +361,15 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - bareboxenv: partition@1 { + bareboxenv: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; - partition@2 { + partition@100000 { label = "ubi"; reg = <0x100000 0x0>; }; diff --git a/arch/arm/dts/imx53-mba53.dts b/arch/arm/dts/imx53-mba53.dts index c908c61671..28f463c451 100644 --- a/arch/arm/dts/imx53-mba53.dts +++ b/arch/arm/dts/imx53-mba53.dts @@ -28,9 +28,9 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + partition@e0000 { label = "environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index 85e1b8bd01..f363af975d 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -43,9 +43,9 @@ #address-cells = <1>; #size-cells = <1>; - bareboxenv: partition@0 { + bareboxenv: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x20000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/dts/imx53-voipac-dmm-668.dtsi index 6f76d2867a..e91c7d02a2 100644 --- a/arch/arm/dts/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/dts/imx53-voipac-dmm-668.dtsi @@ -15,20 +15,20 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; - partition@2 { + partition@100000 { label = "kernel"; reg = <0x100000 0x400000>; }; - partition@3 { + partition@500000 { label = "rootfs"; reg = <0x500000 0x07B00000>; }; diff --git a/arch/arm/dts/imx6dl-eltec-hipercam.dts b/arch/arm/dts/imx6dl-eltec-hipercam.dts index f272e78a59..4fe174437e 100644 --- a/arch/arm/dts/imx6dl-eltec-hipercam.dts +++ b/arch/arm/dts/imx6dl-eltec-hipercam.dts @@ -37,15 +37,15 @@ partition@0 { label = "barebox"; - reg = <0x0 0xc0000>; + reg = <0x0 0xe0000>; }; - environment_nor0: partition@1 { + environment_nor0: partition@e0000 { label = "bareboxenv"; - reg = <0xc0000 0x8000>; + reg = <0xe0000 0x20000>; }; - partition@2 { + partition@100000 { label = "persistent"; reg = <0x100000 0xf00000>; }; diff --git a/arch/arm/dts/imx6dl-hummingboard.dts b/arch/arm/dts/imx6dl-hummingboard.dts index 2314965260..7f4d2b42f2 100644 --- a/arch/arm/dts/imx6dl-hummingboard.dts +++ b/arch/arm/dts/imx6dl-hummingboard.dts @@ -29,11 +29,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6dl-phytec-phyboard-subra.dts b/arch/arm/dts/imx6dl-phytec-phyboard-subra.dts index 34e414413c..3d1069a965 100644 --- a/arch/arm/dts/imx6dl-phytec-phyboard-subra.dts +++ b/arch/arm/dts/imx6dl-phytec-phyboard-subra.dts @@ -11,24 +11,9 @@ /dts-v1/; #include "imx6s-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-phyboard-subra.dtsi" / { model = "Phytec phyBOARD SUBRA"; compatible = "phytec,imx6dl-pbab05", "phytec,imx6s-pfla02", "fsl,imx6dl"; - - chosen { - stdout-path = &uart4; - }; -}; - -&fec { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usdhc3 { - status = "okay"; }; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts new file mode 100644 index 0000000000..fc153a6b05 --- /dev/null +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 PHYTEC Messtechnik GmbH, + * Author: Stefan Christ <s.christ@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <arm/imx6dl.dtsi> +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 DualLite/SOLO with eMMC"; + compatible = "phytec,imx6dl-pcm058-emmc", "fsl,imx6dl"; +}; + +&ecspi1 { + status = "okay"; +}; + +&eeprom { + status = "okay"; +}; + +&fec { + status = "okay"; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 14 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + max-speed = <100>; + }; + }; +}; + +&flash { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc4 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts index 2324f3a6e5..3f2f1c7320 100644 --- a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -53,11 +53,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6dl-wandboard.dts b/arch/arm/dts/imx6dl-wandboard.dts index a8674004c8..873e9d6985 100644 --- a/arch/arm/dts/imx6dl-wandboard.dts +++ b/arch/arm/dts/imx6dl-wandboard.dts @@ -27,11 +27,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0xc0000>; + reg = <0x0 0xe0000>; }; - environment_usdhc3: partition@c0000 { + environment_usdhc3: partition@e0000 { label = "barebox-environment"; - reg = <0xc0000 0x40000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/dts/imx6q-dmo-edmqmx6.dts index 071f5f5c5e..3576211be4 100644 --- a/arch/arm/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/dts/imx6q-dmo-edmqmx6.dts @@ -53,12 +53,12 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x20000>; + reg = <0xe0000 0x20000>; }; }; }; @@ -97,11 +97,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; @@ -111,10 +111,10 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts index 726d620681..3bbb60bba3 100644 --- a/arch/arm/dts/imx6q-embedsky-e9.dts +++ b/arch/arm/dts/imx6q-embedsky-e9.dts @@ -41,11 +41,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - environment_mmc1: partition@1 { + environment_mmc1: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; @@ -55,10 +55,10 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - environment_mmc3: partition@1 { + environment_mmc3: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts index 27f538a356..2bd1a26317 100644 --- a/arch/arm/dts/imx6q-guf-santaro.dts +++ b/arch/arm/dts/imx6q-guf-santaro.dts @@ -587,9 +587,9 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-hummingboard.dts b/arch/arm/dts/imx6q-hummingboard.dts index e1d2fa8ce2..e707eb91c9 100644 --- a/arch/arm/dts/imx6q-hummingboard.dts +++ b/arch/arm/dts/imx6q-hummingboard.dts @@ -29,11 +29,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi index 05224657dc..a6ea7b5cce 100644 --- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi +++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi @@ -139,22 +139,22 @@ reg = <0x0 0x400000>; }; - environment_nand: partition@1 { + environment_nand: partition@400000 { label = "barebox-environment"; reg = <0x400000 0x20000>; }; - partition@2 { + partition@420000 { label = "oftree"; reg = <0x420000 0x20000>; }; - partition@3 { + partition@440000 { label = "kernel"; reg = <0x440000 0x800000>; }; - partition@4 { + partition@C40000 { label = "root"; reg = <0xC40000 0x0>; }; @@ -181,10 +181,10 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - environment_usdhc3: partition@1 { + environment_usdhc3: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-phytec-phyboard-alcor.dts b/arch/arm/dts/imx6q-phytec-phyboard-alcor.dts index a60fc186e2..1c4a78552d 100644 --- a/arch/arm/dts/imx6q-phytec-phyboard-alcor.dts +++ b/arch/arm/dts/imx6q-phytec-phyboard-alcor.dts @@ -35,4 +35,5 @@ &usdhc3 { status = "okay"; + max-frequency = <25000000>; /* 25 Mhz */ }; diff --git a/arch/arm/dts/imx6q-phytec-phyboard-subra.dts b/arch/arm/dts/imx6q-phytec-phyboard-subra.dts new file mode 100644 index 0000000000..561e985604 --- /dev/null +++ b/arch/arm/dts/imx6q-phytec-phyboard-subra.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2015 PHYTEC Messtechnik GmbH, + * Author: Stefan Christ <s.christ@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx6q-phytec-pfla02.dtsi" +#include "imx6qdl-phytec-phyboard-subra.dtsi" + +/ { + model = "Phytec phyBOARD SUBRA"; + compatible = "phytec,imx6q-pbab05", "phytec,imx6q-pfla02", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts index 6e19ab553e..74bc09b5d5 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -20,6 +20,10 @@ compatible = "phytec,imx6q-pcm058-emmc", "fsl,imx6q"; }; +&ecspi1 { + status = "okay"; +}; + &eeprom { status = "okay"; }; @@ -41,8 +45,25 @@ }; }; +&flash { + status = "okay"; +}; + &usdhc1 { status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; }; &usdhc4 { diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts index 06f2f71537..aa2c94abee 100644 --- a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -62,11 +62,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6q-var-custom.dts b/arch/arm/dts/imx6q-var-custom.dts index ef6981e3bc..fe03589454 100644 --- a/arch/arm/dts/imx6q-var-custom.dts +++ b/arch/arm/dts/imx6q-var-custom.dts @@ -127,17 +127,17 @@ reg = <0x0 0x200000>; }; - partition@1 { + partition@200000 { label = "barebox-environment"; reg = <0x200000 0x20000>; }; - partition@2 { + partition@220000 { label = "kernel"; reg = <0x220000 0x600000>; }; - partition@3 { + partition@820000 { label = "rootfs"; reg = <0x820000 0x18000000>; }; diff --git a/arch/arm/dts/imx6q-var-som.dtsi b/arch/arm/dts/imx6q-var-som.dtsi index d005f319d6..63a17fc660 100644 --- a/arch/arm/dts/imx6q-var-som.dtsi +++ b/arch/arm/dts/imx6q-var-som.dtsi @@ -42,17 +42,17 @@ reg = <0x0 0x200000>; }; - environment_nand: partition@1 { + environment_nand: partition@200000 { label = "barebox-environment"; reg = <0x200000 0x20000>; }; - partition@2 { + partition@220000 { label = "kernel"; reg = <0x220000 0x600000>; }; - partition@3 { + partition@820000 { label = "rootfs"; reg = <0x820000 0x1F7E0000>; }; diff --git a/arch/arm/dts/imx6q-wandboard.dts b/arch/arm/dts/imx6q-wandboard.dts index 26d8a0077d..0606727a11 100644 --- a/arch/arm/dts/imx6q-wandboard.dts +++ b/arch/arm/dts/imx6q-wandboard.dts @@ -27,11 +27,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0xc0000>; + reg = <0x0 0xe0000>; }; - environment_usdhc3: partition@c0000 { + environment_usdhc3: partition@e0000 { label = "barebox-environment"; - reg = <0xc0000 0x40000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index ea5739ddcb..5f8e489aeb 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -31,7 +31,7 @@ reg = <0x0 0x400000>; }; - partition@1 { + partition@400000 { label = "barebox-environment"; reg = <0x400000 0x20000>; }; diff --git a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi index 8fcd4e48a4..9ff7395f45 100644 --- a/arch/arm/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/dts/imx6qdl-nitrogen6x.dtsi @@ -31,12 +31,12 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi index b79ce2c0f9..9a8c7024a3 100644 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi @@ -66,17 +66,17 @@ reg = <0x0 0x100000>; }; - partition@1 { + partition@100000 { label = "barebox-environment"; reg = <0x100000 0x20000>; }; - partition@2 { + partition@120000 { label = "oftree"; reg = <0x120000 0x20000>; }; - partition@3 { + partition@140000 { label = "kernel"; reg = <0x140000 0x0>; }; @@ -85,6 +85,7 @@ &fec { phy-handle = <ðphy>; + phy-reset-duration = <10>; /* in msecs */ mdio { #address-cells = <1>; @@ -108,22 +109,22 @@ reg = <0x0 0x400000>; }; - partition@1 { + partition@400000 { label = "barebox-environment"; reg = <0x400000 0x100000>; }; - partition@2 { + partition@500000 { label = "oftree"; reg = <0x500000 0x100000>; }; - partition@3 { + partition@600000 { label = "kernel"; reg = <0x600000 0x800000>; }; - partition@4 { + partition@e00000 { label = "root"; reg = <0xe00000 0x0>; }; @@ -180,11 +181,23 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; }; }; diff --git a/arch/arm/dts/imx6qdl-phytec-phyboard-subra.dtsi b/arch/arm/dts/imx6qdl-phytec-phyboard-subra.dtsi new file mode 100644 index 0000000000..a38765b142 --- /dev/null +++ b/arch/arm/dts/imx6qdl-phytec-phyboard-subra.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 PHYTEC Messtechnik GmbH, + * Author: Stefan Christ <s.christ@phytec.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/ { + chosen { + stdout-path = &uart4; + }; +}; + +&fec { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; + max-frequency = <25000000>; /* 25 Mhz */ +}; diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi index 2a975d103e..d446a5e9af 100644 --- a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -46,6 +46,7 @@ compatible = "m25p80"; spi-max-frequency = <20000000>; reg = <0>; + status = "disabled"; #address-cells = <1>; #size-cells = <1>; @@ -55,17 +56,17 @@ reg = <0x0 0x100000>; }; - partition@1 { + partition@100000 { label = "barebox-environment"; reg = <0x100000 0x20000>; }; - partition@2 { + partition@120000 { label = "oftree"; reg = <0x120000 0x20000>; }; - partition@3 { + partition@140000 { label = "kernel"; reg = <0x140000 0x0>; }; @@ -91,22 +92,22 @@ reg = <0x0 0x400000>; }; - partition@1 { + partition@400000 { label = "barebox-environment"; reg = <0x400000 0x100000>; }; - partition@2 { + partition@500000 { label = "oftree"; reg = <0x500000 0x100000>; }; - partition@3 { + partition@600000 { label = "kernel"; reg = <0x600000 0x800000>; }; - partition@4 { + partition@e00000 { label = "root"; reg = <0xe00000 0x0>; }; @@ -256,11 +257,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi b/arch/arm/dts/imx6qdl-sabrelite.dtsi index d5a6ff4b1f..10b0002ec2 100644 --- a/arch/arm/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi @@ -31,12 +31,12 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - partition@1 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi index 32318cf389..6b10229c88 100644 --- a/arch/arm/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -31,11 +31,11 @@ partition@0 { label = "barebox"; - reg = <0x0 0x80000>; + reg = <0x0 0xe0000>; }; - environment_usdhc3: partition@1 { + environment_usdhc3: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6qdl-tx6x.dtsi b/arch/arm/dts/imx6qdl-tx6x.dtsi index 9c5d676a74..3898425d9c 100644 --- a/arch/arm/dts/imx6qdl-tx6x.dtsi +++ b/arch/arm/dts/imx6qdl-tx6x.dtsi @@ -32,7 +32,7 @@ reg = <0x0 0x400000>; }; - partition@1 { + partition@400000 { label = "barebox-environment"; reg = <0x400000 0x100000>; }; diff --git a/arch/arm/dts/imx6s-riotboard.dts b/arch/arm/dts/imx6s-riotboard.dts index 3d0a930c3f..09ac534625 100644 --- a/arch/arm/dts/imx6s-riotboard.dts +++ b/arch/arm/dts/imx6s-riotboard.dts @@ -233,9 +233,9 @@ reg = <0x0 0x80000>; }; - environment_usdhc4: partition@1 { + environment_usdhc4: partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x80000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts index fbf098bbe6..7b60f9326a 100644 --- a/arch/arm/dts/imx6sx-sdb.dts +++ b/arch/arm/dts/imx6sx-sdb.dts @@ -52,9 +52,9 @@ #address-cells = <1>; #size-cells = <1>; - partition@0 { + partition@e0000 { label = "barebox-environment"; - reg = <0x80000 0x20000>; + reg = <0xe0000 0x20000>; }; }; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 47b2487dd9..cafd4d36ed 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -34,7 +34,7 @@ label = "barebox"; reg = <0x0 0x80000>; }; - partition@1 { + partition@80000 { label = "barebox-environment"; reg = <0x80000 0x80000>; }; diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 724ebb0787..b98b3e52a4 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -90,8 +90,8 @@ extern char elf_platform[]; #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) -/* When the program starts, a1 contains a pointer to a function to be - registered with atexit, as per the SVR4 ABI. A value of 0 means we +/* When the program starts, a1 contains a pointer to a function to be + registered with atexit, as per the SVR4 ABI. A value of 0 means we have no such handler. */ #define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0 diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 28b4f4a4b4..f6024c80ec 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -67,21 +67,30 @@ static int sdram_start_and_size(unsigned long *start, unsigned long *size) return 0; } -static void get_kernel_addresses(unsigned long mem_start, size_t image_size, +static int get_kernel_addresses(size_t image_size, int verbose, unsigned long *load_address, - unsigned long *spacing) + unsigned long *mem_free) { + unsigned long mem_start, mem_size; + int ret; + size_t image_decomp_size; + unsigned long spacing; + + ret = sdram_start_and_size(&mem_start, &mem_size); + if (ret) + return ret; + /* * We don't know the exact decompressed size so just use a conservative * default of 4 times the size of the compressed image. */ - size_t image_decomp_size = PAGE_ALIGN(image_size * 4); + image_decomp_size = PAGE_ALIGN(image_size * 4); /* * By default put oftree/initrd close behind compressed kernel image to * avoid placing it outside of the kernels lowmem region. */ - *spacing = SZ_1M; + spacing = SZ_1M; if (*load_address == UIMAGE_INVALID_ADDRESS) { /* @@ -99,8 +108,12 @@ static void get_kernel_addresses(unsigned long mem_start, size_t image_size, * spacing to allow this relocation to happen without * overwriting anything placed behind the kernel. */ - *spacing += image_decomp_size; + spacing += image_decomp_size; } + + *mem_free = PAGE_ALIGN(*load_address + image_size + spacing); + + return 0; } static int __do_bootm_linux(struct image_data *data, unsigned long free_mem, int swap) @@ -160,24 +173,20 @@ static int __do_bootm_linux(struct image_data *data, unsigned long free_mem, int static int do_bootm_linux(struct image_data *data) { - unsigned long load_address, mem_start, mem_size, mem_free, spacing; + unsigned long load_address, mem_free; int ret; - ret = sdram_start_and_size(&mem_start, &mem_size); - if (ret) - return ret; - load_address = data->os_address; - get_kernel_addresses(mem_start, bootm_get_os_size(data), - bootm_verbose(data), &load_address, &spacing); + ret = get_kernel_addresses(bootm_get_os_size(data), + bootm_verbose(data), &load_address, &mem_free); + if (ret) + return ret; ret = bootm_load_os(data, load_address); if (ret) return ret; - mem_free = PAGE_ALIGN(data->os_res->end + spacing); - return __do_bootm_linux(data, mem_free, 0); } @@ -273,11 +282,7 @@ static int do_bootz_linux(struct image_data *data) u32 end, start; size_t image_size; unsigned long load_address = data->os_address; - unsigned long mem_start, mem_size, mem_free, spacing; - - ret = sdram_start_and_size(&mem_start, &mem_size); - if (ret) - return ret; + unsigned long mem_free; fd = open(data->os_file, O_RDONLY); if (fd < 0) { @@ -315,8 +320,10 @@ static int do_bootz_linux(struct image_data *data) image_size = end - start; load_address = data->os_address; - get_kernel_addresses(mem_start, image_size, bootm_verbose(data), - &load_address, &spacing); + ret = get_kernel_addresses(image_size, bootm_verbose(data), + &load_address, &mem_free); + if (ret) + return ret; data->os_res = request_sdram_region("zimage", load_address, image_size); if (!data->os_res) { @@ -352,8 +359,6 @@ static int do_bootz_linux(struct image_data *data) close(fd); - mem_free = PAGE_ALIGN(data->os_res->end + spacing); - return __do_bootm_linux(data, mem_free, swap); err_out: @@ -570,7 +575,7 @@ static int armlinux_register_image_handler(void) register_image_handler(&aimage_handler); binfmt_register(&binfmt_aimage_hook); } - if (IS_BUILTIN(CONFIG_CMD_BOOTM_FITIMAGE)) + if (IS_BUILTIN(CONFIG_FITIMAGE)) register_image_handler(&arm_fit_handler); binfmt_register(&binfmt_arm_zimage_hook); binfmt_register(&binfmt_barebox_hook); diff --git a/arch/arm/mach-at91/bootstrap.c b/arch/arm/mach-at91/bootstrap.c index 47e78965d9..8502bb00ff 100644 --- a/arch/arm/mach-at91/bootstrap.c +++ b/arch/arm/mach-at91/bootstrap.c @@ -99,49 +99,49 @@ static void boot_nand_barebox_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_nand(true); - getc(); + getchar(); } static void boot_nand_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_nand(false); - getc(); + getchar(); } static void boot_m25p80_barebox_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_nand(true); - getc(); + getchar(); } static void boot_m25p80_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_nand(false); - getc(); + getchar(); } static void boot_dataflash_barebox_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_dataflash(true); - getc(); + getchar(); } static void boot_dataflash_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_dataflash(false); - getc(); + getchar(); } static void boot_mmc_disk_action(struct menu *m, struct menu_entry *me) { at91bootstrap_boot_mmc(); - getc(); + getchar(); } static void boot_reset_action(struct menu *m, struct menu_entry *me) @@ -234,7 +234,7 @@ static int at91_bootstrap(void) { if (is_menu()) { printf("press 'm' to start the menu\n"); - if (tstc() && getc() == 'm') + if (tstc() && getchar() == 'm') at91_bootstrap_menu(); } diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 66ba51cde1..106e648bd3 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -434,7 +434,7 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { } }; -static struct driver_d imx_serial_driver = { +static struct driver_d imx_esdctl_driver = { .name = "imx-esdctl", .probe = imx_esdctl_probe, .id_table = imx_esdctl_ids, @@ -443,7 +443,7 @@ static struct driver_d imx_serial_driver = { static int imx_esdctl_init(void) { - return platform_driver_register(&imx_serial_driver); + return platform_driver_register(&imx_esdctl_driver); } mem_initcall(imx_esdctl_init); diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c index dbd8ccf054..ecaa7e6332 100644 --- a/arch/arm/mach-imx/iim.c +++ b/arch/arm/mach-imx/iim.c @@ -330,7 +330,7 @@ static void imx_iim_add_mac_param(struct iim_priv *iim, int macnum, int bank, in iimmac->offset = offset; iimmac->bank = iim->bank[bank]; - name = asprintf("ethaddr%d", macnum); + name = basprintf("ethaddr%d", macnum); dev_add_param_mac(&iim->dev, name, imx_iim_set_mac, imx_iim_get_mac, iimmac->ethaddr, iimmac); diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h index 45bb0a51ee..6a045dd070 100644 --- a/arch/arm/mach-imx/include/mach/devices.h +++ b/arch/arm/mach-imx/include/mach/devices.h @@ -1,5 +1,5 @@ -#include <fec.h> +#include <platform_data/eth-fec.h> #include <input/matrix_keypad.h> #include <i2c/i2c.h> #include <mach/spi.h> diff --git a/arch/arm/mach-netx/clocksource.c b/arch/arm/mach-netx/clocksource.c index 8f53364e25..263547242e 100644 --- a/arch/arm/mach-netx/clocksource.c +++ b/arch/arm/mach-netx/clocksource.c @@ -1,7 +1,7 @@ /* * * (C) Copyright 2007 - * Sascha Hauer, Pengutronix + * Sascha Hauer, Pengutronix * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h index 8839486fcf..c9730a9454 100644 --- a/arch/arm/mach-omap/include/mach/gpmc_nand.h +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -32,7 +32,6 @@ enum gpmc_ecc_mode { OMAP_ECC_SOFT, OMAP_ECC_HAMMING_CODE_HW_ROMCODE, - OMAP_ECC_BCH4_CODE_HW, OMAP_ECC_BCH8_CODE_HW, OMAP_ECC_BCH8_CODE_HW_ROMCODE, }; diff --git a/arch/arm/mach-omap/omap_devices.c b/arch/arm/mach-omap/omap_devices.c index 9ed3dcf619..f577fa6ea7 100644 --- a/arch/arm/mach-omap/omap_devices.c +++ b/arch/arm/mach-omap/omap_devices.c @@ -1,5 +1,5 @@ #include <driver.h> -#include <ns16550.h> +#include <platform_data/serial-ns16550.h> #include <asm/armlinux.h> #include <mach/omap3-devices.h> diff --git a/arch/arm/mach-omap/omap_generic.c b/arch/arm/mach-omap/omap_generic.c index 34ed94007e..d27c7a867f 100644 --- a/arch/arm/mach-omap/omap_generic.c +++ b/arch/arm/mach-omap/omap_generic.c @@ -130,7 +130,7 @@ static int omap_env_init(void) device_detect_by_name(diskdev); - partname = asprintf("/dev/%s.0", diskdev); + partname = basprintf("/dev/%s.0", diskdev); mkdir("/boot", 0666); ret = mount(partname, "fat", "/boot", NULL); diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c index 8805930215..77938190e1 100644 --- a/arch/arm/mach-omap/xload.c +++ b/arch/arm/mach-omap/xload.c @@ -115,7 +115,7 @@ static void *omap_xload_boot_mmc(void) device_detect_by_name(diskdev); - partname = asprintf("%s.0", diskdev); + partname = basprintf("%s.0", diskdev); ret = mount(partname, NULL, "/", NULL); @@ -280,7 +280,7 @@ static void *am33xx_net_boot(void) return NULL; } - file = asprintf("%s/%s", TFTP_MOUNT, bootfile); + file = basprintf("%s/%s", TFTP_MOUNT, bootfile); buf = read_file(file, &len); if (!buf) diff --git a/arch/arm/mach-socfpga/generic.c b/arch/arm/mach-socfpga/generic.c index 906bc63330..c920bd658f 100644 --- a/arch/arm/mach-socfpga/generic.c +++ b/arch/arm/mach-socfpga/generic.c @@ -4,7 +4,6 @@ #include <init.h> #include <io.h> #include <fs.h> -#include <net/designware.h> #include <linux/clkdev.h> #include <linux/clk.h> #include <linux/stat.h> diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.c b/arch/arm/mach-socfpga/include/mach/sequencer.c index c299f754a8..d2338e6406 100644 --- a/arch/arm/mach-socfpga/include/mach/sequencer.c +++ b/arch/arm/mach-socfpga/include/mach/sequencer.c @@ -292,11 +292,11 @@ static void initialize(void) { IOWR_32DIRECT(PHY_MGR_MUX_SEL, 0, 0x3); - //USER memory clock is not stable we begin initialization + //USER memory clock is not stable we begin initialization IOWR_32DIRECT(PHY_MGR_RESET_MEM_STBL, 0, 0); - //USER calibration status all set to zero + //USER calibration status all set to zero IOWR_32DIRECT(PHY_MGR_CAL_STATUS, 0, 0); IOWR_32DIRECT(PHY_MGR_CAL_DEBUG_INFO, 0, 0); @@ -451,7 +451,7 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode) //USER Given a rank, select the set of shadow registers that is responsible for the //USER delays of such rank, so that subsequent SCC updates will go to those shadow -//USER registers. +//USER registers. static void select_shadow_regs_for_update(uint32_t rank, uint32_t group, uint32_t update_scan_chains) { @@ -494,7 +494,7 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group, uint32_t pha for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { //USER although the h/w doesn't support different phases per shadow register, - //USER for simplicity our scc manager modeling keeps different phase settings per + //USER for simplicity our scc manager modeling keeps different phase settings per //USER shadow reg, and it's important for us to keep them in sync to match h/w. //USER for efficiency, the scan chain update should occur only once to sr0. update_scan_chains = (r == 0) ? 1 : 0; @@ -522,7 +522,7 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group, uint3 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { //USER although the h/w doesn't support different phases per shadow register, - //USER for simplicity our scc manager modeling keeps different phase settings per + //USER for simplicity our scc manager modeling keeps different phase settings per //USER shadow reg, and it's important for us to keep them in sync to match h/w. //USER for efficiency, the scan chain update should occur only once to sr0. update_scan_chains = (r == 0) ? 1 : 0; @@ -749,7 +749,7 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode) DPRINT(1, "Done Setting HHP Extras"); } - //USER multicast to all DQ enables + //USER multicast to all DQ enables IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, 0xff); IOWR_32DIRECT(SCC_MGR_DM_ENA, 0, 0xff); @@ -802,7 +802,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_ //USER multicast to all DQ enables IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, 0xff); - //USER Zero all DM config settings + //USER Zero all DM config settings for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { if (!out_only) { // Do we really need this? @@ -815,7 +815,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_ //USER multicast to all DM enables IOWR_32DIRECT(SCC_MGR_DM_ENA, 0, 0xff); - //USER zero all DQS io settings + //USER zero all DQS io settings if (!out_only) { scc_mgr_set_dqs_io_in_delay(write_group, 0); } @@ -827,33 +827,33 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin, int32_ //USER multicast to all DQS IO enables (only 1) IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0); - //USER hit update to zero everything + //USER hit update to zero everything IOWR_32DIRECT(SCC_MGR_UPD, 0, 0); } } -//USER load up dqs config settings +//USER load up dqs config settings static void scc_mgr_load_dqs(uint32_t dqs) { IOWR_32DIRECT(SCC_MGR_DQS_ENA, 0, dqs); } -//USER load up dqs io config settings +//USER load up dqs io config settings static void scc_mgr_load_dqs_io(void) { IOWR_32DIRECT(SCC_MGR_DQS_IO_ENA, 0, 0); } -//USER load up dq config settings +//USER load up dq config settings static void scc_mgr_load_dq(uint32_t dq_in_group) { IOWR_32DIRECT(SCC_MGR_DQ_ENA, 0, dq_in_group); } -//USER load up dm config settings +//USER load up dm config settings static void scc_mgr_load_dm(uint32_t dm) { @@ -934,20 +934,20 @@ static void scc_mgr_set_group_dqs_io_and_oct_out1_gradual(uint32_t write_group, } } -//USER apply a delay to the entire output side: DQ, DM, DQS, OCT +//USER apply a delay to the entire output side: DQ, DM, DQS, OCT static void scc_mgr_apply_group_all_out_delay(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { - //USER dq shift + //USER dq shift scc_mgr_apply_group_dq_out1_delay(write_group, group_bgn, delay); - //USER dm shift + //USER dm shift scc_mgr_apply_group_dm_out1_delay(write_group, delay); - //USER dqs and oct shift + //USER dqs and oct shift scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, delay); } @@ -968,14 +968,14 @@ static void scc_mgr_apply_group_all_out_delay_all_ranks(uint32_t write_group, ui } } -//USER apply a delay to the entire output side: DQ, DM, DQS, OCT +//USER apply a delay to the entire output side: DQ, DM, DQS, OCT static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t group_bgn, uint32_t delay) { uint32_t i, p, new_delay; - //USER dq shift + //USER dq shift for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { @@ -994,7 +994,7 @@ static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t scc_mgr_load_dq(i); } - //USER dm shift + //USER dm shift for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { new_delay = READ_SCC_DM_IO_OUT2_DELAY(i); @@ -1012,7 +1012,7 @@ static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t scc_mgr_load_dm(i); } - //USER dqs shift + //USER dqs shift new_delay = READ_SCC_DQS_IO_OUT2_DELAY(); new_delay += delay; @@ -1029,7 +1029,7 @@ static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, uint32_t scc_mgr_set_dqs_out2_delay(write_group, new_delay); scc_mgr_load_dqs_io(); - //USER oct shift + //USER oct shift new_delay = READ_SCC_OCT_OUT2_DELAY(write_group); new_delay += delay; @@ -1200,7 +1200,7 @@ static void rw_mgr_mem_initialize(void) //USER indicate that memory is stable IOWR_32DIRECT(PHY_MGR_RESET_MEM_STBL, 0, 1); - //USER transition the RESET to high + //USER transition the RESET to high //USER Wait for 500us //USER num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1 //USER Load counters @@ -1215,12 +1215,12 @@ static void rw_mgr_mem_initialize(void) IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0); - //USER bring up clock enable + //USER bring up clock enable //USER tXRP < 250 ck cycles delay_for_n_mem_clocks(250); - // USER initialize RDIMM buffer so MRS and RZQ Calibrate commands will be + // USER initialize RDIMM buffer so MRS and RZQ Calibrate commands will be // USER propagated to discrete memory devices rw_mgr_rdimm_initialize(); @@ -1231,7 +1231,7 @@ static void rw_mgr_mem_initialize(void) continue; } - //USER set rank + //USER set rank set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); //USER Use Mirror-ed commands for odd ranks if address mirrorring is on @@ -1288,11 +1288,11 @@ static void rw_mgr_mem_handoff(void) //USER set rank set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); - //USER precharge all banks ... + //USER precharge all banks ... IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); - //USER load up MR settings specified by user + //USER load up MR settings specified by user //USER Use Mirror-ed commands for odd ranks if address mirrorring is on if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) { @@ -1397,7 +1397,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group return 1; } else { // case:139851 - if guaranteed read fails, we can retry using different dqs enable phases. - // It is possible that with the initial phase, dqs enable is asserted/deasserted too close + // It is possible that with the initial phase, dqs enable is asserted/deasserted too close // to an dqs edge, truncating the read burst. uint32_t p; for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) { @@ -1411,7 +1411,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks(uint32_t group } } -//USER load up the patterns we are going to use during a read test +//USER load up the patterns we are going to use during a read test static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn, uint32_t all_ranks) { uint32_t r; @@ -1456,96 +1456,96 @@ static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void) //void pe_checkout_pattern (void) //{ // // test RW manager -// +// // // do some reads to check load buffer // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1); // // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2); -// +// // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B); -// +// // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B); -// +// // // clear error word // IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); -// +// // IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_READ_B2B); -// +// // uint32_t readdata; -// +// // // read error word // readdata = IORD_32DIRECT(BASE_RW_MGR, 0); -// +// // // read DI buffer // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0); -// +// // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_1, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_READ_B2B_WAIT1); // // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_2, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_READ_B2B_WAIT2); -// +// // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_0, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_READ_B2B); -// +// // IOWR_32DIRECT (RW_MGR_LOAD_CNTR_3, 0, 0x0); // IOWR_32DIRECT (RW_MGR_LOAD_JUMP_ADD_3, 0, __RW_MGR_READ_B2B); -// +// // // clear error word // IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); -// +// // // do read // IOWR_32DIRECT (RW_MGR_LOOPBACK_MODE, 0, __RW_MGR_READ_B2B); -// +// // // read error word // readdata = IORD_32DIRECT(BASE_RW_MGR, 0); -// +// // // error word should be 0x00 -// +// // // read DI buffer // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0); -// +// // // clear error word // IOWR_32DIRECT (RW_MGR_RESET_READ_DATAPATH, 0, 0); -// -// // do dm read +// +// // do dm read // IOWR_32DIRECT (RW_MGR_LOOPBACK_MODE, 0, __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1); -// +// // // read error word // readdata = IORD_32DIRECT(BASE_RW_MGR, 0); -// +// // // error word should be ff -// +// // // read DI buffer // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 0*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 1*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 2*4, 0); // readdata = IORD_32DIRECT(RW_MGR_DI_BASE + 3*4, 0); -// +// // // exit loopback mode // IOWR_32DIRECT (BASE_RW_MGR, 0, __RW_MGR_IDLE_LOOP2); -// +// // // start of phy manager access -// +// // readdata = IORD_32DIRECT (PHY_MGR_MAX_RLAT_WIDTH, 0); // readdata = IORD_32DIRECT (PHY_MGR_MAX_AFI_WLAT_WIDTH, 0); // readdata = IORD_32DIRECT (PHY_MGR_MAX_AFI_RLAT_WIDTH, 0); // readdata = IORD_32DIRECT (PHY_MGR_CALIB_SKIP_STEPS, 0); -// readdata = IORD_32DIRECT (PHY_MGR_CALIB_VFIFO_OFFSET, 0); +// readdata = IORD_32DIRECT (PHY_MGR_CALIB_VFIFO_OFFSET, 0); // readdata = IORD_32DIRECT (PHY_MGR_CALIB_LFIFO_OFFSET, 0); -// +// // // start of data manager test -// +// // readdata = IORD_32DIRECT (DATA_MGR_DRAM_CFG , 0); // readdata = IORD_32DIRECT (DATA_MGR_MEM_T_WL , 0); // readdata = IORD_32DIRECT (DATA_MGR_MEM_T_ADD , 0); @@ -1560,7 +1560,7 @@ static inline void rw_mgr_mem_calibrate_read_load_patterns_all_ranks(void) // readdata = IORD_32DIRECT (DATA_MGR_CS_WIDTH , 0); // readdata = IORD_32DIRECT (DATA_MGR_ITF_WIDTH , 0); // readdata = IORD_32DIRECT (DATA_MGR_DVC_WIDTH , 0); -// +// //} //USER try a read and see if it returns correct data back. has dummy reads inserted into the mix @@ -1615,7 +1615,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group tmp_bit_chk = 0; for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;; vg--) { - //USER reset the fifos to get pointers to known state + //USER reset the fifos to get pointers to known state IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0); IOWR_32DIRECT(RW_MGR_RESET_READ_DATAPATH, 0, 0); @@ -1664,7 +1664,7 @@ static inline uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group, static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t * v) { - //USER fiddle with FIFO + //USER fiddle with FIFO if (HARD_PHY) { IOWR_32DIRECT(PHY_MGR_CMD_INC_VFIFO_HARD_PHY, 0, grp); } else if (QUARTER_RATE_MODE && !HARD_VFIFO) { @@ -1718,11 +1718,11 @@ static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t * v) } } -//USER find a good dqs enable to use +//USER find a good dqs enable to use #if NEWVERSION_DQSEN -// Navid's version +// Navid's version static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) { @@ -1823,7 +1823,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } if (i >= VFIFO_SIZE) { - //USER cannot find working solution + //USER cannot find working solution DPRINT(2, "find_dqs_en_phase: no vfifo/ptap/dtap"); return 0; } @@ -1831,13 +1831,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) work_end = work_bgn; //USER If d is 0 then the working window covers a phase tap and we can follow the old procedure - //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end + //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end if (d == 0) { //USER ******************************************************************** //USER * step 3a: if we have room, back off by one and increment in dtaps * COV(EN_PHASE_PTAP_OVERLAP); - //USER Special case code for backing up a phase + //USER Special case code for backing up a phase if (p == 0) { p = IO_DQS_EN_PHASE_MAX; rw_mgr_decr_vfifo(grp, &v); @@ -1864,7 +1864,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } } - //USER We have found a working dtap before the ptap found above + //USER We have found a working dtap before the ptap found above if (found_begin == 1) { max_working_cnt++; } @@ -1915,14 +1915,14 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } if (i >= VFIFO_SIZE + 1) { - //USER cannot see edge of failing read + //USER cannot see edge of failing read DPRINT(2, "find_dqs_en_phase: end: failed"); return 0; } //USER ********************************************************* //USER * step 5a: back off one from last, increment in dtaps * - //USER Special case code for backing up a phase + //USER Special case code for backing up a phase if (p == 0) { p = IO_DQS_EN_PHASE_MAX; rw_mgr_decr_vfifo(grp, &v); @@ -1941,7 +1941,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } else { //USER ******************************************************************** - //USER * step 3-5b: Find the right edge of the window using delay taps * + //USER * step 3-5b: Find the right edge of the window using delay taps * COV(EN_PHASE_PTAP_NO_OVERLAP); DPRINT(2, "find_dqs_en_phase: begin found: vfifo=%lu ptap=%lu dtap=%lu begin=%lu", @@ -1956,7 +1956,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) //USER * The actual increment of dtaps is done outside of the if/else loop to share code //USER Only here to counterbalance a subtract later on which is not needed if this branch - //USER of the algorithm is taken + //USER of the algorithm is taken max_working_cnt++; } @@ -1971,7 +1971,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } } - //USER Go back to working dtap + //USER Go back to working dtap if (d != 0) { work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP; } @@ -1984,9 +1984,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) BFM_GBL_SET(dqs_enable_right_edge[grp].ps, work_end); if (work_end >= work_bgn) { - //USER we have a working range + //USER we have a working range } else { - //USER nil range + //USER nil range DPRINT(2, "find_dqs_en_phase: end-2: failed"); return 0; } @@ -1995,12 +1995,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) // *************************************************************** //USER * We need to calculate the number of dtaps that equal a ptap - //USER * To do that we'll back up a ptap and re-find the edge of the + //USER * To do that we'll back up a ptap and re-find the edge of the //USER * window using dtaps DPRINT(2, "find_dqs_en_phase: calculate dtaps_per_ptap for tracking"); - //USER Special case code for backing up a phase + //USER Special case code for backing up a phase if (p == 0) { p = IO_DQS_EN_PHASE_MAX; rw_mgr_decr_vfifo(grp, &v); @@ -2033,7 +2033,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } if (found_passing_read) { - //USER Find a failing read + //USER Find a failing read DPRINT(2, "find_dqs_en_phase: find failing read"); for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) { DPRINT(2, "find_dqs_en_phase: testing read d=%lu", d); @@ -2069,7 +2069,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) tmp_delay = 0; DPRINT(2, "work_bgn=%ld work_end=%ld work_mid=%ld", work_bgn, work_end, work_mid); - //USER Get the middle delay to be less than a VFIFO delay + //USER Get the middle delay to be less than a VFIFO delay for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++, tmp_delay += IO_DELAY_PER_OPA_TAP) ; DPRINT(2, "vfifo ptap delay %ld", tmp_delay); while (work_mid > tmp_delay) @@ -2113,7 +2113,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } #if 0 -// Ryan's algorithm +// Ryan's algorithm static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) { @@ -2201,20 +2201,20 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } if (i >= VFIFO_SIZE) { - //USER cannot find working solution + //USER cannot find working solution return 0; } min_working_p = p; //USER If d is 0 then the working window covers a phase tap and we can follow the old procedure - //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end + //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end if (d == 0) { //USER ******************************************************************** //USER * step 3a: if we have room, back off by one and increment in dtaps * min_working_d = 0; - //USER Special case code for backing up a phase + //USER Special case code for backing up a phase if (p == 0) { p = IO_DQS_EN_PHASE_MAX; rw_mgr_decr_vfifo(grp, &v); @@ -2235,12 +2235,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } } - //USER We have found a working dtap before the ptap found above + //USER We have found a working dtap before the ptap found above if (found_begin == 1) { min_working_p = p; max_working_cnt++; } - //USER Restore VFIFO to old state before we decremented it + //USER Restore VFIFO to old state before we decremented it p = p + 1; if (p > IO_DQS_EN_PHASE_MAX) { p = 0; @@ -2284,14 +2284,14 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } if (i >= VFIFO_SIZE + 1) { - //USER cannot see edge of failing read + //USER cannot see edge of failing read return 0; } //USER ********************************************************* //USER * step 5a: back off one from last, increment in dtaps * max_working_d = 0; - //USER Special case code for backing up a phase + //USER Special case code for backing up a phase if (p == 0) { p = IO_DQS_EN_PHASE_MAX; rw_mgr_decr_vfifo(grp, &v); @@ -2311,7 +2311,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } } - //USER Go back to working dtap + //USER Go back to working dtap if (d != 0) { max_working_d = d - 1; } @@ -2319,7 +2319,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } else { //USER ******************************************************************** - //USER * step 3-5b: Find the right edge of the window using delay taps * + //USER * step 3-5b: Find the right edge of the window using delay taps * max_working_p = min_working_p; min_working_d = d; @@ -2333,12 +2333,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } } - //USER Go back to working dtap + //USER Go back to working dtap if (d != 0) { max_working_d = d - 1; } //USER Only here to counterbalance a subtract later on which is not needed if this branch - //USER of the algorithm is taken + //USER of the algorithm is taken max_working_cnt++; } @@ -2346,11 +2346,11 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) //USER * step 6: Find the centre of the window * //USER If the number of working phases is even we will step back a phase and find the - //USER edge with a larger delay chain tap + //USER edge with a larger delay chain tap if ((max_working_cnt & 1) == 0) { p = min_working_p + (max_working_cnt - 1) / 2; - //USER Special case code for backing up a phase + //USER Special case code for backing up a phase if (max_working_p == 0) { max_working_p = IO_DQS_EN_PHASE_MAX; rw_mgr_decr_vfifo(grp, &v); @@ -2378,7 +2378,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } } - //USER Go back to working dtap + //USER Go back to working dtap if (d != 0) { max_working_d = d - 1; } @@ -2395,7 +2395,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) scc_mgr_set_dqs_en_phase_all_ranks(grp, p); scc_mgr_set_dqs_en_delay_all_ranks(grp, d); - //USER push vfifo until we can successfully calibrate + //USER push vfifo until we can successfully calibrate for (i = 0; i < VFIFO_SIZE; i++) { if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { @@ -2415,7 +2415,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) #endif #else -// Val's original version +// Val's original version static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) { @@ -2432,7 +2432,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) fail_cnt = 0; - //USER first push vfifo until we get a failing read + //USER first push vfifo until we get a failing read v = 0; for (i = 0; i < VFIFO_SIZE; i++) { if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) { @@ -2462,7 +2462,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) rw_mgr_mem_calibrate_read_test_all_ranks(grp, NUM_READ_PB_TESTS, PASS_ONE_BIT, &bit_chk, 0); if (bit_chk) { - //USER passing read + //USER passing read if (max_working_cnt == 0) { min_working_d = d; @@ -2471,7 +2471,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) max_working_cnt++; } else { if (max_working_cnt > 0) { - //USER already have one working value + //USER already have one working value break; } } @@ -2481,7 +2481,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) //USER fiddle with FIFO rw_mgr_incr_vfifo(grp, &v); } else { - //USER found working solution! + //USER found working solution! d = min_working_d + (max_working_cnt - 1) / 2; @@ -2494,16 +2494,16 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) } if (i >= VFIFO_SIZE + 1) { - //USER cannot find working solution or cannot see edge of failing read + //USER cannot find working solution or cannot see edge of failing read return 0; } - //USER in the case the number of working steps is even, use 50ps taps to further center the window + //USER in the case the number of working steps is even, use 50ps taps to further center the window if ((max_working_cnt & 1) == 0) { delay_per_ptap_mid = IO_DELAY_PER_OPA_TAP / 2; - //USER increment in 50ps taps until we reach the required amount + //USER increment in 50ps taps until we reach the required amount for (i = 0, j = 0; i <= IO_DQS_EN_DELAY_MAX && j < delay_per_ptap_mid; i++, j += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) ; @@ -2513,7 +2513,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp) scc_mgr_set_dqs_en_phase_all_ranks(grp, d); - //USER push vfifo until we can successfully calibrate + //USER push vfifo until we can successfully calibrate for (i = 0; i < VFIFO_SIZE; i++) { if (rw_mgr_mem_calibrate_read_test_all_ranks @@ -2582,7 +2582,7 @@ static inline uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_ return found; } -//USER per-bit deskew DQ and center +//USER per-bit deskew DQ and center #if NEWVERSION_RDDESKEW @@ -2610,10 +2610,10 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr select_curr_shadow_reg_using_rank(rank_bgn); - //USER per-bit deskew + //USER per-bit deskew - //USER set the left and right edge of each bit to an illegal value - //USER use (IO_IO_IN_DELAY_MAX + 1) as an illegal value + //USER set the left and right edge of each bit to an illegal value + //USER use (IO_IO_IN_DELAY_MAX + 1) as an illegal value sticky_bit_chk = 0; for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { left_edge[i] = IO_IO_IN_DELAY_MAX + 1; @@ -2654,7 +2654,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr //USER Remember a passing test as the left_edge left_edge[i] = d; } else { - //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge + //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge if (left_edge[i] == IO_IO_IN_DELAY_MAX + 1) { right_edge[i] = -(d + 1); } @@ -2667,7 +2667,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr } } - //USER Reset DQ delay chains to 0 + //USER Reset DQ delay chains to 0 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0); sticky_bit_chk = 0; for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) { @@ -2675,14 +2675,14 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr DPRINT(2, "vfifo_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i], i, right_edge[i]); - //USER Check for cases where we haven't found the left edge, which makes our assignment of the the - //USER right edge invalid. Reset it to the illegal value. + //USER Check for cases where we haven't found the left edge, which makes our assignment of the the + //USER right edge invalid. Reset it to the illegal value. if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) { right_edge[i] = IO_IO_IN_DELAY_MAX + 1; DPRINT(2, "vfifo_center: reset right_edge[%lu]: %ld", i, right_edge[i]); } - //USER Reset sticky bit (except for bits where we have seen both the left and right edge) + //USER Reset sticky bit (except for bits where we have seen both the left and right edge) sticky_bit_chk = sticky_bit_chk << 1; if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) && (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) { @@ -2694,7 +2694,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr } } - //USER Search for the right edge of the window for each bit + //USER Search for the right edge of the window for each bit for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) { scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { @@ -2708,7 +2708,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr IOWR_32DIRECT(SCC_MGR_UPD, 0, 0); - //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit if (use_read_test) { stop = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, NUM_READ_PB_TESTS, @@ -2734,11 +2734,11 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr } else { for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { if (bit_chk & 1) { - //USER Remember a passing test as the right_edge + //USER Remember a passing test as the right_edge right_edge[i] = d; } else { if (d != 0) { - //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1) { left_edge[i] = -(d + 1); } @@ -2748,7 +2748,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr && left_edge[i] != IO_IO_IN_DELAY_MAX + 1) { right_edge[i] = -1; } - //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge else if (right_edge[i] == IO_IO_IN_DELAY_MAX + 1) { left_edge[i] = -(d + 1); } @@ -2775,7 +2775,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i] == IO_IO_IN_DELAY_MAX + 1)) { - //USER Restore delay chain settings before letting the loop in + //USER Restore delay chain settings before letting the loop in //USER rw_mgr_mem_calibrate_vfifo to retry different dqs/ck relationships scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs); if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) { @@ -2798,7 +2798,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr } } - //USER Find middle of window for each DQ bit + //USER Find middle of window for each DQ bit mid_min = left_edge[0] - right_edge[0]; min_index = 0; for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) { @@ -2841,13 +2841,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr DPRINT(1, "vfifo_center: start_dqs=%ld start_dqs_en=%ld new_dqs=%ld mid_min=%ld", start_dqs, IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1, new_dqs, mid_min); - //USER Initialize data for export structures + //USER Initialize data for export structures dqs_margin = IO_IO_IN_DELAY_MAX + 1; dq_margin = IO_IO_IN_DELAY_MAX + 1; - //USER add delay to bring centre of all DQ windows to the same "level" + //USER add delay to bring centre of all DQ windows to the same "level" for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { - //USER Use values before divide by 2 to reduce round off error + //USER Use values before divide by 2 to reduce round off error shift_dq = (left_edge[i] - right_edge[i] - (left_edge[min_index] - right_edge[min_index])) / 2 + (orig_mid_min - mid_min); @@ -2866,7 +2866,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr DPRINT(2, "vfifo_center: margin[%lu]=[%ld,%ld]", i, left_edge[i] - shift_dq + (-mid_min), right_edge[i] + shift_dq - (-mid_min)); - //USER To determine values for export structures + //USER To determine values for export structures if (left_edge[i] - shift_dq + (-mid_min) < dq_margin) { dq_margin = left_edge[i] - shift_dq + (-mid_min); } @@ -2889,7 +2889,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t wr scc_mgr_load_dqs(read_group); if (update_fom) { - //USER Export values + //USER Export values gbl->fom_in += (dq_margin + dqs_margin) / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH); @@ -2940,7 +2940,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr } } - //USER determine minimum working value for DQ + //USER determine minimum working value for DQ dq_margin = IO_IO_IN_DELAY_MAX; @@ -2950,7 +2950,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr } } - //USER add delay to bring all DQ windows to the same "level" + //USER add delay to bring all DQ windows to the same "level" for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { if (max_working_dq[i] > dq_margin) { @@ -2981,11 +2981,11 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr scc_mgr_set_dqs_bus_in_delay(grp, start_dqs); - //USER margin on the DQS pin + //USER margin on the DQS pin dqs_margin = d - start_dqs - 1; - //USER find mid point, +1 so that we don't go crazy pushing DQ + //USER find mid point, +1 so that we don't go crazy pushing DQ mid = (dq_margin + dqs_margin + 1) / 2; @@ -2993,7 +2993,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr // TCLRPT_SET(debug_summary_report->fom_in, debug_summary_report->fom_in + (dq_margin + dqs_margin)); // TCLRPT_SET(debug_cal_report->cal_status_per_group[grp].fom_in, (dq_margin + dqs_margin)); - //USER center DQS ... if the headroom is setup properly we shouldn't need to + //USER center DQS ... if the headroom is setup properly we shouldn't need to if (dqs_margin > mid) { scc_mgr_set_dqs_bus_in_delay(grp, READ_SCC_DQS_IN_DELAY(grp) + dqs_margin - mid); @@ -3011,7 +3011,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr scc_mgr_load_dqs(grp); - //USER center DQ + //USER center DQ if (dq_margin > mid) { for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) { @@ -3032,7 +3032,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn, uint32_t gr #endif //USER calibrate the read valid prediction FIFO. -//USER +//USER //USER - read valid prediction will consist of finding a good DQS enable phase, DQS enable delay, DQS input phase, and DQS input delay. //USER - we also do a per-bit deskew on the DQ lines. @@ -3050,7 +3050,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bg uint32_t failed_substage; uint32_t dqs_in_dtaps, orig_start_dqs; - //USER update info for sims + //USER update info for sims reg_file_set_stage(CAL_STAGE_VFIFO); @@ -3074,7 +3074,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bg dtaps_per_ptap--; tmp_delay = 0; } - //USER update info for sims + //USER update info for sims reg_file_set_group(read_group); @@ -3095,7 +3095,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bg } for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) { - //USER set a particular dqdqs phase + //USER set a particular dqdqs phase if (DDRX) { scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p); } @@ -3111,7 +3111,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group, uint32_t test_bg BFM_GBL_SET(gwrite_pos[read_group].p, p); BFM_GBL_SET(gwrite_pos[read_group].d, d); - //USER Load up the patterns used by read calibration using current DQDQS phase + //USER Load up the patterns used by read calibration using current DQDQS phase rw_mgr_mem_calibrate_read_load_patterns_all_ranks(); @@ -3209,7 +3209,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn) uint32_t grp_calibrated; uint32_t failed_substage; - //USER update info for sims + //USER update info for sims reg_file_set_stage(CAL_STAGE_VFIFO); @@ -3217,18 +3217,18 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t g, uint32_t test_bgn) failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; - //USER update info for sims + //USER update info for sims reg_file_set_group(g); grp_calibrated = 0; for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) { - //USER set a particular dqdqs phase + //USER set a particular dqdqs phase if (DDRX) { scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); } - //USER Load up the patterns used by read calibration using current DQDQS phase + //USER Load up the patterns used by read calibration using current DQDQS phase rw_mgr_mem_calibrate_read_load_patterns_all_ranks(); if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) { @@ -3280,7 +3280,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t tes uint32_t grp_calibrated; uint32_t write_group; - //USER update info for sims + //USER update info for sims reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); @@ -3292,7 +3292,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group, uint32_t tes read_group / (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH); } - //USER update info for sims + //USER update info for sims reg_file_set_group(read_group); grp_calibrated = 1; @@ -3330,7 +3330,7 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void) uint32_t found_one; t_btfld bit_chk; - //USER update info for sims + //USER update info for sims reg_file_set_stage(CAL_STAGE_LFIFO); reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY); @@ -3358,12 +3358,12 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void) gbl->curr_read_lat--; } while (gbl->curr_read_lat > 0); - //USER reset the fifos to get pointers to known state + //USER reset the fifos to get pointers to known state IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0); if (found_one) { - //USER add a fudge factor to the read latency that was determined + //USER add a fudge factor to the read latency that was determined gbl->curr_read_lat += 2; IOWR_32DIRECT(PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); @@ -3508,13 +3508,13 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn, uint32_t writ continue; } - //USER set rank + //USER set rank set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); tmp_bit_chk = 0; for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS - 1;; vg--) { - //USER reset the fifos to get pointers to known state + //USER reset the fifos to get pointers to known state IOWR_32DIRECT(PHY_MGR_CMD_FIFO_RESET, 0, 0); tmp_bit_chk = @@ -3584,24 +3584,24 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) reg_file_set_stage(CAL_STAGE_WLEVEL); reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); - //USER maximum phases for the sweep + //USER maximum phases for the sweep dtaps_per_ptap = IORD_32DIRECT(REG_FILE_DTAPS_PER_PTAP, 0); - //USER starting phases + //USER starting phases //USER update info for sims reg_file_set_group(g); - //USER starting and end range where writes work + //USER starting and end range where writes work scc_mgr_spread_out2_delay_all_ranks(g, test_bgn); work_bgn = 0; work_end = 0; - //USER step 1: find first working phase, increment in ptaps, and then in dtaps if ptaps doesn't find a working phase + //USER step 1: find first working phase, increment in ptaps, and then in dtaps if ptaps doesn't find a working phase found_begin = 0; tmp_delay = 0; for (d = 0; d <= dtaps_per_ptap; d++, tmp_delay += IO_DELAY_PER_DCHAIN_TAP) { @@ -3627,7 +3627,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) } if (p > IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles * IO_DLL_CHAIN_LENGTH) { - //USER fail, cannot find first working phase + //USER fail, cannot find first working phase set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); @@ -3639,12 +3639,12 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY); //USER If d is 0 then the working window covers a phase tap and we can follow the old procedure - //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end + //USER otherwise, we've found the beginning, and we need to increment the dtaps until we find the end if (d == 0) { COV(WLEVEL_PHASE_PTAP_OVERLAP); work_end = work_bgn + IO_DELAY_PER_OPA_TAP; - //USER step 2: if we have room, back off by one and increment in dtaps + //USER step 2: if we have room, back off by one and increment in dtaps if (p > 0) { int found = 0; @@ -3693,7 +3693,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) BFM_GBL_SET(dqs_wlevel_left_edge[g].ps, work_bgn); } - //USER step 3: go forward from working phase to non working phase, increment in ptaps + //USER step 3: go forward from working phase to non working phase, increment in ptaps for (p = p + 1; p <= IO_DQDQS_OUT_PHASE_MAX + num_additional_fr_cycles * IO_DLL_CHAIN_LENGTH; @@ -3707,7 +3707,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) } } - //USER step 4: back off one from last, increment in dtaps + //USER step 4: back off one from last, increment in dtaps //USER The actual increment is done outside the if/else statement since it is shared with other code p = p - 1; @@ -3743,9 +3743,9 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) work_end -= IO_DELAY_PER_DCHAIN_TAP; if (work_end >= work_bgn) { - //USER we have a working range + //USER we have a working range } else { - //USER nil range + //USER nil range set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY); @@ -3757,7 +3757,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) BFM_GBL_SET(dqs_wlevel_right_edge[g].d, d - 1); BFM_GBL_SET(dqs_wlevel_right_edge[g].ps, work_end); - //USER center + //USER center work_mid = (work_bgn + work_end) / 2; @@ -3819,20 +3819,20 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) reg_file_set_stage(CAL_STAGE_WLEVEL); reg_file_set_sub_stage(CAL_SUBSTAGE_WORKING_DELAY); - //USER maximum phases for the sweep + //USER maximum phases for the sweep - //USER starting phases + //USER starting phases //USER update info for sims reg_file_set_group(g); - //USER starting and end range where writes work + //USER starting and end range where writes work work_bgn = 0; work_end = 0; - //USER step 1: find first working phase, increment in ptaps + //USER step 1: find first working phase, increment in ptaps for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++, work_bgn += IO_DELAY_PER_OPA_TAP) { scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); @@ -3843,7 +3843,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) } if (p > IO_DQDQS_OUT_PHASE_MAX) { - //USER fail, cannot find first working phase + //USER fail, cannot find first working phase set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_WORKING_DELAY); @@ -3854,7 +3854,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) reg_file_set_sub_stage(CAL_SUBSTAGE_LAST_WORKING_DELAY); - //USER step 2: if we have room, back off by one and increment in dtaps + //USER step 2: if we have room, back off by one and increment in dtaps if (p > 0) { scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1); @@ -3873,7 +3873,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, 0); } - //USER step 3: go forward from working phase to non working phase, increment in ptaps + //USER step 3: go forward from working phase to non working phase, increment in ptaps for (p = p + 1; p <= IO_DQDQS_OUT_PHASE_MAX; p++, work_end += IO_DELAY_PER_OPA_TAP) { scc_mgr_set_dqdqs_output_phase_all_ranks(g, p); @@ -3883,7 +3883,7 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) } } - //USER step 4: back off one from last, increment in dtaps + //USER step 4: back off one from last, increment in dtaps scc_mgr_set_dqdqs_output_phase_all_ranks(g, p - 1); @@ -3900,16 +3900,16 @@ static uint32_t rw_mgr_mem_calibrate_wlevel(uint32_t g, uint32_t test_bgn) scc_mgr_apply_group_all_out_delay_all_ranks(g, test_bgn, 0); if (work_end > work_bgn) { - //USER we have a working range + //USER we have a working range } else { - //USER nil range + //USER nil range set_failing_group_stage(g, CAL_STAGE_WLEVEL, CAL_SUBSTAGE_LAST_WORKING_DELAY); return 0; } - //USER center + //USER center work_mid = (work_bgn + work_end) / 2; @@ -3963,9 +3963,9 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w select_curr_shadow_reg_using_rank(rank_bgn); - //USER per-bit deskew + //USER per-bit deskew - //USER set the left and right edge of each bit to an illegal value + //USER set the left and right edge of each bit to an illegal value //USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value sticky_bit_chk = 0; for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { @@ -3979,7 +3979,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w IOWR_32DIRECT(SCC_MGR_UPD, 0, 0); - //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); @@ -3998,7 +3998,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w //USER Remember a passing test as the left_edge left_edge[i] = d; } else { - //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge + //USER If a left edge has not been seen yet, then a future passing test will mark this edge as the right edge if (left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { right_edge[i] = -(d + 1); } @@ -4011,7 +4011,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w } } - //USER Reset DQ delay chains to 0 + //USER Reset DQ delay chains to 0 scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0); sticky_bit_chk = 0; for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) { @@ -4019,14 +4019,14 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w DPRINT(2, "write_center: left_edge[%lu]: %ld right_edge[%lu]: %ld", i, left_edge[i], i, right_edge[i]); - //USER Check for cases where we haven't found the left edge, which makes our assignment of the the - //USER right edge invalid. Reset it to the illegal value. + //USER Check for cases where we haven't found the left edge, which makes our assignment of the the + //USER right edge invalid. Reset it to the illegal value. if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) && (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) { right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1; DPRINT(2, "write_center: reset right_edge[%lu]: %ld", i, right_edge[i]); } - //USER Reset sticky bit (except for bits where we have seen the left edge) + //USER Reset sticky bit (except for bits where we have seen the left edge) sticky_bit_chk = sticky_bit_chk << 1; if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) { sticky_bit_chk = sticky_bit_chk | 1; @@ -4037,7 +4037,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w } } - //USER Search for the right edge of the window for each bit + //USER Search for the right edge of the window for each bit for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) { scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, d + start_dqs); @@ -4045,7 +4045,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w if (QDRII) { rw_mgr_mem_dll_lock_wait(); } - //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit + //USER Stop searching when the read test doesn't pass AND when we've seen a passing read on every bit stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, PASS_ONE_BIT, &bit_chk, 0); @@ -4072,11 +4072,11 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w } else { for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { if (bit_chk & 1) { - //USER Remember a passing test as the right_edge + //USER Remember a passing test as the right_edge right_edge[i] = d; } else { if (d != 0) { - //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { left_edge[i] = -(d + 1); } @@ -4086,7 +4086,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w && left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1) { right_edge[i] = -1; } - //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge + //USER If a right edge has not been seen yet, then a future passing test will mark this edge as the left edge else if (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) { left_edge[i] = -(d + 1); } @@ -4114,7 +4114,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w } } - //USER Find middle of window for each DQ bit + //USER Find middle of window for each DQ bit mid_min = left_edge[0] - right_edge[0]; min_index = 0; for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { @@ -4142,13 +4142,13 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w DPRINT(1, "write_center: start_dqs=%ld new_dqs=%ld mid_min=%ld", start_dqs, new_dqs, mid_min); - //USER Initialize data for export structures + //USER Initialize data for export structures dqs_margin = IO_IO_OUT1_DELAY_MAX + 1; dq_margin = IO_IO_OUT1_DELAY_MAX + 1; - //USER add delay to bring centre of all DQ windows to the same "level" + //USER add delay to bring centre of all DQ windows to the same "level" for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { - //USER Use values before divide by 2 to reduce round off error + //USER Use values before divide by 2 to reduce round off error shift_dq = (left_edge[i] - right_edge[i] - (left_edge[min_index] - right_edge[min_index])) / 2 + (orig_mid_min - mid_min); @@ -4166,7 +4166,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w DPRINT(2, "write_center: margin[%lu]=[%ld,%ld]", i, left_edge[i] - shift_dq + (-mid_min), right_edge[i] + shift_dq - (-mid_min)); - //USER To determine values for export structures + //USER To determine values for export structures if (left_edge[i] - shift_dq + (-mid_min) < dq_margin) { dq_margin = left_edge[i] - shift_dq + (-mid_min); } @@ -4175,7 +4175,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w } } - //USER Move DQS + //USER Move DQS if (QDRII) { scc_mgr_set_group_dqs_io_and_oct_out1_gradual(write_group, new_dqs); } else { @@ -4185,7 +4185,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w DPRINT(2, "write_center: DM"); - //USER set the left and right edge of each bit to an illegal value + //USER set the left and right edge of each bit to an illegal value //USER use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1; @@ -4204,7 +4204,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1) { bgn_curr = -d; } - //USER If current window is bigger than best seen. Set best seen to be current window + //USER If current window is bigger than best seen. Set best seen to be current window if ((end_curr - bgn_curr + 1) > win_best) { win_best = end_curr - bgn_curr + 1; bgn_best = bgn_curr; @@ -4296,7 +4296,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w DPRINT(2, "dm_calib: left=%ld right=%ld mid=%ld dm_margin=%ld", left_edge[0], right_edge[0], mid, dm_margin); - //USER Export values + //USER Export values gbl->fom_out += dq_margin + dqs_margin; DPRINT(2, "write_center: dq_margin=%ld dqs_margin=%ld dm_margin=%ld", dq_margin, dqs_margin, @@ -4321,7 +4321,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w uint32_t start_dqs; uint32_t stop; - //USER per-bit deskew + //USER per-bit deskew for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) { max_working_dq[i] = 0; @@ -4347,7 +4347,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0); - //USER determine minimum of maximums + //USER determine minimum of maximums dq_margin = IO_IO_OUT1_DELAY_MAX; @@ -4357,7 +4357,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w } } - //USER add delay to center DQ windows + //USER add delay to center DQ windows for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { if (max_working_dq[i] > dq_margin) { @@ -4393,7 +4393,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w dqs_margin = d - start_dqs - 1; - //USER time to center, +1 so that we don't go crazy centering DQ + //USER time to center, +1 so that we don't go crazy centering DQ mid = (dq_margin + dqs_margin + 1) / 2; @@ -4402,7 +4402,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w scc_mgr_load_dqs_io(); scc_mgr_load_dqs_for_write_group(write_group); - //USER center dq + //USER center dq if (dq_margin > mid) { for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { @@ -4413,7 +4413,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn, uint32_t w dqs_margin += dq_margin - mid; dq_margin -= dq_margin - mid; } - //USER do dm centering + //USER do dm centering if (!RLDRAMX) { dm_margin = IO_IO_OUT1_DELAY_MAX; @@ -4496,7 +4496,7 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint3 reg_file_set_stage(CAL_STAGE_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER); - //USER starting phases + //USER starting phases //USER update info for sims @@ -4510,7 +4510,7 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g, uint3 return 1; } -//USER precharge all banks and activate row 0 in bank "000..." and bank "111..." +//USER precharge all banks and activate row 0 in bank "000..." and bank "111..." static void mem_precharge_and_activate(void) { uint32_t r; @@ -4524,7 +4524,7 @@ static void mem_precharge_and_activate(void) //USER set rank set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); - //USER precharge all banks ... + //USER precharge all banks ... IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_PRECHARGE_ALL); IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, 0x0F); @@ -4533,7 +4533,7 @@ static void mem_precharge_and_activate(void) IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, 0x0F); IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_ACTIVATE_0_AND_1_WAIT2); - //USER activate rows + //USER activate rows IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_ACTIVATE_0_AND_1); } } @@ -4548,7 +4548,7 @@ static void mem_config(void) uint32_t rw_wl_nop_cycles; uint32_t max_latency; - //USER read in write and read latency + //USER read in write and read latency wlat = IORD_32DIRECT(MEM_T_WL_ADD, 0); wlat += IORD_32DIRECT(DATA_MGR_MEM_T_ADD, 0); /* WL for hard phy does not include additive latency */ @@ -4595,23 +4595,23 @@ static void mem_config(void) //USER configure for a burst length of 8 if (QUARTER_RATE_MODE) { - //USER write latency + //USER write latency wlat = (wlat + 5) / 4 + 1; //USER set a pretty high read latency initially gbl->curr_read_lat = (rlat + 1) / 4 + 8; } else if (HALF_RATE_MODE) { - //USER write latency + //USER write latency wlat = (wlat - 1) / 2 + 1; - //USER set a pretty high read latency initially + //USER set a pretty high read latency initially gbl->curr_read_lat = (rlat + 1) / 2 + 8; } else { - //USER write latency + //USER write latency // Adjust Write Latency for Hard PHY wlat = wlat + 1; - //USER set a pretty high read latency initially + //USER set a pretty high read latency initially gbl->curr_read_lat = rlat + 16; } @@ -4620,7 +4620,7 @@ static void mem_config(void) } IOWR_32DIRECT(PHY_MGR_PHY_RLAT, 0, gbl->curr_read_lat); - //USER advertise write latency + //USER advertise write latency gbl->curr_write_lat = wlat; IOWR_32DIRECT(PHY_MGR_AFI_WLAT, 0, wlat - 2); @@ -4636,7 +4636,7 @@ static void mem_skip_calibrate(void) uint32_t vfifo_offset; uint32_t i, j, r; - // Need to update every shadow register set used by the interface + // Need to update every shadow register set used by the interface for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r += NUM_RANKS_PER_SHADOW_REG) { // Strictly speaking this should be called once per group to make @@ -4653,7 +4653,7 @@ static void mem_skip_calibrate(void) // // Write data arrives to the I/O two cycles before write latency is reached (720 deg). // -> due to bit-slip in a/c bus - // -> to allow board skew where dqs is longer than ck + // -> to allow board skew where dqs is longer than ck // -> how often can this happen!? // -> can claim back some ptaps for high freq support if we can relax this, but i digress... // @@ -4683,7 +4683,7 @@ static void mem_skip_calibrate(void) IOWR_32DIRECT(SCC_MGR_UPD, 0, 0); } - // Compensate for simulation model behaviour + // Compensate for simulation model behaviour for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) { scc_mgr_set_dqs_bus_in_delay(i, 10); scc_mgr_load_dqs(i); @@ -4741,7 +4741,7 @@ static uint32_t mem_calibrate(void) } if (((DYNAMIC_CALIB_STEPS) & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { - //USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode + //USER Set VFIFO and LFIFO to instant-on settings in skip calibration mode mem_skip_calibrate(); } else { @@ -4781,7 +4781,7 @@ static uint32_t mem_calibrate(void) RW_MGR_MEM_IF_WRITE_DQS_WIDTH && group_failed == 0; read_group++, read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) { - //USER Calibrate the VFIFO + //USER Calibrate the VFIFO if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_VFIFO)) { if (!rw_mgr_mem_calibrate_vfifo (read_group, read_test_bgn)) { @@ -4797,7 +4797,7 @@ static uint32_t mem_calibrate(void) } } - //USER level writes (or align DK with CK for RLDRAMX) + //USER level writes (or align DK with CK for RLDRAMX) if (group_failed == 0) { if ((DDRX || RLDRAMII) && !(ARRIAV || CYCLONEV)) { if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_WLEVEL)) { @@ -4815,7 +4815,7 @@ static uint32_t mem_calibrate(void) } } } - //USER Calibrate the output side + //USER Calibrate the output side if (group_failed == 0) { for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS; @@ -4899,7 +4899,7 @@ static uint32_t mem_calibrate(void) if (failing_groups != 0) { return 0; } - //USER Calibrate the LFIFO + //USER Calibrate the LFIFO if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) { //USER If we're skipping groups as part of debug, don't calibrate LFIFO if (param->skip_groups == 0) { @@ -4952,7 +4952,7 @@ static uint32_t run_mem_calibrate(void) #endif } - //USER Handoff + //USER Handoff //USER Don't return control of the PHY back to AFI when in debug mode if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) { @@ -5045,7 +5045,7 @@ static void initialize_hps_phy(void) // These may need to be included also: // wrap_back_en (false) // atpg_en (false) - // pipelineglobalenable (true) + // pipelineglobalenable (true) uint32_t reg; // Tracking also gets configured here because it's in the same register @@ -5148,7 +5148,7 @@ static int socfpga_mem_calibration(void) // Set the calibration enabled by default gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; // Only enable margining by default if requested - // Only sweep all groups (regardless of fail state) by default if requested + // Only sweep all groups (regardless of fail state) by default if requested //Set enabled read test by default // Initialize the register file diff --git a/arch/arm/mach-socfpga/xload.c b/arch/arm/mach-socfpga/xload.c index fd0d777add..7f8f0320ca 100644 --- a/arch/arm/mach-socfpga/xload.c +++ b/arch/arm/mach-socfpga/xload.c @@ -2,7 +2,7 @@ #include <platform_data/dw_mmc.h> #include <bootsource.h> #include <bootstrap.h> -#include <ns16550.h> +#include <platform_data/serial-ns16550.h> #include <common.h> #include <malloc.h> #include <init.h> diff --git a/arch/arm/mach-tegra/tegra20.c b/arch/arm/mach-tegra/tegra20.c index 8d1cd5b2fb..10c149a955 100644 --- a/arch/arm/mach-tegra/tegra20.c +++ b/arch/arm/mach-tegra/tegra20.c @@ -16,7 +16,6 @@ #include <common.h> #include <init.h> -#include <ns16550.h> #include <asm/memory.h> #include <mach/iomap.h> #include <mach/lowlevel.h> |