diff options
Diffstat (limited to 'arch/arm')
95 files changed, 572 insertions, 199 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index de45bcf82a..b227bb78b6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -314,6 +314,24 @@ source "arch/arm/mach-zynq/Kconfig" source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-zynqmp/Kconfig" +config BOARD_ARM_GENERIC_DT + select LIBFDT + select ARM_AMBA + depends on HAVE_PBL_MULTI_IMAGES + depends on OFDEVICE + bool "Build generic ARM device tree 2nd stage image" + help + This enables compilation of a generic image that can be started 2nd + stage from barebox or from qemu. It picks up a device tree passed + in r2 like the Kernel does, so it could be used anywhere where a Kernel + image could be used. The image will be called images/barebox-dt-2nd.img + +config BOARD_ARM_GENERIC_DT_AARCH64 + bool + depends on CPU_V8 + depends on BOARD_ARM_GENERIC_DT + default y + config ARM_ASM_UNIFIED bool @@ -399,12 +417,14 @@ config ARM_OPTIMZED_STRING_FUNCTIONS increase your binary size. config ARM_EXCEPTIONS + select ARCH_HAS_DATA_ABORT_MASK bool "enable arm exception handling support" default y config ARM_UNWIND bool "enable stack unwinding support" depends on AEABI + select ARCH_HAS_STACK_DUMP help This option enables stack unwinding support in barebox using the information automatically generated by the diff --git a/arch/arm/boards/animeo_ip/lowlevel.c b/arch/arm/boards/animeo_ip/lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/animeo_ip/lowlevel.c +++ b/arch/arm/boards/animeo_ip/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/at91sam9260ek/lowlevel.c b/arch/arm/boards/at91sam9260ek/lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/at91sam9260ek/lowlevel.c +++ b/arch/arm/boards/at91sam9260ek/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c index 0d7f6d6590..bb9b905c65 100644 --- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c +++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c @@ -121,7 +121,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE); at91sam9261ek_init(); } diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c index f5d68cd7e8..ba0ae39c7f 100644 --- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c +++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c @@ -123,7 +123,7 @@ ENTRY_FUNCTION(start_at91sam9263ek, r0, r1, r2) arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16); + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE); if (IS_ENABLED(CONFIG_MACH_AT91SAM9263EK_DT)) fdt = __dtb_at91sam9263ek_start + get_runtime_offset(); diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c index 1d83cdf0bf..0f3a035d1d 100644 --- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c +++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1), NULL); diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c index 4ccbb93557..e07ff892cd 100644 --- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c +++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1), NULL); diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c index f57e439b9e..5bc18f8fca 100644 --- a/arch/arm/boards/at91sam9n12ek/lowlevel.c +++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9N12_SRAM_BASE + AT91SAM9N12_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9N12_SRAM_BASE + AT91SAM9N12_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9n12_get_ddram_size(), NULL); diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c index 50119108c9..9033597e7c 100644 --- a/arch/arm/boards/at91sam9x5ek/lowlevel.c +++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c @@ -14,7 +14,7 @@ ENTRY_FUNCTION(start_at91sam9x5ek, r0, r1, r2) void *fdt; arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9X5_SRAM_BASE + AT91SAM9X5_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9X5_SRAM_BASE + AT91SAM9X5_SRAM_SIZE); fdt = __dtb_at91sam9x5ek_start + get_runtime_offset(); diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c index 462c22e284..adcb30a7ff 100644 --- a/arch/arm/boards/ccxmx51/lowlevel.c +++ b/arch/arm/boards/ccxmx51/lowlevel.c @@ -15,7 +15,7 @@ ENTRY_FUNCTION(start_ccxmx51, r0, r1, r2) imx5_cpu_lowlevel_init(); - arm_setup_stack(0x20000000 - 16); + arm_setup_stack(0x20000000); fdt = __dtb_imx51_ccxmx51_start + get_runtime_offset(); diff --git a/arch/arm/boards/ccxmx53/lowlevel.c b/arch/arm/boards/ccxmx53/lowlevel.c index c27e33098c..1d2d8c6d90 100644 --- a/arch/arm/boards/ccxmx53/lowlevel.c +++ b/arch/arm/boards/ccxmx53/lowlevel.c @@ -37,7 +37,7 @@ ENTRY_FUNCTION(start_ccxmx53_512mb, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); IMD_USED(ccxmx53_memsize_SZ_512M); @@ -51,7 +51,7 @@ ENTRY_FUNCTION(start_ccxmx53_1gib, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); IMD_USED(ccxmx53_memsize_SZ_1G); diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c index 3ecdb66bc5..23074326b5 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c +++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c @@ -145,7 +145,7 @@ ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00940000 - 8); + arm_setup_stack(0x00940000); fdt = __dtb_imx6q_dmo_edmqmx6_start + get_runtime_offset(); diff --git a/arch/arm/boards/dfi-fs700-m60/lowlevel.c b/arch/arm/boards/dfi-fs700-m60/lowlevel.c index b419228505..520ed4c46b 100644 --- a/arch/arm/boards/dfi-fs700-m60/lowlevel.c +++ b/arch/arm/boards/dfi-fs700-m60/lowlevel.c @@ -108,7 +108,7 @@ ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_nanya, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00940000 - 8); + arm_setup_stack(0x00940000); for (i = 0x68; i <= 0x80; i += 4) writel(0xffffffff, MX6_CCM_BASE_ADDR + i); @@ -127,7 +127,7 @@ ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_micron, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00940000 - 8); + arm_setup_stack(0x00940000); for (i = 0x68; i <= 0x80; i += 4) writel(0xffffffff, MX6_CCM_BASE_ADDR + i); @@ -150,7 +150,7 @@ ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); for (i = 0x68; i <= 0x80; i += 4) writel(0xffffffff, MX6_CCM_BASE_ADDR + i); diff --git a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c index ac76a843ac..7bf1db8120 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c +++ b/arch/arm/boards/digi-ccimx6ulsom/lowlevel.c @@ -13,7 +13,7 @@ ENTRY_FUNCTION(start_imx6ul_ccimx6ulsbcpro, r0, r1, r2) imx6ul_cpu_lowlevel_init(); - arm_setup_stack(0x00910000 - 8); + arm_setup_stack(0x00910000); arm_early_mmu_cache_invalidate(); diff --git a/arch/arm/boards/dss11/lowlevel.c b/arch/arm/boards/dss11/lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/dss11/lowlevel.c +++ b/arch/arm/boards/dss11/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/efika-mx-smartbook/lowlevel.c b/arch/arm/boards/efika-mx-smartbook/lowlevel.c index 6da5bfaf55..3881678d85 100644 --- a/arch/arm/boards/efika-mx-smartbook/lowlevel.c +++ b/arch/arm/boards/efika-mx-smartbook/lowlevel.c @@ -12,7 +12,7 @@ ENTRY_FUNCTION(start_imx51_genesi_efikasb, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(0x20000000 - 16); + arm_setup_stack(0x20000000); imx51_init_lowlevel(800); fdt = __dtb_imx51_genesi_efika_sb_start + get_runtime_offset(); diff --git a/arch/arm/boards/eltec-hipercam/lowlevel.c b/arch/arm/boards/eltec-hipercam/lowlevel.c index b0d3155023..2f2cd9aab7 100644 --- a/arch/arm/boards/eltec-hipercam/lowlevel.c +++ b/arch/arm/boards/eltec-hipercam/lowlevel.c @@ -39,7 +39,7 @@ ENTRY_FUNCTION(start_imx6dl_eltec_hipercam, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00940000 - 8); + arm_setup_stack(0x00940000); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 555dd44445..c16316d4a1 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -37,7 +37,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12); + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE); /* restart the MPLL and wait until it's stable */ writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27), diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index be78b48bd0..ab5235f7f0 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -38,7 +38,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE); r = get_cr(); r |= CR_Z; /* Flow prediction (Z) */ diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c index e09f58e29c..6762fdad4b 100644 --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c @@ -6,6 +6,6 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); - arm_setup_stack(0x20000000 - 16); + arm_setup_stack(0x20000000); imx51_barebox_entry(NULL); } diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c index f254db7b7b..e29a647daa 100644 --- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c +++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c @@ -40,7 +40,7 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2) if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); - arm_setup_stack(0x20000000 - 16); + arm_setup_stack(0x20000000); fdt = __dtb_imx51_babbage_start + get_runtime_offset(); diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c index cfe01f7807..c9044011d5 100644 --- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c @@ -13,7 +13,7 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); fdt = __dtb_imx53_qsb_start + get_runtime_offset(); @@ -27,7 +27,7 @@ ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); fdt = __dtb_imx53_qsrb_start + get_runtime_offset(); diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c index c929d274f2..fffbfdf0ba 100644 --- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-smd/lowlevel.c @@ -7,6 +7,6 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); imx53_barebox_entry(NULL); } diff --git a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c index aac784ca6e..ae94538c9e 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c +++ b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c @@ -11,7 +11,7 @@ ENTRY_FUNCTION(start_imx53_vmx53, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(0xf8020000 - 8); + arm_setup_stack(0xf8020000); fdt = __dtb_imx53_voipac_bsb_start + get_runtime_offset(); diff --git a/arch/arm/boards/grinn-liteboard/lowlevel.c b/arch/arm/boards/grinn-liteboard/lowlevel.c index 331ccc2283..bb2e09016e 100644 --- a/arch/arm/boards/grinn-liteboard/lowlevel.c +++ b/arch/arm/boards/grinn-liteboard/lowlevel.c @@ -58,7 +58,7 @@ static void __noreturn start_imx6_liteboard(void) { imx6ul_cpu_lowlevel_init(); - arm_setup_stack(0x00910000 - 8); + arm_setup_stack(0x00910000); arm_early_mmu_cache_invalidate(); diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index e84ae2c415..0d7cfb618c 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -165,7 +165,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(0x10000000 + 128 * 1024 - 16); + arm_setup_stack(0x10000000 + 128 * 1024); /* * ARM1136 init diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index 6c22784599..20f48be7dd 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -39,7 +39,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); /* ahb lite ip interface */ writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); diff --git a/arch/arm/boards/guf-santaro/lowlevel.c b/arch/arm/boards/guf-santaro/lowlevel.c index 1502bb3d38..30c5e9054a 100644 --- a/arch/arm/boards/guf-santaro/lowlevel.c +++ b/arch/arm/boards/guf-santaro/lowlevel.c @@ -35,7 +35,7 @@ ENTRY_FUNCTION(start_imx6q_guf_santaro, r0, r1, r2) { imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); arm_early_mmu_cache_invalidate(); diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c index 715e8b386f..04060b2003 100644 --- a/arch/arm/boards/guf-vincell/lowlevel.c +++ b/arch/arm/boards/guf-vincell/lowlevel.c @@ -21,7 +21,7 @@ static noinline void imx53_guf_vincell_init(void *fdt) void __iomem *ccm = (void *)MX53_CCM_BASE_ADDR; void __iomem *uart = IOMEM(MX53_UART2_BASE_ADDR); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); writel(0x0088494c, ccm + MX5_CCM_CBCDR); writel(0x02b12f0a, ccm + MX5_CCM_CSCMR2); diff --git a/arch/arm/boards/haba-knx/lowlevel.c b/arch/arm/boards/haba-knx/lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/haba-knx/lowlevel.c +++ b/arch/arm/boards/haba-knx/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index 3bbc930931..f79cd91640 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -168,7 +168,7 @@ ENTRY_FUNCTION(start_imx25_karo_tx25, r0, r1, r2) { void *fdt; - arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 8); + arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE); fdt = __dtb_imx25_karo_tx25_start + get_runtime_offset(); diff --git a/arch/arm/boards/karo-tx51/lowlevel.c b/arch/arm/boards/karo-tx51/lowlevel.c index e09f58e29c..6762fdad4b 100644 --- a/arch/arm/boards/karo-tx51/lowlevel.c +++ b/arch/arm/boards/karo-tx51/lowlevel.c @@ -6,6 +6,6 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) { imx5_cpu_lowlevel_init(); - arm_setup_stack(0x20000000 - 16); + arm_setup_stack(0x20000000); imx51_barebox_entry(NULL); } diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c index a0bce8a788..230f60ebd9 100644 --- a/arch/arm/boards/karo-tx53/lowlevel.c +++ b/arch/arm/boards/karo-tx53/lowlevel.c @@ -37,7 +37,7 @@ static void __imx53_tx53_init(int is_xx30) setup_c(); barrier(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); if (is_xx30) { imx53_init_lowlevel_early(800); diff --git a/arch/arm/boards/karo-tx6x/lowlevel.c b/arch/arm/boards/karo-tx6x/lowlevel.c index 7b58a496ef..f0ddac284c 100644 --- a/arch/arm/boards/karo-tx6x/lowlevel.c +++ b/arch/arm/boards/karo-tx6x/lowlevel.c @@ -46,7 +46,7 @@ ENTRY_FUNCTION(start_imx6dl_tx6x_512m, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); IMD_USED(tx6x_mx6_memsize_512M); @@ -66,7 +66,7 @@ ENTRY_FUNCTION(start_imx6dl_tx6x_1g, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); IMD_USED(tx6x_mx6_memsize_1G); @@ -86,7 +86,7 @@ ENTRY_FUNCTION(start_imx6q_tx6x_1g, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); IMD_USED(tx6x_mx6_memsize_1G); @@ -106,7 +106,7 @@ ENTRY_FUNCTION(start_imx6q_tx6x_2g, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); IMD_USED(tx6x_mx6_memsize_2G); diff --git a/arch/arm/boards/kindle-mx50/lowlevel.c b/arch/arm/boards/kindle-mx50/lowlevel.c index 20f86c8fcb..992d1fd1a8 100644 --- a/arch/arm/boards/kindle-mx50/lowlevel.c +++ b/arch/arm/boards/kindle-mx50/lowlevel.c @@ -18,7 +18,7 @@ ENTRY_FUNCTION(start_imx50_kindle_d01100, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8); + arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE); fdt = __dtb_imx50_kindle_d01100_start + get_runtime_offset(); @@ -30,7 +30,7 @@ ENTRY_FUNCTION(start_imx50_kindle_d01200, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8); + arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE); fdt = __dtb_imx50_kindle_d01200_start + get_runtime_offset(); @@ -42,7 +42,7 @@ ENTRY_FUNCTION(start_imx50_kindle_ey21, r0, r1, r2) void *fdt; imx5_cpu_lowlevel_init(); - arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE - 8); + arm_setup_stack(MX50_IRAM_BASE_ADDR + MX50_IRAM_SIZE); fdt = __dtb_imx50_kindle_ey21_start + get_runtime_offset(); diff --git a/arch/arm/boards/kindle3/lowlevel.c b/arch/arm/boards/kindle3/lowlevel.c index 689767f8d6..19b95fc376 100644 --- a/arch/arm/boards/kindle3/lowlevel.c +++ b/arch/arm/boards/kindle3/lowlevel.c @@ -39,7 +39,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE); r = get_cr(); r |= CR_Z; /* Flow prediction (Z) */ diff --git a/arch/arm/boards/kontron-samx6i/lowlevel.c b/arch/arm/boards/kontron-samx6i/lowlevel.c index 9742469e20..afb7372323 100644 --- a/arch/arm/boards/kontron-samx6i/lowlevel.c +++ b/arch/arm/boards/kontron-samx6i/lowlevel.c @@ -42,7 +42,7 @@ static void __noreturn start_imx6_samx6i_common(void *fdt_blob_fixed_offset) size = samx6i_get_size(); imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c index 639958a459..0ce2b299ed 100644 --- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c +++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c @@ -20,7 +20,7 @@ ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2) arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); fdt = __dtb_at91_microchip_ksz9477_evb_start + get_runtime_offset(); diff --git a/arch/arm/boards/mx31moboard/lowlevel.c b/arch/arm/boards/mx31moboard/lowlevel.c index c93f76265c..307975d78c 100644 --- a/arch/arm/boards/mx31moboard/lowlevel.c +++ b/arch/arm/boards/mx31moboard/lowlevel.c @@ -107,7 +107,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); /* Temporary stack location in internal SRAM */ - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8); + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE); mx31moboard_startup(); } diff --git a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c index bb2e3623dc..cc0b98e1d8 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c @@ -56,7 +56,7 @@ ENTRY_FUNCTION(start_nxp_imx6ull_evk, r0, r1, r2) imx6ul_cpu_lowlevel_init(); - arm_setup_stack(0x00910000 - 8); + arm_setup_stack(0x00910000); arm_early_mmu_cache_invalidate(); diff --git a/arch/arm/boards/nxp-imx8mq-evk/Makefile b/arch/arm/boards/nxp-imx8mq-evk/Makefile index 7907de411f..2995f06f0f 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/Makefile +++ b/arch/arm/boards/nxp-imx8mq-evk/Makefile @@ -1,2 +1,2 @@ obj-y += board.o -lwl-y += lowlevel.o ddr_init.o ddrphy_train.o trampoline.o +lwl-y += lowlevel.o ddr_init.o ddrphy_train.o diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index a74171e5e5..9d060fb589 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -56,27 +56,6 @@ static void nxp_imx8mq_evk_sram_setup(void) ddr_init(); } -extern unsigned char trampoline_start[]; -extern unsigned char trampoline_end[]; - -static void nxp_imx8mq_evk_install_tfa_trampoline(void) -{ - unsigned int tramp_len; - unsigned int offset; - /* - * Create a trampoline which is places in DRAM and calls back into the - * PBL entry function found in the TCRAM. Register x0 is set to 1 to - * indicate that DRAM setup was already run. - */ - tramp_len = (void *)trampoline_end - (void *)trampoline_start; - memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR, (void *)trampoline_start, - tramp_len); - - offset = get_runtime_offset(); - memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR + tramp_len, &offset, - sizeof(offset)); -} - /* * Power-on execution flow of start_nxp_imx8mq_evk() might not be * obvious for a very first read, so here's, hopefully helpful, @@ -105,23 +84,24 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void) const u8 *bl31; size_t bl31_size; - imx8mq_cpu_lowlevel_init(); - if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); /* - * if register r0 does not contain 1, we are running for the first time - * and need to initialize the DRAM, install the trampoline and run TF-A - * (BL31). - * Otherwise the 1 indicates that the DRAM setup and trampoline are - * already installed and TF-A has been run. In this case we can skip + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. */ if (current_el() == 3) { nxp_imx8mq_evk_sram_setup(); - nxp_imx8mq_evk_install_tfa_trampoline(); get_builtin_firmware(imx8mq_bl31_bin, &bl31, &bl31_size); + /* + * On completion the TF-A will jump to MX8MQ_ATF_BL33_BASE_ADDR in + * EL2. Copy ourselves there. + */ + memcpy((void *)MX8MQ_ATF_BL33_BASE_ADDR, _text, __bss_start - _text); imx8mq_atf_load_bl31(bl31, bl31_size); + /* not reached */ } imx8_get_boot_source(&src, &instance); diff --git a/arch/arm/boards/nxp-imx8mq-evk/trampoline.S b/arch/arm/boards/nxp-imx8mq-evk/trampoline.S deleted file mode 100644 index 54a1b76518..0000000000 --- a/arch/arm/boards/nxp-imx8mq-evk/trampoline.S +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0) */ -#include <linux/linkage.h> -#include <asm/sections.h> - .section .trampoline,"a" - .globl trampoline_start -trampoline_start: - ldr w19, trampoline_end - br x19 - .globl trampoline_end -trampoline_end: diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c index 09994e4492..bd46df0962 100644 --- a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -126,7 +126,7 @@ ENTRY_FUNCTION(start_phytec_phycard_imx27_64mb, r0, r1, r2) { void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); @@ -137,7 +137,7 @@ ENTRY_FUNCTION(start_phytec_phycard_imx27_128mb, r0, r1, r2) { void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start + get_runtime_offset(); diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c index b858ff348b..a9e296a0af 100644 --- a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c @@ -106,7 +106,7 @@ ENTRY_FUNCTION(start_phytec_phycore_imx27, r0, r1, r2) { void *fdt; - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE); fdt = __dtb_imx27_phytec_phycore_rdk_start + get_runtime_offset(); diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c index 19296e5dac..b5f333987a 100644 --- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -38,7 +38,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE); writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index 6bfa0acce3..b80dafec16 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -44,7 +44,7 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint arm_cpu_lowlevel_init(); - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE); r = get_cr(); r |= CR_Z; /* Flow prediction (Z) */ diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 07bb0ed1b5..2de84169c6 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -59,11 +59,11 @@ static void __noreturn start_imx6_phytec_common(uint32_t size, || cpu_type == IMX6_CPUTYPE_IMX6ULL) { imx6ul_cpu_lowlevel_init(); /* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */ - arm_setup_stack(0x00910000 - 8); + arm_setup_stack(0x00910000); } else { imx6_cpu_lowlevel_init(); /* OCRAM Free Area is 0x00907000 to 0x00938000 (196KB) */ - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); } if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL)) diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c index 7127d39943..b18cd067b7 100644 --- a/arch/arm/boards/pm9261/lowlevel_init.c +++ b/arch/arm/boards/pm9261/lowlevel_init.c @@ -115,7 +115,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE); pm9261_init(); } diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c index daeb183831..8f44adee99 100644 --- a/arch/arm/boards/pm9263/lowlevel_init.c +++ b/arch/arm/boards/pm9263/lowlevel_init.c @@ -136,7 +136,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16); + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE); pm9263_board_init(); } diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c index 12cf950685..fc0bfe405b 100644 --- a/arch/arm/boards/pm9g45/lowlevel.c +++ b/arch/arm/boards/pm9g45/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1), NULL); diff --git a/arch/arm/boards/qil-a926x/lowlevel.c b/arch/arm/boards/qil-a926x/lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/qil-a926x/lowlevel.c +++ b/arch/arm/boards/qil-a926x/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c index 4b64f5d1d7..70f1936522 100644 --- a/arch/arm/boards/raspberry-pi/lowlevel.c +++ b/arch/arm/boards/raspberry-pi/lowlevel.c @@ -40,7 +40,7 @@ static inline void start_raspberry_pi(unsigned long memsize, void *fdt, /* Copied from barebox_arm_entry(). We need stack here early * for normal function calls to work. */ - arm_setup_stack(arm_mem_stack_top(membase, membase + memsize) - 16); + arm_setup_stack(arm_mem_stack_top(membase, membase + memsize)); fdt += get_runtime_offset(); diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index b3da58f71f..f910b67d5f 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -77,7 +77,7 @@ static noinline void achilles_start(void) ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2) { arm_cpu_lowlevel_init(); - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 32); + arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); achilles_start(); } @@ -96,7 +96,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2) arm_cpu_lowlevel_init(); - arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 16); + arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K); arm_early_mmu_cache_invalidate(); diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index 8492ae95fb..8653c48c69 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c index 8492ae95fb..8653c48c69 100644 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ b/arch/arm/boards/sama5d3xek/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c index 9021ef57c5..9a6a767e5f 100644 --- a/arch/arm/boards/sama5d4_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE); barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c index 9021ef57c5..9a6a767e5f 100644 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ b/arch/arm/boards/sama5d4ek/lowlevel.c @@ -17,7 +17,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE); barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c index 77f48043da..f59c424dec 100644 --- a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c +++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c @@ -39,7 +39,7 @@ static void __noreturn start_imx6_pico_hobbit_common(uint32_t size, imx6ul_cpu_lowlevel_init(); - arm_setup_stack(0x00910000 - 8); + arm_setup_stack(0x00910000); arm_early_mmu_cache_invalidate(); diff --git a/arch/arm/boards/technexion-wandboard/lowlevel.c b/arch/arm/boards/technexion-wandboard/lowlevel.c index 9aae429d45..af04eadc9f 100644 --- a/arch/arm/boards/technexion-wandboard/lowlevel.c +++ b/arch/arm/boards/technexion-wandboard/lowlevel.c @@ -359,7 +359,7 @@ ENTRY_FUNCTION(start_imx6_wandboard, r0, r1, r2) { imx6_cpu_lowlevel_init(); - arm_setup_stack(0x0091ffb0); + arm_setup_stack(0x00920000); relocate_to_current_adr(); setup_c(); diff --git a/arch/arm/boards/telit-evk-pro3/lowlevel.c b/arch/arm/boards/telit-evk-pro3/lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/telit-evk-pro3/lowlevel.c +++ b/arch/arm/boards/telit-evk-pro3/lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9260_lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c index 868df9d6c8..565ba438d2 100644 --- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c +++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c @@ -122,7 +122,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16); + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE); tny_a9263_init(); } diff --git a/arch/arm/boards/tqma53/lowlevel.c b/arch/arm/boards/tqma53/lowlevel.c index 0d0b16846c..97a7ac556e 100644 --- a/arch/arm/boards/tqma53/lowlevel.c +++ b/arch/arm/boards/tqma53/lowlevel.c @@ -45,7 +45,7 @@ ENTRY_FUNCTION(start_imx53_mba53_512mib, r0, r1, r2) imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); IMD_USED(tqma53_memsize_512M); @@ -64,7 +64,7 @@ ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2) imx5_cpu_lowlevel_init(); - arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE - 8); + arm_setup_stack(MX53_IRAM_BASE_ADDR + MX53_IRAM_SIZE); IMD_USED(tqma53_memsize_1G); diff --git a/arch/arm/boards/tqma6x/lowlevel.c b/arch/arm/boards/tqma6x/lowlevel.c index a90cd4007f..afbc1691eb 100644 --- a/arch/arm/boards/tqma6x/lowlevel.c +++ b/arch/arm/boards/tqma6x/lowlevel.c @@ -32,7 +32,7 @@ ENTRY_FUNCTION(start_imx6q_mba6x, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); if (IS_ENABLED(CONFIG_DEBUG_LL)) { writel(0x2, 0x020e0338); @@ -53,7 +53,7 @@ ENTRY_FUNCTION(start_imx6dl_mba6x, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); if (IS_ENABLED(CONFIG_DEBUG_LL)) { writel(0x2, 0x020e035c); diff --git a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c index 25352672d7..7f52f824df 100644 --- a/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9260_lowlevel.c @@ -18,7 +18,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16); + arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE); barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)), diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c index b362fcf7d4..2ad88d7f22 100644 --- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c +++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c @@ -126,7 +126,7 @@ void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint { arm_cpu_lowlevel_init(); - arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16); + arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE); usb_a9263_init(); } diff --git a/arch/arm/boards/variscite-mx6/lowlevel.c b/arch/arm/boards/variscite-mx6/lowlevel.c index 337bc58c8d..d75d770a7e 100644 --- a/arch/arm/boards/variscite-mx6/lowlevel.c +++ b/arch/arm/boards/variscite-mx6/lowlevel.c @@ -45,7 +45,7 @@ ENTRY_FUNCTION(start_variscite_custom, r0, r1, r2) imx6_cpu_lowlevel_init(); - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c index 9672a69bfd..3f5d90b61d 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c +++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c @@ -271,7 +271,7 @@ static noinline void rdu2_sram_setup(void) enum bootsource bootsrc; int instance; - arm_setup_stack(0x00920000 - 8); + arm_setup_stack(0x00920000); relocate_to_current_adr(); setup_c(); diff --git a/arch/arm/boards/zii-vf610-dev/board.c b/arch/arm/boards/zii-vf610-dev/board.c index 0697a1660e..1d10f12f63 100644 --- a/arch/arm/boards/zii-vf610-dev/board.c +++ b/arch/arm/boards/zii-vf610-dev/board.c @@ -128,7 +128,7 @@ static int zii_vf610_dev_set_hostname(void) { "zii,vf610cfu1", "cfu1" }, { "zii,vf610dev-b", "dev-rev-b" }, { "zii,vf610dev-c", "dev-rev-c" }, - { "zii,vf610scu4-aib-c", "scu4-aib-rev-c" }, + { "zii,vf610scu4-aib", "scu4-aib" }, }; if (!of_machine_is_compatible("zii,vf610dev")) diff --git a/arch/arm/boards/zii-vf610-dev/defaultenv-zii-vf610-dev/nv/autoboot_abort_key b/arch/arm/boards/zii-vf610-dev/defaultenv-zii-vf610-dev/nv/autoboot_abort_key new file mode 100644 index 0000000000..55920c9a58 --- /dev/null +++ b/arch/arm/boards/zii-vf610-dev/defaultenv-zii-vf610-dev/nv/autoboot_abort_key @@ -0,0 +1 @@ +ctrl-c
\ No newline at end of file diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig index f8abbccfca..6b4fed5269 100644 --- a/arch/arm/cpu/Kconfig +++ b/arch/arm/cpu/Kconfig @@ -87,6 +87,7 @@ config CPU_V8 select CPU_SUPPORTS_64BIT_KERNEL select ARM_EXCEPTIONS select GENERIC_FIND_NEXT_BIT + select ARCH_HAS_STACK_DUMP config CPU_XSC3 bool diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 9b737f80ef..97e4eb52e3 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -10,6 +10,9 @@ AFLAGS_pbl-hyp.o :=-Wa,-march=armv7-a -Wa,-mcpu=all obj-y += start.o entry.o +pbl-$(CONFIG_BOARD_ARM_GENERIC_DT) += board-dt-2nd.o +pbl-$(CONFIG_BOARD_ARM_GENERIC_DT_AARCH64) += board-dt-2nd-aarch64.o + obj-pbl-y += setupc$(S64).o cache$(S64).o obj-$(CONFIG_BOOTM_OPTEE) += start-kernel-optee.o diff --git a/arch/arm/cpu/board-dt-2nd-aarch64.S b/arch/arm/cpu/board-dt-2nd-aarch64.S new file mode 100644 index 0000000000..0540a1690d --- /dev/null +++ b/arch/arm/cpu/board-dt-2nd-aarch64.S @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <linux/linkage.h> +#include <asm/barebox-arm64.h> + +ENTRY_PROC(start_dt_2nd) + adr x1, stack + mov sp, x1 + b dt_2nd_aarch64 +.word 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 +stack: +ENTRY_PROC_END(start_dt_2nd) diff --git a/arch/arm/cpu/board-dt-2nd.c b/arch/arm/cpu/board-dt-2nd.c new file mode 100644 index 0000000000..4e7d575e8a --- /dev/null +++ b/arch/arm/cpu/board-dt-2nd.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <common.h> +#include <linux/sizes.h> +#include <asm/barebox-arm-head.h> +#include <asm/barebox-arm.h> +#include <io.h> +#include <debug_ll.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <linux/libfdt.h> + +static void of_find_mem(void *fdt, unsigned long *membase, unsigned long *memsize) +{ + const __be32 *nap, *nsp, *reg; + uint32_t na, ns; + uint64_t memsize64, membase64; + int node, size, i; + + /* Make sure FDT blob is sane */ + if (fdt_check_header(fdt) != 0) { + pr_err("Invalid device tree blob\n"); + goto err; + } + + /* Find the #address-cells and #size-cells properties */ + node = fdt_path_offset(fdt, "/"); + if (node < 0) { + pr_err("Cannot find root node\n"); + goto err; + } + + nap = fdt_getprop(fdt, node, "#address-cells", &size); + if (!nap || (size != 4)) { + pr_err("Cannot find #address-cells property"); + goto err; + } + na = fdt32_to_cpu(*nap); + + nsp = fdt_getprop(fdt, node, "#size-cells", &size); + if (!nsp || (size != 4)) { + pr_err("Cannot find #size-cells property"); + goto err; + } + ns = fdt32_to_cpu(*nap); + + /* Find the memory range */ + node = fdt_node_offset_by_prop_value(fdt, -1, "device_type", + "memory", sizeof("memory")); + if (node < 0) { + pr_err("Cannot find memory node\n"); + goto err; + } + + reg = fdt_getprop(fdt, node, "reg", &size); + if (size < (na + ns) * sizeof(u32)) { + pr_err("cannot get memory range\n"); + goto err; + } + + membase64 = 0; + for (i = 0; i < na; i++) + membase64 = (membase64 << 32) | fdt32_to_cpu(*reg++); + + /* get the memsize and truncate it to under 4G on 32 bit machines */ + memsize64 = 0; + for (i = 0; i < ns; i++) + memsize64 = (memsize64 << 32) | fdt32_to_cpu(*reg++); + + *membase = membase64; + *memsize = memsize64; + + return; +err: + pr_err("No memory, cannot continue\n"); + while (1); +} + +#ifdef CONFIG_CPU_V8 + +static noinline void dt_2nd_continue_aarch64(void *fdt) +{ + unsigned long membase, memsize; + + if (!fdt) + hang(); + + of_find_mem(fdt, &membase, &memsize); + + barebox_arm_entry(membase, memsize, fdt); +} + +/* called from assembly */ +void dt_2nd_aarch64(void *fdt); + +void dt_2nd_aarch64(void *fdt) +{ + unsigned long image_start = (unsigned long)_text + global_variable_offset(); + + arm_setup_stack(image_start); + + relocate_to_current_adr(); + setup_c(); + + dt_2nd_continue_aarch64(fdt); +} + +#else + +static noinline void dt_2nd_continue(void *fdt) +{ + unsigned long membase, memsize; + + if (!fdt) + hang(); + + of_find_mem(fdt, &membase, &memsize); + + barebox_arm_entry(membase, memsize, fdt); +} + +ENTRY_FUNCTION(start_dt_2nd, r0, r1, r2) +{ + unsigned long image_start = (unsigned long)_text + global_variable_offset(); + + arm_setup_stack(image_start); + + relocate_to_current_adr(); + setup_c(); + barrier(); + + dt_2nd_continue((void *)r2); +} +#endif diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c index 4d957da1dc..c81b2b3791 100644 --- a/arch/arm/cpu/common.c +++ b/arch/arm/cpu/common.c @@ -84,6 +84,8 @@ void relocate_to_current_adr(void) unsigned long *fixup = (unsigned long *)(rel->r_offset + offset); *fixup = rel->r_addend + offset; + rel->r_addend += offset; + rel->r_offset += offset; } else { putc_ll('>'); puthex_ll(rel->r_info); diff --git a/arch/arm/cpu/entry.c b/arch/arm/cpu/entry.c index b48c1ca11d..30df95f078 100644 --- a/arch/arm/cpu/entry.c +++ b/arch/arm/cpu/entry.c @@ -27,7 +27,7 @@ void NAKED __noreturn barebox_arm_entry(unsigned long membase, unsigned long memsize, void *boarddata) { - arm_setup_stack(arm_mem_stack_top(membase, membase + memsize) - 16); + arm_setup_stack(arm_mem_stack_top(membase, membase + memsize)); arm_early_mmu_cache_invalidate(); if (IS_ENABLED(CONFIG_PBL_MULTI_IMAGES)) diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index 9cc3b358b0..4f16af22f8 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -42,18 +42,14 @@ unsigned long free_mem_end_ptr; extern unsigned char input_data[]; extern unsigned char input_data_end[]; -extern unsigned char sha_sum[]; -extern unsigned char sha_sum_end[]; - void __noreturn barebox_multi_pbl_start(unsigned long membase, unsigned long memsize, void *boarddata) { - uint32_t pg_len, uncompressed_len, pbl_hash_len; + uint32_t pg_len, uncompressed_len; void __noreturn (*barebox)(unsigned long, unsigned long, void *); unsigned long endmem = membase + memsize; unsigned long barebox_base; void *pg_start, *pg_end; - void *pbl_hash_start, *pbl_hash_end; unsigned long pc = get_pc(); pg_start = input_data + global_variable_offset(); @@ -96,17 +92,6 @@ void __noreturn barebox_multi_pbl_start(unsigned long membase, pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx (uncompressed size: 0x%08x)\n", pg_start, pg_len, barebox_base, uncompressed_len); - if (IS_ENABLED(CONFIG_PBL_VERIFY_PIGGY)) { - pbl_hash_start = sha_sum; - pbl_hash_end = sha_sum_end; - pbl_hash_len = pbl_hash_end - pbl_hash_start; - if (pbl_barebox_verify(pg_start, pg_len, pbl_hash_start, - pbl_hash_len) != 0) { - putc_ll('!'); - panic("hash mismatch, refusing to decompress"); - } - } - pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len); sync_caches_for_execution(); diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi index 53679b0d3c..6e41e820b8 100644 --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi @@ -23,6 +23,15 @@ }; }; + aliases { + /* + * NVMEM device corresponding to EEPROM attached to + * the switch shared DT node with it, so we use that + * fact to create a desirable naming + */ + switch-eeprom = &switch; + }; + mdio0: bitbang-mdio { compatible = "virtual,mdio-gpio"; pinctrl-names = "default"; diff --git a/arch/arm/dts/vf610-zii-cfu1.dts b/arch/arm/dts/vf610-zii-cfu1.dts index 1de9ee9ad2..70cd9d1ba9 100644 --- a/arch/arm/dts/vf610-zii-cfu1.dts +++ b/arch/arm/dts/vf610-zii-cfu1.dts @@ -11,10 +11,25 @@ / { aliases { /* - * NVMEM device corresponding to EEPROM attached to - * the switch shared DT node with it, so we use that - * fact to create a desirable naming - */ + * NVMEM device corresponding to EEPROM attached to + * the switch shared DT node with it, so we use that + * fact to create a desirable naming + */ switch-eeprom = &switch0; + fiber-eeprom0 = &fiber_eeprom0; + }; + + gpio-leds { + led-status { + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + fiber_eeprom0: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber0"; }; }; diff --git a/arch/arm/dts/vf610-zii-dev-rev-b.dts b/arch/arm/dts/vf610-zii-dev-rev-b.dts index c90af91a9f..abc5237080 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-b.dts @@ -10,7 +10,7 @@ / { spi0 { - m25p128@0 { + flash@0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts index ecec0b1830..62c70c8905 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts @@ -21,7 +21,7 @@ }; &dspi0 { - m25p128@0 { + flash@0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts index abe9e14fd7..43a13e243d 100644 --- a/arch/arm/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/dts/vf610-zii-scu4-aib.dts @@ -17,5 +17,95 @@ switch1-eeprom = &switch1; switch2-eeprom = &switch2; switch3-eeprom = &switch3; + fiber-eeprom0 = &fiber_eeprom0; + fiber-eeprom1 = &fiber_eeprom1; + fiber-eeprom2 = &fiber_eeprom2; + fiber-eeprom3 = &fiber_eeprom3; + fiber-eeprom4 = &fiber_eeprom4; + fiber-eeprom5 = &fiber_eeprom5; + fiber-eeprom6 = &fiber_eeprom6; + fiber-eeprom7 = &fiber_eeprom7; + fiber-eeprom8 = &fiber_eeprom8; + fiber-eeprom9 = &fiber_eeprom9; + }; +}; + +&sff0_i2c { + fiber_eeprom0: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber0"; + }; +}; + +&sff1_i2c { + fiber_eeprom1: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber1"; + }; +}; + +&sff2_i2c { + fiber_eeprom2: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber2"; + }; +}; + +&sff3_i2c { + fiber_eeprom3: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber3"; + }; +}; + +&sff4_i2c { + fiber_eeprom4: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber4"; + }; +}; + +&sff5_i2c { + fiber_eeprom5: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber5"; + }; +}; + +&sff6_i2c { + fiber_eeprom6: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber6"; + }; +}; + +&sff7_i2c { + fiber_eeprom7: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber7"; + }; +}; + +&sff8_i2c { + fiber_eeprom8: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber8"; + }; +}; + +&sff9_i2c { + fiber_eeprom9: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber9"; }; }; diff --git a/arch/arm/include/asm/barebox.h b/arch/arm/include/asm/barebox.h deleted file mode 100644 index 4e89466593..0000000000 --- a/arch/arm/include/asm/barebox.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _BAREBOX_H_ -#define _BAREBOX_H_ 1 - -#ifdef CONFIG_ARM_UNWIND -#define ARCH_HAS_STACK_DUMP -#endif - -#ifdef CONFIG_CPU_V8 -#define ARCH_HAS_STACK_DUMP -#endif - -#ifdef CONFIG_ARM_EXCEPTIONS -#define ARCH_HAS_DATA_ABORT_MASK -#endif - -#endif /* _BAREBOX_H_ */ diff --git a/arch/arm/lib64/runtime-offset.S b/arch/arm/lib64/runtime-offset.S index 6624fdfa15..5e5ab9a8d1 100644 --- a/arch/arm/lib64/runtime-offset.S +++ b/arch/arm/lib64/runtime-offset.S @@ -1,31 +1,25 @@ #include <linux/linkage.h> #include <asm/assembler.h> -/* - * The .section directive below intentionally omits "a", since that - * appears to be the simplest way to force assembler to not generate - * R_AARCH64_RELATIVE relocation for - * - * linkadr: - * .quad get_runtime_offset - * - * statement below. While having that relocating was relatively - * harmless with GCC8, builging the code with GCC5 resulted in - * "linkaddr" being initialized to 0 causing complete boot breakdown - */ -.section ".text_bare_init","x" +.section ".text_bare_init","ax" /* * Get the offset between the link address and the address * we are currently running at. */ ENTRY(get_runtime_offset) -1: adr x0, 1b +1: adr x0, _text ldr x1, linkadr subs x0, x0, x1 ret .align 3 linkadr: -.quad get_runtime_offset +/* + * With older gcc versions (gcc5) function pointers will not be filled + * into the binary during compile time and instead rely on relocation + * during runtime. In the binary we'll always have 0x0 here. We deliberately + * use _text here since that is 0x0 and is correct without relocation. + */ +.quad _text ENDPROC(get_runtime_offset) diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index a563b3bc29..946a3e9a77 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -87,6 +87,7 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler, const void *buf, int image_len) { int fd, ret, offset = 0; + struct stat st; fd = open(devicefile, O_RDWR | O_CREAT); if (fd < 0) @@ -101,6 +102,15 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler, if (imx_handler->handler.flags & IMX_BBU_FLAG_KEEP_HEAD) offset += imx_handler->flash_header_offset; + ret = fstat(fd, &st); + if (ret) + goto err_close; + + if (image_len > st.st_size) { + ret = -ENOSPC; + goto err_close; + } + ret = imx_bbu_protect(fd, imx_handler, devicefile, offset, image_len, 0); if (ret) diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 63914d306e..0942d50695 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -95,7 +95,7 @@ static int imx_init(void) if (root) { __imx_cpu_type = imx_soc_from_dt(); if (!__imx_cpu_type) - hang(); + return 0; } if (cpu_is_mx1()) @@ -199,9 +199,7 @@ void imx_set_reset_reason(void __iomem *srsr, } } - reset_source_set_priority(type, - RESET_SOURCE_DEFAULT_PRIORITY); - reset_source_set_instance(type, instance); + reset_source_set_prinst(type, RESET_SOURCE_DEFAULT_PRIORITY, instance); pr_info("i.MX reset reason %s (SRSR: 0x%08x)\n", reset_source_name(), reg); diff --git a/arch/arm/mach-imx/imx8-ddrc.c b/arch/arm/mach-imx/imx8-ddrc.c index 736865eb6f..8bb2672102 100644 --- a/arch/arm/mach-imx/imx8-ddrc.c +++ b/arch/arm/mach-imx/imx8-ddrc.c @@ -69,15 +69,8 @@ static void ddrc_phy_fetch_streaming_message(void __iomem *phy) const u16 index = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); u16 i; - putc_ll('|'); - puthex_ll(index); - - for (i = 0; i < index; i++) { - const u32 arg = ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); - - putc_ll('|'); - puthex_ll(arg); - } + for (i = 0; i < index; i++) + ddrc_phy_get_message(phy, PMC_MESSAGE_STREAM); } void ddrc_phy_wait_training_complete(void __iomem *phy) @@ -85,23 +78,14 @@ void ddrc_phy_wait_training_complete(void __iomem *phy) for (;;) { const u32 m = ddrc_phy_get_message(phy, PMC_MESSAGE_ID); - puthex_ll(m); - switch (m) { case PMC_TRAIN_STREAM_START: ddrc_phy_fetch_streaming_message(phy); break; case PMC_TRAIN_SUCCESS: - putc_ll('P'); - putc_ll('\r'); - putc_ll('\n'); return; case PMC_TRAIN_FAIL: - putc_ll('F'); hang(); } - - putc_ll('\r'); - putc_ll('\n'); } } diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index ac066e3f17..5102c34e4c 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -223,6 +223,15 @@ extern unsigned int __imx_cpu_type; # define cpu_is_vf610() (0) #endif +#ifdef CONFIG_BOARD_ARM_GENERIC_DT +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type 0 +# endif +#endif + #define cpu_is_mx23() (0) #define cpu_is_mx28() (0) diff --git a/arch/arm/mach-omap/am33xx_bbu_nand.c b/arch/arm/mach-omap/am33xx_bbu_nand.c index 4c1a28d37e..8c487c8ebb 100644 --- a/arch/arm/mach-omap/am33xx_bbu_nand.c +++ b/arch/arm/mach-omap/am33xx_bbu_nand.c @@ -22,6 +22,8 @@ #include <fcntl.h> #include <libfile.h> #include <filetype.h> +#include <linux/mtd/mtd.h> +#include <mtd/mtd-peb.h> #include <mach/bbu.h> struct nand_bbu_handler { @@ -134,3 +136,147 @@ int am33xx_bbu_nand_slots_register_handler(const char *name, char **devicefile, return ret; } + +#define XLOAD_BLOCKS 4 + +static int nand_update_handler_complete(struct bbu_handler *handler, + struct bbu_data *data) +{ + const void *image = data->image; + size_t size = data->len; + enum filetype filetype; + struct cdev *cdev; + struct mtd_info *mtd; + int ret, i; + int npebs; + + filetype = file_detect_type(image, size); + + cdev = cdev_by_name(handler->devicefile); + if (!cdev) { + pr_err("%s: No NAND device found\n", __func__); + return -ENODEV; + } + + mtd = cdev->mtd; + if (!mtd) { + pr_err("%s: %s is not a mtd device\n", __func__, + handler->devicefile); + return -EINVAL; + } + + npebs = mtd_div_by_eb(mtd->size, mtd); + + /* + * Sanity check: We need at minimum 6 eraseblocks: 4 for the four xload + * binaries and 2 for the barebox images. + */ + if (npebs < XLOAD_BLOCKS + 2) + return -EINVAL; + + if (filetype == filetype_arm_barebox) { + int npebs_bb = (npebs - XLOAD_BLOCKS) / 2; + + pr_info("Barebox image detected, updating 2nd stage\n"); + + /* last chance before erasing the flash */ + ret = bbu_confirm(data); + if (ret) + goto out; + + ret = mtd_peb_write_file(mtd, XLOAD_BLOCKS, npebs_bb, data->image, + data->len); + if (ret) + goto out; + + ret = mtd_peb_write_file(mtd, XLOAD_BLOCKS + npebs_bb, npebs_bb, + data->image, data->len); + if (ret) + goto out; + + } else if (filetype == filetype_ch_image) { + int written = 0; + void *buf; + + pr_info("xload image detected, updating 1st stage\n"); + + if (data->len > mtd->erasesize) { + pr_err("Image is bigger than eraseblock, this is not supported\n"); + ret = -EINVAL; + goto out; + } + + /* last chance before erasing the flash */ + ret = bbu_confirm(data); + if (ret) + goto out; + + buf = xzalloc(mtd->erasesize); + memcpy(buf, data->image, data->len); + + for (i = 0; i < 4; i++) { + if (mtd_peb_is_bad(mtd, i)) { + pr_info("PEB%d is bad, skipping\n", i); + continue; + } + + ret = mtd_peb_erase(mtd, i); + if (ret) + continue; + + ret = mtd_peb_write(mtd, buf, i, 0, mtd->erasesize); + if (ret) { + pr_err("Failed to write MLO to PEB%d: %s\n", i, + strerror(-ret)); + continue; + } + written++; + } + + free(buf); + + if (written) + ret = 0; + else + ret = -EIO; + } else { + pr_err("%s of type %s is not a valid update file image\n", + data->imagefile, file_type_to_string(filetype)); + return -EINVAL; + } +out: + return ret; +} + +/** + * am33xx_bbu_nand_register_handler - register a NAND update handler + * @device: The nand cdev name (usually "nand0.barebox") + * + * This registers an update handler suitable for updating barebox to NAND. This + * update handler takes a single NAND partition for both the xload images and the + * barebox images. The first four blocks are used for the 4 xload copies, the + * remaining space is divided into two equally sized parts for two barebox images. + * The update handler automatically detects based on the filetype if the xload + * or the 2nd stage barebox shall be updated. + * + * FIXME: Currently for actually loading a barebox image from an xload image + * flashed with this layout a suitable layout has to be registered by the xload + * image using omap_set_barebox_part(). In the next step this should be the + * default. + */ +int am33xx_bbu_nand_register_handler(const char *device) +{ + struct bbu_handler *handler; + int ret; + + handler = xzalloc(sizeof(*handler)); + handler->devicefile = device; + handler->handler = nand_update_handler_complete; + handler->name = "nand"; + + ret = bbu_register_handler(handler); + if (ret) + free(handler); + + return ret; +} diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 38fc0f02d2..678a338fd6 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -37,7 +37,7 @@ void am35xx_emif4_init(void) writel(regval, &emif4_base->sdram_iodft_tlgc); /* Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1); + while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); /* Re-verify the DDR PHY status*/ while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); diff --git a/arch/arm/mach-omap/include/mach/bbu.h b/arch/arm/mach-omap/include/mach/bbu.h index c8b0a55acb..94d3f96bb4 100644 --- a/arch/arm/mach-omap/include/mach/bbu.h +++ b/arch/arm/mach-omap/include/mach/bbu.h @@ -23,6 +23,7 @@ int am33xx_bbu_nand_xloadslots_register_handler(const char *name, int num_devicefiles); int am33xx_bbu_nand_slots_register_handler(const char *name, char **devicefile, int num_devicefiles); +int am33xx_bbu_nand_register_handler(const char *device); #else static inline int am33xx_bbu_nand_xloadslots_register_handler(const char *name, char **devicefile, @@ -37,6 +38,11 @@ static inline int am33xx_bbu_nand_slots_register_handler(const char *name, { return 0; } + +static inline int am33xx_bbu_nand_register_handler(const char *device) +{ + return 0; +} #endif #ifdef CONFIG_BAREBOX_UPDATE_AM33XX_EMMC diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h index c9730a9454..f172b576eb 100644 --- a/arch/arm/mach-omap/include/mach/gpmc_nand.h +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -34,6 +34,7 @@ enum gpmc_ecc_mode { OMAP_ECC_HAMMING_CODE_HW_ROMCODE, OMAP_ECC_BCH8_CODE_HW, OMAP_ECC_BCH8_CODE_HW_ROMCODE, + OMAP_ECC_BCH16_CODE_HW, }; /** omap nand platform data structure */ diff --git a/arch/arm/mach-socfpga/include/mach/lowlevel.h b/arch/arm/mach-socfpga/include/mach/lowlevel.h index 03a2ea6435..657e07a881 100644 --- a/arch/arm/mach-socfpga/include/mach/lowlevel.h +++ b/arch/arm/mach-socfpga/include/mach/lowlevel.h @@ -72,7 +72,7 @@ static noinline void SECT(start_socfpga_c5_xload_common)(uint32_t size) { \ arm_cpu_lowlevel_init(); \ \ - arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16); \ + arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K); \ \ start_socfpga_c5_xload_common(memory_size); \ } diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h index c862778fc4..31f99eb175 100644 --- a/arch/arm/mach-tegra/include/mach/lowlevel.h +++ b/arch/arm/mach-tegra/include/mach/lowlevel.h @@ -261,7 +261,7 @@ void tegra_cpu_lowlevel_setup(char *fdt) r |= 0xd3; __asm__ __volatile__("msr cpsr, %0" : : "r"(r)); - arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K - 8); + arm_setup_stack(TEGRA_IRAM_BASE + SZ_256K); if (tegra_cpu_is_maincomplex()) tegra_maincomplex_entry(fdt + get_runtime_offset()); |