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-rw-r--r--arch/arm/Kconfig10
-rw-r--r--arch/arm/boards/Makefile3
-rw-r--r--arch/arm/boards/enclustra-aa1/Makefile (renamed from arch/arm/boards/qemu-virt/.gitignore)3
-rw-r--r--arch/arm/boards/enclustra-aa1/board.c48
-rw-r--r--arch/arm/boards/enclustra-aa1/lowlevel.c124
-rw-r--r--arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c104
-rw-r--r--arch/arm/boards/enclustra-aa1/pll-config-arria10.c56
-rw-r--r--arch/arm/boards/innocomm-imx8mm-wb15/Makefile4
-rw-r--r--arch/arm/boards/innocomm-imx8mm-wb15/board.c40
-rw-r--r--arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg7
-rw-r--r--arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c91
-rw-r--r--arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h9
-rw-r--r--arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c1856
-rw-r--r--arch/arm/boards/ls1046ardb/lowlevel.c6
-rw-r--r--arch/arm/boards/meerkat96/Makefile4
-rw-r--r--arch/arm/boards/meerkat96/board.c10
-rw-r--r--arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg105
-rw-r--r--arch/arm/boards/meerkat96/lowlevel.c34
-rw-r--r--arch/arm/boards/mnt-reform/lowlevel.c34
-rw-r--r--arch/arm/boards/mnt-reform/lpddr4-timing.c1
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/lowlevel.c103
-rw-r--r--arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c1
-rw-r--r--arch/arm/boards/nxp-imx8mn-evk/board.c21
-rw-r--r--arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c1
-rw-r--r--arch/arm/boards/nxp-imx8mn-evk/lowlevel.c153
-rw-r--r--arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c1
-rw-r--r--arch/arm/boards/nxp-imx8mp-evk/lowlevel.c99
-rw-r--r--arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c1
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/lowlevel.c4
-rw-r--r--arch/arm/boards/phytec-som-imx8mq/lowlevel.c4
-rw-r--r--arch/arm/boards/pine64-quartz64/lowlevel.c26
-rw-r--r--arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c40
-rw-r--r--arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c1
-rw-r--r--arch/arm/boards/radxa-rock3/board.c3
-rw-r--r--arch/arm/boards/radxa-rock3/lowlevel.c26
-rw-r--r--arch/arm/boards/raspberry-pi/Makefile1
-rw-r--r--arch/arm/boards/raspberry-pi/lowlevel.c129
-rw-r--r--arch/arm/boards/raspberry-pi/lowlevel.h5
-rw-r--r--arch/arm/boards/raspberry-pi/mbox-helpers.c73
-rw-r--r--arch/arm/boards/raspberry-pi/rpi-common.c310
-rw-r--r--arch/arm/boards/reflex-achilles/board.c3
-rw-r--r--arch/arm/boards/reflex-achilles/lowlevel.c37
-rw-r--r--arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c7
-rw-r--r--arch/arm/boards/rockchip-rk3568-evb/board.c2
-rw-r--r--arch/arm/boards/vscom-baltos/board.c42
-rw-r--r--arch/arm/configs/imx_v7_defconfig12
-rw-r--r--arch/arm/configs/imx_v8_defconfig2
-rw-r--r--arch/arm/configs/rpi_defconfig3
-rw-r--r--arch/arm/configs/rpi_v8a_defconfig113
-rw-r--r--arch/arm/configs/socfpga-arria10_defconfig1
-rw-r--r--arch/arm/cpu/Kconfig7
-rw-r--r--arch/arm/cpu/common.c6
-rw-r--r--arch/arm/cpu/mmu-common.h15
-rw-r--r--arch/arm/cpu/mmu.h9
-rw-r--r--arch/arm/cpu/mmu_64.c10
-rw-r--r--arch/arm/cpu/setupc_64.S2
-rw-r--r--arch/arm/cpu/start.c14
-rw-r--r--arch/arm/cpu/uncompress.c2
-rw-r--r--arch/arm/dts/.gitignore1
-rw-r--r--arch/arm/dts/Makefile8
-rw-r--r--arch/arm/dts/am335x-baltos-minimal.dts153
-rw-r--r--arch/arm/dts/am335x-myirtech-myd.dts35
-rw-r--r--arch/arm/dts/bcm2711-rpi-4.dts18
-rw-r--r--arch/arm/dts/imx6q-marsboard.dts2
-rw-r--r--arch/arm/dts/imx6qdl-zii-rdu2.dtsi14
-rw-r--r--arch/arm/dts/imx7d-ac-sxb.dtsi25
-rw-r--r--arch/arm/dts/imx7d-meerkat96.dts42
-rw-r--r--arch/arm/dts/imx8mm-innocomm-wb15-evk-upstream.dts147
-rw-r--r--arch/arm/dts/imx8mm-innocomm-wb15-evk.dts60
-rw-r--r--arch/arm/dts/imx8mm-innocomm-wb15.dtsi481
-rw-r--r--arch/arm/dts/imx8mm.dtsi52
-rw-r--r--arch/arm/dts/imx8mn-ddr4-evk.dts6
-rw-r--r--arch/arm/dts/imx8mn-evk.dts7
-rw-r--r--arch/arm/dts/imx8mn-evk.dtsi83
-rw-r--r--arch/arm/dts/imx8mn.dtsi32
-rw-r--r--arch/arm/dts/rk3566-quartz64-a.dts1
-rw-r--r--arch/arm/dts/rk3568-bpi-r2-pro.dts521
-rw-r--r--arch/arm/dts/rk3568-evb1-v10.dts1
-rw-r--r--arch/arm/dts/rk3568-rock-3a.dts1
-rw-r--r--arch/arm/dts/rk356x.dtsi9
-rw-r--r--arch/arm/dts/socfpga_arria10_mercury_aa1.dts88
-rw-r--r--arch/arm/dts/stm32mp151.dtsi26
-rw-r--r--arch/arm/include/asm/barebox-arm.h50
-rw-r--r--arch/arm/include/asm/cputype.h22
-rw-r--r--arch/arm/include/asm/dma.h5
-rw-r--r--arch/arm/include/asm/io.h10
-rw-r--r--arch/arm/include/asm/reloc.h42
-rw-r--r--arch/arm/include/asm/system_info.h6
-rw-r--r--arch/arm/lib/pbl.lds.S8
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/at91sam9_sdramc_ll.c71
-rw-r--r--arch/arm/mach-at91/at91sam9_xload_mmc.c118
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h14
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam926x.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h165
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h25
-rw-r--r--arch/arm/mach-at91/include/mach/sam92_ll.h54
-rw-r--r--arch/arm/mach-at91/include/mach/xload.h7
-rw-r--r--arch/arm/mach-at91/sam9263_ll.c215
-rw-r--r--arch/arm/mach-at91/sama5d2.c4
-rw-r--r--arch/arm/mach-at91/xload-mmc.c2
-rw-r--r--arch/arm/mach-bcm283x/Kconfig29
-rw-r--r--arch/arm/mach-bcm283x/Makefile2
-rw-r--r--arch/arm/mach-bcm283x/core.c57
-rw-r--r--arch/arm/mach-bcm283x/include/mach/core.h23
-rw-r--r--arch/arm/mach-bcm283x/include/mach/debug_ll.h26
-rw-r--r--arch/arm/mach-bcm283x/include/mach/mbox.h4
-rw-r--r--arch/arm/mach-bcm283x/include/mach/platform.h5
-rw-r--r--arch/arm/mach-bcm283x/mbox.c26
-rw-r--r--arch/arm/mach-imx/Kconfig23
-rw-r--r--arch/arm/mach-imx/Makefile3
-rw-r--r--arch/arm/mach-imx/atf.c157
-rw-r--r--arch/arm/mach-imx/boot.c6
-rw-r--r--arch/arm/mach-imx/imx-bbu-external-nand.c30
-rw-r--r--arch/arm/mach-imx/include/mach/atf.h23
-rw-r--r--arch/arm/mach-imx/include/mach/imx25-regs.h1
-rw-r--r--arch/arm/mach-imx/include/mach/imx8m-regs.h1
-rw-r--r--arch/arm/mach-imx/include/mach/romapi.h37
-rw-r--r--arch/arm/mach-imx/include/mach/tzasc.h16
-rw-r--r--arch/arm/mach-imx/include/mach/xload.h11
-rw-r--r--arch/arm/mach-imx/romapi.c44
-rw-r--r--arch/arm/mach-imx/tzasc.c47
-rw-r--r--arch/arm/mach-layerscape/Kconfig2
-rw-r--r--arch/arm/mach-layerscape/boot.c4
-rw-r--r--arch/arm/mach-mxs/Kconfig1
-rw-r--r--arch/arm/mach-mxs/imx.c3
-rw-r--r--arch/arm/mach-mxs/include/mach/imx23.h2
-rw-r--r--arch/arm/mach-omap/am33xx_generic.c3
-rw-r--r--arch/arm/mach-omap/omap3_generic.c3
-rw-r--r--arch/arm/mach-omap/omap4_generic.c3
-rw-r--r--arch/arm/mach-omap/omap_devices.c8
-rw-r--r--arch/arm/mach-rockchip/Kconfig2
-rw-r--r--arch/arm/mach-rockchip/rk3288.c3
-rw-r--r--arch/arm/mach-rockchip/rk3568.c9
-rw-r--r--arch/arm/mach-socfpga/Kconfig5
-rw-r--r--arch/arm/mach-socfpga/Makefile1
-rw-r--r--arch/arm/mach-socfpga/arria10-bootsource.c3
-rw-r--r--arch/arm/mach-socfpga/cpu_init.c12
-rw-r--r--arch/arm/mach-socfpga/cyclone5-bootsource.c6
-rw-r--r--arch/arm/mach-socfpga/include/mach/init.h8
-rw-r--r--arch/arm/mach-stm32mp/init.c3
-rw-r--r--arch/arm/mach-vexpress/v2m.c13
-rw-r--r--arch/arm/mach-zynq/zynq.c2
-rw-r--r--arch/arm/mach-zynqmp/zynqmp.c3
146 files changed, 5727 insertions, 1443 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8a1d75c19b..59fce0c601 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -60,6 +60,8 @@ config ARCH_BCM283X
select OFTREE
select OFDEVICE
select HAVE_PBL_MULTI_IMAGES
+ select CPU_SUPPORTS_32BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
config ARCH_CLPS711X
bool "Cirrus Logic EP711x/EP721x/EP731x"
@@ -276,7 +278,7 @@ config ARCH_ZYNQMP
select OFDEVICE
select OFTREE
select RELOCATABLE
- select SYS_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
select HAS_MACB
config ARCH_ARM64_VIRT
@@ -286,7 +288,7 @@ config ARCH_ARM64_VIRT
select OFDEVICE
select OFTREE
select RELOCATABLE
- select SYS_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
select ARM_AMBA
select BOARD_ARM_VIRT
select HW_HAS_PCI
@@ -397,13 +399,13 @@ choice
config 32BIT
bool "32-bit barebox"
- depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
+ depends on CPU_SUPPORTS_32BIT_KERNEL
help
Select this option if you want to build a 32-bit barebox.
config 64BIT
bool "64-bit barebox"
- depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
+ depends on CPU_SUPPORTS_64BIT_KERNEL
select ARCH_DMA_ADDR_T_64BIT
help
Select this option if you want to build a 64-bit barebox.
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 3ccde26f1b..a0e84c24d7 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += freescale-mx53-qsb/
obj-$(CONFIG_MACH_FREESCALE_MX53_SMD) += freescale-mx53-smd/
obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/
obj-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += freescale-mx7-sabresd/
+obj-$(CONFIG_MACH_MEERKAT96) += meerkat96/
obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/
obj-$(CONFIG_MACH_GK802) += gk802/
obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += globalscale-guruplug/
@@ -65,6 +66,7 @@ obj-$(CONFIG_MACH_HABA_KNX_LITE) += haba-knx/
obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/
obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/
obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/
+obj-$(CONFIG_MACH_INNOCOMM_WB15) += innocomm-imx8mm-wb15/
obj-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += kamstrup-mx7-concentrator/
obj-$(CONFIG_MACH_KINDLE3) += kindle3/
obj-$(CONFIG_MACH_KONTRON_SAMX6I) += kontron-samx6i/
@@ -134,6 +136,7 @@ obj-$(CONFIG_MACH_SCB9328) += scb9328/
obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/
obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
+obj-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += enclustra-aa1/
obj-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += reflex-achilles/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += terasic-de0-nano-soc/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += terasic-de10-nano/
diff --git a/arch/arm/boards/qemu-virt/.gitignore b/arch/arm/boards/enclustra-aa1/Makefile
index 3e3932a3bf..5678718188 100644
--- a/arch/arm/boards/qemu-virt/.gitignore
+++ b/arch/arm/boards/enclustra-aa1/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
-*.dtb*
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/enclustra-aa1/board.c b/arch/arm/boards/enclustra-aa1/board.c
new file mode 100644
index 0000000000..6261eb4b83
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/board.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <bbu.h>
+#include <mach/arria10-system-manager.h>
+
+static int aa1_init(void)
+{
+ int pbl_index = 0;
+ uint32_t flag_barebox1 = 0;
+ uint32_t flag_barebox2 = 0;
+
+ if (!of_machine_is_compatible("enclustra,mercury-aa1"))
+ return 0;
+
+ pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
+
+ pr_debug("Current barebox instance %d\n", pbl_index);
+
+ switch (pbl_index) {
+ case 0:
+ flag_barebox1 |= BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ case 1:
+ flag_barebox2 |= BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ };
+
+ bbu_register_std_file_update("emmc-barebox1-xload", flag_barebox1,
+ "/dev/mmc0.barebox1-xload",
+ filetype_socfpga_xload);
+
+ bbu_register_std_file_update("emmc-barebox1", 0,
+ "/dev/mmc0.barebox1",
+ filetype_arm_barebox);
+
+ bbu_register_std_file_update("emmc-barebox2-xload", flag_barebox2,
+ "/dev/mmc0.barebox2-xload",
+ filetype_socfpga_xload);
+
+ bbu_register_std_file_update("emmc-barebox2", 0,
+ "/dev/mmc0.barebox2",
+ filetype_arm_barebox);
+ return 0;
+}
+postcore_initcall(aa1_init);
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
new file mode 100644
index 0000000000..901adc4640
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <memory.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/unaligned.h>
+#include <debug_ll.h>
+#include <pbl.h>
+#include <mach/arria10-sdram.h>
+#include <mach/arria10-regs.h>
+#include <mach/arria10-reset-manager.h>
+#include <mach/arria10-clock-manager.h>
+#include <mach/arria10-pinmux.h>
+#include <mach/arria10-fpga.h>
+#include <mach/init.h>
+#include "pll-config-arria10.c"
+#include "pinmux-config-arria10.c"
+#include <mach/generic.h>
+#include <mach/init.h>
+
+#define BAREBOX_PART 0
+// the bitstream is located in the second partition in the partition table
+#define BITSTREAM_PART 1
+#define BAREBOX1_OFFSET SZ_1M
+#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_1M)
+// Offset from the start of the second partition on the eMMC.
+#define BITSTREAM1_OFFSET 0x0
+#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M)
+
+extern char __dtb_z_socfpga_arria10_mercury_aa1_start[];
+
+#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K)
+
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2)
+{
+ int pbl_index = 0;
+ int barebox = 0;
+ int bitstream = 0;
+
+ arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+
+ setup_c();
+
+ arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ arria10_prepare_mmc(BAREBOX_PART, BITSTREAM_PART);
+
+ pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
+
+ /* Allow booting from both PBL0 and PBL1 to allow atomic updates.
+ * Bitstreams redundant too and expected to reside in the second
+ * partition.
+ * There is a fixed relation between the PBL/barebox instance and its
+ * bitstream location (offset) that requires to update them together */
+ switch (pbl_index) {
+ case 0:
+ barebox = BAREBOX1_OFFSET;
+ bitstream = BITSTREAM1_OFFSET;
+ break;
+ case 1:
+ barebox = BAREBOX2_OFFSET;
+ bitstream = BITSTREAM2_OFFSET;
+ break;
+ case 2:
+ case 3:
+ /* Left blank for future extension */
+ break;
+ default:
+ /* If we get an undefined pbl index, use the first and hope for the best.
+ * We could bail out, but user wouldn't see anything on the console
+ * and wouldn't know what happend anyway. */
+ barebox = BAREBOX1_OFFSET;
+ bitstream = BITSTREAM1_OFFSET;
+ break;
+ }
+
+ arria10_load_fpga(bitstream, SZ_32M);
+
+ arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ arria10_ddr_calibration_sequence();
+
+ arria10_start_image(barebox);
+}
+
+ENTRY_FUNCTION(start_socfpga_aa1, r0, r1, r2)
+{
+ void *fdt;
+
+ fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_2G, fdt);
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2)
+{
+ void *fdt;
+
+ arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ /* wait for fpga_usermode */
+ a10_wait_for_usermode(0x1000000);
+
+ arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ arria10_ddr_calibration_sequence();
+
+ fdt = __dtb_z_socfpga_arria10_mercury_aa1_start + get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_2G, fdt);
+}
diff --git a/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c
new file mode 100644
index 0000000000..3e250dbf6f
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/pinmux-config-arria10.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/arria10-pinmux.h>
+
+static uint32_t pinmux[] = {
+[arria10_pinmux_shared_io_q3_7] = 0,
+[arria10_pinmux_shared_io_q3_6] = 15,
+[arria10_pinmux_shared_io_q3_5] = 15,
+[arria10_pinmux_shared_io_q3_4] = 15,
+[arria10_pinmux_shared_io_q3_3] = 15,
+[arria10_pinmux_shared_io_q3_2] = 15,
+[arria10_pinmux_shared_io_q3_1] = 15,
+[arria10_pinmux_shared_io_q2_12] = 4,
+[arria10_pinmux_shared_io_q2_11] = 4,
+[arria10_pinmux_shared_io_q2_10] = 4,
+[arria10_pinmux_shared_io_q2_8] = 4,
+[arria10_pinmux_shared_io_q2_9] = 4,
+[arria10_pinmux_shared_io_q2_7] = 4,
+[arria10_pinmux_shared_io_q2_6] = 4,
+[arria10_pinmux_shared_io_q2_5] = 4,
+[arria10_pinmux_shared_io_q2_4] = 4,
+[arria10_pinmux_shared_io_q2_3] = 4,
+[arria10_pinmux_shared_io_q2_2] = 4,
+[arria10_pinmux_shared_io_q2_1] = 4,
+[arria10_pinmux_shared_io_q1_12] = 8,
+[arria10_pinmux_shared_io_q1_10] = 8,
+[arria10_pinmux_shared_io_q1_11] = 8,
+[arria10_pinmux_shared_io_q1_9] = 8,
+[arria10_pinmux_shared_io_q1_8] = 8,
+[arria10_pinmux_shared_io_q1_7] = 8,
+[arria10_pinmux_shared_io_q1_6] = 8,
+[arria10_pinmux_shared_io_q1_5] = 8,
+[arria10_pinmux_shared_io_q1_4] = 8,
+[arria10_pinmux_shared_io_q1_3] = 8,
+[arria10_pinmux_shared_io_q1_2] = 8,
+[arria10_pinmux_shared_io_q1_1] = 8,
+[arria10_pinmux_shared_io_q4_12] = 15,
+[arria10_pinmux_shared_io_q4_11] = 15,
+[arria10_pinmux_shared_io_q4_10] = 3,
+[arria10_pinmux_shared_io_q4_9] = 3,
+[arria10_pinmux_shared_io_q4_8] = 3,
+[arria10_pinmux_shared_io_q4_7] = 3,
+[arria10_pinmux_shared_io_q4_6] = 10,
+[arria10_pinmux_shared_io_q4_4] = 10,
+[arria10_pinmux_shared_io_q4_5] = 10,
+[arria10_pinmux_shared_io_q4_3] = 10,
+[arria10_pinmux_shared_io_q4_2] = 10,
+[arria10_pinmux_shared_io_q4_1] = 10,
+[arria10_pinmux_shared_io_q3_12] = 1,
+[arria10_pinmux_shared_io_q3_11] = 1,
+[arria10_pinmux_shared_io_q3_10] = 15,
+[arria10_pinmux_shared_io_q3_9] = 15,
+[arria10_pinmux_shared_io_q3_8] = 0,
+[arria10_pinmux_dedicated_io_7] = 8,
+[arria10_pinmux_dedicated_io_8] = 8,
+[arria10_pinmux_dedicated_io_9] = 8,
+[arria10_pinmux_dedicated_io_10] = 15,
+[arria10_pinmux_dedicated_io_11] = 15,
+[arria10_pinmux_dedicated_io_12] = 8,
+[arria10_pinmux_dedicated_io_13] = 8,
+[arria10_pinmux_dedicated_io_14] = 8,
+[arria10_pinmux_dedicated_io_15] = 8,
+[arria10_pinmux_dedicated_io_16] = 13,
+[arria10_pinmux_dedicated_io_17] = 13,
+[arria10_pinmux_dedicated_io_4] = 8,
+[arria10_pinmux_dedicated_io_5] = 8,
+[arria10_pinmux_dedicated_io_6] = 8,
+[arria10_pincfg_dedicated_io_bank] = 0x101,
+[arria10_pincfg_dedicated_io_1] = 0xb080a,
+[arria10_pincfg_dedicated_io_2] = 0xb080a,
+[arria10_pincfg_dedicated_io_3] = 0xb080a,
+[arria10_pincfg_dedicated_io_4] = 0xa282a,
+[arria10_pincfg_dedicated_io_5] = 0xa282a,
+[arria10_pincfg_dedicated_io_6] = 0x8282a,
+[arria10_pincfg_dedicated_io_7] = 0xa282a,
+[arria10_pincfg_dedicated_io_8] = 0xa282a,
+[arria10_pincfg_dedicated_io_9] = 0xa282a,
+[arria10_pincfg_dedicated_io_10] = 0xa280a,
+[arria10_pincfg_dedicated_io_11] = 0xa280a,
+[arria10_pincfg_dedicated_io_12] = 0xa280a,
+[arria10_pincfg_dedicated_io_13] = 0xa280a,
+[arria10_pincfg_dedicated_io_14] = 0xa280a,
+[arria10_pincfg_dedicated_io_15] = 0xa280a,
+[arria10_pincfg_dedicated_io_16] = 0x8282a,
+[arria10_pincfg_dedicated_io_17] = 0xa280a,
+[arria10_pinmux_rgmii0_usefpga] = 0,
+[arria10_pinmux_rgmii1_usefpga] = 0,
+[arria10_pinmux_rgmii2_usefpga] = 0,
+[arria10_pinmux_nand_usefpga] = 0,
+[arria10_pinmux_qspi_usefpga] = 0,
+[arria10_pinmux_sdmmc_usefpga] = 0,
+[arria10_pinmux_spim0_usefpga] = 0,
+[arria10_pinmux_spim1_usefpga] = 0,
+[arria10_pinmux_spis0_usefpga] = 0,
+[arria10_pinmux_spis1_usefpga] = 0,
+[arria10_pinmux_uart0_usefpga] = 0,
+[arria10_pinmux_uart1_usefpga] = 0,
+[arria10_pinmux_i2c0_usefpga] = 0,
+[arria10_pinmux_i2c1_usefpga] = 0,
+[arria10_pinmux_i2cemac0_usefpga] = 0,
+[arria10_pinmux_i2cemac1_usefpga] = 0,
+[arria10_pinmux_i2cemac2_usefpga] = 0,
+};
+
diff --git a/arch/arm/boards/enclustra-aa1/pll-config-arria10.c b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c
new file mode 100644
index 0000000000..41aad354bc
--- /dev/null
+++ b/arch/arm/boards/enclustra-aa1/pll-config-arria10.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/arria10-clock-manager.h>
+
+static struct arria10_mainpll_cfg mainpll_cfg = {
+ .cntr15clk_cnt = 900,
+ .cntr2clk_cnt = 900,
+ .cntr3clk_cnt = 900,
+ .cntr4clk_cnt = 900,
+ .cntr5clk_cnt = 900,
+ .cntr6clk_cnt = 7,
+ .cntr7clk_cnt = 15,
+ .cntr7clk_src = 0,
+ .cntr8clk_cnt = 7,
+ .cntr9clk_cnt = 900,
+ .cntr9clk_src = 0,
+ .mpuclk_cnt = 0,
+ .mpuclk_src = 0,
+ .nocclk_cnt = 0,
+ .nocclk_src = 0,
+ .nocdiv_csatclk = 0,
+ .nocdiv_cspdbgclk = 1,
+ .nocdiv_cstraceclk = 0,
+ .nocdiv_l4mainclk = 0,
+ .nocdiv_l4mpclk = 1,
+ .nocdiv_l4spclk = 2,
+ .vco0_psrc = 0,
+ .vco1_denom = 32,
+ .vco1_numer = 1584,
+ .mpuclk = 0x3840001,
+ .nocclk = 0x3840007,
+};
+
+static struct arria10_perpll_cfg perpll_cfg = {
+ .cntr2clk_cnt = 5,
+ .cntr2clk_src = 1,
+ .cntr3clk_cnt = 900,
+ .cntr3clk_src = 1,
+ .cntr4clk_cnt = 14,
+ .cntr4clk_src = 1,
+ .cntr5clk_cnt = 374,
+ .cntr5clk_src = 1,
+ .cntr6clk_cnt = 900,
+ .cntr6clk_src = 0,
+ .cntr7clk_cnt = 900,
+ .cntr8clk_cnt = 900,
+ .cntr8clk_src = 0,
+ .cntr9clk_cnt = 900,
+ .emacctl_emac0sel = 0,
+ .emacctl_emac1sel = 0,
+ .emacctl_emac2sel = 0,
+ .gpiodiv_gpiodbclk = 32000,
+ .vco0_psrc = 0,
+ .vco1_denom = 32,
+ .vco1_numer = 1485,
+};
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/Makefile b/arch/arm/boards/innocomm-imx8mm-wb15/Makefile
new file mode 100644
index 0000000000..10abebc539
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/board.c b/arch/arm/boards/innocomm-imx8mm-wb15/board.c
new file mode 100644
index 0000000000..8bc4dabb66
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <init.h>
+#include <mach/bbu.h>
+
+static int innocomm_wb15_evk_probe(struct device_d *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc0", emmc_bbu_flag);
+ imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
+
+ return 0;
+}
+
+static const struct of_device_id innocomm_wb15_evk_of_match[] = {
+ { .compatible = "innocomm,wb15-evk" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(innocomm_wb15_evk_of_match);
+
+static struct driver_d innocomm_wb15_evkboard_driver = {
+ .name = "board-innocomm-wb15-evk",
+ .probe = innocomm_wb15_evk_probe,
+ .of_compatible = DRV_OF_COMPAT(innocomm_wb15_evk_of_match),
+};
+coredevice_platform_driver(innocomm_wb15_evkboard_driver);
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg b/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg
new file mode 100644
index 0000000000..10606ce29c
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/flash-header-imx8mm-wb15.imxcfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+ivtofs 0x400
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c
new file mode 100644
index 0000000000..2077d3c88e
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <debug_ll.h>
+#include <asm/barebox-arm.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
+#include <mach/esdctl.h>
+#include <mach/atf.h>
+#include <mach/generic.h>
+#include <mach/iomux-mx8mm.h>
+#include <mach/imx8m-ccm-regs.h>
+#include <mfd/bd71837.h>
+#include <mach/xload.h>
+#include <soc/imx8m/ddr.h>
+#include <image-metadata.h>
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mm_innocomm_wb15_evk_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+ void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
+
+ imx8m_early_setup_uart_clock();
+
+ imx8mm_setup_pad(IMX8MM_PAD_UART2_TXD_UART2_TX | UART_PAD_CTRL);
+ imx8m_uart_setup(uart);
+
+ pbl_set_putc(imx_uart_putc, uart);
+ putc_ll('>');
+}
+
+static struct pmic_config bd71837_cfg[] = {
+ /* decrease RESET key long push time from the default 10s to 10ms */
+ { BD718XX_PWRONCONFIG1, 0x0 },
+ /* unlock the PMIC regs */
+ { BD718XX_REGLOCK, 0x1 },
+ /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
+ { BD718XX_BUCK1_VOLT_RUN, 0xf },
+ /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+ { BD718XX_1ST_NODVS_BUCK_VOLT, 0x83 },
+ /* lock the PMIC regs */
+ { BD718XX_REGLOCK, 0x11 },
+};
+
+void innocomm_wb15_power_init_board(void)
+{
+ struct pbl_i2c *i2c;
+
+ imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
+ imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
+
+ imx8mm_early_clock_init();
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
+
+ i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR));
+
+ pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg));
+}
+
+ENTRY_FUNCTION(start_innocomm_wb15_evk, r0, r1, r2)
+{
+ IMD_USED_OF(imx8mm_innocomm_wb15_evk);
+
+ imx8mm_cpu_lowlevel_init();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ setup_uart();
+
+ /*
+ * If we are in EL3 we are running for the first time out of OCRAM,
+ * we'll need to initialize the DRAM and run TF-A (BL31). The TF-A
+ * will then jump to DRAM in EL2
+ */
+ if (current_el() == 3) {
+ innocomm_wb15_power_init_board();
+
+ imx8mm_ddr_init(&innocomm_wb15_dram_timing, DRAM_TYPE_LPDDR4);
+
+ imx8mm_load_and_start_image_via_tfa();
+ }
+
+ /* Standard entry we hit once we initialized both DDR and ATF */
+ imx8mm_barebox_entry(__dtb_z_imx8mm_innocomm_wb15_evk_start);
+}
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h
new file mode 100644
index 0000000000..3b0ea9ccc3
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lowlevel.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef INNOCOMM_WB15_LOWLEVEL_H_
+#define INNOCOMM_WB15_LOWLEVEL_H_
+
+void innocomm_wb15_power_init_board(void);
+extern struct dram_timing_info innocomm_wb15_dram_timing;
+
+#endif
diff --git a/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c
new file mode 100644
index 0000000000..006ee37df5
--- /dev/null
+++ b/arch/arm/boards/innocomm-imx8mm-wb15/lpddr4-timing.c
@@ -0,0 +1,1856 @@
+/*
+ * Copyright 2018 InnoComm Mobile Technology Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <common.h>
+#include <soc/imx8m/ddr.h>
+
+#define DDR_ONE_RANK
+#include <soc/imx8m/lpddr4_define.h>
+
+#include "lowlevel.h"
+
+static struct dram_cfg_param ddr_ddrc_cfg_1g_2ch1cs15r10cx32[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304,0x1},
+ {0x3d400030,0x1},
+ {0x3d400000,0xa1080020},
+ {0x3d400020,0x223},
+ {0x3d400024,0x2ee00},
+ {0x3d400064,0x49006c},
+ {0x3d4000d0,0xc0030495},
+ {0x3d4000d4,0x770000},
+ {0x3d4000dc,0xc40024},
+ {0x3d4000e0,0x310000},
+ {0x3d4000e8,0x66004d},
+ {0x3d4000ec,0x16004d},
+ {0x3d400100,0x1618141a},
+ {0x3d400104,0x504a6},
+ {0x3d40010c,0x909000},
+ {0x3d400110,0xb04060b},
+ {0x3d400114,0x2030909},
+ {0x3d400118,0x1010006},
+ {0x3d40011c,0x301},
+ {0x3d400130,0x20500},
+ {0x3d400134,0xb100002},
+ {0x3d400138,0x71},
+ {0x3d400144,0x78003c},
+ {0x3d400180,0x2580012},
+ {0x3d400184,0x1e0493e},
+ {0x3d400188,0x0},
+ {0x3d400190,0x4938208},
+ {0x3d400194,0x80303},
+ {0x3d4001b4,0x1308},
+ {0x3d4001a0,0xe0400018},
+ {0x3d4001a4,0xdf00e4},
+ {0x3d4001a8,0x80000000},
+ {0x3d4001b0,0x11},
+ {0x3d4001c0,0x1},
+ {0x3d4001c4,0x1},
+ {0x3d4000f4,0xc99},
+ {0x3d400108,0x60c1514},
+ {0x3d400200,0x1f},
+ {0x3d40020c,0x0},
+ {0x3d400210,0x1f1f},
+ {0x3d400204,0x80808},
+ {0x3d400214,0x7070707},
+ {0x3d400218,0xf070707},
+ {0x3d40021c,0xf0f},
+ {0x3d400250,0x29001701},
+ {0x3d400254,0x2c},
+ {0x3d40025c,0x4000030},
+ {0x3d400264,0x900093e7},
+ {0x3d40026c,0x2005574},
+ {0x3d400400,0x111},
+ {0x3d400408,0x72ff},
+ {0x3d400494,0x2100e07},
+ {0x3d400498,0x620096},
+ {0x3d40049c,0x1100e07},
+ {0x3d4004a0,0xc8012c},
+ {0x3d402020,0x21},
+ {0x3d402024,0x7d00},
+ {0x3d402050,0x20d040},
+ {0x3d402064,0xc0012},
+ {0x3d4020dc,0x840000},
+ {0x3d4020e0,0x310000},
+ {0x3d4020e8,0x66004d},
+ {0x3d4020ec,0x16004d},
+ {0x3d402100,0xa040305},
+ {0x3d402104,0x30407},
+ {0x3d402108,0x203060b},
+ {0x3d40210c,0x505000},
+ {0x3d402110,0x2040202},
+ {0x3d402114,0x2030202},
+ {0x3d402118,0x1010004},
+ {0x3d40211c,0x301},
+ {0x3d402130,0x20300},
+ {0x3d402134,0xa100002},
+ {0x3d402138,0x13},
+ {0x3d402144,0x14000a},
+ {0x3d402180,0x640004},
+ {0x3d402190,0x3818200},
+ {0x3d402194,0x80303},
+ {0x3d4021b4,0x100},
+ {0x3d4020f4,0xc99},
+ {0x3d403020,0x21},
+ {0x3d403024,0x1f40},
+ {0x3d403050,0x20d040},
+ {0x3d403064,0x30005},
+ {0x3d4030dc,0x840000},
+ {0x3d4030e0,0x310000},
+ {0x3d4030e8,0x66004d},
+ {0x3d4030ec,0x16004d},
+ {0x3d403100,0xa010102},
+ {0x3d403104,0x30404},
+ {0x3d403108,0x203060b},
+ {0x3d40310c,0x505000},
+ {0x3d403110,0x2040202},
+ {0x3d403114,0x2030202},
+ {0x3d403118,0x1010004},
+ {0x3d40311c,0x301},
+ {0x3d403130,0x20300},
+ {0x3d403134,0xa100002},
+ {0x3d403138,0x5},
+ {0x3d403144,0x50003},
+ {0x3d403180,0x190004},
+ {0x3d403190,0x3818200},
+ {0x3d403194,0x80303},
+ {0x3d4031b4,0x100},
+ {0x3d4030f4,0xc99},
+ {0x3d400028,0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0,0x0},
+ {0x100a1,0x1},
+ {0x100a2,0x2},
+ {0x100a3,0x3},
+ {0x100a4,0x4},
+ {0x100a5,0x5},
+ {0x100a6,0x6},
+ {0x100a7,0x7},
+ {0x110a0,0x0},
+ {0x110a1,0x1},
+ {0x110a2,0x3},
+ {0x110a3,0x4},
+ {0x110a4,0x5},
+ {0x110a5,0x2},
+ {0x110a6,0x7},
+ {0x110a7,0x6},
+ {0x120a0,0x0},
+ {0x120a1,0x1},
+ {0x120a2,0x3},
+ {0x120a3,0x2},
+ {0x120a4,0x5},
+ {0x120a5,0x4},
+ {0x120a6,0x7},
+ {0x120a7,0x6},
+ {0x130a0,0x0},
+ {0x130a1,0x1},
+ {0x130a2,0x2},
+ {0x130a3,0x3},
+ {0x130a4,0x4},
+ {0x130a5,0x5},
+ {0x130a6,0x6},
+ {0x130a7,0x7},
+ {0x1005f,0x1ff},
+ {0x1015f,0x1ff},
+ {0x1105f,0x1ff},
+ {0x1115f,0x1ff},
+ {0x1205f,0x1ff},
+ {0x1215f,0x1ff},
+ {0x1305f,0x1ff},
+ {0x1315f,0x1ff},
+ {0x11005f,0x1ff},
+ {0x11015f,0x1ff},
+ {0x11105f,0x1ff},
+ {0x11115f,0x1ff},
+ {0x11205f,0x1ff},
+ {0x11215f,0x1ff},
+ {0x11305f,0x1ff},
+ {0x11315f,0x1ff},
+ {0x21005f,0x1ff},
+ {0x21015f,0x1ff},
+ {0x21105f,0x1ff},
+ {0x21115f,0x1ff},
+ {0x21205f,0x1ff},
+ {0x21215f,0x1ff},
+ {0x21305f,0x1ff},
+ {0x21315f,0x1ff},
+ {0x55,0x1ff},
+ {0x1055,0x1ff},
+ {0x2055,0x1ff},
+ {0x3055,0x1ff},
+ {0x4055,0x1ff},
+ {0x5055,0x1ff},
+ {0x6055,0x1ff},
+ {0x7055,0x1ff},
+ {0x8055,0x1ff},
+ {0x9055,0x1ff},
+ {0x200c5,0xa},
+ {0x1200c5,0x7},
+ {0x2200c5,0x7},
+ {0x2002e,0x2},
+ {0x12002e,0x2},
+ {0x22002e,0x2},
+ {0x90204,0x0},
+ {0x190204,0x0},
+ {0x290204,0x0},
+ {0x20024,0x1ab},
+ {0x2003a,0x0},
+ {0x120024,0x1ab},
+ {0x2003a,0x0},
+ {0x220024,0x1ab},
+ {0x2003a,0x0},
+ {0x20056,0x2},
+ {0x120056,0xa},
+ {0x220056,0xa},
+ {0x1004d,0xe00},
+ {0x1014d,0xe00},
+ {0x1104d,0xe00},
+ {0x1114d,0xe00},
+ {0x1204d,0xe00},
+ {0x1214d,0xe00},
+ {0x1304d,0xe00},
+ {0x1314d,0xe00},
+ {0x11004d,0xe00},
+ {0x11014d,0xe00},
+ {0x11104d,0xe00},
+ {0x11114d,0xe00},
+ {0x11204d,0xe00},
+ {0x11214d,0xe00},
+ {0x11304d,0xe00},
+ {0x11314d,0xe00},
+ {0x21004d,0xe00},
+ {0x21014d,0xe00},
+ {0x21104d,0xe00},
+ {0x21114d,0xe00},
+ {0x21204d,0xe00},
+ {0x21214d,0xe00},
+ {0x21304d,0xe00},
+ {0x21314d,0xe00},
+ {0x10049,0xeba},
+ {0x10149,0xeba},
+ {0x11049,0xeba},
+ {0x11149,0xeba},
+ {0x12049,0xeba},
+ {0x12149,0xeba},
+ {0x13049,0xeba},
+ {0x13149,0xeba},
+ {0x110049,0xeba},
+ {0x110149,0xeba},
+ {0x111049,0xeba},
+ {0x111149,0xeba},
+ {0x112049,0xeba},
+ {0x112149,0xeba},
+ {0x113049,0xeba},
+ {0x113149,0xeba},
+ {0x210049,0xeba},
+ {0x210149,0xeba},
+ {0x211049,0xeba},
+ {0x211149,0xeba},
+ {0x212049,0xeba},
+ {0x212149,0xeba},
+ {0x213049,0xeba},
+ {0x213149,0xeba},
+ {0x43,0x63},
+ {0x1043,0x63},
+ {0x2043,0x63},
+ {0x3043,0x63},
+ {0x4043,0x63},
+ {0x5043,0x63},
+ {0x6043,0x63},
+ {0x7043,0x63},
+ {0x8043,0x63},
+ {0x9043,0x63},
+ {0x20018,0x3},
+ {0x20075,0x4},
+ {0x20050,0x0},
+ {0x20008,0x258},
+ {0x120008,0x64},
+ {0x220008,0x19},
+ {0x20088,0x9},
+ {0x200b2,0xdc},
+ {0x10043,0x5a1},
+ {0x10143,0x5a1},
+ {0x11043,0x5a1},
+ {0x11143,0x5a1},
+ {0x12043,0x5a1},
+ {0x12143,0x5a1},
+ {0x13043,0x5a1},
+ {0x13143,0x5a1},
+ {0x1200b2,0xdc},
+ {0x110043,0x5a1},
+ {0x110143,0x5a1},
+ {0x111043,0x5a1},
+ {0x111143,0x5a1},
+ {0x112043,0x5a1},
+ {0x112143,0x5a1},
+ {0x113043,0x5a1},
+ {0x113143,0x5a1},
+ {0x2200b2,0xdc},
+ {0x210043,0x5a1},
+ {0x210143,0x5a1},
+ {0x211043,0x5a1},
+ {0x211143,0x5a1},
+ {0x212043,0x5a1},
+ {0x212143,0x5a1},
+ {0x213043,0x5a1},
+ {0x213143,0x5a1},
+ {0x200fa,0x1},
+ {0x1200fa,0x1},
+ {0x2200fa,0x1},
+ {0x20019,0x1},
+ {0x120019,0x1},
+ {0x220019,0x1},
+ {0x200f0,0x660},
+ {0x200f1,0x0},
+ {0x200f2,0x4444},
+ {0x200f3,0x8888},
+ {0x200f4,0x5665},
+ {0x200f5,0x0},
+ {0x200f6,0x0},
+ {0x200f7,0xf000},
+ {0x20025,0x0},
+ {0x2002d,0x0},
+ {0x12002d,0x0},
+ {0x22002d,0x0},
+ {0x200c7,0x21},
+ {0x1200c7,0x21},
+ {0x2200c7,0x21},
+ {0x200ca,0x24},
+ {0x1200ca,0x24},
+ {0x2200ca,0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg_1g_2ch1cs15r10cx32[] = {
+ {0xd0000, 0x0},
+ {0x54003,0x960},
+ {0x54004,0x2},
+ {0x54005,0x2228},
+ {0x54006,0x11},
+ {0x54008,0x131f},
+ {0x54009,0xc8},
+ {0x5400b,0x2},
+ {0x5400d,0x100},
+ {0x54012,0x110},
+ {0x54019,0x24c4},
+ {0x5401a,0x31},
+ {0x5401b,0x4d66},
+ {0x5401c,0x4d00},
+ {0x5401e,0x16},
+ {0x5401f,0x24c4},
+ {0x54020,0x31},
+ {0x54021,0x4d66},
+ {0x54022,0x4d00},
+ {0x54024,0x16},
+ {0x5402b,0x1000},
+ {0x5402c,0x1},
+ {0x54032,0xc400},
+ {0x54033,0x3124},
+ {0x54034,0x6600},
+ {0x54035,0x4d},
+ {0x54036,0x4d},
+ {0x54037,0x1600},
+ {0x54038,0xc400},
+ {0x54039,0x3124},
+ {0x5403a,0x6600},
+ {0x5403b,0x4d},
+ {0x5403c,0x4d},
+ {0x5403d,0x1600},
+ {0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg_1g_2ch1cs15r10cx32[] = {
+ {0xd0000, 0x0},
+ {0x54002,0x101},
+ {0x54003,0x190},
+ {0x54004,0x2},
+ {0x54005,0x2228},
+ {0x54006,0x11},
+ {0x54008,0x121f},
+ {0x54009,0xc8},
+ {0x5400b,0x2},
+ {0x5400d,0x100},
+ {0x54012,0x110},
+ {0x54019,0x84},
+ {0x5401a,0x31},
+ {0x5401b,0x4d66},
+ {0x5401c,0x4d00},
+ {0x5401e,0x16},
+ {0x5401f,0x84},
+ {0x54020,0x31},
+ {0x54021,0x4d66},
+ {0x54022,0x4d00},
+ {0x54024,0x16},
+ {0x5402b,0x1000},
+ {0x5402c,0x1},
+ {0x54032,0x8400},
+ {0x54033,0x3100},
+ {0x54034,0x6600},
+ {0x54035,0x4d},
+ {0x54036,0x4d},
+ {0x54037,0x1600},
+ {0x54038,0x8400},
+ {0x54039,0x3100},
+ {0x5403a,0x6600},
+ {0x5403b,0x4d},
+ {0x5403c,0x4d},
+ {0x5403d,0x1600},
+ {0xd0000, 0x1},
+};
+
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg_1g_2ch1cs15r10cx32[] = {
+ {0xd0000, 0x0},
+ {0x54002,0x102},
+ {0x54003,0x64},
+ {0x54004,0x2},
+ {0x54005,0x2228},
+ {0x54006,0x11},
+ {0x54008,0x121f},
+ {0x54009,0xc8},
+ {0x5400b,0x2},
+ {0x5400d,0x100},
+ {0x54012,0x110},
+ {0x54019,0x84},
+ {0x5401a,0x31},
+ {0x5401b,0x4d66},
+ {0x5401c,0x4d00},
+ {0x5401e,0x16},
+ {0x5401f,0x84},
+ {0x54020,0x31},
+ {0x54021,0x4d66},
+ {0x54022,0x4d00},
+ {0x54024,0x16},
+ {0x5402b,0x1000},
+ {0x5402c,0x1},
+ {0x54032,0x8400},
+ {0x54033,0x3100},
+ {0x54034,0x6600},
+ {0x54035,0x4d},
+ {0x54036,0x4d},
+ {0x54037,0x1600},
+ {0x54038,0x8400},
+ {0x54039,0x3100},
+ {0x5403a,0x6600},
+ {0x5403b,0x4d},
+ {0x5403c,0x4d},
+ {0x5403d,0x1600},
+ {0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32[] = {
+ {0xd0000, 0x0},
+ {0x54003,0x960},
+ {0x54004,0x2},
+ {0x54005,0x2228},
+ {0x54006,0x11},
+ {0x54008,0x61},
+ {0x54009,0xc8},
+ {0x5400b,0x2},
+ {0x5400f,0x100},
+ {0x54010,0x1f7f},
+ {0x54012,0x110},
+ {0x54019,0x24c4},
+ {0x5401a,0x31},
+ {0x5401b,0x4d66},
+ {0x5401c,0x4d00},
+ {0x5401e,0x16},
+ {0x5401f,0x24c4},
+ {0x54020,0x31},
+ {0x54021,0x4d66},
+ {0x54022,0x4d00},
+ {0x54024,0x16},
+ {0x5402b,0x1000},
+ {0x5402c,0x1},
+ {0x54032,0xc400},
+ {0x54033,0x3124},
+ {0x54034,0x6600},
+ {0x54035,0x4d},
+ {0x54036,0x4d},
+ {0x54037,0x1600},
+ {0x54038,0xc400},
+ {0x54039,0x3124},
+ {0x5403a,0x6600},
+ {0x5403b,0x4d},
+ {0x5403c,0x4d},
+ {0x5403d,0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000,0x10},
+ {0x90001,0x400},
+ {0x90002,0x10e},
+ {0x90003,0x0},
+ {0x90004,0x0},
+ {0x90005,0x8},
+ {0x90029,0xb},
+ {0x9002a,0x480},
+ {0x9002b,0x109},
+ {0x9002c,0x8},
+ {0x9002d,0x448},
+ {0x9002e,0x139},
+ {0x9002f,0x8},
+ {0x90030,0x478},
+ {0x90031,0x109},
+ {0x90032,0x0},
+ {0x90033,0xe8},
+ {0x90034,0x109},
+ {0x90035,0x2},
+ {0x90036,0x10},
+ {0x90037,0x139},
+ {0x90038,0xf},
+ {0x90039,0x7c0},
+ {0x9003a,0x139},
+ {0x9003b,0x44},
+ {0x9003c,0x630},
+ {0x9003d,0x159},
+ {0x9003e,0x14f},
+ {0x9003f,0x630},
+ {0x90040,0x159},
+ {0x90041,0x47},
+ {0x90042,0x630},
+ {0x90043,0x149},
+ {0x90044,0x4f},
+ {0x90045,0x630},
+ {0x90046,0x179},
+ {0x90047,0x8},
+ {0x90048,0xe0},
+ {0x90049,0x109},
+ {0x9004a,0x0},
+ {0x9004b,0x7c8},
+ {0x9004c,0x109},
+ {0x9004d,0x0},
+ {0x9004e,0x1},
+ {0x9004f,0x8},
+ {0x90050,0x0},
+ {0x90051,0x45a},
+ {0x90052,0x9},
+ {0x90053,0x0},
+ {0x90054,0x448},
+ {0x90055,0x109},
+ {0x90056,0x40},
+ {0x90057,0x630},
+ {0x90058,0x179},
+ {0x90059,0x1},
+ {0x9005a,0x618},
+ {0x9005b,0x109},
+ {0x9005c,0x40c0},
+ {0x9005d,0x630},
+ {0x9005e,0x149},
+ {0x9005f,0x8},
+ {0x90060,0x4},
+ {0x90061,0x48},
+ {0x90062,0x4040},
+ {0x90063,0x630},
+ {0x90064,0x149},
+ {0x90065,0x0},
+ {0x90066,0x4},
+ {0x90067,0x48},
+ {0x90068,0x40},
+ {0x90069,0x630},
+ {0x9006a,0x149},
+ {0x9006b,0x10},
+ {0x9006c,0x4},
+ {0x9006d,0x18},
+ {0x9006e,0x0},
+ {0x9006f,0x4},
+ {0x90070,0x78},
+ {0x90071,0x549},
+ {0x90072,0x630},
+ {0x90073,0x159},
+ {0x90074,0xd49},
+ {0x90075,0x630},
+ {0x90076,0x159},
+ {0x90077,0x94a},
+ {0x90078,0x630},
+ {0x90079,0x159},
+ {0x9007a,0x441},
+ {0x9007b,0x630},
+ {0x9007c,0x149},
+ {0x9007d,0x42},
+ {0x9007e,0x630},
+ {0x9007f,0x149},
+ {0x90080,0x1},
+ {0x90081,0x630},
+ {0x90082,0x149},
+ {0x90083,0x0},
+ {0x90084,0xe0},
+ {0x90085,0x109},
+ {0x90086,0xa},
+ {0x90087,0x10},
+ {0x90088,0x109},
+ {0x90089,0x9},
+ {0x9008a,0x3c0},
+ {0x9008b,0x149},
+ {0x9008c,0x9},
+ {0x9008d,0x3c0},
+ {0x9008e,0x159},
+ {0x9008f,0x18},
+ {0x90090,0x10},
+ {0x90091,0x109},
+ {0x90092,0x0},
+ {0x90093,0x3c0},
+ {0x90094,0x109},
+ {0x90095,0x18},
+ {0x90096,0x4},
+ {0x90097,0x48},
+ {0x90098,0x18},
+ {0x90099,0x4},
+ {0x9009a,0x58},
+ {0x9009b,0xa},
+ {0x9009c,0x10},
+ {0x9009d,0x109},
+ {0x9009e,0x2},
+ {0x9009f,0x10},
+ {0x900a0,0x109},
+ {0x900a1,0x5},
+ {0x900a2,0x7c0},
+ {0x900a3,0x109},
+ {0x900a4,0x10},
+ {0x900a5,0x10},
+ {0x900a6,0x109},
+ {0x40000,0x811},
+ {0x40020,0x880},
+ {0x40040,0x0},
+ {0x40060,0x0},
+ {0x40001,0x4008},
+ {0x40021,0x83},
+ {0x40041,0x4f},
+ {0x40061,0x0},
+ {0x40002,0x4040},
+ {0x40022,0x83},
+ {0x40042,0x51},
+ {0x40062,0x0},
+ {0x40003,0x811},
+ {0x40023,0x880},
+ {0x40043,0x0},
+ {0x40063,0x0},
+ {0x40004,0x720},
+ {0x40024,0xf},
+ {0x40044,0x1740},
+ {0x40064,0x0},
+ {0x40005,0x16},
+ {0x40025,0x83},
+ {0x40045,0x4b},
+ {0x40065,0x0},
+ {0x40006,0x716},
+ {0x40026,0xf},
+ {0x40046,0x2001},
+ {0x40066,0x0},
+ {0x40007,0x716},
+ {0x40027,0xf},
+ {0x40047,0x2800},
+ {0x40067,0x0},
+ {0x40008,0x716},
+ {0x40028,0xf},
+ {0x40048,0xf00},
+ {0x40068,0x0},
+ {0x40009,0x720},
+ {0x40029,0xf},
+ {0x40049,0x1400},
+ {0x40069,0x0},
+ {0x4000a,0xe08},
+ {0x4002a,0xc15},
+ {0x4004a,0x0},
+ {0x4006a,0x0},
+ {0x4000b,0x623},
+ {0x4002b,0x15},
+ {0x4004b,0x0},
+ {0x4006b,0x0},
+ {0x4000c,0x4028},
+ {0x4002c,0x80},
+ {0x4004c,0x0},
+ {0x4006c,0x0},
+ {0x4000d,0xe08},
+ {0x4002d,0xc1a},
+ {0x4004d,0x0},
+ {0x4006d,0x0},
+ {0x4000e,0x623},
+ {0x4002e,0x1a},
+ {0x4004e,0x0},
+ {0x4006e,0x0},
+ {0x4000f,0x4040},
+ {0x4002f,0x80},
+ {0x4004f,0x0},
+ {0x4006f,0x0},
+ {0x40010,0x2604},
+ {0x40030,0x15},
+ {0x40050,0x0},
+ {0x40070,0x0},
+ {0x40011,0x708},
+ {0x40031,0x5},
+ {0x40051,0x0},
+ {0x40071,0x2002},
+ {0x40012,0x8},
+ {0x40032,0x80},
+ {0x40052,0x0},
+ {0x40072,0x0},
+ {0x40013,0x2604},
+ {0x40033,0x1a},
+ {0x40053,0x0},
+ {0x40073,0x0},
+ {0x40014,0x708},
+ {0x40034,0xa},
+ {0x40054,0x0},
+ {0x40074,0x2002},
+ {0x40015,0x4040},
+ {0x40035,0x80},
+ {0x40055,0x0},
+ {0x40075,0x0},
+ {0x40016,0x60a},
+ {0x40036,0x15},
+ {0x40056,0x1200},
+ {0x40076,0x0},
+ {0x40017,0x61a},
+ {0x40037,0x15},
+ {0x40057,0x1300},
+ {0x40077,0x0},
+ {0x40018,0x60a},
+ {0x40038,0x1a},
+ {0x40058,0x1200},
+ {0x40078,0x0},
+ {0x40019,0x642},
+ {0x40039,0x1a},
+ {0x40059,0x1300},
+ {0x40079,0x0},
+ {0x4001a,0x4808},
+ {0x4003a,0x880},
+ {0x4005a,0x0},
+ {0x4007a,0x0},
+ {0x900a7,0x0},
+ {0x900a8,0x790},
+ {0x900a9,0x11a},
+ {0x900aa,0x8},
+ {0x900ab,0x7aa},
+ {0x900ac,0x2a},
+ {0x900ad,0x10},
+ {0x900ae,0x7b2},
+ {0x900af,0x2a},
+ {0x900b0,0x0},
+ {0x900b1,0x7c8},
+ {0x900b2,0x109},
+ {0x900b3,0x10},
+ {0x900b4,0x2a8},
+ {0x900b5,0x129},
+ {0x900b6,0x8},
+ {0x900b7,0x370},
+ {0x900b8,0x129},
+ {0x900b9,0xa},
+ {0x900ba,0x3c8},
+ {0x900bb,0x1a9},
+ {0x900bc,0xc},
+ {0x900bd,0x408},
+ {0x900be,0x199},
+ {0x900bf,0x14},
+ {0x900c0,0x790},
+ {0x900c1,0x11a},
+ {0x900c2,0x8},
+ {0x900c3,0x4},
+ {0x900c4,0x18},
+ {0x900c5,0xe},
+ {0x900c6,0x408},
+ {0x900c7,0x199},
+ {0x900c8,0x8},
+ {0x900c9,0x8568},
+ {0x900ca,0x108},
+ {0x900cb,0x18},
+ {0x900cc,0x790},
+ {0x900cd,0x16a},
+ {0x900ce,0x8},
+ {0x900cf,0x1d8},
+ {0x900d0,0x169},
+ {0x900d1,0x10},
+ {0x900d2,0x8558},
+ {0x900d3,0x168},
+ {0x900d4,0x70},
+ {0x900d5,0x788},
+ {0x900d6,0x16a},
+ {0x900d7,0x1ff8},
+ {0x900d8,0x85a8},
+ {0x900d9,0x1e8},
+ {0x900da,0x50},
+ {0x900db,0x798},
+ {0x900dc,0x16a},
+ {0x900dd,0x60},
+ {0x900de,0x7a0},
+ {0x900df,0x16a},
+ {0x900e0,0x8},
+ {0x900e1,0x8310},
+ {0x900e2,0x168},
+ {0x900e3,0x8},
+ {0x900e4,0xa310},
+ {0x900e5,0x168},
+ {0x900e6,0xa},
+ {0x900e7,0x408},
+ {0x900e8,0x169},
+ {0x900e9,0x6e},
+ {0x900ea,0x0},
+ {0x900eb,0x68},
+ {0x900ec,0x0},
+ {0x900ed,0x408},
+ {0x900ee,0x169},
+ {0x900ef,0x0},
+ {0x900f0,0x8310},
+ {0x900f1,0x168},
+ {0x900f2,0x0},
+ {0x900f3,0xa310},
+ {0x900f4,0x168},
+ {0x900f5,0x1ff8},
+ {0x900f6,0x85a8},
+ {0x900f7,0x1e8},
+ {0x900f8,0x68},
+ {0x900f9,0x798},
+ {0x900fa,0x16a},
+ {0x900fb,0x78},
+ {0x900fc,0x7a0},
+ {0x900fd,0x16a},
+ {0x900fe,0x68},
+ {0x900ff,0x790},
+ {0x90100,0x16a},
+ {0x90101,0x8},
+ {0x90102,0x8b10},
+ {0x90103,0x168},
+ {0x90104,0x8},
+ {0x90105,0xab10},
+ {0x90106,0x168},
+ {0x90107,0xa},
+ {0x90108,0x408},
+ {0x90109,0x169},
+ {0x9010a,0x58},
+ {0x9010b,0x0},
+ {0x9010c,0x68},
+ {0x9010d,0x0},
+ {0x9010e,0x408},
+ {0x9010f,0x169},
+ {0x90110,0x0},
+ {0x90111,0x8b10},
+ {0x90112,0x168},
+ {0x90113,0x0},
+ {0x90114,0xab10},
+ {0x90115,0x168},
+ {0x90116,0x0},
+ {0x90117,0x1d8},
+ {0x90118,0x169},
+ {0x90119,0x80},
+ {0x9011a,0x790},
+ {0x9011b,0x16a},
+ {0x9011c,0x18},
+ {0x9011d,0x7aa},
+ {0x9011e,0x6a},
+ {0x9011f,0xa},
+ {0x90120,0x0},
+ {0x90121,0x1e9},
+ {0x90122,0x8},
+ {0x90123,0x8080},
+ {0x90124,0x108},
+ {0x90125,0xf},
+ {0x90126,0x408},
+ {0x90127,0x169},
+ {0x90128,0xc},
+ {0x90129,0x0},
+ {0x9012a,0x68},
+ {0x9012b,0x9},
+ {0x9012c,0x0},
+ {0x9012d,0x1a9},
+ {0x9012e,0x0},
+ {0x9012f,0x408},
+ {0x90130,0x169},
+ {0x90131,0x0},
+ {0x90132,0x8080},
+ {0x90133,0x108},
+ {0x90134,0x8},
+ {0x90135,0x7aa},
+ {0x90136,0x6a},
+ {0x90137,0x0},
+ {0x90138,0x8568},
+ {0x90139,0x108},
+ {0x9013a,0xb7},
+ {0x9013b,0x790},
+ {0x9013c,0x16a},
+ {0x9013d,0x1f},
+ {0x9013e,0x0},
+ {0x9013f,0x68},
+ {0x90140,0x8},
+ {0x90141,0x8558},
+ {0x90142,0x168},
+ {0x90143,0xf},
+ {0x90144,0x408},
+ {0x90145,0x169},
+ {0x90146,0xc},
+ {0x90147,0x0},
+ {0x90148,0x68},
+ {0x90149,0x0},
+ {0x9014a,0x408},
+ {0x9014b,0x169},
+ {0x9014c,0x0},
+ {0x9014d,0x8558},
+ {0x9014e,0x168},
+ {0x9014f,0x8},
+ {0x90150,0x3c8},
+ {0x90151,0x1a9},
+ {0x90152,0x3},
+ {0x90153,0x370},
+ {0x90154,0x129},
+ {0x90155,0x20},
+ {0x90156,0x2aa},
+ {0x90157,0x9},
+ {0x90158,0x0},
+ {0x90159,0x400},
+ {0x9015a,0x10e},
+ {0x9015b,0x8},
+ {0x9015c,0xe8},
+ {0x9015d,0x109},
+ {0x9015e,0x0},
+ {0x9015f,0x8140},
+ {0x90160,0x10c},
+ {0x90161,0x10},
+ {0x90162,0x8138},
+ {0x90163,0x10c},
+ {0x90164,0x8},
+ {0x90165,0x7c8},
+ {0x90166,0x101},
+ {0x90167,0x8},
+ {0x90168,0x0},
+ {0x90169,0x8},
+ {0x9016a,0x8},
+ {0x9016b,0x448},
+ {0x9016c,0x109},
+ {0x9016d,0xf},
+ {0x9016e,0x7c0},
+ {0x9016f,0x109},
+ {0x90170,0x0},
+ {0x90171,0xe8},
+ {0x90172,0x109},
+ {0x90173,0x47},
+ {0x90174,0x630},
+ {0x90175,0x109},
+ {0x90176,0x8},
+ {0x90177,0x618},
+ {0x90178,0x109},
+ {0x90179,0x8},
+ {0x9017a,0xe0},
+ {0x9017b,0x109},
+ {0x9017c,0x0},
+ {0x9017d,0x7c8},
+ {0x9017e,0x109},
+ {0x9017f,0x8},
+ {0x90180,0x8140},
+ {0x90181,0x10c},
+ {0x90182,0x0},
+ {0x90183,0x1},
+ {0x90184,0x8},
+ {0x90185,0x8},
+ {0x90186,0x4},
+ {0x90187,0x8},
+ {0x90188,0x8},
+ {0x90189,0x7c8},
+ {0x9018a,0x101},
+ {0x90006,0x0},
+ {0x90007,0x0},
+ {0x90008,0x8},
+ {0x90009,0x0},
+ {0x9000a,0x0},
+ {0x9000b,0x0},
+ {0xd00e7,0x400},
+ {0x90017,0x0},
+ {0x9001f,0x2a},
+ {0x90026,0x6a},
+ {0x400d0,0x0},
+ {0x400d1,0x101},
+ {0x400d2,0x105},
+ {0x400d3,0x107},
+ {0x400d4,0x10f},
+ {0x400d5,0x202},
+ {0x400d6,0x20a},
+ {0x400d7,0x20b},
+ {0x2003a,0x2},
+ {0x2000b,0x4b},
+ {0x2000c,0x96},
+ {0x2000d,0x5dc},
+ {0x2000e,0x2c},
+ {0x12000b,0xc},
+ {0x12000c,0x19},
+ {0x12000d,0xfa},
+ {0x12000e,0x10},
+ {0x22000b,0x3},
+ {0x22000c,0x6},
+ {0x22000d,0x3e},
+ {0x22000e,0x10},
+ {0x9000c,0x0},
+ {0x9000d,0x173},
+ {0x9000e,0x60},
+ {0x9000f,0x6110},
+ {0x90010,0x2152},
+ {0x90011,0xdfbd},
+ {0x90012,0x60},
+ {0x90013,0x6152},
+ {0x20010,0x5a},
+ {0x20011,0x3},
+ {0x120010,0x5a},
+ {0x120011,0x3},
+ {0x220010,0x5a},
+ {0x220011,0x3},
+ {0x40080,0xe0},
+ {0x40081,0x12},
+ {0x40082,0xe0},
+ {0x40083,0x12},
+ {0x40084,0xe0},
+ {0x40085,0x12},
+ {0x140080,0xe0},
+ {0x140081,0x12},
+ {0x140082,0xe0},
+ {0x140083,0x12},
+ {0x140084,0xe0},
+ {0x140085,0x12},
+ {0x240080,0xe0},
+ {0x240081,0x12},
+ {0x240082,0xe0},
+ {0x240083,0x12},
+ {0x240084,0xe0},
+ {0x240085,0x12},
+ {0x400fd,0xf},
+ {0x10011,0x1},
+ {0x10012,0x1},
+ {0x10013,0x180},
+ {0x10018,0x1},
+ {0x10002,0x6209},
+ {0x100b2,0x1},
+ {0x101b4,0x1},
+ {0x102b4,0x1},
+ {0x103b4,0x1},
+ {0x104b4,0x1},
+ {0x105b4,0x1},
+ {0x106b4,0x1},
+ {0x107b4,0x1},
+ {0x108b4,0x1},
+ {0x11011,0x1},
+ {0x11012,0x1},
+ {0x11013,0x180},
+ {0x11018,0x1},
+ {0x11002,0x6209},
+ {0x110b2,0x1},
+ {0x111b4,0x1},
+ {0x112b4,0x1},
+ {0x113b4,0x1},
+ {0x114b4,0x1},
+ {0x115b4,0x1},
+ {0x116b4,0x1},
+ {0x117b4,0x1},
+ {0x118b4,0x1},
+ {0x12011,0x1},
+ {0x12012,0x1},
+ {0x12013,0x180},
+ {0x12018,0x1},
+ {0x12002,0x6209},
+ {0x120b2,0x1},
+ {0x121b4,0x1},
+ {0x122b4,0x1},
+ {0x123b4,0x1},
+ {0x124b4,0x1},
+ {0x125b4,0x1},
+ {0x126b4,0x1},
+ {0x127b4,0x1},
+ {0x128b4,0x1},
+ {0x13011,0x1},
+ {0x13012,0x1},
+ {0x13013,0x180},
+ {0x13018,0x1},
+ {0x13002,0x6209},
+ {0x130b2,0x1},
+ {0x131b4,0x1},
+ {0x132b4,0x1},
+ {0x133b4,0x1},
+ {0x134b4,0x1},
+ {0x135b4,0x1},
+ {0x136b4,0x1},
+ {0x137b4,0x1},
+ {0x138b4,0x1},
+ {0x2003a,0x2},
+ {0xc0080,0x2},
+ {0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg_1g_2ch1cs15r10cx32[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg_1g_2ch1cs15r10cx32,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1g_2ch1cs15r10cx32),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg_1g_2ch1cs15r10cx32,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1g_2ch1cs15r10cx32),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg_1g_2ch1cs15r10cx32,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1g_2ch1cs15r10cx32),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1g_2ch1cs15r10cx32),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info innocomm_wb15_dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg_1g_2ch1cs15r10cx32,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1g_2ch1cs15r10cx32),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg_1g_2ch1cs15r10cx32,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1g_2ch1cs15r10cx32),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 400, 100, },
+};
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 0a30f05aa2..055e5f4c99 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -5,7 +5,7 @@
#include <ddr_spd.h>
#include <image-metadata.h>
#include <platform_data/mmc-esdhc-imx.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
#include <soc/fsl/fsl_ddr_sdram.h>
#include <soc/fsl/immap_lsch2.h>
#include <asm/barebox-arm-head.h>
@@ -187,7 +187,7 @@ static struct fsl_ddr_info ls1046a_info = {
static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
- struct fsl_i2c *i2c;
+ struct pbl_i2c *i2c;
int ret;
if (get_pc() >= membase) {
@@ -205,7 +205,7 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
IMD_USED_OF(fsl_ls1046a_rdb);
i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR));
- ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom);
+ ret = spd_read_eeprom(i2c, 0x51, &spd_eeprom);
if (ret) {
pr_err("Cannot read SPD EEPROM: %d\n", ret);
goto err;
diff --git a/arch/arm/boards/meerkat96/Makefile b/arch/arm/boards/meerkat96/Makefile
new file mode 100644
index 0000000000..5678718188
--- /dev/null
+++ b/arch/arm/boards/meerkat96/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/meerkat96/board.c b/arch/arm/boards/meerkat96/board.c
new file mode 100644
index 0000000000..49e9c06f78
--- /dev/null
+++ b/arch/arm/boards/meerkat96/board.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <of.h>
+#include <deep-probe.h>
+
+static const struct of_device_id meerkat96_match[] = {
+ { .compatible = "novtech,imx7d-meerkat96" },
+ { /* Sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(meerkat96_match);
diff --git a/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg b/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg
new file mode 100644
index 0000000000..a49b816178
--- /dev/null
+++ b/arch/arm/boards/meerkat96/flash-header-mx7-meerkat96.imxcfg
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+soc imx7
+loadaddr 0x80000000
+ivtofs 0x400
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable OCRAM EPDC */
+wm 32 0x30340004 0x4F400005
+
+/* =============================================================================
+ * DDR Controller Registers
+ * =============================================================================
+ * Memory type: DDR3
+ * Manufacturer: ISSI
+ * Device Part Number: IS43TR16256AL-125KBL
+ * Clock Freq.: 533MHz
+ * Density per CS in Gb: 4
+ * Chip Selects used: 1
+ * Number of Banks: 8
+ * Row address: 15
+ * Column address: 10
+ * Data bus width: 16
+ * ROW-BANK interleave: ENABLED
+ * =============================================================================
+ */
+
+wm 32 0x30391000 0x00000002 // deassert presetn
+wm 32 0x307A0000 0x01041001 // DDRC_MSTR
+wm 32 0x307A0064 0x00400046 // DDRC_RFSHTMG
+wm 32 0x307a0490 0x00000001 // DDRC_PCTRL_0
+wm 32 0x307A00D4 0x00690000 // DDRC_INIT1
+wm 32 0x307A00D0 0x00020083 // DDRC_INIT0
+wm 32 0x307A00DC 0x09300004 // DDRC_INIT3
+wm 32 0x307A00E0 0x04080000 // DDRC_INIT4
+wm 32 0x307A00E4 0x00100004 // DDRC_INIT5
+wm 32 0x307A00F4 0x0000033F // DDRC_RANKCTL
+wm 32 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
+wm 32 0x307A0104 0x0007020D // DDRC_DRAMTMG1
+wm 32 0x307A0108 0x03040407 // DDRC_DRAMTMG2
+wm 32 0x307A010C 0x00002006 // DDRC_DRAMTMG3
+wm 32 0x307A0110 0x04020205 // DDRC_DRAMTMG4
+wm 32 0x307A0114 0x03030202 // DDRC_DRAMTMG5
+wm 32 0x307A0120 0x00000803 // DDRC_DRAMTMG8
+wm 32 0x307A0180 0x00800020 // DDRC_ZQCTL0
+wm 32 0x307A0190 0x02098204 // DDRC_DFITMG0
+wm 32 0x307A0194 0x00030303 // DDRC_DFITMG1
+wm 32 0x307A01A0 0x80400003 // DDRC_DFIUPD0
+wm 32 0x307A01A4 0x00100020 // DDRC_DFIUPD1
+wm 32 0x307A01A8 0x80100004 // DDRC_DFIUPD2
+wm 32 0x307A0200 0x00000015 // DDRC_ADDRMAP0
+wm 32 0x307A0204 0x00070707 // DDRC_ADDRMAP1
+wm 32 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
+wm 32 0x307A0214 0x06060606 // DDRC_ADDRMAP5
+wm 32 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
+wm 32 0x307A0240 0x06000604 // DDRC_ODTCFG
+wm 32 0x307A0244 0x00000001 // DDRC_ODTMAP
+
+
+/* =============================================================================
+ * PHY Control Register
+ * =============================================================================
+ */
+
+wm 32 0x30391000 0x00000000 // deassert presetn
+wm 32 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
+wm 32 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
+wm 32 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
+wm 32 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
+wm 32 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
+wm 32 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
+wm 32 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
+wm 32 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
+wm 32 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
+wm 32 0x30790018 0x0000000F // DDR_PHY_LP_CON0
+wm 32 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
+wm 32 0x307900C0 0x0E447304
+wm 32 0x307900C0 0x0E447306
+wm 32 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
+wm 32 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
+
+
+/* =============================================================================
+ * Final Initialization start sequence
+ * =============================================================================
+ */
+
+wm 32 0x30384130 0x00000000 // Disable Clock
+wm 32 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
+wm 32 0x30384130 0x00000002 // Enable Clock
+/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
diff --git a/arch/arm/boards/meerkat96/lowlevel.c b/arch/arm/boards/meerkat96/lowlevel.c
new file mode 100644
index 0000000000..1c9baeacfb
--- /dev/null
+++ b/arch/arm/boards/meerkat96/lowlevel.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <debug_ll.h>
+#include <io.h>
+#include <linux/sizes.h>
+#include <mach/debug_ll.h>
+#include <mach/iomux-mx7.h>
+#include <mach/imx7-ccm-regs.h>
+#include <mach/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+extern char __dtb_z_imx7d_meerkat96_start[];
+
+static void setup_uart(void)
+{
+ imx7_early_setup_uart_clock();
+ imx7_setup_pad(MX7D_PAD_SD1_WP__UART6_DCE_TX);
+ imx7_uart_setup_ll();
+ putc_ll('>');
+}
+
+ENTRY_FUNCTION_WITHSTACK(start_imx7d_meerkat96, 0, r0, r1, r2)
+{
+ void *fdt;
+
+ imx7_cpu_lowlevel_init();
+
+ setup_uart();
+
+ fdt = __dtb_z_imx7d_meerkat96_start + get_runtime_offset();
+
+ barebox_arm_entry(0x80000000, SZ_512M, fdt);
+}
diff --git a/arch/arm/boards/mnt-reform/lowlevel.c b/arch/arm/boards/mnt-reform/lowlevel.c
index 268dfb611a..d22c8b8a74 100644
--- a/arch/arm/boards/mnt-reform/lowlevel.c
+++ b/arch/arm/boards/mnt-reform/lowlevel.c
@@ -7,7 +7,8 @@
#include <common.h>
#include <debug_ll.h>
#include <firmware.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
#include <mach/atf.h>
#include <mach/esdctl.h>
#include <mach/generic.h>
@@ -18,7 +19,7 @@
#include <mach/xload.h>
#include <soc/imx8m/ddr.h>
-extern char __dtb_imx8mq_mnt_reform2_start[];
+extern char __dtb_z_imx8mq_mnt_reform2_start[];
#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MQ_PAD_CTL_DSE_65R)
@@ -36,7 +37,7 @@ static void mnt_reform_setup_uart(void)
putc_ll('>');
}
-static void i2c_mux_set(void *i2c, u8 channel)
+static void i2c_mux_set(struct pbl_i2c *i2c, u8 channel)
{
int ret;
u8 buf[1];
@@ -50,29 +51,14 @@ static void i2c_mux_set(void *i2c, u8 channel)
buf[0] = 1 << channel;
- ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
+ ret = pbl_i2c_xfer(i2c, msgs, ARRAY_SIZE(msgs));
if (ret != 1)
pr_err("failed to set i2c mux\n");
}
-static void i2c_regulator_set_voltage(void *i2c, u8 reg, u8 voffs)
+static void i2c_regulator_set_voltage(struct pbl_i2c *i2c, u8 reg, u8 voffs)
{
- int ret;
- u8 buf[2];
- struct i2c_msg msgs[] = {
- {
- .addr = 0x60,
- .buf = buf,
- .len = 2,
- },
- };
-
- buf[0] = reg;
- buf[1] = 0x80 + voffs;
-
- ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
- if (ret != 1)
- pr_err("failed to set voltage\n");
+ pmic_reg_write(i2c, 0x60, reg, 0x80 + voffs);
}
#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MQ_PAD_CTL_DSE_45R | \
@@ -81,7 +67,7 @@ static void i2c_regulator_set_voltage(void *i2c, u8 reg, u8 voffs)
static void mnt_reform_init_power(void)
{
- void *i2c;
+ struct pbl_i2c *i2c;
imx8mq_setup_pad(IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
imx8mq_setup_pad(IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
@@ -139,7 +125,7 @@ static __noreturn noinline void mnt_reform_start(void)
mnt_reform_init_power();
- imx8mq_ddr_init(&mnt_reform_dram_timing);
+ imx8mq_ddr_init(&mnt_reform_dram_timing, DRAM_TYPE_LPDDR4);
imx8mq_get_boot_source(&src, &instance);
switch (src) {
@@ -173,7 +159,7 @@ static __noreturn noinline void mnt_reform_start(void)
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mq_barebox_entry(__dtb_imx8mq_mnt_reform2_start);
+ imx8mq_barebox_entry(__dtb_z_imx8mq_mnt_reform2_start);
}
ENTRY_FUNCTION(start_mnt_reform, r0, r1, r2)
diff --git a/arch/arm/boards/mnt-reform/lpddr4-timing.c b/arch/arm/boards/mnt-reform/lpddr4-timing.c
index 0e962890fd..0b5853000d 100644
--- a/arch/arm/boards/mnt-reform/lpddr4-timing.c
+++ b/arch/arm/boards/mnt-reform/lpddr4-timing.c
@@ -1000,7 +1000,6 @@ static struct dram_fsp_msg mnt_reform_lpddr4_dram_fsp_msg[] = {
/* ddr timing config params */
struct dram_timing_info mnt_reform_dram_timing = {
- .dram_type = DRAM_TYPE_LPDDR4,
.ddrc_cfg = mnt_reform_lpddr4_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(mnt_reform_lpddr4_ddrc_cfg),
.ddrphy_cfg = mnt_reform_lpddr4_ddrphy_cfg,
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
index c2f6206cfd..6132df53ec 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c
@@ -3,27 +3,24 @@
#include <io.h>
#include <common.h>
#include <debug_ll.h>
-#include <firmware.h>
#include <asm/mmu.h>
#include <asm/cache.h>
-#include <asm/sections.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
#include <linux/sizes.h>
-#include <mach/atf.h>
-#include <mach/xload.h>
#include <mach/esdctl.h>
#include <mach/generic.h>
#include <mach/imx8mm-regs.h>
#include <mach/iomux-mx8mm.h>
#include <mach/imx8m-ccm-regs.h>
#include <mfd/bd71837.h>
+#include <mach/xload.h>
#include <soc/imx8m/ddr.h>
-#include <soc/fsl/fsl_udc.h>
#include <image-metadata.h>
-extern char __dtb_imx8mm_evk_start[];
+extern char __dtb_z_imx8mm_evk_start[];
#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
@@ -41,30 +38,22 @@ static void setup_uart(void)
putc_ll('>');
}
-static void pmic_reg_write(void *i2c, int reg, uint8_t val)
-{
- int ret;
- u8 buf[32];
- struct i2c_msg msgs[] = {
- {
- .addr = 0x4b,
- .buf = buf,
- },
- };
-
- buf[0] = reg;
- buf[1] = val;
-
- msgs[0].len = 2;
-
- ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
- if (ret != 1)
- pr_err("Failed to write to pmic\n");
-}
+static struct pmic_config bd71837_cfg[] = {
+ /* decrease RESET key long push time from the default 10s to 10ms */
+ { BD718XX_PWRONCONFIG1, 0x0 },
+ /* unlock the PMIC regs */
+ { BD718XX_REGLOCK, 0x1 },
+ /* increase VDD_SOC to typical value 0.85v before first DRAM access */
+ { BD718XX_BUCK1_VOLT_RUN, 0x0f },
+ /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+ { BD718XX_1ST_NODVS_BUCK_VOLT, 0x83 },
+ /* lock the PMIC regs */
+ { BD718XX_REGLOCK, 0x11 },
+};
-static int power_init_board(void)
+static void power_init_board(void)
{
- void *i2c;
+ struct pbl_i2c *i2c;
imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL);
imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA);
@@ -74,33 +63,13 @@ static int power_init_board(void)
i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR));
- /* decrease RESET key long push time from the default 10s to 10ms */
- pmic_reg_write(i2c, BD718XX_PWRONCONFIG1, 0x0);
-
- /* unlock the PMIC regs */
- pmic_reg_write(i2c, BD718XX_REGLOCK, 0x1);
-
- /* increase VDD_SOC to typical value 0.85v before first DRAM access */
- pmic_reg_write(i2c, BD718XX_BUCK1_VOLT_RUN, 0x0f);
-
- /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
- pmic_reg_write(i2c, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
-
- /* lock the PMIC regs */
- pmic_reg_write(i2c, BD718XX_REGLOCK, 0x11);
-
- return 0;
+ pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg));
}
extern struct dram_timing_info imx8mm_evk_dram_timing;
static void start_atf(void)
{
- size_t bl31_size;
- const u8 *bl31;
- enum bootsource src;
- int instance;
-
/*
* If we are in EL3 we are running for the first time and need to
* initialize the DRAM and run TF-A (BL31). The TF-A will then jump
@@ -110,37 +79,9 @@ static void start_atf(void)
return;
power_init_board();
- imx8mm_ddr_init(&imx8mm_evk_dram_timing);
-
- imx8mm_get_boot_source(&src, &instance);
- switch (src) {
- case BOOTSOURCE_MMC:
- imx8m_esdhc_load_image(instance, false);
- break;
- case BOOTSOURCE_SERIAL:
- imx8mm_barebox_load_usb((void *)MX8M_ATF_BL33_BASE_ADDR);
- break;
- default:
- printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
- hang();
- }
-
- /*
- * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
- * in EL2. Copy the image there, but replace the PBL part of
- * that image with ourselves. On a high assurance boot only the
- * currently running code is validated and contains the checksum
- * for the piggy data, so we need to ensure that we are running
- * the same code in DRAM.
- */
- memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
- __image_start, barebox_pbl_size);
-
- get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size);
-
- imx8mm_atf_load_bl31(bl31, bl31_size);
+ imx8mm_ddr_init(&imx8mm_evk_dram_timing, DRAM_TYPE_LPDDR4);
- /* not reached */
+ imx8mm_load_and_start_image_via_tfa();
}
/*
@@ -168,7 +109,7 @@ static __noreturn noinline void nxp_imx8mm_evk_start(void)
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mm_barebox_entry(__dtb_imx8mm_evk_start);
+ imx8mm_barebox_entry(__dtb_z_imx8mm_evk_start);
}
ENTRY_FUNCTION(start_nxp_imx8mm_evk, r0, r1, r2)
diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
index 68efbbdf91..e7c01f9cc9 100644
--- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c
@@ -1965,7 +1965,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
/* lpddr4 timing config params on EVK board */
struct dram_timing_info imx8mm_evk_dram_timing = {
- .dram_type = DRAM_TYPE_LPDDR4,
.ddrc_cfg = lpddr4_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
.ddrphy_cfg = lpddr4_ddrphy_cfg,
diff --git a/arch/arm/boards/nxp-imx8mn-evk/board.c b/arch/arm/boards/nxp-imx8mn-evk/board.c
index 3c478d5f70..3606dabe9d 100644
--- a/arch/arm/boards/nxp-imx8mn-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mn-evk/board.c
@@ -5,6 +5,7 @@
#include <bootsource.h>
#include <common.h>
+#include <deep-probe.h>
#include <init.h>
#include <linux/phy.h>
#include <linux/sizes.h>
@@ -30,14 +31,11 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
return 0;
}
-static int nxp_imx8mn_evk_init(void)
+static int imx8mn_evk_probe(struct device_d *dev)
{
int emmc_bbu_flag = 0;
int sd_bbu_flag = 0;
- if (!of_machine_is_compatible("fsl,imx8mn-evk"))
- return 0;
-
if (bootsource_get() == BOOTSOURCE_MMC) {
if (bootsource_get_instance() == 2) {
of_device_enable_path("/chosen/environment-emmc");
@@ -59,4 +57,17 @@ static int nxp_imx8mn_evk_init(void)
return 0;
}
-coredevice_initcall(nxp_imx8mn_evk_init);
+
+static const struct of_device_id imx8mn_evk_of_match[] = {
+ { .compatible = "fsl,imx8mn-evk" },
+ { .compatible = "fsl,imx8mn-ddr4-evk" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(imx8mn_evk_of_match);
+
+static struct driver_d imx8mn_evkboard_driver = {
+ .name = "board-imx8mn-evk",
+ .probe = imx8mn_evk_probe,
+ .of_compatible = DRV_OF_COMPAT(imx8mn_evk_of_match),
+};
+coredevice_platform_driver(imx8mn_evkboard_driver);
diff --git a/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c b/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c
index 7ce371384e..131a63156e 100644
--- a/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mn-evk/ddr4-timing.c
@@ -1040,7 +1040,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
/* ddr timing config params */
struct dram_timing_info imx8mn_evk_ddr4_timing = {
- .dram_type = DRAM_TYPE_DDR4,
.ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = ddr_ddrphy_cfg,
diff --git a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
index de53213ebc..7da9c33565 100644
--- a/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mn-evk/lowlevel.c
@@ -9,7 +9,8 @@
#include <asm/sections.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
#include <linux/sizes.h>
#include <mach/atf.h>
#include <mach/xload.h>
@@ -22,8 +23,6 @@
#include <mfd/bd71837.h>
#include <soc/imx8m/ddr.h>
-extern char __dtb_z_imx8mn_evk_start[];
-
static void setup_uart(void)
{
void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
@@ -38,108 +37,50 @@ static void setup_uart(void)
putc_ll('>');
}
-static void pmic_reg_write(void *i2c, int addr, int reg, uint8_t val)
-{
- int ret;
- u8 buf[32];
- struct i2c_msg msgs[] = {
- {
- .addr = addr,
- .buf = buf,
- },
- };
-
- buf[0] = reg;
- buf[1] = val;
-
- msgs[0].len = 2;
-
- ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
- if (ret != 1)
- pr_err("Failed to write to pmic@%x: %d\n", addr, ret);
-}
-
-static int power_init_board_pca9450(void *i2c, int addr)
-{
- u8 buf[1];
- struct i2c_msg msgs[] = {
- {
- .addr = addr,
- .buf = buf,
- .flags = I2C_M_RD,
- .len = 1,
- },
- };
-
- if (i2c_fsl_xfer(i2c, msgs, 1) != 1)
- return -ENODEV;
-
+static struct pmic_config pca9450_cfg[] = {
/* BUCKxOUT_DVS0/1 control BUCK123 output */
- pmic_reg_write(i2c, addr, PCA9450_BUCK123_DVS, 0x29);
-
+ { PCA9450_BUCK123_DVS, 0x29 },
/*
* increase VDD_SOC to typical value 0.95V before first
* DRAM access, set DVS1 to 0.85v for suspend.
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
- pmic_reg_write(i2c, addr, PCA9450_BUCK1OUT_DVS0, 0x1C);
-
+ { PCA9450_BUCK1OUT_DVS0, 0x1C },
/* Set DVS1 to 0.85v for suspend */
/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
- pmic_reg_write(i2c, addr, PCA9450_BUCK1OUT_DVS1, 0x14);
- pmic_reg_write(i2c, addr, PCA9450_BUCK1CTRL, 0x59);
-
+ { PCA9450_BUCK1OUT_DVS1, 0x14 },
+ { PCA9450_BUCK1CTRL, 0x59 },
/* set VDD_SNVS_0V8 from default 0.85V */
- pmic_reg_write(i2c, addr, PCA9450_LDO2CTRL, 0xC0);
-
+ { PCA9450_LDO2CTRL, 0xC0 },
/* enable LDO4 to 1.2v */
- pmic_reg_write(i2c, addr, PCA9450_LDO4CTRL, 0x44);
-
+ { PCA9450_LDO4CTRL, 0x44 },
/* set WDOG_B_CFG to cold reset */
- pmic_reg_write(i2c, addr, PCA9450_RESET_CTRL, 0xA1);
-
- return 0;
-}
+ { PCA9450_RESET_CTRL, 0xA1 },
+};
-static int power_init_board_bd71837(void *i2c, int addr)
-{
+static struct pmic_config bd71837_cfg[] = {
/* decrease RESET key long push time from the default 10s to 10ms */
- pmic_reg_write(i2c, addr, BD718XX_PWRONCONFIG1, 0x0);
-
+ { BD718XX_PWRONCONFIG1, 0x0 },
/* unlock the PMIC regs */
- pmic_reg_write(i2c, addr, BD718XX_REGLOCK, 0x1);
-
+ { BD718XX_REGLOCK, 0x1 },
/* Set VDD_ARM to typical value 0.85v for 1.2Ghz */
- pmic_reg_write(i2c, addr, BD718XX_BUCK2_VOLT_RUN, 0xf);
-
+ { BD718XX_BUCK2_VOLT_RUN, 0xf },
/* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
- pmic_reg_write(i2c, addr, BD718XX_BUCK1_VOLT_RUN, 0xf);
-
+ { BD718XX_BUCK1_VOLT_RUN, 0xf },
/* Set VDD_SOC 0.85v for suspend */
- pmic_reg_write(i2c, addr, BD718XX_BUCK1_VOLT_SUSP, 0xf);
-
- /* increase NVCC_DRAM_1V2 to 1.2v for DDR4
- * */
- pmic_reg_write(i2c, addr, BD718XX_4TH_NODVS_BUCK_CTRL, 0x28);
-
+ { BD718XX_BUCK1_VOLT_SUSP, 0xf },
+ /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+ { BD718XX_4TH_NODVS_BUCK_CTRL, 0x28 },
/* lock the PMIC regs */
- pmic_reg_write(i2c, addr, BD718XX_REGLOCK, 0x11);
-
- return 0;
-}
+ { BD718XX_REGLOCK, 0x11 },
+};
extern struct dram_timing_info imx8mn_evk_ddr4_timing, imx8mn_evk_lpddr4_timing;
static void start_atf(void)
{
- struct dram_timing_info *dram_timing = &imx8mn_evk_lpddr4_timing;
- size_t bl31_size;
- const u8 *bl31;
- enum bootsource src;
- void *i2c;
- int instance;
- int ret;
+ struct pbl_i2c *i2c;
/*
* If we are in EL3 we are running for the first time and need to
@@ -157,40 +98,15 @@ static void start_atf(void)
i2c = imx8m_i2c_early_init(IOMEM(MX8MN_I2C1_BASE_ADDR));
- ret = power_init_board_pca9450(i2c, 0x25);
- if (ret) {
- power_init_board_bd71837(i2c, 0x4b);
- dram_timing = &imx8mn_evk_ddr4_timing;
- }
-
- imx8mn_ddr_init(dram_timing);
-
- imx8mn_get_boot_source(&src, &instance);
- switch (src) {
- case BOOTSOURCE_MMC:
- imx8mn_esdhc_load_image(instance, false);
- break;
- default:
- printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
- hang();
+ if (i2c_dev_probe(i2c, 0x25, true) == 0) {
+ pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
+ imx8mn_ddr_init(&imx8mn_evk_lpddr4_timing, DRAM_TYPE_LPDDR4);
+ } else {
+ pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg));
+ imx8mn_ddr_init(&imx8mn_evk_ddr4_timing, DRAM_TYPE_DDR4);
}
- /*
- * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
- * in EL2. Copy the image there, but replace the PBL part of
- * that image with ourselves. On a high assurance boot only the
- * currently running code is validated and contains the checksum
- * for the piggy data, so we need to ensure that we are running
- * the same code in DRAM.
- */
- memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
- __image_start, barebox_pbl_size);
-
- get_builtin_firmware(imx8mn_bl31_bin, &bl31, &bl31_size);
-
- imx8mn_atf_load_bl31(bl31, bl31_size);
-
- /* not reached */
+ imx8mn_load_and_start_image_via_tfa();
}
/*
@@ -211,14 +127,23 @@ static void start_atf(void)
*/
static __noreturn noinline void nxp_imx8mn_evk_start(void)
{
+ extern char __dtb_z_imx8mn_evk_start[], __dtb_z_imx8mn_ddr4_evk_start[];
+ void *fdt;
+
setup_uart();
start_atf();
+ /* Check if we configured DDR4 in EL3 */
+ if (readl(MX8M_DDRC_CTL_BASE_ADDR) & BIT(4))
+ fdt = __dtb_z_imx8mn_ddr4_evk_start;
+ else
+ fdt = __dtb_z_imx8mn_evk_start;
+
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mn_barebox_entry(__dtb_z_imx8mn_evk_start);
+ imx8mn_barebox_entry(fdt);
}
ENTRY_FUNCTION(start_nxp_imx8mn_evk, r0, r1, r2)
diff --git a/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c
index c53bcc705d..940b21cedb 100644
--- a/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mn-evk/lpddr4-timing.c
@@ -1576,7 +1576,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
/* ddr timing config params */
struct dram_timing_info imx8mn_evk_lpddr4_timing = {
- .dram_type = DRAM_TYPE_LPDDR4,
.ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = ddr_ddrphy_cfg,
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
index c7916e4962..4f24dd4cd4 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
@@ -10,7 +10,8 @@
#include <asm/sections.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
-#include <i2c/i2c-early.h>
+#include <pbl/i2c.h>
+#include <pbl/pmic.h>
#include <linux/sizes.h>
#include <mach/atf.h>
#include <mach/xload.h>
@@ -23,7 +24,7 @@
#include <soc/imx8m/ddr.h>
#include <soc/fsl/fsl_udc.h>
-extern char __dtb_imx8mp_evk_start[];
+extern char __dtb_z_imx8mp_evk_start[];
#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
MX8MP_PAD_CTL_FSEL)
@@ -48,30 +49,25 @@ static void setup_uart(void)
putc_ll('>');
}
-static void pmic_reg_write(void *i2c, int reg, uint8_t val)
-{
- int ret;
- u8 buf[32];
- struct i2c_msg msgs[] = {
- {
- .addr = 0x25,
- .buf = buf,
- },
- };
-
- buf[0] = reg;
- buf[1] = val;
-
- msgs[0].len = 2;
-
- ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs));
- if (ret != 1)
- pr_err("Failed to write to pmic\n");
-}
+static struct pmic_config pca9450_cfg[] = {
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ { PCA9450_BUCK123_DVS, 0x29 },
+ /*
+ * increase VDD_SOC to typical value 0.95V before first
+ * DRAM access, set DVS1 to 0.85v for suspend.
+ * Enable DVS control through PMIC_STBY_REQ and
+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
+ */
+ { PCA9450_BUCK1OUT_DVS0, 0x1C },
+ { PCA9450_BUCK1OUT_DVS1, 0x14 },
+ { PCA9450_BUCK1CTRL, 0x59 },
+ /* set WDOG_B_CFG to cold reset */
+ { PCA9450_RESET_CTRL, 0xA1 },
+};
-static int power_init_board(void)
+static void power_init_board(void)
{
- void *i2c;
+ struct pbl_i2c *i2c;
imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
@@ -81,34 +77,13 @@ static int power_init_board(void)
i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
- /* BUCKxOUT_DVS0/1 control BUCK123 output */
- pmic_reg_write(i2c, PCA9450_BUCK123_DVS, 0x29);
-
- /*
- * increase VDD_SOC to typical value 0.95V before first
- * DRAM access, set DVS1 to 0.85v for suspend.
- * Enable DVS control through PMIC_STBY_REQ and
- * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
- */
- pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS0, 0x1C);
- pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS1, 0x14);
- pmic_reg_write(i2c, PCA9450_BUCK1CTRL, 0x59);
-
- /* set WDOG_B_CFG to cold reset */
- pmic_reg_write(i2c, PCA9450_RESET_CTRL, 0xA1);
-
- return 0;
+ pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
}
extern struct dram_timing_info imx8mp_evk_dram_timing;
static void start_atf(void)
{
- size_t bl31_size;
- const u8 *bl31;
- enum bootsource src;
- int instance;
-
/*
* If we are in EL3 we are running for the first time and need to
* initialize the DRAM and run TF-A (BL31). The TF-A will then jump
@@ -119,35 +94,9 @@ static void start_atf(void)
power_init_board();
- imx8mp_ddr_init(&imx8mp_evk_dram_timing);
-
- imx8mp_get_boot_source(&src, &instance);
- switch (src) {
- case BOOTSOURCE_MMC:
- imx8mp_esdhc_load_image(instance, false);
- break;
- default:
- printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
- hang();
- }
-
-
- /*
- * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
- * in EL2. Copy the image there, but replace the PBL part of
- * that image with ourselves. On a high assurance boot only the
- * currently running code is validated and contains the checksum
- * for the piggy data, so we need to ensure that we are running
- * the same code in DRAM.
- */
- memcpy((void *)MX8M_ATF_BL33_BASE_ADDR,
- __image_start, barebox_pbl_size);
-
- get_builtin_firmware(imx8mp_bl31_bin, &bl31, &bl31_size);
-
- imx8mp_atf_load_bl31(bl31, bl31_size);
+ imx8mp_ddr_init(&imx8mp_evk_dram_timing, DRAM_TYPE_LPDDR4);
- /* not reached */
+ imx8mp_load_and_start_image_via_tfa();
}
/*
@@ -175,7 +124,7 @@ static __noreturn noinline void nxp_imx8mp_evk_start(void)
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mp_barebox_entry(__dtb_imx8mp_evk_start);
+ imx8mp_barebox_entry(__dtb_z_imx8mp_evk_start);
}
ENTRY_FUNCTION(start_nxp_imx8mp_evk, r0, r1, r2)
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c
index 681e70d060..3028bc084c 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c
@@ -1834,7 +1834,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
/* ddr timing config params */
struct dram_timing_info imx8mp_evk_dram_timing = {
- .dram_type = DRAM_TYPE_LPDDR4,
.ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = ddr_ddrphy_cfg,
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 92cc22e022..0c9f6345ff 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -21,7 +21,7 @@
#include "ddr.h"
-extern char __dtb_imx8mq_evk_start[];
+extern char __dtb_z_imx8mq_evk_start[];
#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
@@ -97,7 +97,7 @@ static __noreturn noinline void nxp_imx8mq_evk_start(void)
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mq_barebox_entry(__dtb_imx8mq_evk_start);
+ imx8mq_barebox_entry(__dtb_z_imx8mq_evk_start);
}
ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
index 05226866f8..d35f9b0d39 100644
--- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
@@ -23,7 +23,7 @@
#include "ddr.h"
-extern char __dtb_imx8mq_phytec_phycore_som_start[];
+extern char __dtb_z_imx8mq_phytec_phycore_som_start[];
#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
@@ -90,7 +90,7 @@ static __noreturn noinline void phytec_phycore_imx8mq_start(void)
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start);
+ imx8mq_barebox_entry(__dtb_z_imx8mq_phytec_phycore_som_start);
}
/*
diff --git a/arch/arm/boards/pine64-quartz64/lowlevel.c b/arch/arm/boards/pine64-quartz64/lowlevel.c
index b295885522..ae1f0cf920 100644
--- a/arch/arm/boards/pine64-quartz64/lowlevel.c
+++ b/arch/arm/boards/pine64-quartz64/lowlevel.c
@@ -10,18 +10,9 @@
extern char __dtb_rk3566_quartz64_a_start[];
-static noinline void start_quartz64(void *fdt)
+static noinline void start_quartz64(void)
{
- /*
- * Image execution starts at 0x0, but this is used for ATF and
- * OP-TEE later, so move away from here.
- */
- if (current_el() == 3)
- relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
- else
- relocate_to_current_adr();
-
- setup_c();
+ void *fdt = __dtb_rk3566_quartz64_a_start;
if (current_el() == 3) {
rk3568_lowlevel_init();
@@ -35,5 +26,16 @@ static noinline void start_quartz64(void *fdt)
ENTRY_FUNCTION(start_quartz64a, r0, r1, r2)
{
- start_quartz64(__dtb_rk3566_quartz64_a_start);
+ /*
+ * Image execution starts at 0x0, but this is used for ATF and
+ * OP-TEE later, so move away from here.
+ */
+ if (current_el() == 3)
+ relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+ else
+ relocate_to_current_adr();
+
+ setup_c();
+
+ start_quartz64();
}
diff --git a/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
index 24d98fe6c9..bfae39ea52 100644
--- a/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
+++ b/arch/arm/boards/protonic-imx8m/lowlevel-prt8mm.c
@@ -15,7 +15,7 @@
#include <soc/fsl/fsl_udc.h>
#include <soc/imx8m/ddr.h>
-extern char __dtb_imx8mm_prt8mm_start[];
+extern char __dtb_z_imx8mm_prt8mm_start[];
#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
@@ -37,11 +37,6 @@ extern struct dram_timing_info prt8mm_dram_timing;
static void start_atf(void)
{
- size_t bl31_size;
- const u8 *bl31;
- enum bootsource src;
- int instance;
-
/*
* If we are in EL3 we are running for the first time and need to
* initialize the DRAM and run TF-A (BL31). The TF-A will then jump
@@ -52,36 +47,9 @@ static void start_atf(void)
imx8mm_early_clock_init();
- imx8mm_ddr_init(&prt8mm_dram_timing);
-
- imx8mm_get_boot_source(&src, &instance);
- switch (src) {
- case BOOTSOURCE_MMC:
- imx8m_esdhc_load_image(instance, false);
- break;
- case BOOTSOURCE_SERIAL:
- imx8mm_barebox_load_usb((void *)MX8M_ATF_BL33_BASE_ADDR);
- break;
- default:
- printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
- hang();
- }
-
- /*
- * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
- * in EL2. Copy the image there, but replace the PBL part of
- * that image with ourselves. On a high assurance boot only the
- * currently running code is validated and contains the checksum
- * for the piggy data, so we need to ensure that we are running
- * the same code in DRAM.
- */
- memcpy((void *)MX8MM_ATF_BL33_BASE_ADDR,
- __image_start, barebox_pbl_size);
-
- get_builtin_firmware(imx8mm_bl31_bin, &bl31, &bl31_size);
- imx8mm_atf_load_bl31(bl31, bl31_size);
+ imx8mm_ddr_init(&prt8mm_dram_timing, DRAM_TYPE_LPDDR4);
- /* not reached */
+ imx8mm_load_and_start_image_via_tfa();
}
/*
@@ -109,7 +77,7 @@ static __noreturn noinline void prt_prt8mm_start(void)
/*
* Standard entry we hit once we initialized both DDR and ATF
*/
- imx8mm_barebox_entry(__dtb_imx8mm_prt8mm_start);
+ imx8mm_barebox_entry(__dtb_z_imx8mm_prt8mm_start);
}
ENTRY_FUNCTION(start_prt_prt8mm, r0, r1, r2)
diff --git a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
index ea5c0b9154..2c55e7d451 100644
--- a/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
+++ b/arch/arm/boards/protonic-imx8m/lpddr4-timing-prt8mm.c
@@ -1981,7 +1981,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
/* lpddr4 timing config params on EVK board */
struct dram_timing_info prt8mm_dram_timing = {
- .dram_type = DRAM_TYPE_LPDDR4,
.ddrc_cfg = lpddr4_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
.ddrphy_cfg = lpddr4_ddrphy_cfg,
diff --git a/arch/arm/boards/radxa-rock3/board.c b/arch/arm/boards/radxa-rock3/board.c
index aef5ec5df6..cea00b9773 100644
--- a/arch/arm/boards/radxa-rock3/board.c
+++ b/arch/arm/boards/radxa-rock3/board.c
@@ -21,13 +21,14 @@ static int rock3_probe(struct device_d *dev)
barebox_set_model(model->name);
barebox_set_hostname(model->shortname);
- if (bootsource == BOOTSOURCE_MMC && instance == 1)
+ if (bootsource == BOOTSOURCE_MMC && instance == 0)
of_device_enable_path("/chosen/environment-sd");
else
of_device_enable_path("/chosen/environment-emmc");
rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT,
"/dev/mmc1");
+ rk3568_bbu_mmc_register("sd", 0, "/dev/mmc0");
return 0;
}
diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c
index 00a68889cd..2a449c17ae 100644
--- a/arch/arm/boards/radxa-rock3/lowlevel.c
+++ b/arch/arm/boards/radxa-rock3/lowlevel.c
@@ -10,18 +10,9 @@
extern char __dtb_rk3568_rock_3a_start[];
-static noinline void rk3568_start(void *fdt)
+static noinline void rk3568_start(void)
{
- /*
- * Image execution starts at 0x0, but this is used for ATF and
- * OP-TEE later, so move away from here.
- */
- if (current_el() == 3)
- relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
- else
- relocate_to_current_adr();
-
- setup_c();
+ void *fdt = __dtb_rk3568_rock_3a_start;
/*
* Enable vccio4 1.8V and vccio6 1.8V
@@ -40,5 +31,16 @@ static noinline void rk3568_start(void *fdt)
ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
{
- rk3568_start(__dtb_rk3568_rock_3a_start);
+ /*
+ * Image execution starts at 0x0, but this is used for ATF and
+ * OP-TEE later, so move away from here.
+ */
+ if (current_el() == 3)
+ relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+ else
+ relocate_to_current_adr();
+
+ setup_c();
+
+ rk3568_start();
}
diff --git a/arch/arm/boards/raspberry-pi/Makefile b/arch/arm/boards/raspberry-pi/Makefile
index 6f995b5640..e4f91b4979 100644
--- a/arch/arm/boards/raspberry-pi/Makefile
+++ b/arch/arm/boards/raspberry-pi/Makefile
@@ -2,4 +2,5 @@
obj-$(CONFIG_MACH_RPI_COMMON) += rpi-common.o
lwl-y += lowlevel.o
+obj-pbl-y += mbox-helpers.o
bbenv-y += defaultenv-rpi
diff --git a/arch/arm/boards/raspberry-pi/lowlevel.c b/arch/arm/boards/raspberry-pi/lowlevel.c
index 7b9809b86c..5ead895767 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.c
+++ b/arch/arm/boards/raspberry-pi/lowlevel.c
@@ -4,7 +4,10 @@
#include <asm/cache.h>
#include <common.h>
#include <linux/sizes.h>
+#include <asm/unaligned.h>
#include <mach/platform.h>
+#include <debug_ll.h>
+#include <mach/mbox.h>
#include <of.h>
#include "lowlevel.h"
@@ -33,7 +36,7 @@ static void copy_vc_fdt(void *dest, void *src, unsigned long max_size)
memmove(dest, src, size);
}
-/* A pointer to the FDT created by VideoCore was passed to us in r2. We
+/* A pointer to the FDT created by VideoCore was passed to us in x0/r2. We
* reserve some memory just above the region used for Barebox and copy
* this FDT there. We fetch it from there later in rpi_devices_init().
*/
@@ -45,8 +48,6 @@ static inline void start_raspberry_pi(unsigned long memsize, void *fdt,
{
unsigned long endmem = rpi_stack_top(memsize);
- arm_cpu_lowlevel_init();
-
copy_vc_fdt((void *)endmem, vc_fdt, VIDEOCORE_FDT_SZ);
fdt += get_runtime_offset();
@@ -54,29 +55,123 @@ static inline void start_raspberry_pi(unsigned long memsize, void *fdt,
barebox_arm_entry(BCM2835_SDRAM_BASE, endmem - BCM2835_SDRAM_BASE, fdt);
}
-#define RPI_ENTRY_FUNCTION(name, memsize, r2) \
- ENTRY_FUNCTION_WITHSTACK(name, rpi_stack_top(memsize), __r0, __r1, r2)
+#ifdef CONFIG_CPU_V8
+#define RPI_ENTRY_FUNCTION(name, memsize, fdt) \
+ ENTRY_FUNCTION_WITHSTACK(name, rpi_stack_top(memsize), fdt, __x1, __x2)
+#else
+#define RPI_ENTRY_FUNCTION(name, memsize, fdt) \
+ ENTRY_FUNCTION_WITHSTACK(name, rpi_stack_top(memsize), __r0, __r1, fdt)
+#endif
+
+extern char __dtb_z_bcm2835_rpi_start[];
+extern char __dtb_z_bcm2836_rpi_2_start[];
+extern char __dtb_z_bcm2837_rpi_3_start[];
+extern char __dtb_z_bcm2837_rpi_cm3_start[];
+extern char __dtb_z_bcm2711_rpi_4_start[];
+
+RPI_ENTRY_FUNCTION(start_raspberry_pi1, SZ_128M, fdt)
+{
+ arm_cpu_lowlevel_init();
+
+ start_raspberry_pi(SZ_128M, __dtb_z_bcm2835_rpi_start, (void *)fdt);
+}
+
+RPI_ENTRY_FUNCTION(start_raspberry_pi2, SZ_512M, fdt)
+{
+ arm_cpu_lowlevel_init();
+
+ start_raspberry_pi(SZ_512M, __dtb_z_bcm2836_rpi_2_start, (void *)fdt);
+}
-extern char __dtb_bcm2835_rpi_start[];
-RPI_ENTRY_FUNCTION(start_raspberry_pi1, SZ_128M, r2)
+RPI_ENTRY_FUNCTION(start_raspberry_pi3, SZ_512M, fdt)
{
- start_raspberry_pi(SZ_128M, __dtb_bcm2835_rpi_start, (void *)r2);
+ arm_cpu_lowlevel_init();
+
+ start_raspberry_pi(SZ_512M, __dtb_z_bcm2837_rpi_3_start, (void *)fdt);
}
-extern char __dtb_bcm2836_rpi_2_start[];
-RPI_ENTRY_FUNCTION(start_raspberry_pi2, SZ_512M, r2)
+RPI_ENTRY_FUNCTION(start_raspberry_pi_cm3, SZ_512M, fdt)
{
- start_raspberry_pi(SZ_512M, __dtb_bcm2836_rpi_2_start, (void *)r2);
+ arm_cpu_lowlevel_init();
+
+ start_raspberry_pi(SZ_512M, __dtb_z_bcm2837_rpi_cm3_start, (void *)fdt);
}
-extern char __dtb_bcm2837_rpi_3_start[];
-RPI_ENTRY_FUNCTION(start_raspberry_pi3, SZ_512M, r2)
+#define DT_IF_ENABLED(dt, cfg) \
+ (IS_ENABLED(cfg) ? (dt) : NULL)
+
+static void *rpi_get_board_fdt(int rev)
{
- start_raspberry_pi(SZ_512M, __dtb_bcm2837_rpi_3_start, (void *)r2);
+ if (!(rev & 0x800000))
+ return DT_IF_ENABLED(__dtb_z_bcm2835_rpi_start, CONFIG_MACH_RPI);
+
+ switch (((rev >> 4) & 0xff)) {
+ case BCM2835_BOARD_REV_A:
+ case BCM2835_BOARD_REV_B:
+ case BCM2835_BOARD_REV_A_PLUS:
+ case BCM2835_BOARD_REV_B_PLUS:
+ case BCM2835_BOARD_REV_CM1:
+ case BCM2835_BOARD_REV_ZERO:
+ case BCM2835_BOARD_REV_ZERO_W:
+ return DT_IF_ENABLED(__dtb_z_bcm2835_rpi_start, CONFIG_MACH_RPI);
+
+ case BCM2836_BOARD_REV_2_B:
+ return DT_IF_ENABLED(__dtb_z_bcm2836_rpi_2_start, CONFIG_MACH_RPI2);
+
+ case BCM2837_BOARD_REV_3_B:
+ case BCM2837B0_BOARD_REV_3B_PLUS:
+ case BCM2837B0_BOARD_REV_3A_PLUS:
+ case BCM2837B0_BOARD_REV_ZERO_2:
+ return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_3_start, CONFIG_MACH_RPI3);
+
+ case BCM2837_BOARD_REV_CM3:
+ case BCM2837B0_BOARD_REV_CM3_PLUS:
+ return DT_IF_ENABLED(__dtb_z_bcm2837_rpi_cm3_start, CONFIG_MACH_RPI_CM3);
+
+ case BCM2711_BOARD_REV_4_B:
+ case BCM2711_BOARD_REV_400:
+ case BCM2711_BOARD_REV_CM4:
+ return DT_IF_ENABLED(__dtb_z_bcm2711_rpi_4_start, CONFIG_MACH_RPI4);
+ }
+
+ return NULL;
}
-extern char __dtb_bcm2837_rpi_cm3_start[];
-RPI_ENTRY_FUNCTION(start_raspberry_pi_cm3, SZ_512M, r2)
+RPI_ENTRY_FUNCTION(start_raspberry_pi_generic, SZ_128M, vc_fdt)
{
- start_raspberry_pi(SZ_512M, __dtb_bcm2837_rpi_cm3_start, (void *)r2);
+ void *fdt = NULL;
+ ssize_t memsize;
+ int rev;
+
+ arm_cpu_lowlevel_init();
+
+ debug_ll_init();
+
+ putc_ll('>');
+
+ relocate_to_current_adr();
+ setup_c();
+
+ memsize = rpi_get_arm_mem();
+ if (memsize < 0) {
+ pr_warn("mbox: failed to query ARM memory size. 128M assumed.\n");
+ memsize = SZ_128M;
+ }
+
+ rev = rpi_get_board_rev();
+ if (rev >= 0) {
+ pr_debug("Detected revision %08x\n", rev);
+ fdt = rpi_get_board_fdt(rev);
+ }
+
+ if (!fdt) {
+ fdt = (void *)vc_fdt;
+
+ pr_warn("Unknown Rpi board with rev %08x.\n", rev);
+
+ if (get_unaligned_be32(fdt) != 0xd00dfeed)
+ panic("No suitable built-in or videocore-supplied DT\n");
+ }
+
+ start_raspberry_pi(memsize, fdt, (void *)vc_fdt);
}
diff --git a/arch/arm/boards/raspberry-pi/lowlevel.h b/arch/arm/boards/raspberry-pi/lowlevel.h
index eacf973fb6..a29860d607 100644
--- a/arch/arm/boards/raspberry-pi/lowlevel.h
+++ b/arch/arm/boards/raspberry-pi/lowlevel.h
@@ -3,9 +3,14 @@
#ifndef __ARCH_ARM_BOARDS_LOWLEVEL_H__
#define __ARCH_ARM_BOARDS_LOWLEVEL_H__
+#include <linux/types.h>
#include <linux/sizes.h>
#define VIDEOCORE_FDT_SZ SZ_1M
#define VIDEOCORE_FDT_ERROR 0xdeadfeed
+ssize_t rpi_get_arm_mem(void);
+int rpi_get_usbethaddr(u8 mac[6]);
+int rpi_get_board_rev(void);
+
#endif /* __ARCH_ARM_BOARDS_LOWLEVEL_H__ */
diff --git a/arch/arm/boards/raspberry-pi/mbox-helpers.c b/arch/arm/boards/raspberry-pi/mbox-helpers.c
new file mode 100644
index 0000000000..9f252c68ff
--- /dev/null
+++ b/arch/arm/boards/raspberry-pi/mbox-helpers.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-FileCopyrightText: 2009 Carlo Caione <carlo@carlocaione.org>
+
+#include <mach/mbox.h>
+#include "lowlevel.h"
+
+struct msg_get_arm_mem {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+ u32 end_tag;
+};
+
+struct msg_get_board_rev {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+ u32 end_tag;
+};
+
+struct msg_get_mac_address {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+ u32 end_tag;
+};
+
+ssize_t rpi_get_arm_mem(void)
+{
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret)
+ return ret;
+
+ return msg->get_arm_mem.body.resp.mem_size;
+}
+
+int rpi_get_usbethaddr(u8 mac[6])
+{
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ pr_info("bcm2835: Could not query MAC address\n");
+ return ret;
+ }
+
+ memcpy(mac, msg->get_mac_address.body.resp.mac, 6);
+ return 0;
+}
+
+int rpi_get_board_rev(void)
+{
+ int ret;
+
+ BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg);
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ pr_err("Could not query board revision\n");
+ return ret;
+ }
+
+ return msg->get_board_rev.body.resp.rev;
+}
diff --git a/arch/arm/boards/raspberry-pi/rpi-common.c b/arch/arm/boards/raspberry-pi/rpi-common.c
index 05d59ae6bf..77935e5c88 100644
--- a/arch/arm/boards/raspberry-pi/rpi-common.c
+++ b/arch/arm/boards/raspberry-pi/rpi-common.c
@@ -23,13 +23,28 @@
#include <linux/sizes.h>
#include <globalvar.h>
#include <asm/system_info.h>
+#include <reset_source.h>
#include <mach/core.h>
#include <mach/mbox.h>
#include <mach/platform.h>
+#include <soc/bcm283x/wdt.h>
+
#include "lowlevel.h"
+//https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#BOOT_ORDER
+static const char * const boot_mode_names[] = {
+ [0x0] = "unknown",
+ [0x1] = "sd",
+ [0x2] = "net",
+ [0x3] = "rpiboot",
+ [0x4] = "usbmsd",
+ [0x5] = "usbc",
+ [0x6] = "nvme",
+ [0x7] = "http",
+};
+
struct rpi_priv;
struct rpi_machine_data {
int (*init)(struct rpi_priv *priv);
@@ -45,57 +60,14 @@ struct rpi_priv {
const char *name;
};
-struct msg_get_arm_mem {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
- u32 end_tag;
-};
-
-struct msg_get_board_rev {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_board_rev get_board_rev;
- u32 end_tag;
-};
-
-struct msg_get_mac_address {
- struct bcm2835_mbox_hdr hdr;
- struct bcm2835_mbox_tag_get_mac_address get_mac_address;
- u32 end_tag;
-};
-
-static int rpi_get_arm_mem(u32 *size)
-{
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_arm_mem, msg);
- int ret;
-
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret)
- return ret;
-
- *size = msg->get_arm_mem.body.resp.mem_size;
-
- return 0;
-}
-
static void rpi_set_usbethaddr(void)
{
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_mac_address, msg);
- int ret;
+ u8 mac[ETH_ALEN];
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+ if (rpi_get_usbethaddr(mac))
+ return; /* Ignore error; not critical */
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret) {
- printf("bcm2835: Could not query MAC address\n");
- /* Ignore error; not critical */
- return;
- }
-
- eth_register_ethaddr(0, msg->get_mac_address.body.resp.mac);
+ eth_register_ethaddr(0, mac);
}
static void rpi_set_usbotg(const char *alias)
@@ -185,48 +157,19 @@ static int rpi_0_w_init(struct rpi_priv *priv)
return of_device_disable_by_alias("serial0");
}
-static int rpi_get_board_rev(struct rpi_priv *priv)
-{
- int ret;
-
- BCM2835_MBOX_STACK_ALIGN(struct msg_get_board_rev, msg);
- BCM2835_MBOX_INIT_HDR(msg);
- BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
-
- ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
- if (ret) {
- dev_err(priv->dev, "Could not query board revision\n");
- return ret;
- }
-
- /* Comments from u-boot:
- * For details of old-vs-new scheme, see:
- * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
- * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
- * (a few posts down)
- *
- * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
- * lower byte to use as the board rev:
- * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
- * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
- */
- priv->hw_id = msg->get_board_rev.body.resp.rev;
-
- return 0;
-}
-
static int rpi_mem_init(void)
{
- u32 size = 0;
- int ret;
+ ssize_t size;
- ret = rpi_get_arm_mem(&size);
- if (ret)
+ size = rpi_get_arm_mem();
+ if (size < 0) {
printf("could not query ARM memory size\n");
+ size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);
+ }
bcm2835_add_device_sdram(size);
- return ret;
+ return 0;
}
mem_initcall(rpi_mem_init);
@@ -258,54 +201,133 @@ static int rpi_env_init(void)
return 0;
}
-/* Extract /chosen/bootargs from the VideoCore FDT into vc.bootargs
- * global variable. */
-static int rpi_vc_fdt_bootargs(void *fdt)
+/* Some string properties in fdt passed to us from vc may be
+ * malformed by not being null terminated, so just create and
+ * return a fixed copy.
+ */
+static char *of_read_vc_string(struct device_node *node,
+ const char *prop_name)
+{
+ int len;
+ const char *str;
+
+ str = of_get_property(node, prop_name, &len);
+ if (!str) {
+ pr_warn("no property '%s' found in vc fdt's '%s' node\n",
+ prop_name, node->full_name);
+ return NULL;
+ }
+ return xstrndup(str, len);
+}
+
+static enum reset_src_type rpi_decode_pm_rsts(struct device_node *chosen,
+ struct device_node *bootloader)
{
- int ret = 0;
- struct device_node *root = NULL, *node;
- const char *cmdline;
+ u32 pm_rsts;
+ int ret;
+
+ ret = of_property_read_u32(chosen, "pm_rsts", &pm_rsts);
+ if (ret && bootloader)
+ ret = of_property_read_u32(bootloader, "rsts", &pm_rsts);
+
+ if (ret) {
+ pr_warn("'pm_rsts' value not found in vc fdt\n");
+ return RESET_UKWN;
+ }
+ /*
+ * https://github.com/raspberrypi/linux/issues/932#issuecomment-93989581
+ */
+
+ if (pm_rsts & PM_RSTS_HADPOR_SET)
+ return RESET_POR;
+ if (pm_rsts & PM_RSTS_HADDR_SET)
+ return RESET_JTAG;
+ if (pm_rsts & PM_RSTS_HADWR_SET)
+ return RESET_WDG;
+ if (pm_rsts & PM_RSTS_HADSR_SET)
+ return RESET_RST;
+
+ return RESET_UKWN;
+}
+
+static u32 rpi_boot_mode, rpi_boot_part;
+/* Extract useful information from the VideoCore FDT we got.
+ * Some parameters are defined here:
+ * https://www.raspberrypi.com/documentation/computers/configuration.html#part4
+ */
+static void rpi_vc_fdt_parse(void *fdt)
+{
+ int ret;
+ struct device_node *root, *chosen, *bootloader;
+ char *str;
root = of_unflatten_dtb(fdt, INT_MAX);
- if (IS_ERR(root)) {
- ret = PTR_ERR(root);
- root = NULL;
- goto out;
+ if (IS_ERR(root))
+ return;
+
+ str = of_read_vc_string(root, "serial-number");
+ if (str) {
+ barebox_set_serial_number(str);
+ free(str);
}
- node = of_find_node_by_path_from(root, "/chosen");
- if (!node) {
- pr_err("no /chosen node\n");
- ret = -ENOENT;
- goto out;
+ str = of_read_vc_string(root, "model");
+ if (str) {
+ barebox_set_model(str);
+ free(str);
}
- cmdline = of_get_property(node, "bootargs", NULL);
- if (!cmdline) {
- pr_err("no bootargs property in the /chosen node\n");
- ret = -ENOENT;
+ chosen = of_find_node_by_path_from(root, "/chosen");
+ if (!chosen) {
+ pr_err("no '/chosen' node found in vc fdt\n");
goto out;
}
- globalvar_add_simple("vc.bootargs", cmdline);
+ bootloader = of_find_node_by_name(chosen, "bootloader");
- switch(cpu_architecture()) {
- case CPU_ARCH_ARMv6:
- globalvar_add_simple("vc.kernel", "kernel.img");
- break;
- case CPU_ARCH_ARMv7:
- globalvar_add_simple("vc.kernel", "kernel7.img");
- break;
- case CPU_ARCH_ARMv8:
- globalvar_add_simple("vc.kernel", "kernel7l.img");
- break;
+ str = of_read_vc_string(chosen, "bootargs");
+ if (str) {
+ globalvar_add_simple("vc.bootargs", str);
+ free(str);
}
+ str = of_read_vc_string(chosen, "overlay_prefix");
+ if (str) {
+ globalvar_add_simple("vc.overlay_prefix", str);
+ free(str);
+ }
+
+ str = of_read_vc_string(chosen, "os_prefix");
+ if (str) {
+ globalvar_add_simple("vc.os_prefix", str);
+ free(str);
+ }
+
+ ret = of_property_read_u32(chosen, "boot-mode", &rpi_boot_mode);
+ if (ret && bootloader)
+ ret = of_property_read_u32(bootloader, "boot-mode", &rpi_boot_mode);
+ if (ret)
+ pr_debug("'boot-mode' property not found in vc fdt\n");
+ else
+ globalvar_add_simple_enum("vc.boot_mode", &rpi_boot_mode,
+ boot_mode_names,
+ ARRAY_SIZE(boot_mode_names));
+
+ ret = of_property_read_u32(chosen, "partition", &rpi_boot_part);
+ if (ret && bootloader)
+ ret = of_property_read_u32(bootloader, "partition", &rpi_boot_part);
+ if (ret)
+ pr_debug("'partition' property not found in vc fdt\n");
+ else
+ globalvar_add_simple_int("vc.boot_partition", &rpi_boot_part, "%u");
+
+ if (IS_ENABLED(CONFIG_RESET_SOURCE))
+ reset_source_set(rpi_decode_pm_rsts(chosen, bootloader));
+
out:
if (root)
of_delete_node(root);
-
- return ret;
+ return;
}
static void rpi_vc_fdt(void)
@@ -313,7 +335,6 @@ static void rpi_vc_fdt(void)
void *saved_vc_fdt;
struct fdt_header *oftree;
unsigned long magic, size;
- int ret;
/* VideoCore FDT was copied in PBL just above Barebox memory */
saved_vc_fdt = (void *)(arm_mem_endmem_get());
@@ -332,16 +353,23 @@ static void rpi_vc_fdt(void)
return;
size = be32_to_cpu(oftree->totalsize);
- if (write_file("/vc.dtb", saved_vc_fdt, size)) {
+ if (write_file("/vc.dtb", saved_vc_fdt, size))
pr_err("failed to save videocore fdt to a file\n");
- return;
- }
- ret = rpi_vc_fdt_bootargs(saved_vc_fdt);
- if (ret) {
- pr_err("failed to extract bootargs from videocore fdt: %d\n",
- ret);
- return;
+ rpi_vc_fdt_parse(saved_vc_fdt);
+}
+
+static void rpi_set_kernel_name(void) {
+ switch(cpu_architecture()) {
+ case CPU_ARCH_ARMv6:
+ globalvar_add_simple("vc.kernel", "kernel.img");
+ break;
+ case CPU_ARCH_ARMv7:
+ globalvar_add_simple("vc.kernel", "kernel7.img");
+ break;
+ case CPU_ARCH_ARMv8:
+ globalvar_add_simple("vc.kernel", "kernel8.img");
+ break;
}
}
@@ -355,6 +383,18 @@ static const struct rpi_machine_data *rpi_get_dcfg(struct rpi_priv *priv)
return NULL;
}
+ /* Comments from u-boot:
+ * For details of old-vs-new scheme, see:
+ * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282
+ * (a few posts down)
+ *
+ * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the
+ * lower byte to use as the board rev:
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250
+ * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594
+ */
+
for (; dcfg->hw_id != U8_MAX; dcfg++) {
if (priv->hw_id & 0x800000) {
if (dcfg->hw_id != ((priv->hw_id >> 4) & 0xff))
@@ -386,10 +426,12 @@ static int rpi_devices_probe(struct device_d *dev)
priv = xzalloc(sizeof(*priv));
priv->dev = dev;
- ret = rpi_get_board_rev(priv);
- if (ret)
+ ret = rpi_get_board_rev();
+ if (ret < 0)
goto free_priv;
+ priv->hw_id = ret;
+
dcfg = rpi_get_dcfg(priv);
if (IS_ERR(dcfg))
goto free_priv;
@@ -406,6 +448,7 @@ static int rpi_devices_probe(struct device_d *dev)
armlinux_set_architecture(MACH_TYPE_BCM2708);
rpi_env_init();
rpi_vc_fdt();
+ rpi_set_kernel_name();
if (dcfg && dcfg->init)
dcfg->init(priv);
@@ -532,6 +575,18 @@ static const struct rpi_machine_data rpi_3_ids[] = {
},
};
+static const struct rpi_machine_data rpi_4_ids[] = {
+ {
+ .hw_id = BCM2711_BOARD_REV_4_B,
+ }, {
+ .hw_id = BCM2711_BOARD_REV_400,
+ }, {
+ .hw_id = BCM2711_BOARD_REV_CM4,
+ }, {
+ .hw_id = U8_MAX
+ },
+};
+
static const struct of_device_id rpi_of_match[] = {
/* BCM2835 based Boards */
{ .compatible = "raspberrypi,model-a", .data = rpi_1_ids },
@@ -556,6 +611,11 @@ static const struct of_device_id rpi_of_match[] = {
{ .compatible = "raspberrypi,3-compute-module", .data = rpi_3_ids },
{ .compatible = "raspberrypi,3-compute-module-lite", .data = rpi_3_ids },
+ /* BCM2711 based Boards */
+ { .compatible = "raspberrypi,4-model-b", .data = rpi_4_ids },
+ { .compatible = "raspberrypi,4-compute-module", .data = rpi_4_ids },
+ { .compatible = "raspberrypi,400", .data = rpi_4_ids },
+
{ /* sentinel */ },
};
BAREBOX_DEEP_PROBE_ENABLE(rpi_of_match);
diff --git a/arch/arm/boards/reflex-achilles/board.c b/arch/arm/boards/reflex-achilles/board.c
index 43e3a69be7..0fbb967ff9 100644
--- a/arch/arm/boards/reflex-achilles/board.c
+++ b/arch/arm/boards/reflex-achilles/board.c
@@ -4,6 +4,7 @@
#include <init.h>
#include <io.h>
#include <bbu.h>
+#include <mach/arria10-system-manager.h>
static int achilles_init(void)
{
@@ -14,7 +15,7 @@ static int achilles_init(void)
if (!of_machine_is_compatible("reflex,achilles"))
return 0;
- pbl_index = readl(0xFFD06210);
+ pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
pr_debug("Current barebox instance %d\n", pbl_index);
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index e8d1a9cee4..511b41fd01 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -16,6 +16,7 @@
#include <mach/arria10-clock-manager.h>
#include <mach/arria10-pinmux.h>
#include <mach/arria10-fpga.h>
+#include <mach/init.h>
#include "pll-config-arria10.c"
#include "pinmux-config-arria10.c"
#include <mach/generic.h>
@@ -23,21 +24,25 @@
#define BAREBOX_PART 0
#define BITSTREAM_PART 1
#define BAREBOX1_OFFSET SZ_1M
-#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K
-#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K
-#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K
+#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_512K)
+#define BAREBOX3_OFFSET (BAREBOX2_OFFSET + SZ_512K)
+#define BAREBOX4_OFFSET (BAREBOX3_OFFSET + SZ_512K)
+// Offset from the start of the second partition on the eMMC.
#define BITSTREAM1_OFFSET 0x0
-#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M
+#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M)
-extern char __dtb_socfpga_arria10_achilles_start[];
+extern char __dtb_z_socfpga_arria10_achilles_start[];
-static noinline void achilles_start(void)
+#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K)
+
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2)
{
int pbl_index = 0;
int barebox = 0;
int bitstream = 0;
- arm_early_mmu_cache_invalidate();
+ arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
relocate_to_current_adr();
setup_c();
@@ -76,31 +81,21 @@ static noinline void achilles_start(void)
arria10_start_image(barebox);
}
-ENTRY_FUNCTION(start_socfpga_achilles_xload, r0, r1, r2)
-{
- arm_cpu_lowlevel_init();
- arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K);
- achilles_start();
-}
-
ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
{
void *fdt;
- fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+ fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset();
barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
}
-ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
+ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r1, r2)
{
void *fdt;
arm_cpu_lowlevel_init();
-
- arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K);
-
- arm_early_mmu_cache_invalidate();
+ arria10_cpu_lowlevel_init();
relocate_to_current_adr();
setup_c();
@@ -114,7 +109,7 @@ ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
arria10_ddr_calibration_sequence();
- fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+ fdt = __dtb_z_socfpga_arria10_achilles_start + get_runtime_offset();
barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
}
diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c
index e472f13c8b..b5d406576f 100644
--- a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/board.c
@@ -23,13 +23,14 @@ static int rk3568_bpi_r2pro_probe(struct device_d *dev)
barebox_set_hostname("bpi-r2pro");
machine_is_bpi_r2pro = true;
- if (bootsource == BOOTSOURCE_MMC && instance == 1)
+ if (bootsource == BOOTSOURCE_MMC && instance == 0)
of_device_enable_path("/chosen/environment-sd");
else
of_device_enable_path("/chosen/environment-emmc");
- rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT, "/dev/emmc");
- rk3568_bbu_mmc_register("sd", 0, "/dev/sd");
+ rk3568_bbu_mmc_register("sd", 0, "/dev/mmc0");
+ rk3568_bbu_mmc_register("emmc", BBU_HANDLER_FLAG_DEFAULT,
+ "/dev/mmc1");
return 0;
}
diff --git a/arch/arm/boards/rockchip-rk3568-evb/board.c b/arch/arm/boards/rockchip-rk3568-evb/board.c
index a466d385a2..212c801c93 100644
--- a/arch/arm/boards/rockchip-rk3568-evb/board.c
+++ b/arch/arm/boards/rockchip-rk3568-evb/board.c
@@ -23,7 +23,7 @@ static int rk3568_evb_probe(struct device_d *dev)
barebox_set_hostname("rk3568-evb");
machine_is_rk3568_evb = true;
- if (bootsource == BOOTSOURCE_MMC && instance == 1)
+ if (bootsource == BOOTSOURCE_MMC && instance == 0)
of_device_enable_path("/chosen/environment-sd");
else
of_device_enable_path("/chosen/environment-emmc");
diff --git a/arch/arm/boards/vscom-baltos/board.c b/arch/arm/boards/vscom-baltos/board.c
index 83c7dbc8b0..b9ce356264 100644
--- a/arch/arm/boards/vscom-baltos/board.c
+++ b/arch/arm/boards/vscom-baltos/board.c
@@ -49,6 +49,7 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
{
uint16_t maj, min;
uint8_t dip = 0;
+ int inputs[4];
maj = rev >> 16;
min = rev & 0xffff;
@@ -59,10 +60,14 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
switch(id) {
case 214:
case 215:
- dip = !gpio_get_value(44);
- dip += !gpio_get_value(45) << 1;
- dip += !gpio_get_value(46) << 2;
- dip += !gpio_get_value(47) << 3;
+ inputs[0] = gpio_find_by_name("SW2_0_alt");
+ inputs[1] = gpio_find_by_name("SW2_1_alt");
+ inputs[2] = gpio_find_by_name("SW2_2_alt");
+ inputs[3] = gpio_find_by_name("SW2_3_alt");
+ dip = !gpio_get_value(inputs[0]);
+ dip += !gpio_get_value(inputs[1]) << 1;
+ dip += !gpio_get_value(inputs[2]) << 2;
+ dip += !gpio_get_value(inputs[3]) << 3;
break;
case 212:
case 221:
@@ -72,10 +77,14 @@ static uint8_t get_dip_switch(uint16_t id, uint32_t rev)
case 226:
case 227:
case 230:
- dip = !gpio_get_value(82);
- dip += !gpio_get_value(83) << 1;
- dip += !gpio_get_value(105) << 2;
- dip += !gpio_get_value(106) << 3;
+ inputs[0] = gpio_find_by_name("SW2_0");
+ inputs[1] = gpio_find_by_name("SW2_1");
+ inputs[2] = gpio_find_by_name("SW2_2");
+ inputs[3] = gpio_find_by_name("SW2_3");
+ dip = !gpio_get_value(inputs[0]);
+ dip += !gpio_get_value(inputs[1]) << 1;
+ dip += !gpio_get_value(inputs[2]) << 2;
+ dip += !gpio_get_value(inputs[3]) << 3;
break;
}
@@ -89,6 +98,7 @@ static int baltos_read_eeprom(void)
int rc;
unsigned char mac_addr[6];
uint8_t dip;
+ int mpcie_pwr_pin;
if (!of_machine_is_compatible("vscom,onrisc"))
return 0;
@@ -136,14 +146,20 @@ static int baltos_read_eeprom(void)
globalvar_add_simple("board.id", var_buf);
/* enable mPCIe slot */
- gpio_direction_output(100, 1);
+ mpcie_pwr_pin = gpio_find_by_name("3G_PWR_EN");
+ gpio_direction_output(mpcie_pwr_pin, 1);
/* configure output signals of the external GPIO controller */
if (hw_param.SystemId == 210 || hw_param.SystemId == 211) {
- gpio_direction_output(132, 0);
- gpio_direction_output(133, 0);
- gpio_direction_output(134, 0);
- gpio_direction_output(135, 0);
+ int outs[4];
+ outs[0] = gpio_find_by_name("GP_OUT0");
+ outs[1] = gpio_find_by_name("GP_OUT1");
+ outs[2] = gpio_find_by_name("GP_OUT2");
+ outs[3] = gpio_find_by_name("GP_OUT3");
+ gpio_direction_output(outs[0], 0);
+ gpio_direction_output(outs[1], 0);
+ gpio_direction_output(outs[2], 0);
+ gpio_direction_output(outs[3], 0);
}
dip = get_dip_switch(hw_param.SystemId, hw_param.HwRev);
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 8e707b9602..d07abe28ae 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -13,7 +13,6 @@ CONFIG_MACH_FREESCALE_MX53_VMX53=y
CONFIG_MACH_TX53=y
CONFIG_MACH_PHYTEC_SOM_IMX6=y
CONFIG_MACH_PROTONIC_IMX6=y
-CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR=y
CONFIG_MACH_KONTRON_SAMX6I=y
CONFIG_MACH_DFI_FS700_M60=y
CONFIG_MACH_GUF_SANTARO=y
@@ -38,7 +37,8 @@ CONFIG_MACH_GW_VENTANA=y
CONFIG_MACH_CM_FX6=y
CONFIG_MACH_ADVANTECH_ROM_742X=y
CONFIG_MACH_WARP7=y
-CONFIG_MACH_WEBASTO_CCBV2=y
+CONFIG_MACH_AC_SXB=y
+CONFIG_MACH_MEERKAT96=y
CONFIG_MACH_VF610_TWR=y
CONFIG_MACH_ZII_RDU1=y
CONFIG_MACH_ZII_RDU2=y
@@ -46,9 +46,12 @@ CONFIG_MACH_ZII_VF610_DEV=y
CONFIG_MACH_ZII_IMX7D_DEV=y
CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y
CONFIG_MACH_FREESCALE_MX7_SABRESD=y
+CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR=y
CONFIG_MACH_NXP_IMX6ULL_EVK=y
CONFIG_MACH_GRINN_LITEBOARD=y
CONFIG_MACH_DIGI_CCIMX6ULSBCPRO=y
+CONFIG_MACH_WEBASTO_CCBV2=y
+CONFIG_MACH_SKOV_IMX6=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
@@ -87,6 +90,7 @@ CONFIG_CMD_MMC_EXTCSD=y
CONFIG_CMD_GO=y
CONFIG_CMD_RESET=y
CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_BOOTCHOOSER=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_EXPORT=y
@@ -139,7 +143,6 @@ CONFIG_CMD_OF_OVERLAY=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_STATE=y
-CONFIG_CMD_BOOTCHOOSER=y
CONFIG_NET=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OF_BAREBOX_DRIVERS=y
@@ -198,15 +201,16 @@ CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_PWM=y
CONFIG_PWM_IMX=y
-CONFIG_IMX_OCOTP_WRITE=y
CONFIG_MXS_APBH_DMA=y
CONFIG_GPIO_STMPE=y
+CONFIG_IMX_OCOTP_WRITE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED=y
CONFIG_GENERIC_PHY=y
CONFIG_USB_NOP_XCEIV=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
+CONFIG_FS_TFTP_MAX_WINDOW_SIZE=8
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
index fe6398cc87..d1d67514cf 100644
--- a/arch/arm/configs/imx_v8_defconfig
+++ b/arch/arm/configs/imx_v8_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_PROTONIC_IMX8M=y
+CONFIG_MACH_INNOCOMM_WB15=y
CONFIG_MACH_ZII_IMX8MQ_DEV=y
CONFIG_MACH_NXP_IMX8MM_EVK=y
CONFIG_MACH_NXP_IMX8MN_EVK=y
@@ -88,6 +89,7 @@ CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_AT803X_PHY=y
CONFIG_DP83867_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_REALTEK_PHY=y
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index e0e1497481..e7d695f8ae 100644
--- a/arch/arm/configs/rpi_defconfig
+++ b/arch/arm/configs/rpi_defconfig
@@ -24,7 +24,6 @@ CONFIG_BOOTM_OFTREE=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ALLOW_COLOR=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH=""
CONFIG_CMD_DMESG=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
@@ -83,6 +82,8 @@ CONFIG_SERIAL_AMBA_PL011=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_NET_USB=y
CONFIG_NET_USB_SMSC95XX=y
+CONFIG_I2C=y
+CONFIG_I2C_BCM283X=y
CONFIG_USB_HOST=y
CONFIG_USB_DWC2_HOST=y
CONFIG_MCI=y
diff --git a/arch/arm/configs/rpi_v8a_defconfig b/arch/arm/configs/rpi_v8a_defconfig
new file mode 100644
index 0000000000..75f62ddb65
--- /dev/null
+++ b/arch/arm/configs/rpi_v8a_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARCH_BCM283X=y
+CONFIG_MACH_RPI3=y
+CONFIG_MACH_RPI_CM3=y
+CONFIG_MACH_RPI4=y
+CONFIG_64BIT=y
+CONFIG_IMAGE_COMPRESSION_NONE=y
+CONFIG_MMU=y
+# CONFIG_MMU_EARLY is not set
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_PROMPT="R-Pi> "
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_BOOTM_SHOW_TYPE=y
+CONFIG_BOOTM_VERBOSE=y
+CONFIG_BOOTM_INITRD=y
+CONFIG_BOOTM_OFTREE=y
+CONFIG_BLSPEC=y
+CONFIG_CONSOLE_ACTIVATE_ALL=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_DEFAULTENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_CMP=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_LOGIN=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_PASSWD=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_WD=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_NET=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_BCMGENET=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_SMSC95XX=y
+CONFIG_I2C=y
+CONFIG_I2C_BCM283X=y
+CONFIG_USB_HOST=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_DWC2_GADGET=y
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_AUTOSTART is not set
+CONFIG_MCI=y
+CONFIG_MCI_BCM283X=y
+CONFIG_MCI_BCM283X_SDHOST=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_BCM2835=y
+CONFIG_GPIO_RASPBERRYPI_EXP=y
+CONFIG_PINCTRL_BCM283X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED=y
+CONFIG_GENERIC_PHY=y
+CONFIG_USB_NOP_XCEIV=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_ZLIB=y
diff --git a/arch/arm/configs/socfpga-arria10_defconfig b/arch/arm/configs/socfpga-arria10_defconfig
index a37bae6217..5ac2198d41 100644
--- a/arch/arm/configs/socfpga-arria10_defconfig
+++ b/arch/arm/configs/socfpga-arria10_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1=y
CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig
index 0a493754a4..9b5a833abf 100644
--- a/arch/arm/cpu/Kconfig
+++ b/arch/arm/cpu/Kconfig
@@ -87,7 +87,6 @@ config CPU_V7
config CPU_V8
bool
select CPU_64v8
- select CPU_SUPPORTS_64BIT_KERNEL
select ARM_EXCEPTIONS
select GENERIC_FIND_NEXT_BIT
select ARCH_HAS_STACK_DUMP
@@ -156,12 +155,6 @@ config CACHE_L2X0
bool "Enable L2x0 PrimeCell"
depends on MMU && ARCH_HAS_L2X0
-config SYS_SUPPORTS_32BIT_KERNEL
- bool
-
-config SYS_SUPPORTS_64BIT_KERNEL
- bool
-
config CPU_SUPPORTS_32BIT_KERNEL
bool
diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c
index 8cfcc8f6ce..5ccacf2047 100644
--- a/arch/arm/cpu/common.c
+++ b/arch/arm/cpu/common.c
@@ -23,6 +23,12 @@
*/
void sync_caches_for_execution(void)
{
+ /* if caches are disabled, don't do data cache maintenance */
+ if (!(get_cr() & CR_C)) {
+ icache_invalidate();
+ return;
+ }
+
/*
* Despite the name arm_early_mmu_cache_flush not only flushes the
* data cache, but also invalidates the instruction cache.
diff --git a/arch/arm/cpu/mmu-common.h b/arch/arm/cpu/mmu-common.h
index ed7d5bc316..c9ea2c1228 100644
--- a/arch/arm/cpu/mmu-common.h
+++ b/arch/arm/cpu/mmu-common.h
@@ -3,6 +3,11 @@
#ifndef __ARM_MMU_COMMON_H
#define __ARM_MMU_COMMON_H
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+
void dma_inv_range(void *ptr, size_t size);
void dma_flush_range(void *ptr, size_t size);
void *dma_alloc_map(size_t size, dma_addr_t *dma_handle, unsigned flags);
@@ -19,4 +24,14 @@ static inline void arm_mmu_not_initialized_error(void)
panic("MMU not initialized\n");
}
+static inline size_t resource_first_page(const struct resource *res)
+{
+ return ALIGN_DOWN(res->start, SZ_4K);
+}
+
+static inline size_t resource_count_pages(const struct resource *res)
+{
+ return ALIGN(resource_size(res), SZ_4K);
+}
+
#endif
diff --git a/arch/arm/cpu/mmu.h b/arch/arm/cpu/mmu.h
index d48522d166..1499b70dd6 100644
--- a/arch/arm/cpu/mmu.h
+++ b/arch/arm/cpu/mmu.h
@@ -73,15 +73,20 @@ create_sections(uint32_t *ttb, unsigned long first,
#define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
#define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
-static inline void create_flat_mapping(uint32_t *ttb)
+static inline unsigned long attrs_uncached_mem(void)
{
unsigned int flags = PMD_SECT_DEF_UNCACHED;
if (cpu_architecture() >= CPU_ARCH_ARMv7)
flags |= PMD_SECT_XN;
+ return flags;
+}
+
+static inline void create_flat_mapping(uint32_t *ttb)
+{
/* create a flat mapping using 1MiB sections */
- create_sections(ttb, 0, 0xffffffff, flags);
+ create_sections(ttb, 0, 0xffffffff, attrs_uncached_mem());
}
#endif /* __ARM_MMU_H */
diff --git a/arch/arm/cpu/mmu_64.c b/arch/arm/cpu/mmu_64.c
index 06049e0003..f43ac9a121 100644
--- a/arch/arm/cpu/mmu_64.c
+++ b/arch/arm/cpu/mmu_64.c
@@ -201,9 +201,17 @@ void __mmu_init(bool mmu_on)
create_sections(0, 0, 1UL << (BITS_PER_VA - 1), attrs_uncached_mem());
/* Map sdram cached. */
- for_each_memory_bank(bank)
+ for_each_memory_bank(bank) {
+ struct resource *rsv;
+
create_sections(bank->start, bank->start, bank->size, CACHED_MEM);
+ for_each_reserved_region(bank, rsv) {
+ create_sections(resource_first_page(rsv), resource_first_page(rsv),
+ resource_count_pages(rsv), attrs_uncached_mem());
+ }
+ }
+
/* Make zero page faulting to catch NULL pointer derefs */
zero_page_faulting();
diff --git a/arch/arm/cpu/setupc_64.S b/arch/arm/cpu/setupc_64.S
index b5f4a643fa..d64281c148 100644
--- a/arch/arm/cpu/setupc_64.S
+++ b/arch/arm/cpu/setupc_64.S
@@ -29,7 +29,7 @@ ENDPROC(setup_c)
/* x0: target address */
#ifdef __PBL__
ENTRY(relocate_to_adr_full)
- ldr x2, =__piggydata_end
+ ldr x2, =__image_end
b 1f
#endif
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 14cc310312..672f26e006 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -52,8 +52,7 @@ u32 barebox_arm_machine(void)
void *barebox_arm_boot_dtb(void)
{
void *dtb;
- void *data;
- int ret;
+ int ret = 0;
struct barebox_boarddata_compressed_dtb *compressed_dtb;
static void *boot_dtb;
@@ -76,10 +75,13 @@ void *barebox_arm_boot_dtb(void)
if (!dtb)
return NULL;
- data = compressed_dtb + 1;
+ if (IS_ENABLED(CONFIG_IMAGE_COMPRESSION_NONE))
+ memcpy(dtb, compressed_dtb->data,
+ compressed_dtb->datalen_uncompressed);
+ else
+ ret = uncompress(compressed_dtb->data, compressed_dtb->datalen,
+ NULL, NULL, dtb, NULL, NULL);
- ret = uncompress(data, compressed_dtb->datalen, NULL, NULL,
- dtb, NULL, NULL);
if (ret) {
pr_err("uncompressing dtb failed\n");
free(dtb);
@@ -169,7 +171,7 @@ __noreturn __no_sanitize_address void barebox_non_pbl_start(unsigned long membas
} else {
pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb);
arm_early_mmu_cache_invalidate();
- mmu_early_enable(membase, memsize, ttb);
+ mmu_early_enable(membase, memsize - OPTEE_SIZE, ttb);
}
}
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index 2250b8ccd3..537ee63229 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -84,7 +84,7 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
if (IS_ENABLED(CONFIG_MMU_EARLY)) {
unsigned long ttb = arm_mem_ttb(membase, endmem);
pr_debug("enabling MMU, ttb @ 0x%08lx\n", ttb);
- mmu_early_enable(membase, memsize, ttb);
+ mmu_early_enable(membase, memsize - OPTEE_SIZE, ttb);
}
free_mem_ptr = arm_mem_early_malloc(membase, endmem);
diff --git a/arch/arm/dts/.gitignore b/arch/arm/dts/.gitignore
deleted file mode 100644
index 077903c50a..0000000000
--- a/arch/arm/dts/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*dtb*
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 723bd2a123..99f44e7b04 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -26,6 +26,7 @@ lwl-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o
lwl-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += imx6ul-ccimx6ulsbcpro.dtb.o
lwl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
lwl-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += imx7d-sdb.dtb.o
+lwl-$(CONFIG_MACH_MEERKAT96) += imx7d-meerkat96.dtb.o
lwl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
lwl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o
lwl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o
@@ -114,11 +115,13 @@ lwl-$(CONFIG_MACH_RPI) += bcm2835-rpi.dtb.o
lwl-$(CONFIG_MACH_RPI2) += bcm2836-rpi-2.dtb.o
lwl-$(CONFIG_MACH_RPI3) += bcm2837-rpi-3.dtb.o
lwl-$(CONFIG_MACH_RPI_CM3) += bcm2837-rpi-cm3.dtb.o
+lwl-$(CONFIG_MACH_RPI4) += bcm2711-rpi-4.dtb.o
lwl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
lwl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o imx6qp-sabresd.dtb.o
lwl-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += imx6sx-sdb.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += socfpga_cyclone5_socdk.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
+lwl-$(CONFIG_MACH_SOCFPGA_ENCLUSTRA_AA1) += socfpga_arria10_mercury_aa1.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += socfpga_arria10_achilles.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += socfpga_cyclone5_de0_nano_soc.dtb.o
lwl-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += socfpga_cyclone5_de10_nano.dtb.o
@@ -139,9 +142,10 @@ lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboar
lwl-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o
lwl-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o
lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o
-lwl-$(CONFIG_MACH_NXP_IMX8MN_EVK) += imx8mn-evk.dtb.o
+lwl-$(CONFIG_MACH_NXP_IMX8MN_EVK) += imx8mn-evk.dtb.o imx8mn-ddr4-evk.dtb.o
lwl-$(CONFIG_MACH_NXP_IMX8MP_EVK) += imx8mp-evk.dtb.o
lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o
+lwl-$(CONFIG_MACH_INNOCOMM_WB15) += imx8mm-innocomm-wb15-evk.dtb.o
lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
lwl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
@@ -197,4 +201,4 @@ lwl-$(CONFIG_MACH_TQMLS1046A) += fsl-tqmls1046a-mbls10xxa.dtb.o
lwl-$(CONFIG_MACH_ZEDBOARD) += zynq-zed.dtb.o
lwl-$(CONFIG_MACH_MNT_REFORM) += imx8mq-mnt-reform2.dtb.o
-clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
+clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z
diff --git a/arch/arm/dts/am335x-baltos-minimal.dts b/arch/arm/dts/am335x-baltos-minimal.dts
index dff901f050..28a550aa84 100644
--- a/arch/arm/dts/am335x-baltos-minimal.dts
+++ b/arch/arm/dts/am335x-baltos-minimal.dts
@@ -45,6 +45,18 @@
};
&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dip_switch_pins>;
+
+ dip_switch_pins: pinmux_dip_switch_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ };
+
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0xf0 (INPUT_EN | PULL_UP) MUX_MODE0 /* mmc0_dat3.mmc0_dat3 */
@@ -285,6 +297,10 @@
interrupts = <20 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
+ gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
+ "GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
+ "ModeA0", "ModeA1", "ModeA2", "ModeA3",
+ "ModeB0", "ModeB1", "ModeB2", "ModeB3";
};
};
@@ -399,33 +415,40 @@
};
};
-&mac {
+&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
- dual_emac = <1>;
status = "okay";
};
-&davinci_mdio {
+&davinci_mdio_sw {
+ status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <7>;
+ eee-broken-100tx;
+ eee-broken-1000t;
+ };
};
-&cpsw_emac0 {
- phy_id = <&davinci_mdio>, <0>;
+&cpsw_port1 {
phy-mode = "rmii";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <1>;
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
};
-&cpsw_emac1 {
- phy_id = <&davinci_mdio>, <7>;
- phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <2>;
+&cpsw_port2 {
+ phy-mode = "rgmii-id";
+ ti,dual-emac-pvid = <2>;
+ phy-handle = <&phy1>;
};
&mmc1 {
@@ -438,3 +461,111 @@
&gpio0 {
ti,no-reset-on-init;
};
+
+&gpio1 {
+ gpio-line-names =
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_0_alt",
+ "SW2_1_alt",
+ "SW2_2_alt",
+ "SW2_3_alt",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_0",
+ "SW2_1",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "3G_PWR_EN",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "SW2_2",
+ "SW2_3",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC";
+};
diff --git a/arch/arm/dts/am335x-myirtech-myd.dts b/arch/arm/dts/am335x-myirtech-myd.dts
index 1ea0f2a440..54050816fc 100644
--- a/arch/arm/dts/am335x-myirtech-myd.dts
+++ b/arch/arm/dts/am335x-myirtech-myd.dts
@@ -22,33 +22,14 @@
};
-&nand0 {
- /delete-node/ partition@0;
- /delete-node/ partition@20000;
-
- nand_parts: partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "MLO";
- reg = <0x00000 0x20000>;
- };
-
- partition@80000 {
- label = "boot";
- reg = <0x80000 0x100000>;
- };
-
- nand_environment: partition@180000 {
- label = "env";
- reg = <0x180000 0x40000>;
- };
+&nand_parts {
+ nand_environment: partition@180000 {
+ label = "env";
+ reg = <0x180000 0x40000>;
+ };
- partition@1c0000 {
- label = "system";
- reg = <0x1c0000 0>;
- };
+ partition@1c0000 {
+ label = "system";
+ reg = <0x1c0000 0>;
};
};
diff --git a/arch/arm/dts/bcm2711-rpi-4.dts b/arch/arm/dts/bcm2711-rpi-4.dts
new file mode 100644
index 0000000000..3c0caa73f8
--- /dev/null
+++ b/arch/arm/dts/bcm2711-rpi-4.dts
@@ -0,0 +1,18 @@
+#include <arm64/broadcom/bcm2711-rpi-4-b.dts>
+
+&{/memory@0} {
+ reg = <0x0 0x0 0x0>;
+};
+
+&sdhci {
+ /* no use for SDIO WiFi in barebox */
+ status = "disabled";
+};
+
+&uart1 {
+ /* VPU core clock is reported at 200MHz, but needs to be 500Mhz
+ * for ns16550 driver to set correct baudrate. Until that's
+ * figured out, hardcode clock frequency to the expected value
+ */
+ clock-frequency = <500000000>;
+};
diff --git a/arch/arm/dts/imx6q-marsboard.dts b/arch/arm/dts/imx6q-marsboard.dts
index cc5edfff66..4dfb17489c 100644
--- a/arch/arm/dts/imx6q-marsboard.dts
+++ b/arch/arm/dts/imx6q-marsboard.dts
@@ -18,7 +18,7 @@
};
&ecspi1 {
- m25p80@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
index b593545ffe..714ba8e755 100644
--- a/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/dts/imx6qdl-zii-rdu2.dtsi
@@ -234,16 +234,6 @@
&i2c1 {
edp-bridge@68 {
pinctrl-0 = <&pinctrl_tc358767>, <&pinctrl_disp0>;
-
- ports {
- port@1 {
- reg = <1>;
-
- tc358767_in: endpoint {
- remote-endpoint = <&disp0_out>;
- };
- };
- };
};
};
@@ -253,10 +243,6 @@
};
};
-&ipu1_di0_disp0 {
- remote-endpoint = <&tc358767_in>;
-};
-
&ldb {
lvds-channel@0 {
fsl,data-width = <24>;
diff --git a/arch/arm/dts/imx7d-ac-sxb.dtsi b/arch/arm/dts/imx7d-ac-sxb.dtsi
index 00b0fd11c6..6d7a6d2d54 100644
--- a/arch/arm/dts/imx7d-ac-sxb.dtsi
+++ b/arch/arm/dts/imx7d-ac-sxb.dtsi
@@ -41,9 +41,15 @@
keep-power-in-suspend;
status = "okay";
- usdhc1_sdcard: state@4100000 {
- reg = <0x4100000 0xffffff>;
- label = "state-sdcard";
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usdhc1_sdcard: state@4100000 {
+ reg = <0x0 0x4100000 0x0 0xffffff>;
+ label = "state-sdcard";
+ };
};
};
@@ -56,11 +62,16 @@
non-removable;
status = "okay";
- usdhc3_emmc: usdhc3_emmc@1e800000 {
- reg = <0x1e800000 0xffffff>;
- label = "state-emmc";
- };
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ usdhc3_emmc: usdhc3_emmc@1e800000 {
+ reg = <0x0 0x1e800000 0x0 0xffffff>;
+ label = "state-emmc";
+ };
+ };
};
&wdog1 {
diff --git a/arch/arm/dts/imx7d-meerkat96.dts b/arch/arm/dts/imx7d-meerkat96.dts
new file mode 100644
index 0000000000..f9d18f355b
--- /dev/null
+++ b/arch/arm/dts/imx7d-meerkat96.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+#include <arm/imx7d-meerkat96.dts>
+
+/ {
+ chosen {
+ environment {
+ compatible = "barebox,environment";
+ device-path = &bareboxenv;
+ };
+ };
+};
+
+&usdhc1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ barebox@0 {
+ label = "barebox";
+ reg = <0x0 0x180000>;
+ };
+
+ bareboxenv: bareboxenv@180000 {
+ label = "bareboxenv";
+ reg = <0x180000 0x80000>;
+ };
+};
+
+/* FIXME: barebox serial is broken when barebox applies requested reparenting */
+&uart1 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&uart3 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+&uart6 {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
diff --git a/arch/arm/dts/imx8mm-innocomm-wb15-evk-upstream.dts b/arch/arm/dts/imx8mm-innocomm-wb15-evk-upstream.dts
new file mode 100644
index 0000000000..0a28e7ceab
--- /dev/null
+++ b/arch/arm/dts/imx8mm-innocomm-wb15-evk-upstream.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Bang & Olufsen
+ * Copyright 2022 Pengutronix
+ */
+
+/dts-v1/;
+
+#include "imx8mm-innocomm-wb15.dtsi"
+
+/ {
+ model = "InnoComm WB15-EVK";
+ compatible = "innocomm,wb15-evk", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+ status = "okay";
+
+ led-0 {
+ label = "debug";
+ gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_vsd_3v3: regulator-vsd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_ethphy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy_reg>;
+ regulator-name = "PHY_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy>;
+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-supply = <&reg_ethphy>;
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_vsd_3v3>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ >;
+ };
+
+ pinctrl_fec_phy: fecphygrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec_phy_reg: fecphyreggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
+ >;
+ };
+
+ pinctrl_gpio_leds: led_grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
+ >;
+ };
+
+ pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts b/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts
new file mode 100644
index 0000000000..e5c3fc1587
--- /dev/null
+++ b/arch/arm/dts/imx8mm-innocomm-wb15-evk.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mm-innocomm-wb15-evk-upstream.dts"
+
+/ {
+ chosen {
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &usdhc1, "partname:barebox-environment";
+ status = "disabled";
+ };
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+};
+
+&ocotp {
+ barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&usdhc1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x0 0x0 0x100000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0x0 0x100000 0x0 0x100000>;
+ };
+ };
+};
+
+&usdhc2 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x0 0x0 0x100000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0x0 0x100000 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mm-innocomm-wb15.dtsi b/arch/arm/dts/imx8mm-innocomm-wb15.dtsi
new file mode 100644
index 0000000000..7e25450362
--- /dev/null
+++ b/arch/arm/dts/imx8mm-innocomm-wb15.dtsi
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Bang & Olufsen
+ */
+
+#include <arm64/freescale/imx8mm.dtsi>
+#include "imx8mm.dtsi"
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+/ {
+ reg_modem: regulator-modem {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_modem_regulator>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "epdev_on";
+ gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_3v3_out: regulator-3v3-out {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_OUT";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&cpu_alert0 {
+ temperature = <95000>;
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25000000 {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <850000>;
+ rohm,dvs-idle-voltage = <850000>;
+ rohm,dvs-suspend-voltage = <850000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // buck5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // buck6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // buck7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // buck8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ fsl,max-link-speed = <1>;
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4349-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_modem_bt>;
+ device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&reg_3v3_out>;
+ vddio-supply = <&reg_3v3_out>;
+ clocks = <&osc_32k>;
+ max-speed = <3000000>;
+ clock-names = "extclk";
+ };
+};
+
+&uart2 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */
+
+&iomuxc {
+ pinctrl_i2c1: i2c1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
+ pinctrl_pcie0: pcie0-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6
+ >;
+ };
+
+ pinctrl_modem_bt: modembt-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
+ MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19
+ MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
+ MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
+ MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
+ >;
+ };
+
+ pinctrl_modem_regulator: modemreg-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41
+ >;
+ };
+
+ pinctrl_pmic: pmicirq-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 78bbacb2b1..22ae01a20a 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -1,10 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/features/imx8m.h>
+
/ {
aliases {
gpr.reboot_mode = &reboot_mode_gpr;
};
};
+feat: &ocotp {
+ #feature-cells = <1>;
+ barebox,feature-controller;
+};
+
&src {
compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon", "simple-mfd";
@@ -16,3 +24,47 @@
mode-serial = <0x00000010>, <0x40000000>;
};
};
+
+&A53_1 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>;
+};
+
+&A53_2 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&A53_3 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&gpc {
+ barebox,feature-gates = <&feat 0>;
+};
+
+&vpu_g1 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_g2 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&vpu_blk_ctrl {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpumix {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g1 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_g2 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
+
+&pgc_vpu_h1 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_VPU>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts
new file mode 100644
index 0000000000..6ebb4d15e4
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-evk.dts
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <arm64/freescale/imx8mn-ddr4-evk.dts>
+#include "imx8mn-evk.dtsi"
diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts
index b8e7e1acf5..cbb8b8874c 100644
--- a/arch/arm/dts/imx8mn-evk.dts
+++ b/arch/arm/dts/imx8mn-evk.dts
@@ -1,12 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2017 NXP
- * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
/dts-v1/;
#include <arm64/freescale/imx8mn-evk.dts>
+#include "imx8mn-evk.dtsi"
+#include "imx8mn.dtsi"
/ {
chosen {
@@ -89,4 +87,3 @@
#size-cells = <1>;
};
};
-
diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
new file mode 100644
index 0000000000..ceeb5f8b93
--- /dev/null
+++ b/arch/arm/dts/imx8mn-evk.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+/ {
+ chosen {
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &usdhc2, "partname:barebox-environment";
+ status = "disabled";
+ };
+ environment-emmc {
+ compatible = "barebox,environment";
+ device-path = &usdhc3, "partname:barebox-environment";
+ status = "disabled";
+ };
+ };
+};
+
+&usdhc2 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&usdhc3 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0xe0000>;
+ };
+
+ partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+};
+
+&ocotp {
+ barebox,provide-mac-address = <&fec1 0x640>;
+};
+
+&iomuxc {
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
+ MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
+ MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
+ MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
+ MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
+ MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
+ >;
+ };
+};
+
+&flexspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+
+ system_flash: flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
new file mode 100644
index 0000000000..17e8f78bf2
--- /dev/null
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/features/imx8m.h>
+
+feat: &ocotp {
+ #feature-cells = <1>;
+ barebox,feature-controller;
+};
+
+&A53_1 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_CPU_DUAL>;
+};
+
+&A53_2 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&A53_3 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_CPU_QUAD>;
+};
+
+&gpc {
+ barebox,feature-gates = <&feat 0>;
+};
+
+&gpu {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_gpumix {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts
index 8639ca0886..0036ef31f1 100644
--- a/arch/arm/dts/rk3566-quartz64-a.dts
+++ b/arch/arm/dts/rk3566-quartz64-a.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <arm64/rockchip/rk3566-quartz64-a.dts>
+#include "rk356x.dtsi"
/ {
memory@a00000 {
diff --git a/arch/arm/dts/rk3568-bpi-r2-pro.dts b/arch/arm/dts/rk3568-bpi-r2-pro.dts
index da76ab64c1..58a2bc442f 100644
--- a/arch/arm/dts/rk3568-bpi-r2-pro.dts
+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts
@@ -5,23 +5,9 @@
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3568.dtsi"
-
+#include "arm64/rockchip/rk3568-bpi-r2-pro.dts"
/ {
- model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
-
- aliases {
- emmc = &sdhci;
- sd = &sdmmc0;
- };
-
chosen {
- stdout-path = "serial2:1500000n8";
-
environment-sd {
compatible = "barebox,environment";
device-path = &environment_sd;
@@ -39,422 +25,10 @@
device_type = "memory";
reg = <0x0 0x00a00000 0x0 0x7f600000>;
};
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&blue_led_pin &green_led_pin>;
-
- blue_led: led-0 {
- color = <LED_COLOR_ID_BLUE>;
- default-state = "off";
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
- };
-
- green_led: led-1 {
- color = <LED_COLOR_ID_GREEN>;
- default-state = "on";
- function = LED_FUNCTION_POWER;
- gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
- };
- };
-
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- vcc3v3_sys: vcc3v3-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc5v0_sys: vcc5v0-sys {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
- };
-
- vcc3v3_lcd0_n: vcc3v3-lcd0-n {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd0_n";
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_lcd1_n: vcc3v3-lcd1-n {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_lcd1_n";
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc5v0_host: vcc5v0-host-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_host_en>;
- regulator-always-on;
- };
-};
-
-&gmac1 {
- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy1>;
- phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac1m1_miim
- &gmac1m1_tx_bus2
- &gmac1m1_rx_bus2
- &gmac1m1_rgmii_clk
- &gmac1m1_rgmii_bus>;
-
- snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */
- snps,reset-delays-us = <0 20000 100000>;
- tx_delay = <0x3c>;
- rx_delay = <0x2f>;
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
-
- clock-output-names = "rk808-clkout1", "rk808-clkout2";
- /* 1: rst regs (default in codes), 0: rst the pmic */
- pmic-reset-func = <0>;
-
- rockchip,system-power-controller;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-init-microvolt = <900000>;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-init-microvolt = <900000>;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-init-microvolt = <900000>;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c5 {
- /* pin 3 (SDA) + 4 (SCL) of header con2 */
- status = "disabled";
-};
-
-&mdio1 {
- rgmii_phy1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- };
-};
-
-&pinctrl {
- leds {
- blue_led_pin: blue-led-pin {
- rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- green_led_pin: green-led-pin {
- rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- pmic {
- pmic_int: pmic_int {
- rockchip,pins =
- <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
-
- };
-
- usb {
- vcc5v0_host_en: vcc5v0-host-en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pwm8 {
- /* fan 5v - gnd - pwm */
- status = "okay";
-};
-
-&pwm10 {
- /* pin 7 of header con2 */
- status = "disabled";
-};
-
-&pwm11 {
- /* pin 15 of header con2 */
- status = "disabled";
-};
-
-&pwm12 {
- /* pin 21 of header con2 */
- /* shared with uart9 + spi3 */
- pinctrl-0 = <&pwm12m1_pins>;
- status = "disabled";
-};
-
-&pwm13 {
- /* pin 24 of header con2 */
- /* shared with uart9 */
- pinctrl-0 = <&pwm13m1_pins>;
- status = "disabled";
-};
-
-&pwm14 {
- /* pin 23 of header con2 */
- /* shared with spi3 */
- pinctrl-0 = <&pwm14m1_pins>;
- status = "disabled";
-};
-
-&pwm15 {
- /* pin 19 of header con2 */
- /* shared with spi3 */
- pinctrl-0 = <&pwm15m1_pins>;
- status = "disabled";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
};
&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
no-sd;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
- status = "okay";
partitions {
compatible = "fixed-partitions";
@@ -469,18 +43,6 @@
};
&sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
- disable-wp;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- status = "okay";
-
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
@@ -493,87 +55,6 @@
};
};
-&uart0 {
- /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
- status = "disabled";
-};
-
-&uart2 {
- /* debug-uart */
- status = "okay";
-};
-
-&uart7 {
- /* pin 11 (TX) + 13 (RX) of header con2 */
- pinctrl-0 = <&uart7m1_xfer>;
- status = "disabled";
-};
-
-&uart9 {
- /* pin 21 (TX) + 24 (RX) of header con2 */
- /* shared with pwm13 and pwm12/spi3 */
- pinctrl-0 = <&uart9m1_xfer>;
- status = "disabled";
-};
-
-&u2phy0_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy0_otg {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy1_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&u2phy1_otg {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
&usb_host0_xhci {
dr_mode = "host";
- extcon = <&usb2phy0>;
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&combphy0_us {
- status = "okay";
-};
-
-&combphy1_usq {
- status = "okay";
};
diff --git a/arch/arm/dts/rk3568-evb1-v10.dts b/arch/arm/dts/rk3568-evb1-v10.dts
index d2c1fc89a8..82186ff86e 100644
--- a/arch/arm/dts/rk3568-evb1-v10.dts
+++ b/arch/arm/dts/rk3568-evb1-v10.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <arm64/rockchip/rk3568-evb1-v10.dts>
+#include "rk356x.dtsi"
/ {
chosen: chosen {
diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts
index 44d4fc9686..25a0c05737 100644
--- a/arch/arm/dts/rk3568-rock-3a.dts
+++ b/arch/arm/dts/rk3568-rock-3a.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <arm64/rockchip/rk3568-rock-3a.dts>
+#include "rk356x.dtsi"
/ {
chosen: chosen {
diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
new file mode 100644
index 0000000000..254450d78f
--- /dev/null
+++ b/arch/arm/dts/rk356x.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/ {
+ aliases {
+ barebox,bootsource-mmc0 = &sdhci;
+ barebox,bootsource-mmc1 = &sdmmc0;
+ barebox,bootsource-mmc2 = &sdmmc1;
+ };
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts
new file mode 100644
index 0000000000..e225b8883a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include <arm/socfpga_arria10_mercury_aa1.dtsi>
+
+/ {
+ aliases {
+ mmc0 = &mmc;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+
+ environment {
+ compatible = "barebox,environment";
+ device-path = &environment_mmc;
+ };
+ };
+};
+
+// provide reset-names until fixed in the upstream dts. Binding prescribes this property.
+&{/soc/dwmmc0@ff808000} {
+ reset-names = "reset";
+};
+
+// This clock is unused, but fixed-clocks need to have a clock-frequency set
+&{/soc/clkmgr@ffd04000/clocks/cb_intosc_hs_div2_clk} {
+ clock-frequency = <0>;
+};
+
+&{/soc/clkmgr@ffd04000/clocks/cb_intosc_ls_clk} {
+ clock-frequency = <60000000>;
+};
+
+&{/soc/clkmgr@ffd04000/clocks/f2s_free_clk} {
+ clock-frequency = <200000000>;
+};
+
+&mmc {
+ bus-width = <8>;
+ non-removable;
+ disable-wp;
+ no-sd;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ // This must be marked as an "A2" partition in the partition table
+ barebox1_xload: partition@100000 {
+ label = "barebox1-xload";
+ reg = <0x100000 0x40000>;
+ };
+
+ barebox2_xload: partition@140000 {
+ label = "barebox2-xload";
+ reg = <0x140000 0x40000>;
+ };
+
+ barebox1: partition@200000 {
+ label = "barebox1";
+ reg = <0x200000 0x100000>;
+ };
+
+ barebox2: partition@300000 {
+ label = "barebox2";
+ reg = <0x300000 0x100000>;
+ };
+
+ environment_mmc: partition@400000 {
+ label = "environment";
+ reg = <0x400000 0x8000>;
+ };
+
+ // This is actually the second partition on the mmc. It has no filesystem.
+ bitstream1: partition@700000 {
+ label = "bitstream1";
+ reg = <0x700000 0x2000000>;
+ };
+
+ bitstream2: partition@2700000 {
+ label = "bitstream2";
+ reg = <0x2700000 0x2000000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 7b07aaf7cf..ac6536a556 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -31,22 +31,20 @@
compatible = "st,stm32mp1-ddr";
reg = <0x5a003000 0x1000>;
};
-
- tamp@5c00a000 {
- compatible = "simple-bus", "syscon", "simple-mfd";
- reg = <0x5c00a000 0x400>;
-
- reboot_mode_tamp: reboot-mode {
- compatible = "syscon-reboot-mode";
- offset = <0x150>; /* reg20 */
- mask = <0xff>;
- mode-normal = <0>;
- mode-loader = <0xBB>;
- mode-recovery = <0xBC>;
- };
- };
};
&bsec {
barebox,provide-mac-address = <&ethernet0 0x39>;
};
+
+&tamp {
+ reboot_mode_tamp: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x150>; /* reg20 */
+ mask = <0xffff>;
+ mode-normal = <0>;
+ mode-loader = <0xBB>;
+ mode-recovery = <0xBC>;
+ barebox,mode-serial = <0xFF>;
+ };
+};
diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h
index 8240cce9bf..a34f77f2ab 100644
--- a/arch/arm/include/asm/barebox-arm.h
+++ b/arch/arm/include/asm/barebox-arm.h
@@ -20,6 +20,8 @@
#include <asm/barebox-arm-head.h>
#include <asm/common.h>
#include <asm/sections.h>
+#include <asm/reloc.h>
+#include <linux/stringify.h>
/*
* We have a 4GiB address space split into 1MiB sections, with each
@@ -27,34 +29,6 @@
*/
#define ARM_TTB_SIZE (SZ_4G / SZ_1M * sizeof(u32))
-unsigned long get_runtime_offset(void);
-
-/* global_variable_offset() - Access global variables when not running at link address
- *
- * Get the offset of global variables when not running at the address we are
- * linked at.
- */
-static inline unsigned long global_variable_offset(void)
-{
-#ifdef CONFIG_CPU_V8
- unsigned long text;
-
- __asm__ __volatile__(
- "adr %0, _text\n"
- : "=r" (text)
- :
- : "memory");
- return text - (unsigned long)_text;
-#else
- return get_runtime_offset();
-#endif
-}
-
-void setup_c(void);
-void pbl_barebox_break(void);
-void relocate_to_current_adr(void);
-void relocate_to_adr(unsigned long target);
-void relocate_to_adr_full(unsigned long target);
void __noreturn barebox_arm_entry(unsigned long membase, unsigned long memsize, void *boarddata);
struct barebox_arm_boarddata {
@@ -164,23 +138,23 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
#ifdef CONFIG_CPU_64
-#define ____emit_entry_prologue(instr, ...) do { \
- static __attribute__ ((unused,section(".text_head_prologue"))) \
+#define ____emit_entry_prologue(name, instr, ...) do { \
+ static __attribute__ ((unused,section(".text_head_prologue_" __stringify(name)))) \
const u32 __entry_prologue[] = {(instr), ##__VA_ARGS__}; \
barrier_data(__entry_prologue); \
} while(0)
-#define __emit_entry_prologue(instr1, instr2, instr3, instr4, instr5) \
- ____emit_entry_prologue(instr1, instr2, instr3, instr4, instr5)
+#define __emit_entry_prologue(name, instr1, instr2, instr3, instr4, instr5) \
+ ____emit_entry_prologue(name, instr1, instr2, instr3, instr4, instr5)
-#define __ARM_SETUP_STACK(stack_top) \
- __emit_entry_prologue(0x14000002 /* b pc+0x8 */, \
+#define __ARM_SETUP_STACK(name, stack_top) \
+ __emit_entry_prologue(name, 0x14000002 /* b pc+0x8 */, \
stack_top /* 32-bit literal */, \
0x18ffffe9 /* ldr w9, top */, \
0xb4000049 /* cbz x9, pc+0x8 */, \
0x9100013f /* mov sp, x9 */)
#else
-#define __ARM_SETUP_STACK(stack_top) if (stack_top) arm_setup_stack(stack_top)
+#define __ARM_SETUP_STACK(name, stack_top) if (stack_top) arm_setup_stack(stack_top)
#endif
/*
@@ -201,7 +175,7 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
(ulong r0, ulong r1, ulong r2) \
{ \
__barebox_arm_head(); \
- __ARM_SETUP_STACK(stack_top); \
+ __ARM_SETUP_STACK(name, stack_top); \
__##name(r0, r1, r2); \
} \
static void noinline __##name \
@@ -211,7 +185,7 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
static void ____##name(ulong, ulong, ulong); \
ENTRY_FUNCTION(name, arg0, arg1, arg2) \
{ \
- __ARM_SETUP_STACK(stack_top); \
+ __ARM_SETUP_STACK(name, stack_top); \
____##name(arg0, arg1, arg2); \
} \
static void noinline ____##name \
@@ -228,7 +202,7 @@ static inline unsigned long arm_mem_barebox_image(unsigned long membase,
(ulong r0, ulong r1, ulong r2) \
{ \
__barebox_arm_head(); \
- __ARM_SETUP_STACK(0); \
+ __ARM_SETUP_STACK(name, 0); \
__##name(r0, r1, r2); \
} \
static void NAKED noinline __##name \
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7dc027c174..c3fc057650 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -6,6 +6,23 @@
#include <linux/stringify.h>
#include <linux/kernel.h>
+#ifdef CONFIG_CPU_64v8
+
+#define CPUID_ID midr_el1
+#define CPUID_CACHETYPE ctr_el0
+#define CPUID_MPIDR mpidr_el1
+
+#define read_cpuid(reg) \
+ ({ \
+ unsigned int __val; \
+ asm("mrs %0, " __stringify(reg) \
+ : "=r" (__val) \
+ : \
+ : "cc"); \
+ __val; \
+ })
+#else
+
#define CPUID_ID 0
#define CPUID_CACHETYPE 1
#define CPUID_TCM 2
@@ -27,8 +44,6 @@
#define CPUID_EXT_ISAR4 "c2, 4"
#define CPUID_EXT_ISAR5 "c2, 5"
-extern unsigned int processor_id;
-
#define read_cpuid(reg) \
({ \
unsigned int __val; \
@@ -47,6 +62,9 @@ extern unsigned int processor_id;
: "cc"); \
__val; \
})
+#endif
+
+extern unsigned int processor_id;
/*
* The CPU ID never changes at run time, so we might as well tell the
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index 226b1c1464..75a6c1ad86 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -10,6 +10,7 @@ static inline void *dma_alloc(size_t size)
}
#ifndef CONFIG_MMU
+#define dma_alloc_coherent dma_alloc_coherent
static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
{
void *ret = xmemalign(4096, size);
@@ -21,22 +22,26 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
return ret;
}
+#define dma_alloc_writecombine dma_alloc_writecombine
static inline void *dma_alloc_writecombine(size_t size, dma_addr_t *dma_handle)
{
return dma_alloc_coherent(size, dma_handle);
}
+#define dma_free_coherent dma_free_coherent
static inline void dma_free_coherent(void *mem, dma_addr_t dma_handle,
size_t size)
{
free(mem);
}
+#define dma_sync_single_for_cpu dma_sync_single_for_cpu
static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
}
+#define dma_sync_single_for_device dma_sync_single_for_device
static inline void dma_sync_single_for_device(dma_addr_t address, size_t size,
enum dma_data_direction dir)
{
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1c0f522d1d..486b142950 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -18,14 +18,4 @@ extern void memcpy_fromio(void *, const volatile void __iomem *, size_t);
extern void memcpy_toio(volatile void __iomem *, const void *, size_t);
extern void memset_io(volatile void __iomem *, int, size_t);
-static inline void *phys_to_virt(unsigned long phys)
-{
- return (void *)phys;
-}
-
-static inline unsigned long virt_to_phys(volatile void *mem)
-{
- return (unsigned long)mem;
-}
-
#endif /* __ASM_ARM_IO_H */
diff --git a/arch/arm/include/asm/reloc.h b/arch/arm/include/asm/reloc.h
new file mode 100644
index 0000000000..0002c96c01
--- /dev/null
+++ b/arch/arm/include/asm/reloc.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _ASM_RELOC_H_
+#define _ASM_RELOC_H_
+
+#include <asm/sections.h>
+
+unsigned long get_runtime_offset(void);
+
+/* global_variable_offset() - Access global variables when not running at link address
+ *
+ * Get the offset of global variables when not running at the address we are
+ * linked at.
+ */
+static inline unsigned long global_variable_offset(void)
+{
+#ifdef CONFIG_CPU_V8
+ unsigned long text;
+
+ __asm__ __volatile__(
+ "adr %0, _text\n"
+ : "=r" (text)
+ :
+ : "memory");
+ return text - (unsigned long)_text;
+#else
+ return get_runtime_offset();
+#endif
+}
+#define global_variable_offset() global_variable_offset()
+
+void relocate_to_current_adr(void);
+void relocate_to_adr(unsigned long target);
+void relocate_to_adr_full(unsigned long target);
+
+void pbl_barebox_break(void);
+
+void setup_c(void);
+
+#include <asm-generic/reloc.h>
+
+#endif
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index c7f9987748..5a84fde75b 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -44,6 +44,12 @@
#define CPU_IS_CORTEX_A15 0x410fc0f0
#define CPU_IS_CORTEX_A15_MASK 0xff0ffff0
+#define CPU_IS_CORTEX_A53 0x410fd030
+#define CPU_IS_CORTEX_A53_MASK 0xff0ffff0
+
+#define CPU_IS_CORTEX_A72 0x410fd080
+#define CPU_IS_CORTEX_A72_MASK 0xff0ffff0
+
#define CPU_IS_PXA250 0x69052100
#define CPU_IS_PXA250_MASK 0xfffff7f0
diff --git a/arch/arm/lib/pbl.lds.S b/arch/arm/lib/pbl.lds.S
index e77b3220fc..d48f27bc43 100644
--- a/arch/arm/lib/pbl.lds.S
+++ b/arch/arm/lib/pbl.lds.S
@@ -99,7 +99,13 @@ SECTIONS
.piggydata : {
*(.piggydata)
}
- __piggydata_end = .;
+
+ . = ALIGN(4);
+ __pblext_start = .;
+ .pblext : {
+ *(.pblext.*)
+ }
+ __pblext_end = .;
.image_end : { KEEP(*(.__image_end)) }
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bfdc89f680..390d49d03d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += setup.o aic.o
-lwl-y += at91_pmc_ll.o ddramc_ll.o matrix.o
+lwl-y += at91_pmc_ll.o ddramc_ll.o at91sam9_sdramc_ll.o matrix.o
lwl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
@@ -17,6 +17,7 @@ obj-y += at91sam9_reset.o
obj-y += at91sam9g45_reset.o
obj-pbl-$(CONFIG_HAVE_AT91_DDRAMC) += ddramc.o
pbl-$(CONFIG_AT91_MCI_PBL) += xload-mmc.o
+pbl-$(CONFIG_AT91_MCI_PBL) += at91sam9_xload_mmc.o
obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
obj-$(CONFIG_HAVE_AT91SAM9_RST) += at91sam9_rst.o
@@ -30,6 +31,7 @@ ifeq ($(CONFIG_OFDEVICE),)
obj-$(CONFIG_SOC_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o sama5d3_devices.o
endif
+lwl-$(CONFIG_SOC_AT91SAM9263) += sam9263_ll.o
lwl-$(CONFIG_SOC_SAMA5D2) += sama5d2_ll.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
lwl-$(CONFIG_SOC_SAMA5D3) += sama5d3_ll.o
diff --git a/arch/arm/mach-at91/at91sam9_sdramc_ll.c b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
new file mode 100644
index 0000000000..805cfbbe43
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_sdramc_ll.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <mach/at91sam9_sdramc.h>
+#include <mach/early_udelay.h>
+
+static inline void sdramc_wr(const struct at91sam9_sdramc_config *config,
+ unsigned int offset,
+ const unsigned int value)
+{
+ writel(value, config->sdramc + offset);
+}
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+ unsigned int sdram_address)
+{
+ unsigned int i;
+
+ /* Step#1 SDRAM feature must be in the configuration register */
+ sdramc_wr(config, AT91_SDRAMC_CR, config->cr);
+
+ /* Step#2 For mobile SDRAM, temperature-compensated self refresh(TCSR),... */
+
+ /* Step#3 The SDRAM memory type must be set in the Memory Device Register */
+ sdramc_wr(config, AT91_SDRAMC_MDR, config->mdr);
+
+ /* Step#4 The minimum pause of 200 us is provided to precede any single toggle */
+ early_udelay(200);
+
+ /* Step#5 A NOP command is issued to the SDRAM devices */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NOP);
+ writel(0x00000000, sdram_address);
+
+ /* Step#6 An All Banks Precharge command is issued to the SDRAM devices */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+ writel(0x00000000, sdram_address);
+
+ /* Pause cycles */
+ early_udelay(2000);
+
+ /* Step#7 Eight auto-refresh cycles are provided */
+ for (i = 0; i < 8; i++) {
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+ writel(0x00000001 + i, sdram_address + 4 + 4 * i);
+ }
+
+ /* Pause cycles */
+ early_udelay(200);
+
+ /* Step#8 A Mode Register set (MRS) cycle is issued to program (TCSR, PASR, DS) */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+ writel(0xcafedede, sdram_address + 0x24);
+
+ /* Pause cycles */
+ early_udelay(200);
+
+ /* Step#9 For mobile SDRAM initialization, an Extended Mode Register set ... */
+
+ /* Step#10 The application must go into Normal Mode, setting Mode to 0
+ * and perform a write access at any location in the SDRAM.
+ */
+ sdramc_wr(config, AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL); // Set mode
+ writel(0x00000000, sdram_address); // Perform mode
+
+ /* Step#11 Write the refresh rate into the count field in the Refresh Register. */
+ sdramc_wr(config, AT91_SDRAMC_TR, config->tr);
+
+ return 0;
+}
diff --git a/arch/arm/mach-at91/at91sam9_xload_mmc.c b/arch/arm/mach-at91/at91sam9_xload_mmc.c
new file mode 100644
index 0000000000..5cf41c483d
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9_xload_mmc.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: 2022 Sam Ravnborg */
+
+#include <debug_ll.h>
+#include <common.h>
+#include <pbl/bio.h>
+
+#include <linux/sizes.h>
+#include <asm/cache.h>
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam926x.h>
+#include <mach/hardware.h>
+#include <mach/iomux.h>
+#include <mach/xload.h>
+#include <mach/gpio.h>
+
+typedef void (*func)(int zero, int arch, void *params);
+
+/*
+ * Load barebox.bin and start executing the first byte in the barebox image.
+ * barebox.bin is loaded to AT91_CHIPSELECT_1.
+ *
+ * To be able to load barebox.bin do a minimal init of the pheriferals
+ * used by MCI.
+ * This functions runs in PBL code and uses the PBL variant of the
+ * atmel_mci driver.
+ */
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+ bool slot_b)
+{
+ void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOA);
+ void *buf = (void *)AT91_CHIPSELECT_1;
+ void __iomem *base;
+ struct pbl_bio bio;
+ int ret;
+
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_PIOA);
+
+ if (mmc_id == 0) {
+ base = IOMEM(AT91SAM9263_BASE_MCI0);
+
+ /* CLK */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA12), AT91_MUX_PERIPH_A, 0);
+
+ if (!slot_b) {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA1), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA0), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA3), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA4), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA5), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ } else {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA16), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA17), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA18), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA19), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA20), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ }
+
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI0);
+ } else {
+ base = IOMEM(AT91SAM9263_BASE_MCI1);
+
+ /* CLK */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA6), AT91_MUX_PERIPH_A, 0);
+
+ if (!slot_b) {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA7), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA8), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA9), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA10), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA11), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ } else {
+ /* CMD */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA21), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+
+ /* DAT0 to DAT3 */
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA22), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA23), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA24), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PA25), AT91_MUX_PERIPH_A, GPIO_PULL_UP);
+ }
+
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9263_ID_MCI1);
+ }
+
+ ret = at91_mci_bio_init(&bio, base, clock, (int)slot_b);
+ if (ret) {
+ pr_err("atmci_start_image: bio init faild: %d\n", ret);
+ goto out_panic;
+ }
+
+ /* at91sam9x do not support high capacity */
+ at91_mci_bio_set_highcapacity(false);
+
+ ret = pbl_fat_load(&bio, "barebox.bin", buf, SZ_16M);
+ if (ret < 0) {
+ pr_err("pbl_fat_load: error %d\n", ret);
+ goto out_panic;
+ }
+
+ sync_caches_for_execution();
+
+ ((func)buf)(0, 0, NULL);
+
+out_panic:
+ panic("FAT chainloading failed\n");
+}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 2860ea4854..c5ce0f82a1 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -170,6 +170,8 @@
#define AT91_PMC_IPLLA_1 (1 << 8)
#define AT91_PMC_IPLLA_2 (2 << 8)
#define AT91_PMC_IPLLA_3 (3 << 8)
+#define AT91SAM9_PMC_ICPPLLA (1 << 0)
+#define AT91SAM9_PMC_ICPPLLB (1 << 16)
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 2ea9aadafa..229f8d16b3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -108,4 +108,18 @@
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
+/*
+ * External memory
+ */
+#define AT91SAM9263_BASE_EBI0_CS0 0x10000000
+#define AT91SAM9263_BASE_EBI0_CS1 0x20000000 /* EBI0 SDRAMC */
+#define AT91SAM9263_BASE_EBI0_CS2 0x30000000
+#define AT91SAM9263_BASE_EBI0_CS3 0x40000000 /* EBI0 NANDFlash */
+#define AT91SAM9263_BASE_EBI0_CS4 0x50000000 /* Compact Flash Slot 0 */
+#define AT91SAM9263_BASE_EBI0_CS5 0x60000000 /* Compact Flash Slot 1 */
+#define AT91SAM9263_BASE_EBI1_CS0 0x70000000
+#define AT91SAM9263_BASE_EBI1_CS1 0x80000000 /* EBI1 SDRAMC */
+#define AT91SAM9263_BASE_EBI1_CS2 0x90000000 /* EBI1 NANDFlash */
+
+
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 2f10ce096e..837cceb41e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -25,7 +25,7 @@
#define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0)
#define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
#define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
@@ -35,12 +35,22 @@
#define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
#define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
#define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
-#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9263_MATRIX_SLOT_CYCLE_(x) (x << 0)
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I (0x0 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D (0x1 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC (0x2 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC (0x3 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_2DGC (0x4 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_ISI (0x5 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_DMA (0x6 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC (0x7 << 18)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB (0x8 << 18)
#define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
@@ -62,14 +72,23 @@
#define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
#define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
#define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9263_MATRIX_M0PR_(x) (x << 0) /* ARM926EJ-S Instruction priority */
#define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9263_MATRIX_M1PR_(x) (x << 4) /* ARM926EJ-S Data priority */
#define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9263_MATRIX_M2PR_(x) (x << 8) /* PDC priority */
#define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9263_MATRIX_M3PR_(x) (x << 12) /* LCDC priority */
#define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9263_MATRIX_M4PR_(x) (x << 16) /* 2DGC priority */
#define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9263_MATRIX_M5PR_(x) (x << 20) /* ISI priority */
#define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9263_MATRIX_M6PR_(x) (x << 24) /* DMA priority */
#define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9263_MATRIX_M7PR_(x) (x << 28) /* EMAC priority */
#define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9263_MATRIX_M8PR_(x) (x << 0) /* USB Priority */
#define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */
#define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
index 8ef83010d2..ae7e224a7f 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x.h
@@ -7,4 +7,6 @@
#define AT91SAM926X_BASE_RSTC 0xfffffd00
#define AT91SAM926X_BASE_WDT 0xfffffd40
+#define AT91SAM926X_ID_SYS 1 /* System Controller Interrupt */
+
#endif /* __MACH_AT91SAM926X_H */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 80effe2148..0e05387aa0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -47,12 +47,108 @@
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
-#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
-#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
-#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
-#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
-#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
-#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
+#define AT91_SDRAMC_TWR (0xF << 8) /* Number of Write Recovery Time Cycles */
+#define AT91_SDRAMC_TWR_0 (0x0 << 8)
+#define AT91_SDRAMC_TWR_1 (0x1 << 8)
+#define AT91_SDRAMC_TWR_2 (0x2 << 8)
+#define AT91_SDRAMC_TWR_3 (0x3 << 8)
+#define AT91_SDRAMC_TWR_4 (0x4 << 8)
+#define AT91_SDRAMC_TWR_5 (0x5 << 8)
+#define AT91_SDRAMC_TWR_6 (0x6 << 8)
+#define AT91_SDRAMC_TWR_7 (0x7 << 8)
+#define AT91_SDRAMC_TWR_8 (0x8 << 8)
+#define AT91_SDRAMC_TWR_9 (0x9 << 8)
+#define AT91_SDRAMC_TWR_10 (0xA << 8)
+#define AT91_SDRAMC_TWR_11 (0xB << 8)
+#define AT91_SDRAMC_TWR_12 (0xC << 8)
+#define AT91_SDRAMC_TWR_13 (0xD << 8)
+#define AT91_SDRAMC_TWR_14 (0xE << 8)
+#define AT91_SDRAMC_TWR_15 (0xF << 8)
+#define AT91_SDRAMC_TRC (0xF << 12) /* Number of Row Cycle Delay Time Cycles */
+#define AT91_SDRAMC_TRC_0 (0x0 << 12)
+#define AT91_SDRAMC_TRC_1 (0x1 << 12)
+#define AT91_SDRAMC_TRC_2 (0x2 << 12)
+#define AT91_SDRAMC_TRC_3 (0x3 << 12)
+#define AT91_SDRAMC_TRC_4 (0x4 << 12)
+#define AT91_SDRAMC_TRC_5 (0x5 << 12)
+#define AT91_SDRAMC_TRC_6 (0x6 << 12)
+#define AT91_SDRAMC_TRC_7 (0x7 << 12)
+#define AT91_SDRAMC_TRC_8 (0x8 << 12)
+#define AT91_SDRAMC_TRC_9 (0x9 << 12)
+#define AT91_SDRAMC_TRC_10 (0xA << 12)
+#define AT91_SDRAMC_TRC_11 (0xB << 12)
+#define AT91_SDRAMC_TRC_12 (0xC << 12)
+#define AT91_SDRAMC_TRC_13 (0xD << 12)
+#define AT91_SDRAMC_TRC_14 (0xE << 12)
+#define AT91_SDRAMC_TRC_15 (0xF << 12)
+#define AT91_SDRAMC_TRP (0xF << 16) /* Number of Row Precharge Delay Time Cycles */
+#define AT91_SDRAMC_TRP_0 (0x0 << 16)
+#define AT91_SDRAMC_TRP_1 (0x1 << 16)
+#define AT91_SDRAMC_TRP_2 (0x2 << 16)
+#define AT91_SDRAMC_TRP_3 (0x3 << 16)
+#define AT91_SDRAMC_TRP_4 (0x4 << 16)
+#define AT91_SDRAMC_TRP_5 (0x5 << 16)
+#define AT91_SDRAMC_TRP_6 (0x6 << 16)
+#define AT91_SDRAMC_TRP_7 (0x7 << 16)
+#define AT91_SDRAMC_TRP_8 (0x8 << 16)
+#define AT91_SDRAMC_TRP_9 (0x9 << 16)
+#define AT91_SDRAMC_TRP_10 (0xA << 16)
+#define AT91_SDRAMC_TRP_11 (0xB << 16)
+#define AT91_SDRAMC_TRP_12 (0xC << 16)
+#define AT91_SDRAMC_TRP_13 (0xD << 16)
+#define AT91_SDRAMC_TRP_14 (0xE << 16)
+#define AT91_SDRAMC_TRP_15 (0xF << 16)
+#define AT91_SDRAMC_TRCD (0xF << 20) /* Number of Row to Column Delay Time Cycles */
+#define AT91_SDRAMC_TRCD_0 (0x0 << 20)
+#define AT91_SDRAMC_TRCD_1 (0x1 << 20)
+#define AT91_SDRAMC_TRCD_2 (0x2 << 20)
+#define AT91_SDRAMC_TRCD_3 (0x3 << 20)
+#define AT91_SDRAMC_TRCD_4 (0x4 << 20)
+#define AT91_SDRAMC_TRCD_5 (0x5 << 20)
+#define AT91_SDRAMC_TRCD_6 (0x6 << 20)
+#define AT91_SDRAMC_TRCD_7 (0x7 << 20)
+#define AT91_SDRAMC_TRCD_8 (0x8 << 20)
+#define AT91_SDRAMC_TRCD_9 (0x9 << 20)
+#define AT91_SDRAMC_TRCD_10 (0xA << 20)
+#define AT91_SDRAMC_TRCD_11 (0xB << 20)
+#define AT91_SDRAMC_TRCD_12 (0xC << 20)
+#define AT91_SDRAMC_TRCD_13 (0xD << 20)
+#define AT91_SDRAMC_TRCD_14 (0xE << 20)
+#define AT91_SDRAMC_TRCD_15 (0xF << 20)
+#define AT91_SDRAMC_TRAS (0xF << 24) /* Number of Active to Precharge Delay Time Cycles */
+#define AT91_SDRAMC_TRAS_0 (0x0 << 24)
+#define AT91_SDRAMC_TRAS_1 (0x1 << 24)
+#define AT91_SDRAMC_TRAS_2 (0x2 << 24)
+#define AT91_SDRAMC_TRAS_3 (0x3 << 24)
+#define AT91_SDRAMC_TRAS_4 (0x4 << 24)
+#define AT91_SDRAMC_TRAS_5 (0x5 << 24)
+#define AT91_SDRAMC_TRAS_6 (0x6 << 24)
+#define AT91_SDRAMC_TRAS_7 (0x7 << 24)
+#define AT91_SDRAMC_TRAS_8 (0x8 << 24)
+#define AT91_SDRAMC_TRAS_9 (0x9 << 24)
+#define AT91_SDRAMC_TRAS_10 (0xA << 24)
+#define AT91_SDRAMC_TRAS_11 (0xB << 24)
+#define AT91_SDRAMC_TRAS_12 (0xC << 24)
+#define AT91_SDRAMC_TRAS_13 (0xD << 24)
+#define AT91_SDRAMC_TRAS_14 (0xE << 24)
+#define AT91_SDRAMC_TRAS_15 (0xF << 24)
+#define AT91_SDRAMC_TXS (0xF << 28) /* Number of Exit Self Refresh to Active Delay Time Cycles */
+#define AT91_SDRAMC_TXSR_0 (0x0 << 28)
+#define AT91_SDRAMC_TXSR_1 (0x1 << 28)
+#define AT91_SDRAMC_TXSR_2 (0x2 << 28)
+#define AT91_SDRAMC_TXSR_3 (0x3 << 28)
+#define AT91_SDRAMC_TXSR_4 (0x4 << 28)
+#define AT91_SDRAMC_TXSR_5 (0x5 << 28)
+#define AT91_SDRAMC_TXSR_6 (0x6 << 28)
+#define AT91_SDRAMC_TXSR_7 (0x7 << 28)
+#define AT91_SDRAMC_TXSR_8 (0x8 << 28)
+#define AT91_SDRAMC_TXSR_9 (0x9 << 28)
+#define AT91_SDRAMC_TXSR_10 (0xA << 28)
+#define AT91_SDRAMC_TXSR_11 (0xB << 28)
+#define AT91_SDRAMC_TXSR_12 (0xC << 28)
+#define AT91_SDRAMC_TXSR_13 (0xD << 28)
+#define AT91_SDRAMC_TXSR_14 (0xE << 28)
+#define AT91_SDRAMC_TXSR_15 (0xF << 28)
#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
@@ -81,6 +177,22 @@
#ifndef __ASSEMBLY__
#include <io.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9263.h>
+
+struct at91sam9_sdramc_config {
+ void __iomem *sdramc;
+ unsigned int mr;
+ unsigned int tr;
+ unsigned int cr;
+ unsigned int lpr;
+ unsigned int mdr;
+};
+
+int at91sam9_sdramc_initialize(const struct at91sam9_sdramc_config *config,
+ unsigned int sdram_address);
+
static inline u32 at91_get_sdram_size(void *base)
{
u32 val;
@@ -107,14 +219,11 @@ static inline u32 at91_get_sdram_size(void *base)
return size;
}
-
static inline bool at91_is_low_power_sdram(void *base)
{
return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM;
}
-#ifdef CONFIG_SOC_AT91SAM9260
-#include <mach/at91sam9260.h>
static inline u32 at91sam9260_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
@@ -124,20 +233,7 @@ static inline bool at91sam9260_is_low_power_sdram(void)
{
return at91_is_low_power_sdram(IOMEM(AT91SAM9260_BASE_SDRAMC));
}
-#else
-static inline u32 at91sam9260_get_sdram_size(void)
-{
- return 0;
-}
-
-static inline bool at91sam9260_is_low_power_sdram(void)
-{
- return false;
-}
-#endif
-#ifdef CONFIG_SOC_AT91SAM9261
-#include <mach/at91sam9261.h>
static inline u32 at91sam9261_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
@@ -147,20 +243,7 @@ static inline bool at91sam9261_is_low_power_sdram(void)
{
return at91_is_low_power_sdram(IOMEM(AT91SAM9261_BASE_SDRAMC));
}
-#else
-static inline u32 at91sam9261_get_sdram_size(void)
-{
- return 0;
-}
-static inline bool at91sam9261_is_low_power_sdram(void)
-{
- return false;
-}
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9263
-#include <mach/at91sam9263.h>
static inline u32 at91sam9263_get_sdram_size(int bank)
{
switch (bank) {
@@ -184,18 +267,6 @@ static inline bool at91sam9263_is_low_power_sdram(int bank)
return false;
}
}
-#else
-static inline u32 at91sam9263_get_sdram_size(int bank)
-{
- return 0;
-}
-
-static inline bool at91sam9263_is_low_power_sdram(void)
-{
- return false;
-}
-#endif
#endif
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index ddd6971e37..7f84f41e5b 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -151,6 +151,31 @@ static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask)
return (pdsr & mask) != 0;
}
+static inline void at91_mux_pio_pin(void __iomem *pio, unsigned mask,
+ enum at91_mux mux, int gpio_state)
+{
+ at91_mux_disable_interrupt(pio, mask);
+
+ switch(mux) {
+ case AT91_MUX_GPIO:
+ at91_mux_gpio_enable(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_A:
+ at91_mux_set_A_periph(pio, mask);
+ break;
+ case AT91_MUX_PERIPH_B:
+ at91_mux_set_B_periph(pio, mask);
+ break;
+ default:
+ /* ignore everything else */
+ break;
+ }
+ if (mux != AT91_MUX_GPIO)
+ at91_mux_gpio_disable(pio, mask);
+
+ at91_mux_set_pullup(pio, mask, gpio_state & GPIO_PULL_UP);
+}
+
static inline void at91_mux_pio3_pin(void __iomem *pio, unsigned mask,
enum at91_mux mux, int gpio_state)
{
diff --git a/arch/arm/mach-at91/include/mach/sam92_ll.h b/arch/arm/mach-at91/include/mach/sam92_ll.h
new file mode 100644
index 0000000000..f5cef197d3
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sam92_ll.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_SAM92_LL_H__
+#define __MACH_SAM92_LL_H__
+
+#include <debug_ll.h>
+#include <common.h>
+
+#include <mach/at91_pmc_ll.h>
+#include <mach/at91sam9260.h>
+#include <mach/at91sam9261.h>
+#include <mach/at91sam9263.h>
+#include <mach/at91sam926x.h>
+#include <mach/debug_ll.h>
+#include <mach/early_udelay.h>
+#include <mach/iomux.h>
+
+struct sam92_pmc_config {
+ unsigned int diva;
+ unsigned int mula;
+};
+
+void sam9263_lowlevel_init(const struct sam92_pmc_config *config);
+
+static inline void sam92_pmc_enable_periph_clock(int clk)
+{
+ at91_pmc_enable_periph_clock(IOMEM(AT91SAM926X_BASE_PMC), clk);
+}
+
+/* requires relocation */
+static inline void sam92_udelay_init(unsigned int msc)
+{
+ early_udelay_init(IOMEM(AT91SAM926X_BASE_PMC), IOMEM(AT91SAM9263_BASE_PIT),
+ AT91SAM926X_ID_SYS, msc, 0);
+}
+
+static inline void sam92_dbgu_setup_ll(unsigned int mck)
+{
+ void __iomem *pio = IOMEM(AT91SAM9263_BASE_PIOC);
+
+ // Setup clock for pio
+ sam92_pmc_enable_periph_clock(AT91SAM9263_ID_PIOCDE);
+
+ // Setup DBGU uart
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC30), AT91_MUX_PERIPH_A, GPIO_PULL_UP); // DRXD
+ at91_mux_pio_pin(pio, pin_to_mask(AT91_PIN_PC31), AT91_MUX_PERIPH_A, 0); // DTXD
+
+ // Setup dbgu
+ at91_dbgu_setup_ll(IOMEM(AT91_BASE_DBGU1), mck, CONFIG_BAUDRATE);
+ pbl_set_putc(at91_dbgu_putc, IOMEM(AT91_BASE_DBGU1));
+ putc_ll('#');
+}
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/xload.h b/arch/arm/mach-at91/include/mach/xload.h
index e9336d59c9..6b9492193b 100644
--- a/arch/arm/mach-at91/include/mach/xload.h
+++ b/arch/arm/mach-at91/include/mach/xload.h
@@ -4,7 +4,7 @@
#define __MACH_XLOAD_H
#include <linux/compiler.h>
-#include <pbl.h>
+#include <pbl/bio.h>
void __noreturn sama5d2_sdhci_start_image(u32 r4);
void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock,
@@ -13,5 +13,10 @@ void __noreturn sama5d3_atmci_start_image(u32 r4, unsigned int clock,
int at91_sdhci_bio_init(struct pbl_bio *bio, void __iomem *base);
int at91_mci_bio_init(struct pbl_bio *bio, void __iomem *base,
unsigned int clock, unsigned int slot);
+void at91_mci_bio_set_highcapacity(bool highcapacity_card);
+
+void __noreturn sam9263_atmci_start_image(u32 mmc_id, unsigned int clock,
+ bool slot_b);
+
#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-at91/sam9263_ll.c b/arch/arm/mach-at91/sam9263_ll.c
new file mode 100644
index 0000000000..ffde065f6e
--- /dev/null
+++ b/arch/arm/mach-at91/sam9263_ll.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0-only AND BSD-1-Clause
+// SPDX-FileCopyrightText: 2017, Microchip Corporation
+
+#include <mach/at91sam9263_matrix.h>
+#include <mach/barebox-arm.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_wdt.h>
+#include <mach/sam92_ll.h>
+
+static void sam9263_pmc_init(const struct sam92_pmc_config *config)
+{
+ at91_pmc_init(IOMEM(AT91SAM926X_BASE_PMC), 0);
+
+ /* Initialize PLL charge pump, must be done before PLLAR/PLLBR */
+ at91_pmc_init_pll(IOMEM(AT91SAM926X_BASE_PMC), AT91SAM9_PMC_ICPPLLA | AT91SAM9_PMC_ICPPLLB);
+
+ /* Setting PLL A and divider A */
+ at91_pmc_cfg_plla(IOMEM(AT91SAM926X_BASE_PMC),
+ AT91_PMC_MUL_(config->mula) |
+ AT91_PMC_OUT_2 | // 190 to 240 MHz
+ config->diva, // Divider
+ 0);
+
+ /* Selection of Master Clock and Processor Clock */
+
+ /* PCK = PLLA = 2 * MCK */
+ at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+ AT91_PMC_CSS_SLOW
+ | AT91_PMC_PRES_1
+ | AT91SAM9_PMC_MDIV_2
+ | AT91_PMC_PDIV_1,
+ 0);
+
+ /* Switch MCK on PLLA output */
+ at91_pmc_cfg_mck(IOMEM(AT91SAM926X_BASE_PMC),
+ AT91_PMC_CSS_PLLA
+ | AT91_PMC_PRES_1
+ | AT91SAM9_PMC_MDIV_2
+ | AT91_PMC_PDIV_1,
+ 0);
+}
+
+static inline void matrix_wr(unsigned int offset, const unsigned int value)
+{
+ writel(value, IOMEM(AT91SAM9263_BASE_MATRIX + offset));
+}
+
+static void sam9263_matrix_init(void)
+{
+ /* Bus Matrix Master Configuration Register */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG0, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* OHCI */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG1, AT91SAM9263_MATRIX_ULBT_EIGHT); /* ISI */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG2, AT91SAM9263_MATRIX_ULBT_EIGHT); /* 2D */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG3, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DMAC */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG4, AT91SAM9263_MATRIX_ULBT_FOUR); /* MACB */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG5, AT91SAM9263_MATRIX_ULBT_SIXTEEN); /* LCDC */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG6, AT91SAM9263_MATRIX_ULBT_SINGLE); /* PDC */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG7, AT91SAM9263_MATRIX_ULBT_EIGHT); /* DBUS */
+ matrix_wr(AT91SAM9263_MATRIX_MCFG8, AT91SAM9263_MATRIX_ULBT_EIGHT); /* IBUS */
+
+ /* Bus Matrix Slave Configuration Registers */
+
+ /* ROM */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG0,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+ /* RAM80K */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG1,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_EMAC
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+ /* RAM16K */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG2,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_USB
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(16));
+
+ /* PERIPHERALS */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG3,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_PDC
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+ /* EBI0 */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG4,
+ AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926I
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(32));
+
+ /* EBI1 */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG5,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_LCDC
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(64));
+
+ /* APB */
+ matrix_wr(AT91SAM9263_MATRIX_SCFG6,
+ AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY
+ | AT91SAM9263_MATRIX_FIXED_DEFMSTR_ARM926D
+ | AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST
+ | AT91SAM9263_MATRIX_SLOT_CYCLE_(4));
+
+ /* ROM */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS0,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(0)
+ | AT91SAM9263_MATRIX_M2PR_(2)
+ | AT91SAM9263_MATRIX_M3PR_(1)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(3)
+ | AT91SAM9263_MATRIX_M6PR_(2)
+ | AT91SAM9263_MATRIX_M7PR_(3));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS0, AT91SAM9263_MATRIX_M8PR_(0));
+
+ /* RAM80K */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS1,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(2)
+ | AT91SAM9263_MATRIX_M2PR_(1)
+ | AT91SAM9263_MATRIX_M3PR_(3)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(0));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS1, AT91SAM9263_MATRIX_M8PR_(2));
+
+ /* RAM16K */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS2,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(0)
+ | AT91SAM9263_MATRIX_M2PR_(2)
+ | AT91SAM9263_MATRIX_M3PR_(1)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(3)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(2));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS2, AT91SAM9263_MATRIX_M8PR_(0));
+
+ /* PERIPHERALS */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS3,
+ AT91SAM9263_MATRIX_M0PR_(0)
+ | AT91SAM9263_MATRIX_M1PR_(1)
+ | AT91SAM9263_MATRIX_M2PR_(0)
+ | AT91SAM9263_MATRIX_M3PR_(2)
+ | AT91SAM9263_MATRIX_M4PR_(1)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(2));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS3, AT91SAM9263_MATRIX_M8PR_(3));
+
+ /* EBI0 */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS4,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(3)
+ | AT91SAM9263_MATRIX_M2PR_(0)
+ | AT91SAM9263_MATRIX_M3PR_(2)
+ | AT91SAM9263_MATRIX_M4PR_(3)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(0)
+ | AT91SAM9263_MATRIX_M7PR_(1));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS4, AT91SAM9263_MATRIX_M8PR_(2));
+
+ /* EBI1 */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS5,
+ AT91SAM9263_MATRIX_M0PR_(0)
+ | AT91SAM9263_MATRIX_M1PR_(1)
+ | AT91SAM9263_MATRIX_M2PR_(0)
+ | AT91SAM9263_MATRIX_M3PR_(0)
+ | AT91SAM9263_MATRIX_M4PR_(3)
+ | AT91SAM9263_MATRIX_M5PR_(2)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(2));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS5, AT91SAM9263_MATRIX_M8PR_(1));
+
+ /* APB */
+ matrix_wr(AT91SAM9263_MATRIX_PRAS6,
+ AT91SAM9263_MATRIX_M0PR_(1)
+ | AT91SAM9263_MATRIX_M1PR_(0)
+ | AT91SAM9263_MATRIX_M2PR_(2)
+ | AT91SAM9263_MATRIX_M3PR_(1)
+ | AT91SAM9263_MATRIX_M4PR_(0)
+ | AT91SAM9263_MATRIX_M5PR_(0)
+ | AT91SAM9263_MATRIX_M6PR_(3)
+ | AT91SAM9263_MATRIX_M7PR_(3));
+
+ matrix_wr(AT91SAM9263_MATRIX_PRBS6, AT91SAM9263_MATRIX_M8PR_(2));
+}
+
+static void sam9263_rstc_init(void)
+{
+ writel(AT91_RSTC_KEY | AT91_RSTC_URSTEN, IOMEM(AT91SAM926X_BASE_RSTC + AT91_RSTC_MR));
+}
+
+void sam9263_lowlevel_init(const struct sam92_pmc_config *config)
+{
+ at91_wdt_disable(IOMEM(AT91SAM9263_BASE_WDT));
+ sam9263_pmc_init(config);
+ sam9263_matrix_init();
+ sam9263_rstc_init();
+}
diff --git a/arch/arm/mach-at91/sama5d2.c b/arch/arm/mach-at91/sama5d2.c
index a4aa8a2339..b05d6a56bd 100644
--- a/arch/arm/mach-at91/sama5d2.c
+++ b/arch/arm/mach-at91/sama5d2.c
@@ -62,8 +62,8 @@ static int sama5d2_bootsource_init(void)
at91_bootsource = __sama5d2_stashed_bootrom_r4;
- bootsource_set(sama5_bootsource(at91_bootsource));
- bootsource_set_instance(sama5_bootsource_instance(at91_bootsource));
+ bootsource_set_raw(sama5_bootsource(at91_bootsource),
+ sama5_bootsource_instance(at91_bootsource));
return 0;
}
diff --git a/arch/arm/mach-at91/xload-mmc.c b/arch/arm/mach-at91/xload-mmc.c
index 28d122f0a3..33e5b203fe 100644
--- a/arch/arm/mach-at91/xload-mmc.c
+++ b/arch/arm/mach-at91/xload-mmc.c
@@ -9,7 +9,7 @@
#include <mach/gpio.h>
#include <linux/sizes.h>
#include <asm/cache.h>
-#include <pbl.h>
+#include <pbl/bio.h>
static void at91_fat_start_image(struct pbl_bio *bio,
void *buf, unsigned int len,
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 75acee8dad..48209fb5c6 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -8,30 +8,51 @@ config ARCH_TEXT_BASE
config MACH_RPI_COMMON
bool
+ select ARM_USE_COMPRESSED_DTB
+
+config MACH_RPI_AARCH_32_64
+ select MACH_RPI_COMMON
+ select CPU_V7 if 32BIT
+ select ARM_SECURE_MONITOR if 32BIT
+ select CPU_V8 if 64BIT
+ select BOARD_ARM_GENERIC_DT if 64BIT
+ bool
+ help
+ Select this from CPUs that support both AArch32 and AArch64
+ execution modes. barebox can be compiled for only one of
+ these states, depending on the value of
+ CONFIG_32BIT/CONFIG_64BIT.
menu "select Broadcom BCM283X boards to be built"
config MACH_RPI
bool "RaspberryPi (BCM2835/ARM1176JZF-S)"
+ depends on 32BIT
select CPU_V6
select MACH_RPI_COMMON
config MACH_RPI2
bool "RaspberryPi 2 (BCM2836/CORTEX-A7)"
+ depends on 32BIT
select CPU_V7
select MACH_RPI_COMMON
config MACH_RPI3
bool "RaspberryPi 3 (BCM2837/CORTEX-A53)"
- select CPU_V7
+ select MACH_RPI_AARCH_32_64
select MACH_RPI_COMMON
- select ARM_SECURE_MONITOR
+ depends on 32BIT || (64BIT && !MMU_EARLY)
config MACH_RPI_CM3
bool "RaspberryPi Compute Module 3 (BCM2837/CORTEX-A53)"
- select CPU_V7
+ select MACH_RPI_AARCH_32_64
+ select MACH_RPI_COMMON
+ depends on 32BIT || (64BIT && !MMU_EARLY)
+
+config MACH_RPI4
+ bool "RaspberryPi 4 (BCM2711/CORTEX-A72)"
+ select MACH_RPI_AARCH_32_64
select MACH_RPI_COMMON
- select ARM_SECURE_MONITOR
endmenu
diff --git a/arch/arm/mach-bcm283x/Makefile b/arch/arm/mach-bcm283x/Makefile
index e5ef78af97..53343cec8c 100644
--- a/arch/arm/mach-bcm283x/Makefile
+++ b/arch/arm/mach-bcm283x/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y += core.o mbox.o
+obj-pbl-y += mbox.o core.o
diff --git a/arch/arm/mach-bcm283x/core.c b/arch/arm/mach-bcm283x/core.c
index f2528cf1f1..40882fb6d6 100644
--- a/arch/arm/mach-bcm283x/core.c
+++ b/arch/arm/mach-bcm283x/core.c
@@ -1,40 +1,29 @@
-/*
- * Author: Carlo Caione <carlo@carlocaione.org>
- *
- * Based on mach-nomadik
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-only
-#include <common.h>
-#include <init.h>
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/err.h>
-
-#include <io.h>
-#include <asm/armlinux.h>
-#include <linux/sizes.h>
-
-#include <mach/platform.h>
+#include <linux/types.h>
#include <mach/core.h>
-#include <linux/amba/bus.h>
+#include <asm/system_info.h>
-void bcm2835_add_device_sdram(u32 size)
+void __iomem *bcm2835_get_mmio_base_by_cpuid(void)
{
- if (!size)
- size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);
+ static u32 cpuid;
+
+ if (!cpuid) {
+ cpuid = read_cpuid_id();
+ pr_debug("ARM CPUID: %08x\n", cpuid);
+ }
+
+ /* We know ARM1167, Cortex A-7, A-53 and A-72 CPUID mask is identical */
+ switch(cpuid & CPU_IS_ARM1176_MASK) {
+ case CPU_IS_ARM1176: /* bcm2835 */
+ return IOMEM(0x20000000);
+ case CPU_IS_CORTEX_A7: /* bcm2836 */
+ case CPU_IS_CORTEX_A53: /* bcm2837 */
+ return IOMEM(0x3f000000);
+ case CPU_IS_CORTEX_A72: /* bcm2711 */
+ return IOMEM(0xfe000000);
+ }
- arm_add_mem_device("ram0", BCM2835_SDRAM_BASE, size);
+ pr_err("Couldn't determine rpi by CPUID %08x\n", cpuid);
+ return NULL;
}
diff --git a/arch/arm/mach-bcm283x/include/mach/core.h b/arch/arm/mach-bcm283x/include/mach/core.h
index a1c47f9154..c8547351a3 100644
--- a/arch/arm/mach-bcm283x/include/mach/core.h
+++ b/arch/arm/mach-bcm283x/include/mach/core.h
@@ -1,28 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2009 Carlo Caione <carlo@carlocaione.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#ifndef __BCM2835_CORE_H__
#define __BCM2835_CORE_H__
+#include <common.h>
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <asm/memory.h>
#include <mach/platform.h>
-void bcm2835_add_device_sdram(u32 size);
+static void inline bcm2835_add_device_sdram(u32 size)
+{
+ arm_add_mem_device("ram0", BCM2835_SDRAM_BASE, size);
+}
static void inline bcm2835_register_fb(void)
{
add_generic_device("bcm2835_fb", 0, NULL, 0, 0, 0, NULL);
}
+void __iomem *bcm2835_get_mmio_base_by_cpuid(void);
+
#endif
diff --git a/arch/arm/mach-bcm283x/include/mach/debug_ll.h b/arch/arm/mach-bcm283x/include/mach/debug_ll.h
index 4bfa5abc7c..fdb63b4f5a 100644
--- a/arch/arm/mach-bcm283x/include/mach/debug_ll.h
+++ b/arch/arm/mach-bcm283x/include/mach/debug_ll.h
@@ -18,6 +18,7 @@
#define __MACH_BCM2835_DEBUG_LL_H__
#include <mach/platform.h>
+#include <io.h>
#ifdef CONFIG_DEBUG_RPI1_UART
@@ -66,6 +67,31 @@ static inline void debug_ll_init(void)
debug_ll_ns16550_init(divisor);
}
+#elif defined CONFIG_DEBUG_RPI4_MINI_UART
+
+static inline uint8_t debug_ll_read_reg(int reg)
+{
+ return readb(BCM2711_MINIUART_BASE + (reg << 2));
+}
+
+static inline void debug_ll_write_reg(int reg, uint8_t val)
+{
+ writeb(val, BCM2711_MINIUART_BASE + (reg << 2));
+}
+
+#include <debug_ll/ns16550.h>
+
+static inline void debug_ll_init(void)
+{
+ /* Configured by ROM */
+}
+
+#else
+
+static inline void debug_ll_init(void)
+{
+}
+
#endif
#endif /* __MACH_BCM2835_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h
index a9f06512bc..92cadba62c 100644
--- a/arch/arm/mach-bcm283x/include/mach/mbox.h
+++ b/arch/arm/mach-bcm283x/include/mach/mbox.h
@@ -171,7 +171,10 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2837B0_BOARD_REV_3B_PLUS 0x0d
#define BCM2837B0_BOARD_REV_3A_PLUS 0x0e
#define BCM2837B0_BOARD_REV_CM3_PLUS 0x10
+#define BCM2711_BOARD_REV_4_B 0x11
#define BCM2837B0_BOARD_REV_ZERO_2 0x12
+#define BCM2711_BOARD_REV_400 0x13
+#define BCM2711_BOARD_REV_CM4 0x14
struct bcm2835_mbox_tag_get_board_rev {
struct bcm2835_mbox_tag_hdr tag_hdr;
@@ -273,6 +276,7 @@ struct bcm2835_mbox_tag_set_power_state {
#define BCM2835_MBOX_CLOCK_ID_SDRAM 8
#define BCM2835_MBOX_CLOCK_ID_PIXEL 9
#define BCM2835_MBOX_CLOCK_ID_PWM 10
+#define BCM2835_MBOX_CLOCK_ID_EMMC2 12
struct bcm2835_mbox_tag_get_clock_rate {
struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/arch/arm/mach-bcm283x/include/mach/platform.h b/arch/arm/mach-bcm283x/include/mach/platform.h
index 310f2463f2..b957ac8de3 100644
--- a/arch/arm/mach-bcm283x/include/mach/platform.h
+++ b/arch/arm/mach-bcm283x/include/mach/platform.h
@@ -31,9 +31,10 @@
#define BCM2835_CACHELINE_SIZE 64
#define BCM2835_PL011_BASE 0x20201000
-#define BCM2836_PL011_BASE 0x3f201000
+#define BCM2836_PL011_BASE 0x3f201000UL
#define BCM2835_MINIUART_BASE 0x20215040
-#define BCM2836_MINIUART_BASE 0x3f215040
+#define BCM2836_MINIUART_BASE 0x3f215040UL
+#define BCM2711_MINIUART_BASE 0xfe215040UL
#endif
diff --git a/arch/arm/mach-bcm283x/mbox.c b/arch/arm/mach-bcm283x/mbox.c
index 4b14afcfe4..4959a1a652 100644
--- a/arch/arm/mach-bcm283x/mbox.c
+++ b/arch/arm/mach-bcm283x/mbox.c
@@ -14,13 +14,20 @@
#include <init.h>
#include <io.h>
#include <of_address.h>
+#include <pbl.h>
#include <mach/mbox.h>
+#include <mach/core.h>
#define TIMEOUT (MSECOND * 1000)
static void __iomem *mbox_base;
+#ifdef __PBL__
+#define is_timeout_non_interruptible(start, timeout) ((void)start, 0)
+#define get_time_ns() 0
+#endif
+
static int bcm2835_mbox_call_raw(u32 chan, struct bcm2835_mbox_hdr *buffer,
u32 *recv)
{
@@ -109,19 +116,20 @@ static void dump_buf(struct bcm2835_mbox_hdr *buffer)
}
#endif
-static int bcm2835_mbox_probe(void)
+static void __iomem *bcm2835_mbox_probe(void)
{
struct device_node *mbox_node;
+ if (IN_PBL)
+ return bcm2835_get_mmio_base_by_cpuid() + 0xb880;
+
mbox_node = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-mbox");
if (!mbox_node) {
pr_err("Missing mbox node\n");
- return -ENOENT;
+ return NULL;
}
- mbox_base = of_iomap(mbox_node, 0);
-
- return 0;
+ return of_iomap(mbox_node, 0);
}
int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
@@ -132,9 +140,9 @@ int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
int tag_index;
if (!mbox_base) {
- ret = bcm2835_mbox_probe();
- if (ret)
- return ret;
+ mbox_base = bcm2835_mbox_probe();
+ if (!mbox_base)
+ return -ENOENT;
}
pr_debug("mbox: TX buffer\n");
@@ -143,7 +151,7 @@ int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer)
ret = bcm2835_mbox_call_raw(chan, buffer, &rbuffer);
if (ret)
return ret;
- if (rbuffer != (u32)buffer) {
+ if (rbuffer != (uintptr_t)buffer) {
pr_err("mbox: Response buffer mismatch\n");
return -EIO;
}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 6b962dcf7e..dcb70c8c1a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -177,12 +177,13 @@ config ARCH_IMX8M
select CPU_V8
select PINCTRL_IMX_IOMUX_V3
select OFTREE
- select SYS_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
select COMMON_CLK_OF_PROVIDER
select ARCH_HAS_FEC_IMX
select HW_HAS_PCI
select IMX8M_DRAM
select PBL_VERIFY_PIGGY if HABV4
+ select ARM_USE_COMPRESSED_DTB
config ARCH_IMX8MM
select ARCH_IMX8M
@@ -277,7 +278,6 @@ config MACH_CCMX51
select SPI
select DRIVER_SPI_IMX
select MFD_MC13XXX
- select RELOCATABLE
help
Say Y here if you are using Digi ConnectCore (W)i-i.MX51
equipped with a Freescale i.MX51 Processor
@@ -361,6 +361,17 @@ config MACH_PROTONIC_IMX8M
select IMX8M_DRAM
select USB_GADGET_DRIVER_ARC_PBL
+config MACH_INNOCOMM_WB15
+ bool "InnoComm WB15 (i.MX8MM) EVK"
+ select ARCH_IMX8MM
+ select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
+ select FIRMWARE_IMX8MM_ATF
+ select ARM_SMCCC
+ select MCI_IMX_ESDHC_PBL
+ select IMX8M_DRAM
+ select I2C_IMX_EARLY
+ select USB_GADGET_DRIVER_ARC_PBL
+
config MACH_KONTRON_SAMX6I
bool "Kontron sAMX6i"
select ARCH_IMX6
@@ -485,6 +496,11 @@ config MACH_AC_SXB
select MCI_IMX_ESDHC_PBL
select ARM_USE_COMPRESSED_DTB
+config MACH_MEERKAT96
+ bool "96Boards: i.MX7 Meerkat96"
+ select ARCH_IMX7
+ select ARM_USE_COMPRESSED_DTB
+
config MACH_VF610_TWR
bool "Freescale VF610 Tower Board"
select ARCH_VF610
@@ -515,7 +531,6 @@ config MACH_ZII_IMX8MQ_DEV
select ARM_SMCCC
select MCI_IMX_ESDHC_PBL
select MACH_ZII_COMMON
- select ARM_USE_COMPRESSED_DTB
config MACH_ZII_VF610_DEV
bool "ZII VF610 Dev Family"
@@ -575,7 +590,6 @@ config MACH_NXP_IMX8MN_EVK
select MCI_IMX_ESDHC_PBL
select IMX8M_DRAM
select I2C_IMX_EARLY
- select ARM_USE_COMPRESSED_DTB
config MACH_NXP_IMX8MP_EVK
bool "NXP i.MX8MP EVK Board"
@@ -586,7 +600,6 @@ config MACH_NXP_IMX8MP_EVK
select MCI_IMX_ESDHC_PBL
select IMX8M_DRAM
select I2C_IMX_EARLY
- select USB_GADGET_DRIVER_ARC_PBL
config MACH_NXP_IMX8MQ_EVK
bool "NXP i.MX8MQ EVK Board"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 2cafcd77e0..390cdaf502 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -18,7 +18,8 @@ lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
obj-$(CONFIG_ARCH_IMX7) += imx7.o
obj-$(CONFIG_ARCH_VF610) += vf610.o
obj-pbl-$(CONFIG_ARCH_IMX8M) += imx8m.o
-lwl-$(CONFIG_ARCH_IMX8M) += atf.o
+lwl-$(CONFIG_ARCH_IMX8M) += atf.o romapi.o
+obj-pbl-$(CONFIG_ARCH_IMX8M) += tzasc.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c
index 9ab9ddd203..5301c0fbe8 100644
--- a/arch/arm/mach-imx/atf.c
+++ b/arch/arm/mach-imx/atf.c
@@ -1,7 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
+#include <asm/sections.h>
#include <common.h>
+#include <firmware.h>
#include <mach/atf.h>
+#include <mach/generic.h>
+#include <mach/xload.h>
+#include <mach/romapi.h>
+#include <soc/fsl/fsl_udc.h>
/**
* imx8m_atf_load_bl31 - Load ATF BL31 blob and transfer control to it
@@ -29,12 +35,11 @@
*
*/
-static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest)
+static __noreturn void imx8m_atf_start_bl31(const void *fw, size_t fw_size, void *atf_dest)
{
void __noreturn (*bl31)(void) = atf_dest;
- if (WARN_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT))
- return;
+ BUG_ON(fw_size > MX8M_ATF_BL31_SIZE_LIMIT);
memcpy(bl31, fw, fw_size);
@@ -42,24 +47,154 @@ static void imx8m_atf_load_bl31(const void *fw, size_t fw_size, void *atf_dest)
"r" (atf_dest - 16) :
"cc");
bl31();
+ __builtin_unreachable();
}
-void imx8mm_atf_load_bl31(const void *fw, size_t fw_size)
+__noreturn void imx8mm_atf_load_bl31(const void *fw, size_t fw_size)
{
- imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR);
+ imx8m_atf_start_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR);
}
-void imx8mn_atf_load_bl31(const void *fw, size_t fw_size)
+__noreturn void imx8mn_atf_load_bl31(const void *fw, size_t fw_size)
{
- imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MN_ATF_BL31_BASE_ADDR);
+ imx8m_atf_start_bl31(fw, fw_size, (void *)MX8MN_ATF_BL31_BASE_ADDR);
}
-void imx8mp_atf_load_bl31(const void *fw, size_t fw_size)
+__noreturn void imx8mp_atf_load_bl31(const void *fw, size_t fw_size)
{
- imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MP_ATF_BL31_BASE_ADDR);
+ imx8m_atf_start_bl31(fw, fw_size, (void *)MX8MP_ATF_BL31_BASE_ADDR);
}
-void imx8mq_atf_load_bl31(const void *fw, size_t fw_size)
+__noreturn void imx8mq_atf_load_bl31(const void *fw, size_t fw_size)
{
- imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR);
+ imx8m_atf_start_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR);
+}
+
+void imx8mm_load_bl33(void *bl33)
+{
+ enum bootsource src;
+ int instance;
+
+ imx8mm_get_boot_source(&src, &instance);
+ switch (src) {
+ case BOOTSOURCE_MMC:
+ imx8m_esdhc_load_image(instance, false);
+ break;
+ case BOOTSOURCE_SERIAL:
+ /*
+ * Traditionally imx-usb-loader sends the PBL twice. The first
+ * PBL is loaded to OCRAM and executed. Then the full barebox
+ * image including the PBL is sent again and received here. We
+ * might change that in the future in imx-usb-loader so that the
+ * PBL is sent only once and we only receive the rest of the
+ * image here. To prepare that step we check if we get a full
+ * barebox image or piggydata only. When it's piggydata only move
+ * it to the place where it would be if it would have been a
+ * full image.
+ */
+ imx8mm_barebox_load_usb(bl33);
+
+ if (!strcmp("barebox", bl33 + 0x20)) {
+ /* Found the barebox marker, so this is a PBL + piggydata */
+ pr_debug("received PBL + piggydata\n");
+ } else {
+ /* no barebox marker, so this is piggydata only */
+ pr_debug("received piggydata\n");
+ memmove(bl33 + barebox_pbl_size, bl33,
+ barebox_image_size - barebox_pbl_size);
+ }
+
+ break;
+ default:
+ printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+ hang();
+ }
+
+ /*
+ * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+ * in EL2. Copy the image there, but replace the PBL part of
+ * that image with ourselves. On a high assurance boot only the
+ * currently running code is validated and contains the checksum
+ * for the piggy data, so we need to ensure that we are running
+ * the same code in DRAM.
+ */
+ memcpy(bl33, __image_start, barebox_pbl_size);
+}
+
+__noreturn void imx8mm_load_and_start_image_via_tfa(void)
+{
+ imx8mm_load_bl33((void *)MX8M_ATF_BL33_BASE_ADDR);
+ imx8mm_load_and_start_tfa(imx8mm_bl31_bin);
+}
+
+void imx8mp_load_bl33(void *bl33)
+{
+ enum bootsource src;
+ int instance;
+
+ imx8mp_get_boot_source(&src, &instance);
+ switch (src) {
+ case BOOTSOURCE_MMC:
+ imx8mp_esdhc_load_image(instance, false);
+ break;
+ case BOOTSOURCE_SERIAL:
+ imx8mp_bootrom_load_image();
+ break;
+ default:
+ printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+ hang();
+ }
+
+
+ /*
+ * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+ * in EL2. Copy the image there, but replace the PBL part of
+ * that image with ourselves. On a high assurance boot only the
+ * currently running code is validated and contains the checksum
+ * for the piggy data, so we need to ensure that we are running
+ * the same code in DRAM.
+ */
+ memcpy(bl33, __image_start, barebox_pbl_size);
+}
+
+void imx8mp_load_and_start_image_via_tfa(void)
+{
+ imx8mp_load_bl33((void *)MX8M_ATF_BL33_BASE_ADDR);
+ imx8mp_load_and_start_tfa(imx8mp_bl31_bin);
+}
+
+void imx8mn_load_bl33(void *bl33)
+{
+ enum bootsource src;
+ int instance;
+
+ imx8mn_get_boot_source(&src, &instance);
+ switch (src) {
+ case BOOTSOURCE_MMC:
+ imx8mn_esdhc_load_image(instance, false);
+ break;
+ case BOOTSOURCE_SERIAL:
+ imx8mn_bootrom_load_image();
+ break;
+ default:
+ printf("Unhandled bootsource BOOTSOURCE_%d\n", src);
+ hang();
+ }
+
+
+ /*
+ * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR
+ * in EL2. Copy the image there, but replace the PBL part of
+ * that image with ourselves. On a high assurance boot only the
+ * currently running code is validated and contains the checksum
+ * for the piggy data, so we need to ensure that we are running
+ * the same code in DRAM.
+ */
+ memcpy(bl33, __image_start, barebox_pbl_size);
+}
+
+void imx8mn_load_and_start_image_via_tfa(void)
+{
+ imx8mn_load_bl33((void *)MX8M_ATF_BL33_BASE_ADDR);
+ imx8mn_load_and_start_tfa(imx8mn_bl31_bin);
}
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 16a377341c..8c9febb50a 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -34,8 +34,7 @@ imx_boot_save_loc(void (*get_boot_source)(enum bootsource *, int *))
get_boot_source(&src, &instance);
- bootsource_set(src);
- bootsource_set_instance(instance);
+ bootsource_set_raw(src, instance);
}
@@ -309,8 +308,7 @@ void imx53_boot_save_loc(void)
imx53_get_boot_source(&src, &instance);
- bootsource_set(src);
- bootsource_set_instance(instance);
+ bootsource_set_raw(src, instance);
}
#define IMX6_SRC_SBMR1 0x04
diff --git a/arch/arm/mach-imx/imx-bbu-external-nand.c b/arch/arm/mach-imx/imx-bbu-external-nand.c
index 392497e434..40dbaabdc7 100644
--- a/arch/arm/mach-imx/imx-bbu-external-nand.c
+++ b/arch/arm/mach-imx/imx-bbu-external-nand.c
@@ -29,7 +29,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
int size_available, size_need;
int ret;
uint32_t num_bb = 0, bbt = 0;
- loff_t offset = 0;
+ loff_t nand_offset = 0, image_offset = 0;
int block = 0, len, now, blocksize;
void *image = NULL;
@@ -61,27 +61,27 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
* Collect bad blocks and construct BBT
*/
while (size_need > 0) {
- ret = ioctl(fd, MEMGETBADBLOCK, &offset);
+ ret = ioctl(fd, MEMGETBADBLOCK, &nand_offset);
if (ret < 0)
goto out;
if (ret) {
- if (!offset) {
+ if (!nand_offset) {
printf("1st block is bad. This is not supported\n");
ret = -EINVAL;
goto out;
}
- debug("bad block at 0x%08llx\n", offset);
+ debug("bad block at 0x%08llx\n", nand_offset);
num_bb++;
bbt |= (1 << block);
- offset += blocksize;
+ nand_offset += blocksize;
block++;
continue;
}
size_need -= blocksize;
size_available -= blocksize;
- offset += blocksize;
+ nand_offset += blocksize;
block++;
if (size_available < 0) {
@@ -124,7 +124,7 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
}
len = data->len;
- offset = 0;
+ nand_offset = 0;
/* last chance before erasing the flash */
ret = bbu_confirm(data);
@@ -137,13 +137,13 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
while (len > 0) {
now = min(len, blocksize);
- ret = ioctl(fd, MEMGETBADBLOCK, &offset);
+ ret = ioctl(fd, MEMGETBADBLOCK, &nand_offset);
if (ret < 0)
goto out;
if (ret) {
- offset += blocksize;
- if (lseek(fd, offset, SEEK_SET) != offset) {
+ nand_offset += blocksize;
+ if (lseek(fd, nand_offset, SEEK_SET) != nand_offset) {
ret = -errno;
goto out;
}
@@ -151,19 +151,19 @@ static int imx_bbu_external_nand_update(struct bbu_handler *handler, struct bbu_
continue;
}
- debug("writing %d bytes at 0x%08llx\n", now, offset);
+ debug("writing %d bytes at 0x%08llx\n", now, nand_offset);
- ret = erase(fd, blocksize, offset);
+ ret = erase(fd, blocksize, nand_offset);
if (ret)
goto out;
- ret = write(fd, image, now);
+ ret = write(fd, image + image_offset, now);
if (ret < 0)
goto out;
len -= now;
- image += now;
- offset += now;
+ image_offset += now;
+ nand_offset += now;
}
ret = 0;
diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h
index 09396f4646..aed294def9 100644
--- a/arch/arm/mach-imx/include/mach/atf.h
+++ b/arch/arm/mach-imx/include/mach/atf.h
@@ -4,21 +4,34 @@
#define __IMX_ATF_H__
#include <linux/sizes.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
#include <asm/system.h>
#define MX8M_ATF_BL31_SIZE_LIMIT SZ_64K
#define MX8MM_ATF_BL31_BASE_ADDR 0x00920000
#define MX8MN_ATF_BL31_BASE_ADDR 0x00960000
-#define MX8MP_ATF_BL31_BASE_ADDR 0x00960000
+#define MX8MP_ATF_BL31_BASE_ADDR 0x00970000
#define MX8MQ_ATF_BL31_BASE_ADDR 0x00910000
#define MX8M_ATF_BL33_BASE_ADDR 0x40200000
#define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR
#define MX8MQ_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR
-void imx8mm_atf_load_bl31(const void *fw, size_t fw_size);
-void imx8mn_atf_load_bl31(const void *fw, size_t fw_size);
-void imx8mp_atf_load_bl31(const void *fw, size_t fw_size);
-void imx8mq_atf_load_bl31(const void *fw, size_t fw_size);
+void __noreturn imx8mm_atf_load_bl31(const void *fw, size_t fw_size);
+void __noreturn imx8mn_atf_load_bl31(const void *fw, size_t fw_size);
+void __noreturn imx8mp_atf_load_bl31(const void *fw, size_t fw_size);
+void __noreturn imx8mq_atf_load_bl31(const void *fw, size_t fw_size);
+
+#define imx8m_load_and_start_tfa(soc,fw_name) do { \
+ size_t __bl31_size; \
+ const u8 *__bl31; \
+ get_builtin_firmware(fw_name, &__bl31, &__bl31_size); \
+ soc##_atf_load_bl31(__bl31, __bl31_size); \
+} while (0)
+
+#define imx8mm_load_and_start_tfa(fw_name) imx8m_load_and_start_tfa(imx8mm, fw_name)
+#define imx8mn_load_and_start_tfa(fw_name) imx8m_load_and_start_tfa(imx8mn, fw_name)
+#define imx8mp_load_and_start_tfa(fw_name) imx8m_load_and_start_tfa(imx8mp, fw_name)
#endif
diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h
index d63669e1e0..bf89701fe0 100644
--- a/arch/arm/mach-imx/include/mach/imx25-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx25-regs.h
@@ -56,6 +56,7 @@
#define MX25_KPP_BASE_ADDR 0x43fa8000
#define MX25_RNGB_BASE_ADDR 0x53fb0000
#define MX25_SDMA_BASE_ADDR 0x53fd4000
+#define MX25_WATCHDOG_BASE_ADDR 0x53fdc000
#define MX25_USB_BASE_ADDR 0x53ff4000
#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
/*
diff --git a/arch/arm/mach-imx/include/mach/imx8m-regs.h b/arch/arm/mach-imx/include/mach/imx8m-regs.h
index e1c83ee01d..a5017faf83 100644
--- a/arch/arm/mach-imx/include/mach/imx8m-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8m-regs.h
@@ -30,6 +30,7 @@
#define MX8M_UART4_BASE_ADDR 0x30A60000
#define MX8M_USDHC1_BASE_ADDR 0x30B40000
#define MX8M_USDHC2_BASE_ADDR 0x30B50000
+#define MX8M_TZASC_BASE_ADDR 0x32f80000
#define MX8M_DDRC_PHY_BASE_ADDR 0x3c000000
#define MX8M_DDRC_DDR_SS_GPR0 (MX8M_DDRC_PHY_BASE_ADDR + 0x01000000)
#define MX8M_DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
diff --git a/arch/arm/mach-imx/include/mach/romapi.h b/arch/arm/mach-imx/include/mach/romapi.h
new file mode 100644
index 0000000000..8022fc411e
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/romapi.h
@@ -0,0 +1,37 @@
+#ifndef __MACH_IMX_ROMAPI_H
+#define __MACH_IMX_ROMAPI_H
+
+struct rom_api {
+ u16 ver;
+ u16 tag;
+ u32 reserved1;
+ u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor);
+ u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor);
+};
+
+enum boot_dev_type_e {
+ BT_DEV_TYPE_SD = 1,
+ BT_DEV_TYPE_MMC = 2,
+ BT_DEV_TYPE_NAND = 3,
+ BT_DEV_TYPE_FLEXSPINOR = 4,
+ BT_DEV_TYPE_SPI_NOR = 6,
+
+ BT_DEV_TYPE_USB = 0xE,
+ BT_DEV_TYPE_MEM_DEV = 0xF,
+
+ BT_DEV_TYPE_INVALID = 0xFF
+};
+
+#define QUERY_ROM_VER 1
+#define QUERY_BT_DEV 2
+#define QUERY_PAGE_SZ 3
+#define QUERY_IVT_OFF 4
+#define QUERY_BT_STAGE 5
+#define QUERY_IMG_OFF 6
+
+#define ROM_API_OKAY 0xF0
+
+int imx8mp_bootrom_load_image(void);
+int imx8mn_bootrom_load_image(void);
+
+#endif /* __MACH_IMX_ROMAPI_H */
diff --git a/arch/arm/mach-imx/include/mach/tzasc.h b/arch/arm/mach-imx/include/mach/tzasc.h
new file mode 100644
index 0000000000..724ba50ead
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/tzasc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __IMX_TZASC_H__
+#define __IMX_TZASC_H__
+
+#include <linux/types.h>
+#include <asm/system.h>
+
+void imx8mq_tzc380_init(void);
+void imx8mm_tzc380_init(void);
+void imx8mn_tzc380_init(void);
+void imx8mp_tzc380_init(void);
+
+bool tzc380_is_enabled(void);
+
+#endif
diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h
index 03ec23ebbd..82bf663c42 100644
--- a/arch/arm/mach-imx/include/mach/xload.h
+++ b/arch/arm/mach-imx/include/mach/xload.h
@@ -3,6 +3,9 @@
#ifndef __MACH_XLOAD_H
#define __MACH_XLOAD_H
+#include <linux/compiler.h>
+#include <linux/types.h>
+
int imx53_nand_start_image(void);
int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int len);
int imx6_spi_start_image(int instance);
@@ -13,6 +16,14 @@ int imx8m_esdhc_load_image(int instance, bool start);
int imx8mn_esdhc_load_image(int instance, bool start);
int imx8mp_esdhc_load_image(int instance, bool start);
+void imx8mm_load_bl33(void *bl33);
+void imx8mn_load_bl33(void *bl33);
+void imx8mp_load_bl33(void *bl33);
+
+void __noreturn imx8mm_load_and_start_image_via_tfa(void);
+void __noreturn imx8mn_load_and_start_image_via_tfa(void);
+void __noreturn imx8mp_load_and_start_image_via_tfa(void);
+
int imx_image_size(void);
int piggydata_size(void);
diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c
new file mode 100644
index 0000000000..5d00d71154
--- /dev/null
+++ b/arch/arm/mach-imx/romapi.c
@@ -0,0 +1,44 @@
+#include <common.h>
+#include <asm/sections.h>
+#include <mach/romapi.h>
+#include <mach/atf.h>
+
+static int imx8m_bootrom_load(struct rom_api *rom_api, void *adr, size_t size)
+{
+ while (size) {
+ size_t chunksize = min(size, (size_t)1024);
+ int ret;
+
+ ret = rom_api->download_image(adr, 0, chunksize,
+ (uintptr_t)adr ^ chunksize);
+ if (ret != ROM_API_OKAY) {
+ pr_err("Failed to load piggy data (ret = %x)\n", ret);
+ return -EIO;
+ }
+
+ adr += chunksize;
+ size -= chunksize;
+ }
+
+ return 0;
+}
+
+/* read piggydata via a bootrom callback and place it behind our copy in SDRAM */
+static int imx8m_bootrom_load_image(struct rom_api *rom_api)
+{
+ return imx8m_bootrom_load(rom_api,
+ (void *)MX8M_ATF_BL33_BASE_ADDR + barebox_pbl_size,
+ __image_end - __piggydata_start);
+}
+
+int imx8mp_bootrom_load_image(void)
+{
+ struct rom_api *rom_api = (void *)0x980;
+
+ return imx8m_bootrom_load_image(rom_api);
+}
+
+int imx8mn_bootrom_load_image(void)
+{
+ return imx8mp_bootrom_load_image();
+}
diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c
new file mode 100644
index 0000000000..9af0b7ef65
--- /dev/null
+++ b/arch/arm/mach-imx/tzasc.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <mach/tzasc.h>
+#include <linux/bitops.h>
+#include <mach/imx8m-regs.h>
+#include <io.h>
+
+#define GPR_TZASC_EN BIT(0)
+#define GPR_TZASC_SWAP_ID BIT(1)
+#define GPR_TZASC_EN_LOCK BIT(16)
+
+static void enable_tzc380(bool bypass_id_swap)
+{
+ u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
+
+ /* Enable TZASC and lock setting */
+ setbits_le32(&gpr[10], GPR_TZASC_EN);
+ setbits_le32(&gpr[10], GPR_TZASC_EN_LOCK);
+ if (bypass_id_swap)
+ setbits_le32(&gpr[10], BIT(1));
+ /*
+ * set Region 0 attribute to allow secure and non-secure
+ * read/write permission. Found some masters like usb dwc3
+ * controllers can't work with secure memory.
+ */
+ writel(0xf0000000, MX8M_TZASC_BASE_ADDR + 0x108);
+}
+
+void imx8mq_tzc380_init(void)
+{
+ enable_tzc380(false);
+}
+
+void imx8mn_tzc380_init(void) __alias(imx8mm_tzc380_init);
+void imx8mp_tzc380_init(void) __alias(imx8mm_tzc380_init);
+void imx8mm_tzc380_init(void)
+{
+ enable_tzc380(true);
+}
+
+bool tzc380_is_enabled(void)
+{
+ u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR);
+
+ return (readl(&gpr[10]) & (GPR_TZASC_EN | GPR_TZASC_EN_LOCK))
+ == (GPR_TZASC_EN | GPR_TZASC_EN_LOCK);
+}
diff --git a/arch/arm/mach-layerscape/Kconfig b/arch/arm/mach-layerscape/Kconfig
index bdd7d0dbfe..943a474808 100644
--- a/arch/arm/mach-layerscape/Kconfig
+++ b/arch/arm/mach-layerscape/Kconfig
@@ -17,7 +17,7 @@ config ARCH_LAYERSCAPE_PPA
config ARCH_LS1046
select CPU_V8
- select SYS_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
bool
config MACH_LS1046ARDB
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
index c804977d22..c6f816444a 100644
--- a/arch/arm/mach-layerscape/boot.c
+++ b/arch/arm/mach-layerscape/boot.c
@@ -32,8 +32,8 @@ static int ls1046a_bootsource_init(void)
if (!of_machine_is_compatible("fsl,ls1046a"))
return 0;
- bootsource_set(ls1046_bootsource_get());
+ bootsource_set_raw(ls1046_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
return 0;
}
-coredevice_initcall(ls1046a_bootsource_init); \ No newline at end of file
+coredevice_initcall(ls1046a_bootsource_init);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 691c159e36..c8ef2c62af 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -79,6 +79,7 @@ config MACH_DUCKBILL
config MACH_CFA10036
bool "cfa-10036"
select MXS_OCOTP
+ select I2C
select I2C_GPIO
select EEPROM_AT24
help
diff --git a/arch/arm/mach-mxs/imx.c b/arch/arm/mach-mxs/imx.c
index 5af9cca4e9..a8a9500918 100644
--- a/arch/arm/mach-mxs/imx.c
+++ b/arch/arm/mach-mxs/imx.c
@@ -158,8 +158,7 @@ static void mxs_boot_save_loc(void)
case 0x9: src = BOOTSOURCE_MMC; break; /* "SSP SD/MMC #0" */
}
- bootsource_set(src);
- bootsource_set_instance(instance);
+ bootsource_set_raw(src, instance);
}
static int mxs_init(void)
diff --git a/arch/arm/mach-mxs/include/mach/imx23.h b/arch/arm/mach-mxs/include/mach/imx23.h
index bdd3ae4407..03eddabed0 100644
--- a/arch/arm/mach-mxs/include/mach/imx23.h
+++ b/arch/arm/mach-mxs/include/mach/imx23.h
@@ -25,7 +25,7 @@ static inline u32 imx23_get_memsize(void)
cs0 = FIELD_GET(DRAM_CTL14_CS0_EN, ctl14);
cs1 = FIELD_GET(DRAM_CTL14_CS1_EN, ctl14);
- return (1 << columns) * (1 << rows) * banks * (cs0 + cs1);
+ return 2 * (1 << columns) * (1 << rows) * banks * (cs0 + cs1);
}
#endif /* __MACH_IMX23_H */
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index bfe5b3dc73..7f9a2bcf37 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -153,8 +153,7 @@ static int am33xx_bootsource(void)
default:
src = BOOTSOURCE_UNKNOWN;
}
- bootsource_set(src);
- bootsource_set_instance(instance);
+ bootsource_set_raw(src, instance);
return 0;
}
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 69f2d51a62..cb6105cc04 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -475,8 +475,7 @@ static int omap3_bootsource(void)
src = BOOTSOURCE_UNKNOWN;
}
- bootsource_set(src);
- bootsource_set_instance(0);
+ bootsource_set_raw(src, 0);
return 0;
}
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index 6d165b7f68..7c8374eba7 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -498,8 +498,7 @@ static int omap4_bootsource(void)
src = BOOTSOURCE_UNKNOWN;
}
- bootsource_set(src);
- bootsource_set_instance(0);
+ bootsource_set_raw(src, 0);
omap_vector_init();
diff --git a/arch/arm/mach-omap/omap_devices.c b/arch/arm/mach-omap/omap_devices.c
index beae59f74d..022616ba54 100644
--- a/arch/arm/mach-omap/omap_devices.c
+++ b/arch/arm/mach-omap/omap_devices.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <driver.h>
-#include <platform_data/serial-ns16550.h>
#include <asm/armlinux.h>
#include <mach/omap3-devices.h>
@@ -16,15 +15,10 @@ void omap_add_sram0(resource_size_t base, resource_size_t size)
add_mem_device("sram0", base, size, IORESOURCE_MEM_WRITEABLE);
}
-static struct NS16550_plat serial_plat = {
- .clock = 48000000, /* 48MHz (APLL96/2) */
- .shift = 2,
-};
-
struct device_d *omap_add_uart(int id, unsigned long base)
{
return add_generic_device("omap-uart", id, NULL, base, 1024,
- IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
+ IORESOURCE_MEM | IORESOURCE_MEM_8BIT, NULL);
}
#if defined(CONFIG_DRIVER_VIDEO_OMAP)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4b6dfd2c17..1f3ba706ee 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -30,7 +30,7 @@ config ARCH_RK3288
config ARCH_ROCKCHIP_V8
bool
select CPU_V8
- select SYS_SUPPORTS_64BIT_KERNEL
+ select CPU_SUPPORTS_64BIT_KERNEL
select ARM_ATF
select RELOCATABLE
diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c
index 2a1d4ab7a2..f623af6731 100644
--- a/arch/arm/mach-rockchip/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288.c
@@ -69,8 +69,7 @@ static int rk3288_env_init(void)
const char *envpath = "/chosen/environment-emmc";
int ret;
- bootsource_set(BOOTSOURCE_MMC);
- bootsource_set_instance(0);
+ bootsource_set_raw(BOOTSOURCE_MMC, 0);
ret = of_device_enable_path(envpath);
if (ret < 0)
diff --git a/arch/arm/mach-rockchip/rk3568.c b/arch/arm/mach-rockchip/rk3568.c
index 234c6d22d1..19dfa9b871 100644
--- a/arch/arm/mach-rockchip/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568.c
@@ -151,19 +151,16 @@ static struct rk_bootsource bootdev_map[] = {
[0xa] = { .src = BOOTSOURCE_USB, .instance = 0 },
};
-static enum bootsource rk3568_bootsource(void)
+static void rk3568_bootsource(void)
{
u32 v;
v = readl(RK3568_IRAM_BASE + 0x10);
if (v >= ARRAY_SIZE(bootdev_map))
- return BOOTSOURCE_UNKNOWN;
+ return;
- bootsource_set(bootdev_map[v].src);
- bootsource_set_instance(bootdev_map[v].instance);
-
- return bootdev_map[v].src;
+ bootsource_set(bootdev_map[v].src, bootdev_map[v].instance);
}
int rk3568_init(void)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 80344315e3..b23a41d3f9 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -23,6 +23,7 @@ config ARCH_SOCFPGA_CYCLONE5
config ARCH_SOCFPGA_ARRIA10
bool
select CPU_V7
+ select ARM_USE_COMPRESSED_DTB
select RESET_CONTROLLER
select HAVE_PBL_MULTI_IMAGES
select OFDEVICE
@@ -36,6 +37,10 @@ config MACH_SOCFPGA_EBV_SOCRATES
select ARCH_SOCFPGA_CYCLONE5
bool "EBV Socrates"
+config MACH_SOCFPGA_ENCLUSTRA_AA1
+ select ARCH_SOCFPGA_ARRIA10
+ bool "Enclustra AA1"
+
config MACH_SOCFPGA_REFLEX_ACHILLES
select ARCH_SOCFPGA_ARRIA10
bool "Reflex Achilles"
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 935270bfad..008dbc3887 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -3,6 +3,7 @@
pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o
obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+lwl-y += cpu_init.o
pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-xload.o \
arria10-xload-emmc.o
diff --git a/arch/arm/mach-socfpga/arria10-bootsource.c b/arch/arm/mach-socfpga/arria10-bootsource.c
index 3319dc4bf9..9055570c07 100644
--- a/arch/arm/mach-socfpga/arria10-bootsource.c
+++ b/arch/arm/mach-socfpga/arria10-bootsource.c
@@ -55,8 +55,7 @@ static int arria10_boot_save_loc(void)
src = arria10_get_bootsource();
- bootsource_set(src);
- bootsource_set_instance(0);
+ bootsource_set_raw(src, 0);
return 0;
}
diff --git a/arch/arm/mach-socfpga/cpu_init.c b/arch/arm/mach-socfpga/cpu_init.c
new file mode 100644
index 0000000000..1e0df1f6a5
--- /dev/null
+++ b/arch/arm/mach-socfpga/cpu_init.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/errata.h>
+#include <mach/init.h>
+
+void arria10_cpu_lowlevel_init(void)
+{
+ enable_arm_errata_794072_war();
+ enable_arm_errata_845369_war();
+}
diff --git a/arch/arm/mach-socfpga/cyclone5-bootsource.c b/arch/arm/mach-socfpga/cyclone5-bootsource.c
index 717a003425..ab18d03302 100644
--- a/arch/arm/mach-socfpga/cyclone5-bootsource.c
+++ b/arch/arm/mach-socfpga/cyclone5-bootsource.c
@@ -50,8 +50,7 @@ static int cyclone5_boot_save_loc(void)
break;
}
- bootsource_set(src);
- bootsource_set_instance(0);
+ bootsource_set_raw(src, 0);
return 0;
}
@@ -84,8 +83,7 @@ static int arria10_boot_save_loc(void)
break;
}
- bootsource_set(src);
- bootsource_set_instance(0);
+ bootsource_set_raw(src, 0);
return 0;
}
diff --git a/arch/arm/mach-socfpga/include/mach/init.h b/arch/arm/mach-socfpga/include/mach/init.h
new file mode 100644
index 0000000000..c0e073ee13
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/init.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+void arria10_cpu_lowlevel_init(void);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index bcd04b210a..938dea3c3d 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -98,8 +98,7 @@ static void setup_boot_mode(void)
pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d\n",
boot_ctx, boot_mode, instance);
- bootsource_set(src);
- bootsource_set_instance(instance);
+ bootsource_set_raw(src, instance);
}
static int __stm32mp_cputype;
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 3535262848..c60e9dbd75 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,16 +5,8 @@
*/
#include <common.h>
-#include <init.h>
#include <io.h>
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/amba/bus.h>
-
-#include <asm/hardware/arm_timer.h>
#include <asm/hardware/sp810.h>
-
#include <mach/devices.h>
void __iomem *v2m_sysreg_base;
@@ -23,8 +15,7 @@ static void v2m_sysctl_init(void __iomem *base)
{
u32 scctrl;
- if (WARN_ON(!base))
- return;
+ v2m_sysreg_base = base;
/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
scctrl = readl(base + SCCTRL);
@@ -36,13 +27,11 @@ static void v2m_sysctl_init(void __iomem *base)
void vexpress_a9_legacy_init(void)
{
v2m_wdt_base = IOMEM(0x1000f000);
- v2m_sysreg_base = IOMEM(0x10001000);
v2m_sysctl_init(IOMEM(0x10001000));
}
void vexpress_init(void)
{
v2m_wdt_base = IOMEM(0x1c0f0000);
- v2m_sysreg_base = IOMEM(0x1c020000);
v2m_sysctl_init(IOMEM(0x1c020000));
}
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index 806aeb9130..5abd52f6a2 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -71,7 +71,7 @@ static int zynq_init(void)
restart_handler_register_fn("soc", zynq_restart_soc);
- bootsource_set(zynq_bootsource_get());
+ bootsource_set_raw(zynq_bootsource_get(), BOOTSOURCE_INSTANCE_UNKNOWN);
return 0;
}
diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c
index 610d4bba6e..312325956a 100644
--- a/arch/arm/mach-zynqmp/zynqmp.c
+++ b/arch/arm/mach-zynqmp/zynqmp.c
@@ -148,8 +148,7 @@ static int zynqmp_init(void)
int boot_instance;
zynqmp_get_bootsource(&boot_src, &boot_instance);
- bootsource_set(boot_src);
- bootsource_set_instance(boot_instance);
+ bootsource_set_raw(boot_src, boot_instance);
reset_source_set(zynqmp_get_reset_src());